An Assura geometry extraction and Spectre re-simulation

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Xignal Technologies AG develops and markets mixed-signal ICs that enable new systemarchitectures through significant improvements in performance and in power consumption.Xignal Technologies AG

An Assura geometry extraction and Spectre re-simulation flow

to simulate

Shallow Trench Isolation (STI) stress effects

in analogue circuits

Bernd Fischer

Xignal Technologies AG, Germany

CDNLive! EMEA Nice, France

25 – 27 June 2006

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For CMOS technologies below 0.25µm Shallow Trench Isolation (STI) has become the standarddevice isolation scheme.Despite its advantages, STI applies mechanical stress to the MOS transistor changing itselectrical device characteristic. As the stress depends on local layout geometries, the stress hasto be evaluated for each individual device. The bsim3v3 model has been enhanced and newinstance parameters and equations were added to the model to cover this stress effects.

This presentation shows an approach how STI stress effects can be accounted for. Thepresented method is based on an Assura geometry extraction and Spectre re-simulation flow. Forthat the MOS transistors Component Description Format (CDF) were modified and additionalcommands were added to the Assura ‘extract rules‘.

Example layout geometries were extracted and simulated and the influence of the stress effectswere evaluated. As a conclusion appropriate layout techniques will be demonstrated to minimiseSTI stress for sensitive analogue circuits.This approach has been successfully proven at a 14Bit, 40MSps ADC design.

Abstract

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• Process Evolution form LOCOS to STI

• Model Enhancements (bsim3v3)

• Implementation in the CDF and Assura extract rule file

• Design Flow

• Example Layouts

• Conclusion

Contents

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Local Oxidation of Silicon(LOCOS) has been thestandard device isolationscheme of CMOS technologiesdown to ~0.25µm feature size.

Due to shrinking issues furtherdevice isolation with LOCOS isno longer practical and analternative form of isolation wasdeveloped.

LOCOS

Figure 1: MOS cross section with field oxide

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Shallow Trench Isolation(STI) is the device isolationscheme for modern CMOStechnologies below 0.25µm.

STI allows further shrinking,higher device density, flattersurface topology and hasless perimeter sidewallcapacitance than LOCOS.

What is STI?

Figure 2: MOS cross section with STI

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What is STI stress?

Despite its advantages, STI appliesmechanical stress to the MOS transistor.

This effect, known as STI or Length ofOxide Definition (LOD) stress effect,influences the electrical characteristics of aMOS transistor, it impacts mobility (µeff),carrier saturation velocity (Vsat) , thresholdvoltage (Vth) and other second ordereffects [1] [2]. Figure 3: Stress induced by STI

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To account for this stress, standard models like bsim3v3 were enhanced and newinstance parameters and equations were added [1] [3].

The new instance parameters SA and SB are the distance between the OxideDefinition (OD) edge for one respectively the other side to the poly edge.

Figure 4: Typical MOS layout top view

New modelparameters

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The mobility (µeff) and saturation velocity (Vsat) parameters are used to demonstrate howthe extracted layout information is fed into the enhanced bsim3v3 model equations.

Model enhancements

In the above equations µeff0 and Vsat0 are low filed mobility and saturation velocity atSAreff and SBreff. And SAreff and SBreff are reference distances between the OD edgeto the poly edge form one and the other side.

Figure 5: Mobility and saturation velocity related equations

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In general MOS transistors have irregularshapes. To fully describe the shape oftheir OD regions additional instanceparameters are required. However thisresults in to many parameters for thesimulator netlist. A way to overcome thisis the concept of effective SA and SB(SAeff and SBeff) [1] [4].

Figure 6: MOS layout with irregular shape

MOS with irregularshapes

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The concept of SAeff andSBeff allows an accurate andefficient layout extraction.Only one set of SA and SBhas to be extracted tocompletely describe thestress effects of irregularMOS layouts.The resulting equations canthen be implemented directlyin a layout extraction tool likeCadence Assura.

Figure 7: Equations for layout extraction

Concept of effectiveSA and SB

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The measureSTIcommand

• Assura offers the powerful command measureSTI to measure layout dataassociated with the STI stress effect. The measureSTI command can be usedlike the measureParameter command after the extractMOS statement.

• The calculateExpresion is an argument of the measureSTI which allows tocalculate Inv_sa and Inv_sb.

• The measureSTI command evaluates the equations in the calculateExpresionargument for each diffusion shape.

• The result of the calculateExpresion equations is returned in a list of derivedlayers defined in the output argument.

• These output values can be further processed with the calculateParametercommand to get SAeff and SBeff for the extracted MOS.

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if( avSwitch( "Measure_STI" ) thenmeasureSTI(nmos ;; device recognition layerod ;; diffusion layer60 ;; maximum distance to measureoutput( invSA invSB ) ;; <- output parameter valuescalculateExp( ;; calculation of output params.

sw / w_NMOS / ( sa + 0.5 * l_NMOS )sw / w_NMOS / ( sb + 0.5 * l_NMOS )

))

SAeff = calculateParameter( 1e-6 / invSA - 0.5u * l_NMOS ) ;; SA <- invSAnameParameter( SAeff "sa")SBeff = calculateParameter( 1e-6 / invSB - 0.5u * l_NMOS ) ;; SB <- invSBnameParameter( SBeff "sb"))

measureSTI in theextract.rul file

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The ComponentDescription Format(CDF) of the MOStransistor has to bemodified to reflect thetwo additional modelinstance parametersSA and SB.For that reason thetwo parameters wereadded to theparameters section ofthe MOS CDF.

;;; ParameterscdfCreateParam( cdfId

?name "sa"?prompt "OD to Poly distance A (M)"?units "lengthMetric"?defValue "350.00n"?type "string"?display "artParameterInToolDisplay('sa)"?parseAsNumber "yes"?parseAsCEL "yes"

)cdfCreateParam( cdfId

?name "sb"?prompt "OD to Poly distance B (M)"?units "lengthMetric"?defValue "350.00n"?type "string"?display "artParameterInToolDisplay('sb)"?parseAsNumber "yes"?parseAsCEL "yes"

)

Instance parameters inthe CDF

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;;; Simulator InformationcdfId->simInfo->spectre = '( nil

propMapping nilnamePrefix ""otherParameters (model)instParameters (w l as ad ps pd nrd nrs m ... sa sb)termOrder (D G S B)termMapping (nil D \:d G \:g S \:s B \:b)componentName nmos

)

The parameters SA and SB were added to the simulator information CDF section.This causes the parameters to be included into the simulators netlist.

Instance parameters inthe CDF

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Design Flow

Schematic ViewConfiguration View Layout View

1 Create Designs

Run Assura RCXwith output LVS extracted?lvsExtractedCellView “t”

?lvsExtracted “t”creates an extracted viewwith device geometry andconnectivity information,

but without parasitics

3

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The measureSTI command increases the runtime of the LVS run significantly. For atypical standard cell layout a LVS run takes about 8 times longer.Therefore an additional switch if(avSwitch("Measure_STI") is implemented, to enablethe measureSTI command through the user interface for analog layouts only.

Figure 9: Typical standard cell layout

The Meassure_STIswitch

Figure 8: Measure_STI switch

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In simulations the STI stresseffect is noticeable as adrain current (Id) variation.Id increases relative to SAand SB for NMOS anddecreases relative to SAand SB for PMOS transitors.

Id variation relative toSA and SB

Figure 10: NMOS Ids/Vds for different SB‘s

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SA SA

Id variation inmultifinger devices

Figure 10: Single gate and multifinger MOS

In multifinger MOS devices Id variation is caused by different SA and SB per finger.But for sensitive cells like current mirrors where device matching is extremelyimportant such multifinger layouts are state of the art.

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N2N1

IREF=100uA IOUT=150uA

4(1.25u/130n) 6(1.25u/130n)

Figure 10: Typical NMOS current mirror

High precision current mirrors are keyelements in most analog buildingblocks like operational amplifiers [6].The device sizes of the current mirrorin Fig.10 have been chosen todemonstrate the STI effect.Various layouts have been extractedwith the presented measureSTIcommand and the matching of theextracted layouts compared.

A NMOS current mirrorexample

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Figure 11: Typical layout of a NMOS current mirror

22.52+24.38 + 25.19+25.19 + 24.38+22.52=144.0024.90+25.11 + 25.11+24.90 =100.02

A common technique to achievematching in current mirrors is tonest the transistors as pairs,SN2DN2SN1DN1SN2SN2S shown inFig. 11.STI stress causes additionalasymmetry, therefore this techniqueis now not longer sufficient toachieve precise current matching.The re-simulated layout shows anId distribution form the lowest Id atcorner transistors to the highest Idfor the center transistors.

A current mirror layout

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Figure 12: NMOS current mirror with dummies

24.60+24.84 + 25.07+25.07 + 24.84+24.60=149.0224.97+25.04 + 25.04+24.97 =100.02

To get a uniform Id distribution inall transistors the STI stress hasto be identical for all devices.Therefore the distance of thepoly to OD edge for the cornertransistors has to be increased.This is achieved by placingdummy devices with shareddiffusion next to the activedevice.

A current mirror layoutwith dummies

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Figure 12: NMOS current mirror with dummies plus guardring

24.74+24.89 + 25.05+25.05 + 24.89+24.74 =149.3624.98+25.03 + 25.03+24.98 =100.02

A current mirror layoutwith guardring

In addition to dummytransitors it is possible toincrease the distance ofthe poly to OD edge bysurounding the deviceswith a substrateguardring.

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This approach has been successfully proven at a 14Bit, 40MSps ADC design [6].The ADC was designed in a 0.13µm 1-poly 8-metal CMOS technology.

Provenapproach

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• A design flow has been demonstrated to simulate parametermismatch of MOS devices which originate from STI stress.

• This is realized with an Assura layout extraction and a Spectrepost-layout simulation.

• The flow enables the optimisation of layout structures to achievethe matching performance required by analog building blocks.

Conclusion

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References

[1] Xuemei (Jane) Xi et al., “ BSIM4.3.0 MOSFET Model – User‘s Manual“, University ofCalifornia, Berkley, Sept. 2003.

[2] Silvaco International, “Stress Effect Model in BSIM3v3 Model“ , The Simulation Standard,pp. 5 – 6, Jan. 2004.

[3] Cadence Design Systems, “Spectre Circuit Simulator Device Models and CircuitComponents“, Chapter 20, BSIM3v3 Level 11 Model (bsim3v3), LOD Model and StressEffect.

[4] Ke-Wei Su et al., “A Scaleable Model for STI Mechanical Stress Effect on LayoutDependence of MOS Electrical Characteristics“, IEEE Custom Integrated CircuitsConference, pp. 245 – 248, Sept. 2003.

[5] Cadence Design Systems, “Assura Physical Verification Command Reference“, Chapter 3,LVS Commands.

[6] G. Mitteregger et al., “A 14b 20mW 640MHz CMOS CT ADC with 20MHz SignalBandwidth and 12b ENOB“, Proc. of ISSCC 2006.

Documents

An Assura geometry extraction and Spectre re-simulation