Microelectronics Reliability 55 (2015) 38–41

Contents lists available at ScienceDirect

Microelectronics Reliability

journal homepage: www.elsevier .com/locate /microrel

An analytical avalanche breakdown model for double gate MOSFET

http://dx.doi.org/10.1016/j.microrel.2014.08.0190026-2714/� 2014 Elsevier Ltd. All rights reserved.

⇑ Corresponding author.E-mail address: iyun@yonsei.ac.kr (I. Yun).

Edward Namkyu Cho, Yong Hyeon Shin, Ilgu Yun ⇑Department of Electrical and Electronic Engineering, Yonsei University, 50 Yonsei-ro, Seodaemun-gu, Seoul 120-749, Republic of Korea

a r t i c l e i n f o a b s t r a c t

Article history:Received 27 May 2014Received in revised form 4 August 2014Accepted 25 August 2014Available online 27 September 2014

Keywords:DG MOSFETAvalanche breakdown modelChannel length modulationEffective mobility model

An analytical model of avalanche breakdown for double gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) is presented. First of all, the effective mobility (leff) model is defined to replacethe constant mobility model. The channel length modulation (CLM) effect is modeled by solving the Pois-son’s equation. The avalanche multiplication factor (M) is calculated using the length of saturation region(DL). It is shown that the avalanche breakdown characteristics calculated from the analytical model agreewell with commercially available 2D numerical simulation results. Based on the results, the reliability ofthe DG MOSFET can be estimated using the proposed analytical model.

� 2014 Elsevier Ltd. All rights reserved.

1. Introduction

The continuing downscaling of the conventional metal-oxide-semiconductor field-effect transistor (MOSFET) has been inter-rupted by the growing portion of the short-channel effects [1].The multi-gate MOSFET such as double gate (DG) MOSFET has beenconsidered to be a candidate to extend the limitation of scalingcapability of MOSFET [2].

For the short-channel MOSFET, drain-source avalanche break-down becomes significant which limit the scaling capability ofMOSFET. The avalanche breakdown characteristics limit the volt-age applicable to the device. If the higher voltage is applied tothe device, the device operation will be failed related to the devicereliability issue. Therefore, researchers considered the breakdownvoltage as one of the important parameters in MOSFET such asdrain current and threshold voltage [3]. Previously, numericalmodels of drain-source avalanche breakdown for the conventionalMOSFET have been reported [4]. These numerically solving simula-tors have advantages on simulation result accuracy. However,these models need more memory and computation time whichare not suitable for circuit simulation compared to analytical mod-els. Analytical models can allow marginable tolerance of simula-tion accuracy but they take some advantages on memory andcomputation time for circuit simulation. To take the advantages,there have been some analytic models characterizing drain-source

avalanche breakdown for the conventional MOSFET [5,6]. How-ever, drain-source avalanche breakdown models for DG MOSFETwere rarely reported [7].

In this paper, we propose the analytical drain-source avalanchebreakdown model for DG MOSFET. Before establishing the break-down model, we initially define the carrier concentration and ver-tical-field dependent effective mobility (leff) model and thenderive the channel length modulation (CLM) effect from the Pois-son’s equation. After finding the length of saturation region (DL),we calculated the drain current-drain voltage (IDS–VDS) characteris-tics including the avalanche breakdown effect. The proposedmodel is compared with the commercially available 2D ATLASnumerical simulation for validation [8].

2. Model derivation and validation

The schematic structure of a symmetric DG MOSFET used in ouranalysis is shown in Fig. 1, where L is the channel length, tsi is thechannel film thickness and tox is the gate oxide thickness. In addi-tion, the points at x = 0 and y = 0 indicate the source-channel inter-face and the center of the channel, respectively. In this paper,L = 100 nm, tsi = 15 nm and tox = 1 nm (Sample 1)/L = 60 nm,tsi = 10 nm and tox = 1 nm (Sample 2), two different structures, areselected. A uniform p-type doping concentration (NA = 1015 cm�3)is assumed in the channel region. The source and drain regionsare also assumed to be heavily doped with n-type doping concen-tration ND = 1020 cm�3 in this work.

E.N. Cho et al. / Microelectronics Reliability 55 (2015) 38–41 39

2.1. Drain current model

From our previous work [9], we use the expression of IDS fol-lowed as

IDS ¼WL

lntoxt2

sie2si

eoxðC2

S � C2DÞ þ 2

WL

lntsiesiVt

��CS � CD

�

þ qNA

2esiln CS �

qNA

2esi

� �� ln CD �

qNA

2esi

� �� ��ð1Þ

where W, ln, esi, eox and Vt are the channel width, electron mobility,silicon permittivity, SiO2 permittivity and thermal voltage,respectively.

CS and CD can be obtained by the following expression

2C ¼ qesi

n2i

NAexp

VGS � Vfb � toxtsiesieox

C � V

Vt

!þ NA

!ð2Þ

where q, ni, VGS, Vfb and V are the electron charge, intrinsic carrierconcentration of silicon, gate-source voltage, flat band voltage andelectron quasi-Fermi potential, respectively.

For a given VGS and NA, C can be solved as a function of V. CS andCD are the solutions to Eq. (2) when V = 0 and V = drain-source volt-age (VDS), respectively.

2.2. Effective mobility

In this section, we propose an effective mobility model for car-rier concentration and vertical-field dependent carrier mobility.

Carrier concentration dependent mobility equation derived byArora et al. [10] is used to model the low-field mobility (l0) fol-lowed as

l0 ¼ lmin þldiff

ð1þ ðNA=Nref ÞaÞð3Þ

where lmin is the minimum mobility value expected, ldiff is the dif-ference between the maximum and minimum mobility expected,Nref is the reference concentration and a is the exponential factor.lmin, ldiff, Nref and a values are selected as the default values inATLAS device simulator [8].

After modeling the l0, the vertical-field dependent carriermobility (leff) is modeled by modifying the empirical equationwhich is shown to be well fitted with 2D simulations [11]:

leff ¼l0

1þ ðEeff =E0Þnð4Þ

where Eeff is the effective vertical-field, E0 and n are the fittingparameters. Eeff is calculated by the following equation [12]

Eeff �Q m þ Qdep

4eSið5Þ

Fig. 1. Schematic structure of a symmetric DG MOSFET where L, tsi and tox are thechannel length, channel film thickness and gate oxide thickness, respectively.

where Qm is the mobile charge density per unit area and Qdep is thedepletion charge density per unit area (i.e., Qdep = qNAtsi). The term,(Qm + Qdep), can be calculated from the Eq. (17) in Ref. [9].

By fitting the simulated IDS–VGS characteristics, E0 = 1.1 � 106

V/cm and n = 0.98/E0 = 9.2 � 105 V/cm and n = 1.06 are acquiredfor Sample 1/Sample 2, respectively. These values are similar tothe previous report [11]. In order to show how leff model improvesthe fitting, the comparison of IDS–VGS characteristics using leff

model and constant mobility model for Sample 1 is shown inFig. 2. As can be seen from Fig. 2, the analytical model using leff

model represents the simulation results better than the modelusing constant mobility model. Fig. 3(a) and (b) shows the compar-ison of IDS–VGS characteristics using leff model in semi-logarithmicand linear plots between our analytical model and the simulationresults for Sample 1 and Sample 2, respectively. The analyticalmodel results and simulation results are represented as solid linesand open symbols, respectively. As can be seen from Fig. 3, the ana-lytical model results are well matched with the simulation results.

2.3. Channel length modulation

Before deriving an avalanche model, we need to model channellength modulation effect. In order to model CLM, we first solve thePoisson’s equation in the saturation region

@2wðx; yÞ@x2 þ @

2wðx; yÞ@y2 ¼ q

esiðnþ NAÞ ’

qesi

n ð6Þ

with the following boundary conditions:

eox

toxVGS � Vfb � w x;� tsi

2

� �� �¼ �eSi

@wðx; yÞ@y

����y¼�tsi

2

ð7Þ

@wðx; yÞ@y

����y¼0¼ 0 ð8Þ

where w(x,y) is the channel potential.Using the parabolic potential approximation method proposed

by Young [13], w(x,y) can be written as

wðx;yÞ¼wsðxÞ�tsieox

4toxesiðVGS�Vfb�wsðxÞÞþ

eox

toxtsiesiðVGS�Vfb�wsðxÞÞy2

ð9Þ

where ws(x) is the channel surface potential.Integrating Eq. (6) over the y-direction with Eq. (9) gives

@2wsðxÞ@x2 tsi 1þ tsieox

6toxesi

� �þ 2

eox

toxesiðVGS � Vfb � wsðxÞÞ ¼

Q m

esi: ð10Þ

Fig. 2. Comparison of the IDS–VGS characteristics using leff model and constantmobility model for Sample 1 (L = 100 nm, tsi = 15 nm, tox = 1 nm).

Fig. 3. Comparison of the IDS–VGS characteristics using leff model between theanalytical model and ATLAS simulation for (a) Sample 1 (L = 100 nm, tsi = 15 nm,tox = 1 nm) and (b) Sample 2 (L = 60 nm, tsi = 10 nm, tox = 1 nm).

Fig. 4. Comparison of the IDS–VDS characteristics including CLM effect between theanalytical model and ATLAS simulation for (a) Sample 1 (L = 100 nm, tsi = 15 nm,tox = 1 nm) and (b) Sample 2 (L = 60 nm, tsi = 10 nm, tox = 1 nm).

40 E.N. Cho et al. / Microelectronics Reliability 55 (2015) 38–41

Eq. (10) can be rewritten as

@2wsðxÞ@x2 � 2

kCLMwsðxÞ ¼

Q m

esiACLM� 2

kCLMðVGS � VfbÞ ð11Þ

where

tsi 1þ tsieox

6toxesi

� �¼ ACLM ð12Þ

eox

toxesiACLM¼ 1

kCLM: ð13Þ

Eq. (11) can be solved with the following boundary conditions

wsð0Þ ¼ Vbi ð14Þ

wsðLÞ ¼ VDS þ Vbi ð15Þ

where Vbi is the built-in voltage.If we consider that Qm is constant along the x-direction, ws(x) in

Eq. (11) can be solved as

wsðxÞ ¼ k1 exp

ffiffiffiffiffiffiffiffiffi2

kCLM

sx

!þ k2 exp �

ffiffiffiffiffiffiffiffiffi2

kCLM

sx

!

þ VGS � Vfb �kCLMQm

2esiACLM

� �ð16Þ

where

b ¼ Vbi þ Vfb þkCLMQ m

2esiACLM� VGS ð17Þ

k1 ¼VDS þ b 1� exp �

ffiffiffiffiffiffiffi2

kCLM

qL

� �h iexp

ffiffiffiffiffiffiffi2

kCLM

qL

� �� exp �

ffiffiffiffiffiffiffi2

kCLM

qL

� � ð18Þ

k2 ¼ b� k1: ð19Þ

To find DL, we use an additional boundary condition

wsðL� DLÞ ¼ VDSeff þ Vbi ð20Þ

where VDSeff is the effective drain voltage.VDSeff is defined as [14]:

VDSeff ¼ VDSsat � VDSsatln½1þ expðFð1� VDS=VDSsatÞÞ�

ln½1þ expðFÞ� ð21Þ

where VDSsat and F are the saturation drain voltage and fittingparameter which defines the abruptness of the transition VDS toVDSsat, respectively.

We use the expression of VDSsat by the following equation [15]:

VDSsat ¼ ðVGS � VTHÞvsat

leff

2L ðVGS � VTHÞ þ vsat

ð22Þ

where VTH and vsat are the threshold voltage and velocity saturation,respectively.

Using the Eqs. (16) and (20), the DL is obtained as

DL ¼ffiffiffiffiffiffiffiffiffikCLM

2

r

� ln�ðVDSeff þ bÞ þ

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiðVDSeff þ bÞ2 þ 4k1ðk1 � bÞ

q2ðk1 � bÞ= exp

ffiffiffiffiffiffiffi2

kCLM

qL

� �0B@

1CA: ð23Þ

Fig. 5. Comparison of the avalanche breakdown characteristics between theanalytical model and ATLAS simulation for (a) Sample 1 (L = 100 nm, tsi = 15 nm,tox = 1 nm) and (b) Sample 2 (L = 60 nm, tsi = 10 nm, tox = 1 nm).

E.N. Cho et al. / Microelectronics Reliability 55 (2015) 38–41 41

It can be noted that the Qm value in Eq. (23) is obtained by Eq. (17)in Ref. [9] when V = VDSeff.

The IDS with CLM effect can be calculated by replacing L with(L–DL) in our Eq. (1). In Fig. 4(a) and (b), the IDS–VDS characteristicsincluding CLM effect from our model are compared with the simu-lation results for Sample 1 and Sample 2, respectively. It is shownthat our analytical model can well represent the CLM effect.

2.4. Avalanche breakdown

Initially, we start from the previous researches of avalanchebreakdown for single gate MOSFET. The total avalanche drain cur-rent (IDS_Aval) for single gate MOSFET is modeled as [6]:

IDS Aval ¼ MðIDS þ IeÞ þð1� kÞ

kIe ð24Þ

where M is the avalanche multiplication factor, Ie is the total currentinjected across the source junction, and k is the fraction of the elec-trons collected by the drain. Ie can be described as [6]:

Ie ¼ kaTcI0½expðVbs=VtÞ � 1� ð25Þ

where aT, c, I0 and Vbs are the base transport factor, injection effi-ciency, reverse saturation current and bulk-source potential,respectively.

The M is given by

M ¼ 1�Z DL

0a dx

� ��1

ð26Þ

where a is the impact ionization rate which can be approximated as[16]:

a ¼ A expð�B=EÞ ð27Þ

where E is the electric field; A and B are the ionization constants.From the Wong [5] method, the M is obtained from the follow-

ing equation

1M¼ 1� A

BðVDS � VDSsatÞ exp � DL� B

VDS � VDSsat

� �: ð28Þ

In the previous researches for single gate MOSFET, Vbs in Eq. (25)was obtained by fitting the substrate resistance (Rsub) [5,6]. How-ever, in our work for DG MOSFET, we replace Vbs in Eq. (25) withthe center potential (w0) because we assume that the DG MOSFETis formed as two single MOSFETs, which are back-to-back con-nected with each other based on the center of channel. This meansthat we have two current paths of Ie. From the concept, we alsomodify Eq. (24) for DG MOSFET as

IDS Aval ¼ MðIDS þ 2IeÞ þ2ð1� kÞ

kIe ð29Þ

Here, w0 can be obtained from our previous research [9]. The Mvalue is calculated from Eq. (28) by inserting DL value obtainedfrom Eq. (23). Using the calculated M value, IDS_Aval is calculatedfrom Eq. (29). The calculated M values decreases for the same VDS

when VGS decreases. Fig. 5(a) and (b) shows the comparison of theavalanche breakdown characteristics between the analytical modeland the simulation results for Sample 1 and Sample 2, respectively.

3. Conclusion

In this paper, the proposed analytical model of the avalanchebreakdown characteristics for DG MOSFET was presented. At first,we replaced the constant mobility model to leff model for our pre-vious drain current model. Then, by solving the Poisson’s equation,CLM parameter and DL was obtained. From the DL, M was obtainedand used for the calculation of IDS_Aval. The results were comparedwith commercially available 2D numerical simulation. It wasobserved that the analytical model well represented the 2Dnumerical simulation results. Therefore, the proposed avalanchebreakdown model can be applicable to the compact model of DGMOSFET.

Acknowledgment

This work was supported by the IT R&D program of MKE/KEIT.[10039174, Technology Development of 22-nm level FoundryDevices and PDK].

References

[1] Taur Y. IBM J Res Dev 2002;46:213–22.[2] Taur Y, Liang X, Wang W, Lu H. IEEE Electron Device Lett 2004;25:107–9.[3] Masuda H, Nakai M, Kubo M. IEEE Trans Electron Dev 1979;26:980–6.[4] Toyabe T, Yamaguchi K, Asai S, Mock MS. IEEE Trans Electron Dev

1978;25:825–32.[5] Wong H. IEEE Trans Electron Dev 1995;42:2197–202.[6] Young KK, Burns JA. IEEE Trans Electron Dev 1988;35:426–31.[7] Reddy GV, Kumar MJ. IEEE Trans Nanotechnol 2005;4:260–8.[8] ATLAS user’s manual, Silvaco International, Santa Clara, CA; 2008.[9] Cho EN, Shin YH, Yun I. J Appl Phys 2013;113:214507.

[10] Arora ND, Hauser JR, Roulston DJ. IEEE Trans Electron Dev 1982;29:292–5.[11] Diagne B, Prégaldiny F, Lallement C, Sallese J-M, Krummenacher F. Solid-State

Electron 2008;52:99–106.[12] Lázaro A, Nae B, Moldovan O, Iñiguez B. J Appl Phys 2006;100:084320.[13] Young KK. IEEE Trans Electron Dev 1989;36:399–402.[14] Lime F, Iñiguez B, Moldovan O. IEEE Trans Electron Dev 2008;55:1441–8.[15] Iñíguez B, Moreno EG. Analog Integr Circuits Process 1997;13:241–59.[16] Chynoweth A. Phys Rev 1958;109:1537.