AmSSCggAEnhanced SC$l.Bu$ lnterface Gontroller ;

FIAdvanced

MicroDevices

DISTINCTIVE CHAHACTEN|STICSI lrrplemonts full SC$l bus features: arbitratbn,

d iscon n sct, reconnsct, parity gene ntio rVc{redringon both data ports, soft reset, ard syrrchrotsusdata transfers.

r Synchronous offset sefe(*abJs from I lo l ? bytes,wlth selec{able trensfer period up to 5 Mbyte#s.

r Cornpatible with npst microprocessors lhrough anS-bit dsta hrs; supports both ruulfiplexed ard non-multplexed addre$s/data h.ls systerts. Host busdata parity checking and generation is an opti,onalfeature.

r Can be used a$ a ho$t adaper (SCSf Inltiator) orperipheral, adapter (SCSI Target).

r Data transfer options include programmed l/O,single-byte DMA, burst (multibyte) :DlVtR, or directbus accees (DBA Bus) transfers.

I lrrcludee 48-rnA drivers for direct connection to theSCSI 'bus,.

r Burst data transfers up to 4096 bytes.r Programnrable tineout for selectbn and

reselection.l "Combinatbn' coramands greatly reduce intemJpt-

hardling responslbilit les.I Special 'Translate Address'command performs the

Logical- to-Fhysieal address,transf atbn..r Sirqle +5.V sumly.

t Available in 44-pin chrp carrier or 40-pin DlP.I Low power CMOS design.

GENERAL DESCRIPNONThe 33C93A is a MOS/VLSI device imptemented inAdvancod fvfbro Deviees' CMOS prccess. lt operatssfrom a single 5-Volt supply ard is avallable ln either a44-pin chip carrier or a 40-pin dual-in-line package. Allinpuls and outputs are TTL compatible.

The 33C93A is intended for use in systems whhh inter-face to the $rnalt Gompter Sy$em Interface (SC$l)Bus. The 33C93A can operate in both the initiator {typi-cally, a host computer system) ard the target (lypbally,a peripheral device) SCSI hls roles.

When used in the host system, the SgCgOA interfacesto both the ho$t bus ard the scst hrs. To perform aSCSI operation, the host prw-essor issuee a somiilandto the 33C93A to select the desired Targel. The33c93A thsn ait$$ates forthe scsl hrs and selsc*s theceripheral uRit. lf it fails to g,gt the bus becauee ol aCevice with hfiher prbnty, it continues trying ard rcti-'ies the host when it has succoeded by gengrafing annterrupt. At this point, the 33C93A is operating in thenitiator rols. When the periphsral requests a SCSIrcmmand from the host, lho 33CggA receivsg the re-quest and generates another interrupt to the ho$t, Thercst responds to lhis interrupt by issuing a "Transter

lnto" command ard supplying SG$l semmand bytes tothe 33c93A. The 33C93A transfers the SCS| comrnandto the perpheral, ard then waits lor the next bus phaserequest. This prooos$ cor$inues until all $CSl irrfonna-tbn includirq data, status, and messages have besnlransferred.

Ths 33G9-3A also offers high-level Select-ard-Transfercommar,ds which eliminate the interrupt hardling otlrer.wise requirod between each SCSI bus phase.

When the SBC93A is used in a peripheral system, theSSOggA witl operate primarily in a Target role. lt inter-f*cos wilh ,il bcal proces$or and the SCSI bus in thisenvironnw$ iust aS it does when used as a hostadapter. The Target-role comrnard set enables theSgC,SSAto request each $C$l bus phase individually orto ssqrsnce the SCSI bus phases automaticailythrough the uee of combination @rnmands.

ThelSSCSBA has an internal mbromntroller, a registertask file, and SCSI interface logic. This architecture$uppoft$, hth tiglxt control of the protocol for rton-starldard SC$l implernentations, as well a$ a hands-lree mode for standard $CSl applications.

}.ffcdirn t118gt' F.{L A ln rilcfiro

crp Odc: Juno 1S

*m&reff}A

SI,$SK DIAGRAii

IntsrnafBus

$c$lBus

cs

m, TvE, D7-Do, Dp

DRO

n\cl(

An$3SSA&3r

COTINE 'OnqR*SfSl5r':i'l'+r'ir

*rhPIH CHIP 9ry'iEn

G}ID

ffisD6

(HALr)

sD5

si$D3

ffiGND

S-rffi

SEL

cu(DRQ

-....----DACK

DP

INTRO

DO

ol

D2

Dg

D4

t8 ls lH'$� lHNots: Ping ln parentheseo,sl|,br'te*t purpw on$, ard should bs left unmnnocted for mr,rnal chb op

E t q 96 0g

BB Slgrs a$lH, lU{E s6 5 4 3 2 | 4 4 l { e 4 1 4 0

T o g g

388

97I

10 38

11 S

1 2 : 3 4

1A . 3Hl

1 4 s

15 91

1 6 S

17 29s19 19 20 z'�t U 23 24 ?5 e,6 27 28 ./

4&FIN DIPtffi

msc---+

GND-e4ffiffiiCLK6m

EnffiNTrc

DOD1D2D3D4D5D6v7AO

GND

vccNFTffiATNsffiGNDsD7sDsffiffiffie5DnGf\tDs01sD0SFALEffiWE6

lr 40

10 9111 301g 20rg e81 4 ' 2 715 261S 25\7 zrt18 231S 2n20 21

fimeffi*

ORDERING INFOHMATIONstandard Productg

.^!,^r-,^ :- ^^. -AtttD standard produc{s are availabb in sewral packages and operating raRg6s. The order number (Vis formed by a combination of: a 1levbe Numberb. Speed.Optlon (if appllcable)

'

q. Package Typcd. leqperatlrre Rangee. Optlonal Proceselhg

Atf33C93A -2A J C

e. OPTIONAL PROCESSNCBfank . Standard procossing

d. TEIIPERATURE RANGEC - Comrnercial (0 to+70€)

c. PACKAGE WpEp- 40-Pin Plasric DtP (pD O40).; - 44-Pin Plastic Leaded Chlp Carbr

(PL 044)

b. SPEED OPnOill-16 - 16 frrfHz*20.20 MHz

DEVtCg tl UItfB E R/D ESCR|mONAm33C93A

Valld Comblnatlons

AMg3C93A-16JC, PC

AtrI$CagA-20

ValH Comblnsfonc :

Vafid Combinatiolq.llst co$qqptbns planned to be supported in volume forthls devb. Consult the focalAuO sateso*ice to confirm-iviii"niiity "iliijirtvalid corn,binations, to check on newfy relsassd comUinaidns, ari,l to irt*airradditbnal data on AMD'g standard mil,-itary grads proouctJ. -

4 3 f AmStCgSA

PI}I DESCRIPTPNS

PrucaucurlDf A'. lntsrfa&Hrlnr l/o Functbn

CLK

frH

INTHO

AE uo(TRt€rnrel

VfE vo(TRI-STATE)

f f i l

ALE

DEEK Uo1Rffil (oPENDRATN)

Effi, u0(DRQI, {OpENDRAfNI

D7*D0 b0

DP 1,{}

o

8-20 MHz $quers nreve chck .

Reset b an active-loryy input whkrtr forces the 33Cg{tA into an kile state. All SCSI s[nals are forcedto the negated stste.

lntentpt Rcqueet to external mbrryroceemr indietes a sorffilsrd oompbthltermln*bilior aneed to servb the SCS| interf*e. Reading the SCSI STATUS rggbter dears this bit.

ReB�d Enable ie an astive-lqr irput s'fiFft b used nmt ffi'to read,s rsgbtor or wilh DTCRto {oos-ssthg DATA registor ln DMA rnoda. ln DBA Bus mods, lt b uEed as an ouFut to read dsta frorn Eesdor buffer.

Write Enable is an .a{iy-grlow input wJrich p ueed w}th 6ts wrlte a lggreter or with DTERu Wqthe-DATA rqister in DMA mod;. h DBA Bus mode, it is ueed ee sn d.lttrfi to wrfte date to e *sctqrbuffer.

Chb Select b an ac'live-low input whictr qu{ities_nE and VFE when accoesfig,,& fagisrrr,,....Wsfnal must be lnacillve during a DMA cyde 1ffi wtbq in D[fA end Burgt DMA rude, Er fifiilrctivo in DBA Bus rnode).

Address pn A0 is used to rccess the intemal registers lor non-multlplexed ddress/dda bus(1.e. the ALE pin b groundedl. The addrees of the dee$i€d regleter b hdsd into ths AffiAESSregisterdurlng a write cy'rSe with A0-0. Tho ael€d-€d regibier b thsn mespd wlren rd0-l,

Address Latch Enabte is used tor multiplexod ddree,sffafe bus to bad the ad&eee of ths desir€d33C93A register from the dala bus. il indirscf addressing b b bs us€d, the ALE pin shouH begrounded. Ses thg descriptbn of ths AODRE$S ragietor,h E mnplso dis€r*ssbn d dirw{ ardindirec{ addressing.

gffi-d.nowledge input used for intefiacing to an exlernal DMA sfiroller te€. 8834. WhgnSfr,6R is bw, all bue trandere are to#nm t[e DATA rry$*ter regardhss of ths'snter$$ of ttrsADDRESS regi$er. ln DBA 8us mode, thispln furdbns as a RAM cfrip selest ouprt ts altnr thegitcgs to amess a socilor buffer. HE frnd WE are outprrts when'Fffi FAsr chp $elect) is af,*hm.Sinee this pin can be an opgn druin 6ufput, a pullup reEistor may be roquired urtren operating i,n

D*tr rsgueat b en ouput when intedacing b ar sxtsmEl DtlA contlg!:bLand nn irput when in AMBus rnode. When ussd with an extsmal DMA ontro$er,,ffi ard DIER |onn ttp ha;drhrke lorthe data-bytstransfe*.,kt Burot rRode, EFE rerrrsins kfril as bng eothere b date,b traru{ef" ln *MBus mode, thg SSggg{SlMrns burst $ans5l wh{1SRA is h[h, and whgn Src is blr, dateffanslere are inhibited, BCS b fals, and lho nF and lt{E outgns cre disabld.,sne thie pln c*nbo an op6n drain output, a pulhtp rasbtor rnay be required when oporating ln DfrilA or Burct rnode

Processor data hrs.

D$a Perlty, ussd or$ fcr cfitcklqglssnsrrating Far y dudng 6ol* tranglers

AO

SGSI lnterface

lro Func,tbn

rTfr uo

uo

uoC,D'

Tffi

mffi

Ifffi-io qn outpr* in the iniikior rele end an lngn in thn larget mb. li is us€d to irdlcate thsATTEI{TON conditbn.

Iffi is an outprrt in the iniihtot rolE and an input in the larget rob. lt is used to irdicats Enacknqwbdgertent lor a REQ/ACK data transfer hand*hqke

f is an input ln the initidor rob and an output in the taryet role. lt is asserted during aMESSAGE phase.

CO is an i:nput in the initiator role and an output in the target 1016. lt is used to irdicate wh*h*CONTROL or DATA inforrr,rEtion is on the $Cgl data bus.

HE6 is an input in the initiator rolo and an output in the target role. I indicatss a requetlor a REQIAGK data transfer.

HE.6 vo

tnrffi* ikl|fi

$CSl lnterface (Cont)l{anr UO Fune&r

bo

sE'GsD'7SDP

ffi

vo

voyo

uo

b('

BSY

16 is an irput in the initiator rcle and an output in the tflget rde. lt controb the dkectbn d datamovem€nt on the scsl data bus with reopect to an lniliator.

SCSI data bus.

SCSI data bus parity s[nal.

EW is asserted when the 33Cg3A b attemptirg to albtr*e lor the SCSf bus or when conneaedas a Target.

SsssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssI is asserted when the SICgBA is afernsing to sehct or ressleci another SCSI dwb.

fiX***********************************************************************************************************ofe; All pins have open4rain output drivers.

AmSSCSIA REGISTERS

Reglster MAP

Rt/w Reglster AccesscdAddnrr(HEYI

Rw

RWR/WR/WR/WR/WR/WR/WR/WR/WFUWFUWRtwR/WRtWR/WR/WM,1,R/WR/WR/WR/WR/WFUWR

R/WR/W

AUXILIARY STATUS REGISTERADDRESS REGISTEROWN ID REGISTERCONTROL REGISTERTIMEOI'T PERIOD REGISTERTOTAL SECTORS REGISTERTOTAL HEADS REGISTERTOTAL CYLTNDEHS REG|STER (M$B)TOTAL CYLTNDERS REGTSTER (LSB)LOGTCAL ADDRESS (MSB)LOGTCAL ADDRESS (2ND)LOGTCAL ADDRESS (3RD)LOGTCAL ADDRESS (LSB)SECTOR NUMBER REGISTERHEAD NUMBER REGISTERoYL|NDER NUMBER (MSB) REGISTERcYLINDER NUMBER (LSB) REGTSTERTARGET LUN REGISTERCOMMAND PHASE REGISTERSYNCHRONOUS TRANSFER REG]STERTRANSFER COT NT REGTSTER (MSB)TRANSFER COUNT REGTSTER (zND ByrE)TRANSFER COUNT REGTSTER (LSB)DESTINATION ID REGISTERSOURCE ID REGISTERSCSI STATUSCOMMAND REGISTERDATA REGISTER

rcDB SIZE

,CDB lST,CDB zNDICOB 3RD&DB 4TH'cDB sTH,CDB 6TH/CT}B 7THICDB 8THICIIB 9THrcDB loTtl,CDB 1lTHrcDB 12TH

xx)fi0001a203040506070809OA080cODOEOF1 01 11 21g14151 61 71 81 9

ffofe8.' l,

2.

Afl unused tits of a deflnd register are rcserued aN must fu zero.

Reading an undefined or unavailabte register resurfs in an all+lnes data bus outrlul

Rqistor addresses are determined by the ADDRESS register bits ARTthroqh AR1.

Wlen using a multiplexed address/data bus with ALE, the AA pin is igrwrd and the ADD1ESS registerwith ALE. ln this mde, the AUXILIARY STATUS register is mapped-at hex tF.

See Page 14 for a description of how reset affects the internal registera.

i;

1li

4

rf

{.38 Am3{893A

'i*\-*\g,;:ii;i,

Regl*ter l}iffi crlptlons

AUXILIARY STATUS REGISTERSThe AUXILIARY STATUS register is a read-onlyregbter which contains ganeral status informatbn rptdrsctry associated with the intemrpt mndition. The

AUXILIARY STATUS rryiSer may b? aFessed at anytime, except during DMA accessss (ffiR asserted inDMAEurst npde or DnQ as$erted in DBA bus u}.

0

DATA BUFFEH READYPARIW ERROR!,fot UscdlSt U$edCOI'IUAhD N PROGRE$S BUSYBUSYLAST COMMAND ilSNOREDINTERRUPT PENOI}€

. lt's$sl* ,

Btt ilame De*rlpton

DBR

PE

clP

BSY

LCI

DATA BUFFER READY is ussd durirq prcgrammed ll0 ts lndicate to the processoiwhstheror rpt the DA;[A register is available for ruadirg or writing. Durtng Send or Transfercomrnards which transrnit data over tho SCS| bus, the DBR bit is sel when the 33G93A isredy b tako a byte from the tpst; the bit is re6et when tho prooessor writes the byte to theDATA register. During Receive or Trsnsfsr com:mands which recelve dats ovsr ths SCSIbus, the DBR is set when a byte is recelved;',ft ie r€set when the procassor reads the bytefrom the DATA regisler.

PARIW ERROR status irdicates thet ,u,onpfirity was detecfied on * dda b$e rec-eivodduring an intormatbn transfer, Parity is checked on data reseivEd from the b$ bus furingtranslers out to the SCSI bus ard is cheslffi ori data,reoeived frurn the $OS] bus drnr€transfers out to ths host bus. Detection of a padry erTor will set the PE status bit regardless olthe state of ths HHP or H$P bits ln the COfiITftOL register. Tlls PE bit is clsarsd when a newcommand is issued.

GOMMAND lN PROGRESS, when sel, irdicates that the SSGggA ls interpreting the tast@mmand entered into the' COMMAND regflgtsr ard therefore this regisler is unavailable.tfilhen this bit ls reset, a sn1land may be written b the COMMAND reglster

BUSY indbates that a Level ll commard l$ ,cunently execrrttqg ard rtherefsre onfy theCOMMAND regislsr {when CIP = 0}, the ,'[i$TA regiiter, and the AUXILIARY STATU$reg,ister aFs 'aoceasibfe ty the host. A LEvel ll cornrnand r€y rpt,bs written lo thsCOMMAND registsr whoathis bit is one.

I-.AST COMMAND IGNORED irdbates that a comrnand was issued by the fp$ iust prior toor @ncunent with a perding interrupt, ard therefore the @mmard wlit be ignored.

INTERRUPT PENDING indlcates that ths INTRQ prn is assefied. The host should read theSCSI STATUS register to clear INTRO prhr to issuirg any commaruds.

INT

AmS$ffi8^ 4"$?

AOORESg NE$STEHThe ADDRESS register b a writeonV regbter whbhffintains the add,ress of ths registor to be accs$sod.Regi$ers in ths 33cggA may be messed in one of twoways:

. Direct addressir€ {nnrltiplexed addresydala hrg-ses). In direct addressirg, the fallirg e€s of theALE sfinat is used to fatch the addrus ifito thsADDRESS register. The A0 pln shouH be con-nected to grounc when ueirg thb meilrod. The ALEis typbally then toltowed by the F aruC WE or FEsQnab that access ths selected register, Alm, lndirect ackfressirg, the AUxtLtARy STATUS regis-ter is bcated at address lF hex.

. lrdirest addressing (separate address/&ta bus-ses). In irdlrect addressilrg, the regisler access isperfornd in tws separde cyctes. This mettprl isenabled by dtachltlg ALE to ground. First, theADDRESS register is ba@ by perforfniqg o writeof the desirsd address to the ggCggA tWE-anC CSassertedt with-A0-0. Thsn lhe register is amssedby assertirq 6 and WE or FE,-with AO-t A|so,fofftnrtirq svsry access wlth A0-1, fiE ADDRESSregisler wlll automatically increment to polnt at the1ten register, yuith the exceptlon of the folknvirqhcatbns: AUXILIARY STATUS regbter, DATAregister, ard the coMMAND register. fn lndirectadcfressing, tho AUxtLtARy STATUS register isaccsssod by pertormirg a red (eS and HEassefted) with A0=0.

owr{ tD/cDB $tzE nEGSTEnThe owN IDrcDB slzE register, in its firct mode, oon-tains botb rhe e@ to 6t ne 33c93A on lhe sCsrbus and several @rtrot bits that are used to initiellycort'lgure the dwbe furirq the "Reset' comrnard.These bits mntrol 'advarrced feature' selectbn, hosttus panly enabb, ard selection of the divlsor for theinprt cbdc fn ile $eoord rrnde {when danced fea-tures are enabfed, seg B.io), this register is used durlrqthe eortbinatbn cornrnards to seecify ttlg scsr cDBsize if tho onilnard grqrp is urkrpurn to ths gitcggA.

In the first mde, this register (as defined beron) issarrqiled and bgcomcs effective only after a "Reset'commard b issued to the devbe. This register must bslnitialized, ord a "Reset" command rnrst then belssued. Doirq lhis will set the Scsl bus lD, the cbckdivisor, ard operatirq modes before arry otfer @m-mards are issued.

ln the second npde, bits 3-0 of this register are ussdduring the setect-and-Transer aruc wait-for-selectsmrnards to specfy th€ scsl Gomnrard DescrlptorBlock size tr it b r,pt ,a g1otfp 0, group i, or group 5cqwnard. This nnde is er€bfod only when advarpedfeaturse aro ef$hd tsae p.16).

lD bir 0lD bi,t 1lD bir 2Enable A&anced FealuresF-na!!e Host ParityNd UsodFREAUE}SY SELECT OFREQUENCY SELECT I rrE6&tEA

grr Name DesrlSton0-2 lDn $CSl lD Bits &2 set lhe SCSI hrs lD nunberthat the 33C93A will use durirg arbitration ard

selectbn.

ENABLE ADVANCED FEATURES, when set to one, causes the 33CggA to enabte ceilainadvarrced features (see Page 16). when this bit is zero, those features are disabled.

ENABLE HOST PARITY, when set to on€, enables @ parlty checking on the host bus; thsPE bit in the AUXILIARY STATUS register will irdicatd parity enors detected on the hostbu8, and th€ HHP Ht in the CONTROL register will be used. When this bit is'zero, nochecking is performed on the host tus;ths pE bit is not setwhen a parity error is detected onths host hs, and the HHP blt nr.lst be set lo zero. NOTE: Parity is ahrays generated on thehost data parity bit (DP), regardtess of the stato of this bit.

EAF

EHP

{-38 ffi3WSA

Btt Nurc

F$nv7 FREQUET'ICY SELECT 0-l selsc{ tha dvisorlhat b a#ed u ttu il4lut chctr. T}p resrftirgcbck b tsod for dgta trarilstsr timfq srd br $SSl hti arffiratbn timir€. Ths tablg beb;9ftryE input qpd( trequsney f8lp6$ ar-d the currceporwrg,,ff{rlsor8. d'gorrw cugErtorthe lrPut slod( t$rsil bo usd, cr SO$l bus,t*nfu ry,ootrbatbrs,nf,ry fFt be gl€il.

FIPUTCLOCKFREqUENCY

Gfl,{I) F$l Flso

8-1012.15f g-20

11

NEgULTilITIDilVTg(H

0 00 11 0t 1

esI :

U r e d

,Wtp tlffi an ,t MI$Z alcxJ( ru$e Efiputr rp$ &, ssd, ss ffiefrsu*frW S6$t bus dgErdg/€ly trry rribHc$6gf,Wdth$ftns,Tln u1y166 fw oonryrtfuryd,lc alnrenrrn ses, dafi fra,rsf,grr@fit;

lrtratirnum $CSl Transfer Rate -krput Clod( Fequeruy

Clooft $ivi$Er, lt r8scl

CONTROL REGISTERThs COf-{TR*.tgSgr is taed to enabl€fdls#s certain furrc{bns, such as rsspons€ to parit}attentbn wffibn;irfiernrfl rraruffq, ;rfi;t"ir""tfo npdes.

' - rY'se' rr'!'f't"''

HALTm SC$I.PAR,IWERffiR , .HALT on ATTENTION]ilTERMEDIATE DISCONNSCT INTENDING DISCONNECT IHTERRUPTHALT on HOBT PAHIW,ERRORDMA Mode $elecf blt 0DMA tvlode Select,bit 1DMA hrbde $Els€il bit 2

HA

T'hg HALT on SC$l PARIW EfiROR tst enaWu th* SIlCggA to iriunediatsty tsnrltnds Ifrmfue orTransfersrnrnarld:ff,aparity'orcr,}$ dot A on an irroonifig SCSIdata by{e. lnrtle tnirtator rote, terminatbn fte ts 8 scqt Bf,rity oqq cquss tm laR"sn to bs tsftin tfFdlvs state in order to hhhl.rnf,sddilblraf data tranefers tREOs) ty tttr frygor; thisfacilhates error llnotit€ witl the fargot. Svffi* data tlansrers chedr Barny ev€ry4@6 bytes, or at the end of ffia rernainirq transfer @unt, wfrficfrwer ls lees. Aglyrp#orpu;tfirneilers check pari$ on sr$ry-r$1to,. ' :

Ths HALT on nTTENTtOltl'hn fin6* rmoe only) o-nebbs tho a$cggA to tsffiinets aSend or Receive comrnand if the ITfr inp.rt is as#hed- TG **rv ittdbd;r n*-tntIniliator detected a parry ero{ while receivir,q dAa fis{n the 3$CCAA: fhs ffi irp,fr i;tsstd bobre the Sart of a data transfer, every CmO bytes il ths transfetcourtris gr".ifd;4GlSf ar$ etter the ed of ttp transfer. ThE$s rutes appry to both syrphlbrpt s ardasymfmrnug transfers.

The INTERMF!$IE DISCS,INECT INTERRUPT bit, wfien set, enables tm gftCgSA toq|Tot? an 85H ift*p! .tnd -*t{ele^ a Selec{-ard-Transfer. @mrnand if the Tarrytdismnnects acmrclirq to the delirred SCSI protocol. When thls bit is reset, rrr lrterrupi-ngsryr.qlsq !y a,vattd i'isognnsct. This featurd, when ussd wtth td RJs#il bffi ffi*i"[*i[ptsyHsu ry fdr. overlappod SGSf operatione, fDl b also $s6d to selec* cxocutbn$tpm,inTfrffi Cormination cornmards that servo to redl�m froat $yutgrfi orcrhead.Bsfer ts GS$uAI{D$*.p.lE for rnore dstaifs.

IDt

&lH.'

Btr Hame Descrlptlon

EDI

HHP

5-7 DMx

When the ENDING DISCOI{NECT INTERRUPT bit b set, the rOH intemrpt urhidr rnrmasyfolbws th$ COMMAND COMPLETE message drirqthe exocutbn of a Sefecl-ard-Transfar@mrnand will be suppressed until the Target disconnscts lrom the SCSI bus. EDI is aFoused in the Target npde Combination commards to ersle chainirq between tt6se@mmaruds, resulting in reduced host sySem overhead. Referto GOMMANDS p.ts for moredetails.

The HALT on HOST PARITY ERROR bit enables the glGg3A to immediately terminate aSerd or Transfer @mrnand lt a parity enor is deteded cin an incomlng hoS data byte. Hostparlty ono18 are c{red(ed amrding io the rules for ched(irq SCSI parily srrors. Hqrwer, ahalt on a hosl panty eror will rpt hold the Am sbnal assorled when an emtr occurs. Fbstparity checkirq is perfonned at the same intervals as SCSI parily checkirq.

DMA MODE SELECT bits 2-0 ars used to select the DMA ntode ol operatbn, whbfrdescribes the host hrs trans{er mode used durir€ Data In or Data Out phases. The folbwirqtable describes the diflerent DMA rTrodes, ard the stale of these bits to select them:

D[t2 DMl DHO DfnA Hodc $lqotod

[:";,,: i:]-.

i..{i.'':

POLLED MODE, or no DMA en$led, All date phase trangfers ereperformed by polling for DBR in the AUXILIARY sTARts regbter, andthen writing (roading) rho data to (from) the DATA rTpter.

BUB$I!,|ODE sektE a demand_ node DltA inrerfee. ln thie mde,the Dffi sgnal witf bo rerive as bng as there is atJ;pr* fi-fr;intsrnal FIFO to allow the transfer to,csntinue. The DtlA eorrtroltiirosponds S asserting ffieRand HEfrilE as bng as Dffi is mrtve.

DBA tsus lrroDE is selecled when the ggcggA ie mnneEted to a DBABus. This modo also can be callod Direct Buffer Access (DBA) mode. Inthis mode, the 33C93A asts as a bus master, and all data'aee'ss s(lnalsreverso their directbn: The Emouput signal becomesthe DRQ iitput,whbh enables the 33C93A to driye ![e buffer bus ontrol signals. ThoD7reRouput s[nal beomes the EG input, which is assertd as a dlipselect forthe buffer. The RE and WE inputs beome outputs *'hbh drivethe read and write fundbns ol the RAM buffer. As long as the DRosignal is asserted, transfers will continue in a buret mannsr, until the!S$er is emplote or it decides tq pause the transfer by negdlng theDRQ_glgna|;gne mo-re transfer may occur after thb transltion, ard thsnths DACK, RE, ard WE sk;nals are negated.

DMA ftloDE is eelecied when the slC93A is to be usod wilh a DMAmntrolfer in eingle-hile transfer mods. tn thb mod€, Dffi b aEs€rtodand !!gt nggtd, ond the DMA comrofler responds by asserting Dffi-and wE or RE,lor each data byte transferred,tofirom the fflcg3A

TIftiEOUT PERIOD BEGISTERThe TIMEOUT PERIOD register is an B-bit registercontaining a preset value which determines the timeoutporbd for Selsct and Beselect commards. This valuemay be cafculated as a furrction of the input cbcA fre-quenoy ard the desired timeout period, as shown in thefolbtvirg eguation:

registervafue= 4E![80

Where:

Tper * The desired timeout per'rod in millisemrds;

Ficlk = The inpt cbd< frequency at the CLK pin inMHz (with no divisor applied).

The constar$'80' scales the units of the equatbn, as isbased on tho intemal timeout cycle time. Th€ ussrshould round lhe resultlng 'register valus'up to the nodintograf valus to ensure that ths usefs mininurm timeoutreqlirement is met.

The tirneout perbd specifies tprv long th€ 38C9$A willwait for a rsspon$e (indlcatsd by asserlion sf $rs EWg]ggafl aftsr '$$t

@$gun the selection phaso (aesertsEL ard n€gate BSY) before terminatrng tho commard.The tirneout furption can be disabled by loading theTIMEOI T PERTOD register with zero.

NOTE: The foltowing twefu regbters arc u*d exclusivel bythe Tnnslate Address andfur 'nmbination' &m-mendrs. Tftefurr/rrrn of e*h register is ddennined byths tyry of oomnand rbsuad.

4'r*0 AmgltcgsA

TOT'AL SECf,OR8, HEG:IfITER/CDB r ST BYTEI'randats d#ressj Tho- TOTAL ,S.ECfoH$ Jqffiaretpuhf bo $st to ffi |oref mrmbr of egctOe, perlra*prbr to issuirg a Translate Affiruss mrnrnard.

sssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssls6f-arrc-Transfsr: Tfrb regrister sfu.rH be badodwilh tfts firs,t brle of ttu couuAND DEscRtproRBLocK bebre bsuirg a sefect-ard-Transfer ooril-manil.

wait-tor-sbcf-ardl*wvllve;ThaggcggAwillstorethefirst htto ol tte rec€ivod CDB in thils register.

TOTAL HEAI}S REGISTER/CDB 2ND BYTETnnslate A&ress;This reglster tpltfs the total nunberof heads during a Translate A*fress commard.

selocf'ardrmrwfar: This regl$er slpuld .b6 badednlth the sffind-byte of ths cDB before lssurng aSetec{ -arsTransfer ffi mfiEnd.

w ait- tor-.$e bct-a i# R ewrvs; The slcslA will store thesemrd byta of the received CDB in this regi$er.

TOTAL CYTIHDEN$ NEG|$TEN€DBSND AHD {T.HBYTES??anslab Adresr; Thfu is a lsbit regi$terwhich hofdstlm total rrunber of cylinders.

$ol66t*c/x/-Ira4sler This r,egi,ster efpukl bs badedwith ths third ryd fsurth bytee or trrs GDB befsre issuinga Selsct-ard-Tranefer command.

wait-for-Sietect-a r#Rectlive.: The ggcggA wilt stoiethe lhird aruil founh hftes of ths received cDB in thisregister.

-

logLqAL ADDRESS REGTSTER/CDBBYTESrranrilaf,s ,{qs;6gs; Ths t6GlcAL ADDRE$$ ro0istsris a St$lt ruSffiter whhh uturftf bs ba&d wilF fi,.rsbchal sddr.6ss ,to be transfatod prbr lo issuirq thsTrglel$0 Ad$s8$,oonrnerrd.

-

selact-ad-Tratlsfer.'For six byte cDBs, only the firsttuD bytes of thb register sre 6aded witii rrd mttr ;*dsixth bytes of the GDB. For ten ard twelve byte cDBs,thb register b loaded with the flfth, sixth, seventn, ardeSHh Wtee of tfp CDB.

waft-for;&&f-snd-freaeftru: Ths,' $3csg A wilt store theflfth, thdh, seyBnth (if any), erd $bhth (if any) hyteo ofths rscstusd CDB in thb rogleten

SE�TOR IIUT$BEfi NEG$TEA/CDB gTH EYTEr/imsafs Affress; Thls register wllf conlain thoresultirq sector nurnber loflowing a Translate Addresscommarud.

setrct-arfr-Tranefer This regi$er stpuld be badedwith th€ ninth blrte of a ten oi twetve byte cDB beforeissulrq a $eled-fird-Transfer @mmanC,

Wstl-fe7$eh6t-61l&�fieoejya;t,'.fw $il.st *:.wntffi byta sl e ten or twatue qfio r lvd eng ft,thi*,,registar.

HE*D $Uil8,FR RES$STEFIIB$B t0T]t BYTE ,,rransfinfs *dl''ss$ TtB HEAD NuliBER,,rqls[er ffilrtains, tha r€ u[ing neio rnrr&er tglle$irq {rransssAddress cornrnald, ff ,sutormsc eerrpaneEtbn forspare geators oR il, dlsfu ie to bE peffuf,ff*d ry ffB|rnryCg3A, tfpn ths rurr,&r,d,spafiB perc$l*. ,der ilurst be wrltten irrto this regicter hfore bstff$,sraTranslate Address commard. lt shoukt be rp-tedttratwhen @rnFnsatbn b used, the rnaxinu,lm nunber ofcylffiers allqiled is 4096, andthe ma<irrurn ru,nr6erolhsads is 15. An initial value of zero in this reglsterinillcates that no compensatbn is to be prforned

selacf-ardrrarwfor: Thi$ regieter slulH bs,,@lswith the tenth byte of a ten or fiffclve byte:,GDB ,:issuirq a Selsct-ard-Tra ngfer eomrrrand

' ' ' .wafi-for-iseltrf-erfi *F,gcgft €;T,,hs,g3c:slAwillsilolp.splenth byte ol a ten or,tnrshru hrta rrce*rred oDB ln,Slb.,,r o g i s t e r . , i , ,

CYLINDEH NUTfrBER REGISTEB/CDB 1TTH A}ID12TH BYTESTranstate Affiress.'The CYLINDER NUMBER re$Seris a t &bit register tuhictt oonains ths iesu-ning oy-fr*#

'

rrumber following execution of the Translate Addresscrmmard. when a Translate Address @mmand lrnfou-irq automatic conpensation for spar€ sectors is issued(i.e. the HEAD NUMBER register initiaily contains anomero value), then this register,muet bs loadd vstthtotaf rulnsor ol eesb$'per cylindor {totsl eect.rsftfask .total heads - totat spari sectorsfcyt) aeore lssuirq necommard.

setect-a#-Transfer: Thb register sfprrH be bd6dyfi|rrthq glqrynrhSnd rwelfth qnes of atwetw,byte,soBhfore issulrq e Sebot-and-Transtar commant.

wait-for-sbfect-a rfr-Recerve:The g3cggA wilf store theeleventh and tweltth blrtes of a twehrg by,te rsceiuedCDB in this regtster

send-sfafss-ancf- cornmad-coftFtete: The cDBt lrqglt ie us6d tg sp6c{y tho rcil@ Bfistiis'b$e io ue$Or* *trifL a $erd-Stahre-ar$.Co grrnnf"cornrnard, The CSB{a rggiefer ls ussd to Ceterminl ure!q? _ol 9g**"rd-Conptere rnsssage senr by UE33c93A. lf bit 0 ol the cDBt2 reglster is sot to ore, thena linked commarxl Gornplele message wifl be sentdrrirg mmmaru,sxeflitk)n. ln this case, bit I of |hecDtsfa regis{€r is'' used a$ a FI-AG bit to detenr*rewhether a 0A hex (FLAG=O} or a 0B hex (FLAG-1)Linksd comrnard cotrptete message is sen[: r bil 0 6zero, then a simple csmmarrd conrpbte message (fi!hex) i6 ssnt.

AiltStG$ilA +fr

TANGET'LUN REGISTERThe TARGET LUN register is used to tbkf both theLogical Unlt Number (LUN) ard Target status infsnra-tbn during various 33CggA comnnrds ard sesrences.During a select-ard-Transfer o r Reselgct-and-Transf ercommard, the mnlents of this register (alorq h'ith theSOURCE lD register) are used to generate and ctreckthe IDENTfFY messagos transfened acrcss the SCSIhrs. ln adclttion, the TARGET LUN register is used tohold the.Teqet Status byte received d.rring a Select-arSTransfgr @rnmand.

During Wait-for-select-ard-Receive oomrnatds, thisreglster may hoH the image of the ldentfi messagerecoived frorn lhe lniliator. lf the TLV bit is zero, therewas rp ldentify meesags received. ff the TLV bit is one,then a valH ldentify message was received. The DOKbit wifl then indbate whether of rpt the lnitiator hasenabled dismnnects.

During Reselect-ard-Transfer commands, this registeris used to sst the LUN to h used in tfe ldentify mes-sagts sent to the lnitiator after Selection phase. The TLV -ard DOK bits are not used.

In advarrcsd mode, durirg Select-ard-Transfer com-mards, this register is used to hardle reselecthn by anunexpe€tsd Target. ln this case, this register will hoHthe bgical unit nunber of the reselecting target. TheTtV and DOK bits will be zero.

7 0

TARGET LL.F.l bit 0TARGET LUN bit 1TARGET LUN bil 2Not UsedNot UsedNot UssdDisconnects OKTARGET LUN Valid

1860SZA

COMMAND PHASE REGISTERThe COMMAND PHASE register is used during conbi-natbn cornmards to indlcate whbh phases of thesenr.llti.phase commards have been corrpleted. Thus, ilthe mmmand.has terminated abnormally, the proces-sor can read this register to datermine the cause of thetermination and how to respord to it. This register isalso used to resurns combinatbn commarrds by loadingthb register with a value that indicates the next desiredor sxpeqted hls phase, and reissuing the commard.Reler to the description of the specific oommands fordefialls ragarding the va/pus command phases andresume vahres.

Com. Phase blt 0Corn. Phase bft ICom. Fhass Ut 2Com. Phase bit 3Corn. Phase tft 4Com. Phase bfr 5Com. Phase tft 6Not Us€d

fiGtsrA

SYNCHROHOUS TRANSFEN REGISTEFThe SYNCHRONOUS TRANSFER register is used toselect between synchro'rous ard asyrrchrorpus trans-fers, and is also used to deflne the maxlmum transferrate. For inlormatbn phases otlpr than a "data" tranderphase, or when the selected otfset is zero(OF3=OFZ=OFI =OF0=0), asyghrorpus transers willoccur. Values greater than zsro define a syrnhronoustransfsr nr* ard the offset is detennind as shwnbelow. Thie offs€il dstermines tho effec[]ve FfFO rfsshtor syrrchrcmus data transfers, and ls typbally deter-mircd by negptiation with the othar $CSf &vbe (asdefined in the SCSI staruCard). The Transfer Period@rtrol blts selest the minirnum lranster Frlod for bothsynchronous ard asynchrcnous SCSI transfers and, llAM-Bus rnode is used, the transfer period and the wirJthof the AEfiilE srobes for'fpst transfers. The perbd isdefired in tenns of the intemal cbck cycb tirne; thefrequercy of this cbc-k is determined by the divigorselected in the OWN lD register.

OFFSET bit OOFFSET bit 1OFFSET bil 2cFFSEf bil sTRANS. PEfi. b|t OTRAfifS. ffiR. bil 1TFANS. PER. blt 2Not Used

fisc&t

+42 Am33G1XlA

BN f{ams Desffp$on0-.3 OFx Tho OFFSET Hts are usdlo solect the &sired offset amrdirry to tho fotforirq:

3 2 I 0 sehsredoftcat00000000

001100tI001100t

0I0t010t01o1o,l

X

0 (Asynchronuls data phase tranefers)1234567II1 01 11 2

UndefinedUndefined

4-6 TPx The TRANSFER PERIOD ilts are used to selecl the desired transfer period accordirq to thefolbwirq table:

scsl6 5 4

DBA BusTransfer Perlod

(�CSI REO/ACK Synchronous putre Wtdthand DBA Bus FEffiE putse Wdth)

I234567

0 x1 01 10 00 11 0t l

cyclesi

t

I

t

t

(4 qlrcles)( 1 ' � )

( 1 ' )

1 2 ' )( 3 ' � )( 4 " )

( 4 r )

The 'cych' referrgd� to fuve fs lfre perid of the intema! data transfer M dter the divieor chogan inapltd. Thts peritil is cahu|prted by the foltowing forrnula:

CYCLE.DMISOR (from OWN lD)

2. INPUT CL@K FREOUENCY (MHz)(1mec)

TRANSFEN COUNT REGISTERThe TRANSFER couNT register is a 24-bit registercontaining :a preset value for the internal trangercounter. This preset value is baded into lhe intemaltransfer counter when a send, Rgceiv6, oF Transfercommand is isued. This counter is used to definecomrnard completbn by decremeilirq as each databyte is transfened over the sc$l bus and gausing a"successlul completbn' interrupt when the coulierreaches zero. fn combinatbn ofiunards, this registerlpecifies'the nunber of bytes to be transfened during aData phase.

The counter furution can be disabled by bading theTRANSFER couNT register with zeros prlor toissuing a commard or byr setting the SINGLE-BYTETRANSFER bit in the CoMMAND register concunefiwith iseuing tho omrnard. If the counter is disabled, the

send, Receive, or Transfer commard will be conpletedwhen a single byte has been transferred.

After the completion of any successful transfer, theTRANSFER couNT registerwifi be zero. This incfudescommards issued in Singfe Byte Transler npde.

when a transler is interrupted by a halt on effor condi-tion, a SCSI h.rs phase change, or an abort, theTRANSFER couNT register wiil contain the number ofbytes Nor sumessfully transfened to/from the scslPgr, incluling clearing the internat F|FO of any bflesleft in the FlFo (see DATA register). This FtFo dtearirEproces$ may cause the TRANSFER couNT registertodiffer with the user's DMA controller count, becausesome bytes may have been trans{ered into the FlFo,but not to the scsl bus; therefore, the TRANSFERcouNT should be used to determine the actual numberof bfles transfened toffrom the SCSI bus.

AmlXffiftIA 4-fi1

, I . , ,

EG$jrxf{fifi$}t tu nggf$TgnThs OE$TIF,IATION,ID rogistor @nte#rs ttp ermdodSCSI bns lD of the &vlce; which is to be sobded orreselected when a Rseslsd or $elsd sonffi,Hrd ls

b'susd. This regieter'alsoooilaifts mrilrol bits tfnt efffffiths opcrdbn of wrtEfin bn itomnufds.

SESTINATfi)N ID UtODESTINATON ID blt T.DESTINATT}N ID. Ht 2Not UssdNd UsedNd UsedDATA PHASE DHECTIDilSELECT COMTJIAND OHAF{

7

8rr De*dptlon

0*8 Dfx

DFD

scc

D'E$TlNATlOll lD Bite DfO-Dfl cortqin the ermd€d SCSI bu lD of tfre dev*m whldr b tbbe sabuted or resetsctsd w{ *,BE$ELECT or I SELrcT eonmard &s bsued.

DATA PHASE DIRECTION, when advanced features are Gnabbd (ss€ p.14), is used tosrelfy tha eryected diredion of the $csl data phase, whsn lt owlrs. ThF alfows tfptrlG93A to verity the direstion durfng Sefect-and-Trarsfer commandg before @innirq thstrensler. whsn this bit b zero, the exFcied dirsctbn ls out (to the Target). when this bit isqfie, the eryeeled directbn is in (from lfie Target). An unexpected irfonrutbn phase enorwilf occnr if tho'direcfibn does rst'r$atsh,the setting of this bft.

SELECT COMMA|-|D GHAIN is used only whsn the Reseld-arxf*Tranefsr mr,rffTtafd bissued wlth,EDl-l. This blt selec{s whbh cornmand is chained to when tfre data transler bermfeted. Whnthis bit is zero, a Serd-$tatus-and-Commard4onptete cornrrardbeginsexecutir€. When ffris bit b one, a Sen&Dis@nnect+vlessagp conmard bogins oxecutirq.

SOUNCE IO REGISTERThs souRcE lD r,egrister b used to report ths scsl fus lD of tm that has selsdEd or rerIt also mrfrains bitg that enabte ard control re$ponse to selecfiion ard' resslection.

Blr hfsmg Semrlpelon

0-2

I'

5 , " '' : , J

. .

6.,. 't ' "

Slx

slv

DSP

SOU,RCE lD,B}b O*e are valid onry il the $lV bit is set to one. Theee bits lrdhats ttp $QSlh.ls lD of the devlcs that selectd or reselec[ed the 33G93A.

SOURGE'ID VAttD is sotto one afterths 33C9SA is sebcted orreselected tr the other$C$tbus devies assertd its siln hrs lD bit (in addltbn to the h.rs lD blt'of the 33C9SA) durirq theselectlreselec{ phaee. This M is zero il only the bus lD bit c}t ths 33C93A was asserted.

DISABLE SELECT PARITY, when sel to ons, causes the 33C93A to igrnre ths bus parilywhen resFordirq:to sele6{bn or reseledbn. When this bit is zetro, any ielec{bn or resebC-tion with a parity error is igrrcred.

ENABLE SELECTION, when set to one, enabbe the 38C93A to resporxil to a sstection byanother devi:e on the SCSI hrs. When thls bit is Esro, any selecilion ls bnored.ENABLE RESELECTION, when set to ons, enablesths 83CggA to ruprxd to e reselacfiionby another devhe sn ths SCSI bus. When this bit is saro, any reseledion is (7nored,

ES,i, E H

AnS$SgA

sclst sTATrf s'nE G ISTE RThe $Q$l'rsfATus ragsor is a readrnS reglsterwhi0h i ated the. cause of the rpst recent INTRQasssrtion. INTRQ is asserted whenever a mrditionoccurs wit[gr tl.te 6633993A that rsquires interuefiionby" tha fn$;,foJ' Gnrf,rfiple :

' Tns mC93A has been reset;. The @mmard completed successfulU;. The bus phase changed;o An qrmr occuned.

Once INTRQ has been asserted, the conterila of thisregister wilf not change until after the SCSI STATUSregister has been read or urflif the gACgSA hss beenrgset.

0

sosl STATUS bit 0scsl $TATUS bil 1scst stATus bit 2scsl sTATus bir 3scsf STATUS bir 4scst sTArus bir sscsl,sTATus bn 6scst STATUS bft 7 fi85&Or2A

Btr Name Descflptlon

0-3

#7

SSx

SSx

SCSI STATUS bits 0-3 are $atus qualilierc wlpse meaning depends upon whbh upper(F7l status bit is set.

SCSI STATUS bfis +-7 de{ine tle type of internrpt that ocqrrred. The possible codes aredefined in the folbuving table:

qmo0001001 001 00

1 000

xxHxxnxxxxxxxx

xxru(

The 33C93A is in a resol stats.A 33C93A command has compteted successfutly.A ggcg3A mmrnand has paussd or was aborted by an Abort mmmand.A 33C93A command has been terminated prematurely du.e to an enor orother unexpected condition.An event on the SCSI bus requires service.

All other $tatus code groups are curently not used andare reserved for ftrture use.

ln the followirq tables, the '$TATE colurnn,,ffibatesthe cunent date in ufibh the Status Code can omur.Also, ths'M0l fieH refers to the signats tfgt defirp aSCSI hrs inforrnatbn transfer phase: MSG, C/D, endl/o. A bit st to one indbates that the slgnaf is assenedon the SCSI h.rs. A zero indbates negation. Whsneverone of lhese Status Codes occurs, the REQ signal isasserted on lhe scsl bus. The tabls below summarizesthe meaning of tho MCI field:

uc,f coDE MEANING

0000010100 1 11m1011 1 01 1 1

Data Out phaseData In phaseCommand phaseStatus phageUnspecified fnfo Out phaseUnepecifbd Info ln phaseMessage Out phaseMess4e In phase

Amen93A &rl$

ftDl$triaFtbrugr

sr$l|| 'cdr

SEtr WSelhrnflgW

0000

mm

@01

tlTr

oTt

gtGggA Hesst. The dwhm has b€en rerol, or a Resd command has €xscutsd suec€rs-lulfy with no advaneed fedures enaUed. The nw $atc of the $rcs}A is dbconrnded.ggq0S4 t Tha&vhe has suseaslulsomflsted a ReadcsrnmendwlBr dveircedfeatwe* ensled. The new stde ol the agcgsn ie dbenns.ted.

$rcmrtul Gompbtbn fnt rru$r

Stur s[|b $fficmrnftg0001

s001

00010001

0001

@00

0001

@10001 I

01 00

01 0101 100 1 1 1lMCl

D

D

OT

OT

DTDI

I

0&1molqoo!000r

A Resobcn co FflId .*bd $rocegailulU, Ttrs neru cilete af the SgCSg b connectedaB a Targd.

. A Selecioommard complrtsd $rooesddry. Ths ms stete otm€ 33CggA is onneated asen Initiets.R$eryed'hrtsura uE{g.A Rslvq Ssnd, Resel€ct-ard-Trarder, Wait-for-Scld-and-Receiw, Send-Stetrp-and-Gofirry49ornpl{te, or a Send'Dbsflnsct- tlessqe oommand cunphted srn-cascfully 1Fffi' b rsaeserted).A' fuebg, S-md, Rg6ded-*rd-Trangfs, Wafr-hr€ehg-and{le€ivu, $eld-$tstts-and&mtnand-Complete, or a Sand-Disconnecil-Meeeqe ommand com$etsdeumcedugy 1ffi ie asseiled).A Transldo Address commard ompletod wwcsfulfi.A Selecil-ard-Trenefer oommard onpleted umeefulfi.Rsseffod for futun usc.A Transfer (non.MESSAGE IN Srase) oonrrnard er@ted strcceasfully. l{Cl ddines thrnsw ldormetbn tlpe (SCSI bue phase) bdng nguessd.

Prurrd or Abortrd htrnupts

&df $ecruthnhE0010 ' 00m

0010 , 0001

ooro ooto0010 00110010 0100

0010 0101mto 01100010 0t t 1

I

I

DTT

A Ttenefer fnfo (MESSAGE4H S*asel oommand has paussd with EeR assertsd. Thlsallo*s lhe hoet to exsmine the messsge before rcg$rq lt.A Save0ata-Poirfier messags was received durirq a'scfern-an&Transfer oomrnand. Theho$ ehouH save ilg current C*. hrffer pointer.A Selecr or Reselect command was abofied.A Receive o-r Send mrnmand has luttrd by an error or $as aborted tffil. nd asswted).{ lgeive * SonO comrnqnd has hrttsd bi an enor or by ae$ortbn dl ffi or was #ned(mis aseertd).Reg3$vod for futurg u8e.Reeerwd for future use. : ::Ths SilCggA has been resslected durirlg a Select-and-Tranefer (rvlfr E)l-O) by e Taqrstthat does ld mddt the SC€l but lF haded into tha DESTINATilCI-| O regieter or thetol$irq Hrrffy mess{e did not rnddf the LUH bded hto the TARGET LLrN register.AeK has been lefl assertsd folfou*rry ttn Hentr'fi mesEagp, ard the bus lD arrd LUN of ttreresel*lirq Targlet dre evailde. In r$,n SOUACE D ard fARGef f-Unf .rugkrters.(Advanced Mode onry)A Traffifer smmand was aborLd. ltQldsfkrg thr mn lnfrorrnatlon typs (SCgt Slr phare)being reque*ed

g0t0 tfiFl

t :

' a a a t, :.,

a

' : 1a:.q' ' , 1

. . 4

{.'{{s{.!i

5

{' i l

t1'11

i

,d_:!i

ji4

If. {

;-s-;il

{.i|�fi *tr${ISffiA

Tcrmlnrted lnterruptr

$cclffa trbanFtg$tetss Cdi Shte

010001m

0100

0100

0100

01000100

01 0001 00

0010

0011'

0t00

01 0101 10

0 1 1 11MC]

DTII

D

TI

TI

DTD

00000wl

An invalid command was lssued.An unexp€cted dkrconnect iSCSf bus free) by the Tuget eused I6mmgrd to terminate.The nsw state of the SlCggA is dismnnociled.A tim@ut ocalred dwing a Seleet or Regelod ernmar-d. T state of the ggCSA b

A panty errcr caused a @mmand to termindo 1Fffi- is nd assertod). The tran$er dpectiondelermines whether fr b a SCSI or host parny errof,.A panU enor carced a cqmmand to ternrinate fiTF ig $serted). The transler dlrg6tbndetennines whether il b a SCSI or host parnv et$oF.The Logical Addrees excesded the diek boundaries.A Target whose scsl bus device lD does rpt mateh the bus lD set in the DESTINATIoN lDregister has rosel€ded the 33c93A during e $ehcn-and-Transfer ommard (with lDl-O).This intorrupt oocur8 when the 3tlCg3A b not in Advanced tfode. The new state of the

ffiffi lffillfr il-:'* tmlh

d uring a setecr.and -rran ere r co m m and.An unelqrec'ted inlormatbn phase was requested. MCI define the SCSf bus phase whbh isreqmsod. This ig typicalfr causod by a phase change before the Transler Count hasroached zBro or ry an unexpec{ed phaee ssquer}m oelning durirq a Select-and- Transforcomrngnd.

$ervlcr Rrquhad fnterruptr

$tatus Code Spcdflc iileanlng1 000

1000

1 000

1000

I 0001 00010001000

0000

0001

001 0

0011

010001 0101 100 1 1 1

D

D

The 3IlCgSA has been reselocled. The new aiate of the 33C93A is ennected as an fnitlator.No ldentily message transfer has yet rotrrred.The 3$93Abaa boen r€8elsc't€d in Advancad Mode, The SCSI bus lD of the Target may beread frorn the SOURCE lD=r.eglster. The Hentify messag€ from the Target may bJread f;;the'BAfA rtgisrter. Tfre AGR signal is teft asserted. me n€w state of tho ggCggA isconnested as an Iniliebr.Tho SSCSA,hee bson selected (trfi was not asssrted). The n6w etate of the 33Og3A isonnestod as a Target.Ths SIC$BA has been sdecild (Hffi was asserted). The nEw $e19 of the ggCgAA isonneciled aB a Target.The Im sgnat has-been aseerted.A disconneci has oacurred. The new state of the 3ll0ggA b disconnecled.Reserved for future use.The lfVeit'fsr'$elst-8ftd-Recslve commard has pausod beoatrcs the'firsl Uts: of thsi*Try GDB ie not a ltrpwn command mup. The OWH D reglrter mug Oe 6eded nlthqts CqB hng$t, ?4d the commqnd resumed. The CDBI rql*r msy bg examined todetermine the SCSI €mmand group fiom the opmde. Ths new stete of ths gggggA lgonneded as e Targg. {Advancod lriode only}The ffEQ signal,has been assorted foltowing connscibn or when ths 3$IGggA is in thslnitialor slate and no smmand i* exsautirtg, The informatbn phaee ty1pn ehotrld be erErn-ined. MCI dEfine the information phae (SCSf bus phaoe) whiit is beidg roque$ed.

D

D

TI

T

.tn

1m0 1i,rc|

ffi8iffi}A &{7

CO.m[tAf{D REGISTSR :The COMITAND regfister ie used h hsue the 33Cg$A@rnrnaFrds. This register should neverbs lodsd whenthe CIP or INT bits (in AUXILIARY STATUS) aro sot toone, and a Level ll command shouH nevor be bdedwhen the BSY bit is set to one.

The SINGLE€YTE TRANSFEH (StsT) bn in theCOMMAND register is only usqd dlrirq ir$.onnatbntransfer type commards. When thF ffi b sst in

7

coniurdbn wfrh ong of these &nunsnds, the trandsrmlnter i dlssblsd ars exacilly oR8 ryte is to bo trens-forred, regerdless ol the vah.re in th6 TRAI{SFERCOUNT reglster, Ths prevbus mrsents ol thsTRAI{SFER COUNT register are nd preserved.

Refar to the COMMANDS secilbn for a descri$bn ofth conmar{ts and their con€sporulirg omrnardcodss.

0 i

DATA REGISTERThe DATA register is used to transfer datd'Wes ''b6-tween the ho$t and the SCSI bus firrir€ the SCSIinforrnation transfer phases (conrnard, data, status, ormessage phase). lt nuy be aocessed by fte prosessorduring any type of informatbn phase (slnple Level'flcommarxls) or via the DMA/DBA Bus interface during ascsl Data ln phase.or Dara Qrt phase (sintrle ardcornbinatbn Level l! comrnards).

The DATA reglster is actualty a port for the host inter-face inlo the intemal twelve byre flFo of the 3Ec93A.The' FIFO i$ ussd for,all transfers {syrrchronous ardasyrrchronous) between the SCSI bus and the host fus,for both DMA arut prgcogsor access tranefers. ff tlmp3SC93A is to be haltedtor any reason (thrgt4gh ABORT,for exam$e), then data transfors with thb FIFO rrustcontlnue until anrintemJpt offilm. ThH rT,ilitit be &ne mthat ths'FlFO is returned to a ready stats for subseqgenttransfsrs, and to fftrsh inornirtg data to the host hts, ,

The DATA register is meesed by the procsssor dlringa data phase when'ttre CONTROL register DttA rrpdeselect bits are all reset {-S}, and when fte DBR blt in theAUXILIARY STATUS register is true. Ths processorwrites (reads) tho DATA register by bading theADDRESS registerwith a hex value of 19 ard assertirqthe WE (m ard 6 pins. This a@ess also occursduring non-data phases.

When the CONTROL register DMA rnde select bits are$et for DMA mode or BURST mode, the DMA interfaceis enabled. In this case, the.F$ register b written(read) when the ffi and WE (HE) pins are assertedin responss to the assertion by the 33C93A of the Dmpin.

When the DBA Bus is selected by the DMA mode selec{bits, ttre HCS pin furrctions as an exlemal bufier chip

COITMAITD @DE Bt OcofrfiiaND ooDE Bir 1csrM No coDE Bir 2COil,IMAND CODE Blt 3qOMMAI.ID CODE BiI4C0ililillAf.lD @DE Blt 5@Iffi'IAND COOE Blt 6SIHCLE€YIE TRANSFER nc!.omA

sefoct gd the tdlE ard RE pins becone outtr*s, albw-itg ths 33C93A to *rtomaticalV trander data betweenfts DATA rogister ard the extemal hrffer. In this trpde,bus corfrdcqnbe returrcd tothc enemal processororany other device by negating the DRO pin.

Asqqt Gonoi$oncHANSWARENESETThsfstbtning resuils'omrrwhsn the ggC93A ls reset bytm ss$dtbn of t'frs,mT'signal:

. ThB AUXfIIARY STATUS register ls reset to zslo.Tho fNT bil tand the |NTRQ pin) is set to one whentlp har$rare ressl cornpletes.

. Th$ O.|N lD r.eglster is reset to zero.

. Advanosdirnods is disabbd.r The ES; EH, erd DSP bits in the SOURCE lD

reglsler are resst to zeto.. Tlre gCSr STATITS register is reset to zero.. Ths isernsl FIFO, irrtemal transfer courter (not

tho 'h6t accesshle register), offsets, ard statemachines are deared.The internal cbck dtulder circuit is set to divkfe bytwo.

The folbwing -hgst aocessble registers are NOTaffected by the MR signal:

. Regis{ers 01 hex through 15 hex;

. SOURCE lD (16 hex) register bt'ts 0-3;

. COMMAND register (18 hex);

Note: Ifre SCSI Sott freset may b tmplemented by usfrg fheSGSI bus reset srtynal lo cause a resef of thw 83C934(for example, Ofr tie hosf poyrer on reset s$1nal withthe received SCSI bus reset fiST) s$nal). The lwstnay examine tto rryiisters flret are tlrlt afteded by ttnMH s$nal to recrorv*r from fhe SCS/ rsset orndftbn.

e48 .AmSlG$ilA

SOFTWARE RESETThe folbwirg res.rlts occw wfren the gScggA executegthe Reset mmrnard:

. Th8 DBR bil intho AuxlLfARy STATU$ register isresst to zsro. The lNT btt (and INTRO $n) is set toons wlren the Reset @mrnand ls corplete.

. All SCSI hls spnah are reset to the negated state.' The irfiemal FIFO, lnternal trangfer counter (rpt the

hosl accessible rqgister), offsets, and statemachines.are deared. .

coMMAt{DSGommand Llst

. The OWN lD register is interpreted ard the cbckdivisor, tpst panty, ard advarrced rfpde arg oon-figured.

. Registers 01 hex through 16 hex aro rcset to zerc.The COMMAND register (tB hex) is atso reset tozero.

. The SCSI STATU$ register is set as commardedby the EAF bit in the owN tD register.

Commandcode vand(HEX) Command States Lovel

0001g2

030405060708sOAOB0cODOEOF1 01 1121314r5t6r71820

Reset D,T,lAbon D,T,lAssert ATN INegats ACK IDisconnect T,lReselecf D$elect-wlth-ATN DSelect-without-ATN DSel€ct.with-Imq and-Transfer D,lSelect-without-ffiN and-Transfer D,lReselect-and-Reeive-Data D,TReseled-ard-Serd-Data D,TWait-for-Sglgct-ard-Receive D,T$erd-Status-arilt-Cornmand-Complete T,lS€rd-Disconnect-Message TSet lDl D,T,lRecoive Comrnand TReceive Data TRecsive Messaga &rt TRoceive Unspecillsd Info Out TSerd Status TSend Data TSerd"Message In T$ard Un$pecilid Info In T'Translate Address D,TTransfer lnfo I

cl

iltll ltfI Ilfl ltlItlIiltll ll ltll ltltltll l

33Cg.tA s!€te€,' &mmand Levets:D --Disr:;elnnected- I - Level lcommandT - hnnectedas a Tuget ll - Level ll commandI - funneded a$ 6u, lnitietor

I!--

AmSllSA /*-{0

$$C$S Co TypesThere are truo basft: types of ffl093A mnrnards: LevefI and LevEl ll. Levsl I oonmrards may b€ lssued while aLsvel ll mnrrnrd i$ in progres (irdi€ted by anAUXtttARY $TATU$ ot B$Y*1,G|PFO) ard, exffpt forthe "Amil" afd "Re$gt" wmrnands, do rpt gensrats aninilsrtrr$ Wq0lf$lr mrlpletion. Level ll mrrunard exe-qltbn will ailrays result, in an lr$errupl. lf a Levsf llcomrnard is is$usd while amther Level ll comrnard iscxqgqtirg, urprodbtaple- results may oecur.

There are two tlpas of l-evel ll cornmarffi. '$irplo'

Levsl ll srffnands are associated with a slngle opor&.tbn or phase (for exarn$e, sslsction or ir*orrnationtmngfefl. 'Gonbinatbn' Lsvel ll snunarde combinemultl$s phases irtto a sirqls 33C93A omruand tominimize ir*errupt overhsad. The lnitiator comHnationffirnrnands 'expect'csfiain SC$l bus phases at certaintimes &rirq a sequence. These expec{ed phases arebassd on cornrnon sequencss peilormed by a Targeton the SCSI h.rs; any dGviation causes an intemrpt.Target csmbin ion commands can bs chalned to-gether to furllmr minirnize interrupt overfead bycreating bngor phase sequences.

I@TE: When usit:ggg command draining, eare must be takenbto ensum thd, all canmands in the ehain an inltial-Esd prior to issuing the ammad.

ThE 3SC93A wl$ bs ln ono ol three lstates' duringepr,f,t$rn: Dlwonnedsd, Connecited as a Targol, orConnoe{ed as an lnltjator. Certain cornmards are validonly in partkxrlar silates as irdbated in the COMMAFIDUST, An attemS to iesue a Level ll mmrnard whish birwalH lorthe preser$ 33C93A state will cau$s an Tnva-lid conrnarrl" intemJpt. Level I commards issled inirwallt states will be ilgrrcred.

Adllgncod,:Modg,,Fml u rosTfia $3CS$A has'ssrs,raf r€rnr featureg irahded whbhsdd nsil, frrnctbn$ to th original 3tl093 dosign. Someof tfrcss features causs ths 33CggA to be lrreompatiblewilh ths SgC93. Tho,ss features have been gnoupedtqg€ther urder the headlrq of 'Advarrced Mode' fea-tures. These features are disabled when the 33G93A isrseet by ttre MF'signal (turdnvare reset). They nnrst b€ensbtsd by the host by bsuirq ths lReeet' mmmardwith the'Enable Advarrced Features' (EAF) bit set in theOVtfN lD registsr. Ttrs host can determine il advanedfeatures have been enabled (thereby inplying that as3Cg3A b instalfedl by examining the SO$l STATUSrrytiuter alter issuirg the 'Regalt mrnmand.

Tha fealurss enabled by this bit are descrbed in thefolbvirg.

Ul- lEI tFEgfEOFgSELlg 'CnOi l r i " ' ' ' i " : : ' i ' f i

Whsn in nonnal (33CS3A} rno&, s rumhtilbn ndrsnklle (ER-l) or urhen dlscorslactod drrlrq s Seld-ardiTran$ef mttm ,.(ard $s "T.8rggl, bus lS doss llotnuEh the DE$ifl NATIOI'I Hl' rrufi$ter] caroos an lltsns-date lnft$lfir$ aftar tfn rsgeMhn ,har$gfiake bs1rplete" In Advancsd Moda, tha SSCggA will rcnlinueto the Message In phass to fetch the ldentify rnessage.lf'the'S$ggA was HlE, the $CSl STATUS rugfister wiflbe set to 81 hex, and tho kkrltify msssage srill bo in thgDATA regbter. lf the 33C93A was exeantirq a Slect-ard'Transfer smrflard, tho SCSf STATUS regieter willbe set ta 27 hox, and the Hentffy messagp wilt be h theTARGET LUN reglster. ln eilhercass, tlB ffi,ltrcE lD,register wlll eontain the $C$l bus fD of tlp reseMirqTarget, anilth€ ACK s$nal remains aeeorted sottrat tholdemify rneesgp'fiEy bs reigctsd,

UNKNOWH SgSl COIffi'*ND GBOUPSWhen a SCSI GonsnanC Descfiu Bbd( is lransfenedon the SCSI bus, the omrnand lerqrth in bytes is dster-mined by the group €de, which is tourd in Uts 7-6 olthe first commard byte, or o@e. Group 0 (opoodes00 to lF hex), gmup t (opoOe$ g0 to 3F hex), ardgroup 5 (o'pcodes A0 to BF hex) Gomrnarxte are definedby the SC$f st ff ()6.13f -1986) as six, ten, aftdtwelve byte camrnnds, reepectively. All other conr-mard grcups ap urdefinEd by th$ stardard. fn nsrmalmsds,,,tt$ S3C9{}A'will assurne thet ttrees urdefinedgrgffi;,cro$ix by{e csmmaruls lfhgn executing $e&ct-aiuf.Trenster or Wait-for-$elact-an$Rocgive mm-mards. tn Advarned Mode, the tollowirq events willoGcrrf:

''$e tnnsfar: rnmsn bsding the CDB lnto theCDB regieters prbr to issuirg tte mnunetd, the fpSaFo'bffithe expeetEd mmmarnil'len$h lnto the OWtllD roglsturr, The 3S93A usss this value to make surstho ffirf'$# inumbar of byteo are then tran$0rrod ln thsmmm$dlpha$e.

Wait-for-Sbtecf-a rd'-Recerva; When receiving the CDBfrom the ilfiiator, the 33G93A will c*redr the tlrst CDBbyteao Wrr as it is received. lf the grrouB ls undefltled,an interyupt will offirr so that ths host cen examine thetirst mrnr$Sr�d byte in the CDB 1$T regiser, ord thenbad th€ T0fel commard brsh inlo ths OWN lDregister, l't6 SCSI STATUS regiser is sst to 87 hex,ard the COMMAND PHASE register is eet to 31 h€X,whsn this interrupt occurs.

After the intgm.tpt, the 33c934 wilf onry accspt aR e su me Wait -fo r-Se I ect- ard -R eceive co mmard, Abort,Disffinnect, or Rssgt comrnard. ,All other mmmardsare invalH; during the intsrrupt prg -cessirg, tha 33C93Awill contirue to transfer the first six b$es of the corn-mard into its intemal Ff FO.

,,i,i,,:,lti

#t0.. 81ffi$*

n*?A PHASE,Slf,Et:mamDuring a sebd-arxt-Transfer ooilunand in rprmalrnodo, lhe Data phase directbn is determined solely by .the Taqet; il thb direction does rK)t match the oireaionexpoc{eel by tha host, ths 33cg3A wiil not detect thisenor hlt expscts that the transfer will contirrue. InAdvarrcsd Mode, the DPD bit in the DESTINATfON tDregf$Ier ls compared $dth ths state of ths lro slgnal onths sc$l bus. lf the expected and actuat directbns enot match, an interuS will occur with ,unexpectedphase' status in the SSt STATUS regbter.

Level I Cornrnards

RESET (m HEX)The Reset @mmard performs a similar furrction to thehardrare r€set causod by assertir€ the t[F'gn exceptthat the ovvNl lD register is sanpted for infonnatbncotrcerning th6 operaiing configurdtion of the ggcggl.The 33c93A is also initialized as described in the

- RESET coNDlfloNs section. The Reset cornmandmay be executed in any 33cggA state and willtorce the33c934 into the Dlsconnected state, abortirg any previ.ously is$ued command in progress. upon conpletion ofthe Reset ommard, an interrupt is generated the scsl$TATUS will be 00 hex or 01 hexl dsperding on ttreffntonts ol the OWN lD rugistor.

ABORT (01 HEX)The Abort fffilrnard is valu in the Disoonnected ardconnsctsd-fls-B-Targst statos.The Abort @mmard hasdllfersht efiects deperdir€ on the state ard tho Fm-mard that h affentry exscutirq, as dsscrhed below:

Diesonnected stats: In the Dlsmnnect€d state, theAbort commard may be used to halt an attenptedsebct, select-ard-Transfer" Reselgct, or Reeefed-ard-Trangfer @mmand. lf the Abort command is issuedfolbwing a select or Reselect command ard theA|T!33C93A lus won arbitration, the Am33cg3Arsleases the scsl h.rs by removing the Bus lD bits$ilr ffi n assertsd and-checkirq rir llgg",sd ETis{pal. lt after at leas 200 ps, there is no BEV response,the Afig3c93A guoslo a Bus Free condition and gener-ates a pausedlaborted interrupt. lf there is a responsewithin this time period, then a "successfur compietion'intemls will result instead

Nols that th8 Am33cg3* wiH neglect Abon cornrnafdunlsss the comrnard is mnpleted. After the cornpletbnof a oorffrland, tho Am33Gg3A wit| s-ceept an Ahort$rnrnard and :will. go to thg Bus Free phaso ardgsnerate a {Pause/Aborted lril€rrupl'.

DrscoNHEcT (04 HEX)The Dismnnect @mnrand may be used in either fiETarget or tha fnitiator connected sates. fn the Targretrole, tho Dis@nnect commard b lhe nonnal procodrrulor dismnnectirg from the scsl bus forknrirry the infrcr-mation transfer phase. In the lnitiator roh, Disconnsdcan be ussd to refeaso the bus loflowirq a tirrmutcorditlon. The Disconnect commard causss the imme-diate release of all bus slgnals and, in Target rpde,retums the SCSf bus to the Bus Free phase. tf theDisconned command is issued durirg an active Level llcommard, lhs Level ll comrnand ls lilrnsdietely lenni-nated ard the 33c93A transitbns to the Dimnnectedstate.

, t .

ASSERT ATN (02 HEX)The Assert ATN mmrnand is onty valkJ when Con-nected as an Initiator. lt is normally used to ahw theInitiator to irform a Target that it has a rnsssage psrd-ing (The Targef _is expected to respond by performing aMessage Qrt Phase).-ATN is automatically negated:

. Before the last bfte of a Transfer lnfo conunardissued in response to the Message Out phase;

' when the ldentily message out is transfened to tfreTarget during a Sebc{-ard-Transfer command;

. When a SCSI Bus Free phase occurs.

The sefect-with-ATN and $etect-with-ATN-ard-Trans{er@mmandswi$ cause tho 33cg3A to automati-cally assgrt fffi prre'^r to the release of m providirqthe bus arbitratbn is won.

NEGATE ACK (03 HEX)The Negate ACK commard causes AEKto be negated.It may be used in the fol|owing sltuations:

. after auccessfuf mmpletion of a Messag€.lnTransfer Inlo commands;

. after the 33C93A has detected a parity effor on arryreceived SCS| infonnatbn ard the HALT on SCdtPARITY ERROR (HSp) bil is ser;

. after unexpocted reselection in advarrced mode;ard

r &fter a ggyg-rlgltfointer message is recsivd,&rring 8 $sfo{t.and-transfsr comrnard.

Host partty effors do not affec[ the lffi'slgnar. For arlother lnitiator transfers, m negation is auiomatb.

Amfim0(}A &5f

ln thg ca$s of a lile,wAgo-ln t lr lrssrsryss Frsy bs r#cilsd ard the tnitidor msy irdicate itsmtafit to,,sord efthar a IT|ESSASE nAIEC-r or I"IIESSAGE PARITY ERROR'Messqe by beuirg theAswrl rtThf,ogrfilTtitrtd prbr to lsurir,q the Nsg#e A*ceqmsrs. ll tha inmrrfrrg me$sagp is b,bs ascess4only the Negnte Ad( conrmard sfprfiil bs hsnsd.

Drrfrrg rpn-Messag€-ln trensters, il the Tnansfer conFmanl is tsnninated by a parfiy srTotr, the Asssrt ATNGo-rnrm$ oan'qaFr bs'bsrr d pbr to Nogate ACK, thismq irdbetirq tho lrsthtofs trfent to send 8n"lNfflATOR DETECTED ERROR" Mess€s.

sET rrlr (0F HEX)Tha $st lDl mrrrnam- is ueed h thq |nitistor tole tos.FBort overlapped SCSI opsrations. ff a SCSI mm-r$gr-,S. is exoartfE,vh a $elsst-ard'Tranefer srnrnard,thn the Sst f Dl comrnard may h usedto sttho lDl ffiin the CONTROL register, whicfr lhen causes an iriler-nfr to mrr upon a Targot disconnedion. This abilitya$ows tf tBl bft to b left roeet wfpn the first $CSfopgratbn lg $arted, whicfr may re*a0e,tfiG mrr,tgr,of!qC93A mafnlss, Id slso ahw$ a eeoond opo€ttlnto be staned when meded wilhout waltirg for tha lirstryeratbn to be onpleted.

Slrnpile,Lsrr l'$ GgrnmaildssELECT.Wfrlt-ATil (06 HER$sbct',$ftf,l'ATN is val$ on|y in ths Offinlwed stdestld r$en ,htuod'ryllt causs the 33Cg3A t'o eehd aTerget. &fErs lssrrl!€,this @rnmand, th $CS,l &ls lOof tfts Target daviso uhouH bo Hrlilsn ir$o,, 'lhsDESTiNATIS| lD ragnuilBr; Utlhen ttu $etsct- wHtrATNsonur*ud le lssrJsq the 83Cg8A hryins buo art$tratbn.lf .:tho,, 39CggA F oebtf;od ,or"''rguqlecil6d by another&vbs durirry the arbitratbn, the $elecf,-with-ATN @,n1.,mand k abofted ard a lservbe rcryired ifiorrufl(Sx frux) b ggnorals. r ; :.- ': '

$lWtH tlB gACg$A w,in,rtf,p, arWr$ion,, 6Et ard Itrfrars scso6gq[, ltg Targrst, @rlnitiato{ gue f 08 pro Sa€don ths $CSf {tats hl$, n{S,han ffi U d*asooded. *tthb tlne, a tFfioor$ sqnrm wfioee lsrrytfl b &tor-rffned by the vatue ln the ilEOUT:trRtOO rsgtstsrhg$ns. ff B$Y is t$t asssftsd, b,y th8 Taryot bsfsre affinc{ut oodhtrs,,ttts ffi$9A Wifis its sletilisn abort$qr€rs {ae,desorhrf in thetbnl, ard,ff thers is rF Tf,rgct, rc$poru$e tha $sfect-wilh-ATN ommand is termlnsted and a tenninatefirtsmrs b generated. tf ttu Target respords before thetirruot$ psrbd has dqpsd or before tho sElactbn atoilsqt€nce ie mnql|ete, tfp 33C93A negatcs ths ffi*[nal, F$tlng the 33Cg3A in e Coruucted-?$-dh-In$tiator atate. A "Sr.lccesgful mnpletion" ir*erruS

sdbatss $rt tf$ ssld-$ilF*TT{ mmmf: |.t8f. .aor@ed alwssfuHy.

lf tho 3llC93A Ses rpt win tte arUtratbn or tture is mrossorl$s fmrn tf-ffo Taryel a4 the titlle-out feature iedisablsd, ths Sstsst:lffih-ATN commard caa bsabortd with an Abort mmmand. l/llhen tho Abofioommarril is guccassfully exealted un&r these cilcunrstarrces, lhs StlCgSA ia dlsconneciled from ttp bus anda lausad/abortsf intemrg is gernrated.

$E|.ECT;WITHOUT.ATil (W HEX}The Select-wnhotil-ATN comrnand b ffintlcal,to SpSslest-wfrh-ATN conmard except tfrat Fffi h rpt set&ring the Sslectbn Phase.

RESETEGT (05 HEX)The Reselsct cqmnf,rd is irtontirpf to ths $efgd-withfi-ATN consnard exceg $lat the UO sfinal isessertsd upon mm$atbn of ths Ahitration Phaso.Succes$ul conpletiln of the Reeelect conunardresults in the 3gC93A being Connected ae a Targot.

RECEUE (1S13 HEX)Thgrs ar€ f€ur ,Rscsfue srxnald$ whiSt,,firg di$in-guiehod frorn ef,sh otfier offy by th etats of ttreg SCSIil*srfm g$nals and ths typs of data that b transteFr€d.Thess 6-ornmands, consisting of.,. the Re-csivaQrynnnA, :Roceive Dsta, Rgqive,Memqe Out, aruilR Unopeclfisd lnfo O,4 oonunando are vafil on$in,,tho,,Gfrilracted.gg-a-Targgt Gtale. Ttlg $ps of thsRSffiVs oornrnand solestsd dstgrrnirps the stqt€ ol thet6, C/D, and M-S ouputs during ths comrnardffifdirry lo the fosowirq charl (lco$ssrld):

Rreh$ sornmand Tm OFG€IDE fFC , GrO UO

Rqsivs Command 10Reaeive0da

' tI

Rssive Message Or$ 12Rsceive Unspee$f,i :lnfo Out 13

The Receive mmnur&, are lnfofin$lqn trangfefiingmmmards arxl are fiFrafore deperdert on the SBT bitln tfn COIIMAND regbter for detennlnatbn d a $rc-cessful conpfetbn. ln a*fitbn to a tsrminatbn causodby reset (via eilhsr a Reset @mrnand beirq issnled orassertlorl olf,rthe,tfrFl pin], a fiwive mmn.tlm mns-'tbrf ori filtldbnwlll ffi$ uressr any of thggg wld.-tbrx: tf l T:,fu ,ir*omal translsr muntgr is dieabbd(SBT*{, or tfulTHAN$FEfr GOUNT regiuter b loaddwith zero) ard a slrgle $fie has been read frcm theDATA register; {2) The munter has decrementd torero ,(wfth $Ef=91 irdicating that the spsgffled rrun$arof bytas have been transfened; (3) A parity tinor has

0 1 00 0 01 1 01 0 0

i

;r;lx

: : ' : - r d

em *ffilffisr*r

been dstffited on ons d the rccoivd data bytes (ard The Ssrd comrnands are aho iffio .fir!6sn cflffiteo on ons d ffie rcceivd data bytes (ardHSP-I); (4) The Fffi prn b asserted (and HA=rli tSt mmrnar,rds anq as sugF *rs also doBefssnt 'ffiThs Ahfi cornrnf,rxl is issued; or (6) A Disconnwtcofiunand is iasugd.

when the freceivg rcmmard is completed as a resuft olreceiving the conect rumber of bytes, a "successfufcompfetbn' intemrpt witl be gen€rated. lf a parity enorhas caused terminatbn, a tenninded" irilemrpt williretead h generatd. In this cass, ths THA}-t'SfdncouNT register wiff mntain the number of bytes yet tobe transferred. Alter any conpletion or termination ofthe Re@ive commands except thoss d.re to a sub€e.qrent Dismnnect command or reset, the ggcggA is inthe Connected-as-a-Target state.

As data tran$er cornlmrds, the Receive commandsare d frdent on the DMA rnode s€fect bits in theCONTROL reg*ster for ths DATA reEister accessirqmod8. These blts dotennine wtether the DATA rogisilorrcceeses will be hardled by the processor or through aDMA/$BA irfisrfaco. wh$n ttp proc€ssor ts reqrirsd braad the 0ATA register (i.o. DMA nFds selsct bfrs-0), itrarsl rnpnltor the DBR status bit (in AUXlLlAiiySTATUS}. to datermins when'a byte b avaifabls forreadirg. Durif€ Receive comrnsfids, thb status bit ryiflbs rse€t when a byte'is read from ffiB DATA rogisterardset when a byte is baded into the DATA regster via theSCSI interlace. DBfl is also reeot whsn a REceive@mrnand is issued.

All informatbn transfers inrrolvirg oherthan dffi infor-mgtion, ar$ a$yncfiromug., lfueveF, lf 'thg inlon tbnplrese hvolws data , the SYNCHROf{OUSTHANSFEH registerwill be waluated. ln this case, anyselected offset other than zoro results in synchrorpultranehm. Ths minimum Trang{sr Psrfod lor botlr typesol lransferc is detennined by the Fanster pgrbd hlts inthis same register

: :"'. :

l

SEHD (14-17 HEX)As in the csse of tho Rmive corrunands, there ara hrSent mmmarde wtrlch sra-$Btingutshed onty by $resiate of the iF, CrD, and ffi pirrs-and the rypl of dsatf,Ht is transtgned. The tour arld,comfFard$,, abs,,voftlin the Conrpcte*as-a silate only, are the Sgrud$tatus,, Send Dstg,, Eetd Mgggngg,- [$,, grd Ser,SUnspecifbd lnfo,ln mmrngrss. Tfie SC$t pln statffi.d.lring the $erd ffimmards, ere deternilinsd by Srs psF.tirular corntnand ss follows {aEEefied*l,}: .,.

$and Conmal..rd Typl opcoDEScnd StatusSond DalaSend Meseqe InSgnd Unspecified Into ln

SBT bit in ttm COIdMAND rqister frir enunar$.pletbn. In additbn to that causd by reeet (via eit$wr.eReset corunard beirq issued or assofibn of the Mn'pin), a Serut @mmard mnpletbn or termination willl@ur urder any of these @rsitbns: (t) The lrfiemsltransfer s$ntar b disal*od ($8T,*t ortho TRANSFERCOUf{T r{ilsbr b bffi wfih zero} ,at$ e sinds, hytghas boen red fromths DATA r,ogistec {e} Tfrc @ur$srhas @rsrnersed to zero (wth Ser.'ol iii#stirE filatths wifbd nurrsar ol Sptes he\rio bssn t{urfisrsned;(3) A parity eror has hssn,detgqtod onotn oi,,tf$ &taHfiee from ttu host (and HHP*l); (4) lf ffi pin:isasso-rled t*rd HA*l); t5) TIE Abon mmrnrrd b.bsugd;0{r(6} A Disconnect consnsrd is fq$od. Th ffiSgArumains Conn*tg$as-a-Target fotbw@ the ,SMcornrnard oorrpbtftrrfiennlnatHrn unlees the Dhoon-r€atco-rrunard or reget wae used to brc€ a terminfiilon.

During a Serd oornmard, DATA regbter aqstsirrg iscontrulbd by tho DMA npde selest bits in th6CONTROL register. When these bits are set to ttre approprkte npdo, batlirq of the DATA register is amm-plished by a DktA controllsr or through the Am-Busifierfrce. lt the DMA nrgde mbet bits are.zero, lheprocessor rnrst poll tho AUXfLIARY STATUS registerard can write to the DATA register only when the DATABUFFER READY blt is sst (DBR=1).

-Serd conrnands

eaUsg tho SBR bil to be res€il every time ths pnoees&rbads a bge into the DATA regFter and set $hsn a grteis transtsned from the DATA rggister onto ths SCS|data bu,s. The DBR bit wllf afso b set upon iss$rg aSerd comrnand.

As in the cass of Receh€ oornmard$, symhroturrstransfers will occur only when data tranders ars ln-vofued ard an oflset other than zero is selected.

mANSFER fNFO (20 HEXIThe Transfer fnfo oomrnrd b vaffi onry when CoB-rpctod as an,lnitistor ard ie used to serd end receiwdfita, @mmarril, status,, arNd rngosagg irsorma$on.

The firs{ Rm asseilbn tollonrirtrX connectbn as anlnitiator results in a lservbe reqnired" inlernrs. Theprocessor should exarnine tha SCSI STATUS registerto delermine the typg arfr dlrsdion of ir$ormatbn trans,fer reqrested by tho Target, ard then iszue a TransferInfo commard in re$ponso. While an Initiator, ths3rc93A wilf also generate an interrupt each time theTarget devbe reguests a nsw type of inlormatbntnari$er $aso.

lmG, GitD ss

1 4r51 6r7

0 i t

, 0 01 11 0

AmSASSA +$�s

*r

AB .in.tfts sas of the $erd s t Rgwht,:etrrnltrat!&,ufien coilFlstklrr of ths Transfer lrfo wmrnand &.pords upon the lnternaltransfer countsr, the processorshould load th€ TRANSFER COUNT reglster pbr toisruirg,this ffinmand. The DMA'rDd-e ssf€ct bits IntheGONTH,OL regfetur, tfro offsst and trshsfer period btts tnrho sYNcHnbNous TRANSFER regist'er, ard theSBT bil in the COMMAT{D regluter aie ueed drrirqTranster lrto emmar$ iust as they are durlrq the$dffi. srd,:Rscelvs ornfnfilde. Honever, for proc{ssorffis s of the DATA re$$gr durirg Transfer frrfo srn-mande (when the DMA rnods selecl br'ts are zsro or thebus:,phrrcs b otfrer than Data phase), hhavbr of theDATA BUFFER READY (DBR) status bit is dEtennirpdllthe directbn of informatbn transfer as defirrcd by thel/O pin When the transfer is from lnfrialorto Targiet; tfreDBR bit is rsset by writing to the DATA registor and isset when thb byte b transfarred fmm the DATA regi$sroFrto",tfte'$C$l data" hls. Wherf 'the transter'i$ ffufiTaqet to lnitiator, DBR is set when a byte i$ ecefu€dover the SCSI data bus ard transferred ir*o the DATAregister and is reset by reading the DATA registar. DBRis aM re$€t whenever a TmnsJer k$g.cotnmard ieissued.

There aro several causes ol a Transler lrfo corrnandmrnpletbn/tennination in adfrtbn to a reset. Just m fora $erd or Receiw eornmand, tfie Transfer lnfo com-mand can be terminaled by issuing a subsqquent Dis-mnnect or Abort comrnard. The Abott comrnard willcause a lausecUaborted" irterrud to be genarated af-tsr executbn (leavlr6 th€ 33c93A in' a aofmodedsta{e}; while the Disconnect:o0mmarid causes an lrnrne-diate dismnnect ard &es not generate an intemlpt.

A Transfer lnfo oommand will either conplato or paueswfmn the'specffied mrmbsr of bytes (oithOr a sirqle byteof rnrfiiple bylas as defined by thB SINGLE-BYTETfiA}{SFER bit in tns COMMAI.ID rcgbter} hae beensgrlt ot recgi\ted. Tho 33C93A,gsnerat€s e *Bucceesulcsrylstion" lRterrug onty afier,rereivlrg gpttpr HEeifroil| 16s Target durlng ren-Msssrye-ln tnfonrntbnphases h.rt gerrerstes e ?zused/abortd interng torUersage-ln phases without waitirg for an additbnalREO (Note that when the corpleted Transfer lnfo mm-mand was a Message"ln transfer phass, ttn ACK plnwitl be left asserted by the trl0g3A in the last HEQ-ACKcyc{e of the command, ard the prace$sor is required toissue a Negate ACK or an Assert ATN folbwed by aNegate ACK command to accept or reiect themessage).

lf a pariiy effor is dete.Asd on a data byte rs.olvsd frcmths SC$l bus (srd H$P-l) or on a data $te hrterecetued,frorn the host (and HHP*I), then ths SSG9SAwlll lerrriiqa!-e the commard ar'dd, for S€$l parily arrors,will leave Effi assertsd (to also hatt the Tirget). tn thiscaso a terminated" intemJ$ is generated. Finally, a

nsgatbn of-the ffi signal (i.e,lho Tgpst srd&Ifidismnnocts) sr I transltbn In the l/O, Ci/D, andor M8Gpins durirq a Transfer mmrnard wil abo temFrate theoomrnand anC gerrcrate a terminated interug.

lf e pq$y error ls dstdod on e byta but parifi€nor conunard terminatbn b disabbcl (HSP-O srHHP"'O, 8s approprfate), the 3tfC93A wiH dill sst thePARTW ERROR s{atJs bil in the AUXILIAHY STATUSreglstar hlt will not terminata the mnrnard as a resu[ol this error.

' . . :TRANSLATE ADDRESS {rS HEX}The Translate Address Comrnard perfoms a logisahadtrees to physbal-dhoss translatbn. Certain SCSIcommatda irwska a Q[cal sdrees whhh may be Wto gA bn$ in bnsth. Vllhsn 4'st''ilrnard,is dst€c*ed's,hblrreqlires d#,€$ translatbn, tho'rcc€gsorffil relO$the lqgieal .address into ths gSCgSA LOGICAIADDRESS ro$ster snd then lsara the T,rEnElateAddress mrnrnar$ to have tfu gg0gqA do the"mmrer-sion; Upon receiviqg a lsuccs sftrl oorrpplbn' intor-rupt, lhs proces$of can red tte CYL${DER NI9MBER,HEAD NUMBER;,a;d SECTOR NUMBER ruffitBrc todf,tract the Fghal e*lress. Tho,ffik pqramot€rs @n*tsir"rW in the TOTAL SECTORS,,TOT:AL HEADS, sndTOTAL CYLINDERS rqisters rrust also be velid beforeis€rllr€ a Trandats Addrese oorurrard

tf a$tomatic conperusation for epars sectors ls to b'ppffifnlqd by tf€ ArnS$€ggA,,thn tfle runrbsr of sparesdQ*p,p6r c$irder and total rrumber of gec*oru"porcyffi,fiu$t 'als,bs bM; respedivsly, lnto theH EAD; hlul, B€ R ar$ OYLIIIOE R N t lt{BER roflstere.,-Atert$-ffiEd1 interrupt.wifl offur il arry divisbn operdionper,f@during this commard resu$s in an overflow.

:a 'Conblnaflon Levef ll CommandsSELECTTfiND.TRANSFER (OS AND Og HEX}The Solsc.t-and-Transf er mmmands $tsatry rsdrs-thghost sr bcal processu lrfrsnryt-fuandlirg burden byenstirlg,the gSCSilA's tilternaf rniuoproms$or to nnn-agp'ths b.w-lsvsl,,$C$f pffiml, resufiirE ln as fsuv eeone irtsfr,Upt', Ff S0$I,sperEtbil;' $OlSd Ard-Trarnsfercommande are used wheR in an Initiator rob, ard typi.calty corwbt of at teast the folhrirg SCSI phases: (1)Slwtbn of a Targ€il dsvice; (2' Ssndfqil d s srn-mar$; r{31 freceptiun ol $Blrrr! lrfrormstbn; ard t4}Rece$bm, of a CCFvIftfAND GOMPLETE Mossqo.Th€ss',ffir.1tmgrd$ optionally onsist of ' a' Data Trenglsphase ard additbnal Message TranSer phasas.

The SSCSA wilf update the COMMAND PHASE rqi$-ter a8 thg Sglgd-aruC-Transfer command execules.Upon mnpletbn or termination of the corunard, thehal processcr can read lhis regiser to dotennlnewhere $B SC$l operati,on $opped.

im$f,@$A+a[

Th$' ftvo,$glectand-Trensfer colrunards ditfer fromeffih other only by wherher or tu fire ffi-O;is il-ffird during $p Solection phase. The abiilty to ass€rtlrlf rturtru $efeetbn silrffirts ths ssl MeseagnProtoml whictr catfs for an |DENTTFY Message cjlrtphtee folkxring tho SsMiOn. tJVtton exeafiing aSelec{wATN-anc-Transer commands, the gtlcggA expectsths Tafsrst to r€gus$t a Meesags afi phase inrneoi-alely folbwirry eebdion, whersas for a select woATt{-ard-Trarufer @mrnar$, il expecls the Target todirectly enter command phaee. The selectanc-Trqnsfer @mmands, fiproover, suport Group 0(6-brte CD8), Group I (t0-byre CDB), and Group 5(l2-bfle CDB) SCSI commarxfs.

whsn a Selmt-erd-Transfer',comrnand is issued, the33c98A abitratds for the bus and sebcts a Targnt justag.durlru a selgct commard. lf tlp rar,gret does not-respord before a tirrpout occufs,. the seld-ancl-Transfer command hails ard a tenninated' irrtemrpt isgenerated. Failure to mnpbte ths sef86{ion phase isalse irdlcated by the fact that ttle cs{*tAND pHAsEreglstsr@rsslne all aBro8. lf fi,rg sbction is gLrcess{ul,rp intemrpt ls gen€ratod, h* tho contMAND pHAsEregister wiil be eet to a hex 10.

Ittr.r conpletirg the setoction phase,_l& g{tcgi}Abegins'an informatiori transfer Fhase. lf ffi tras beenassorted (i.e. a solect wATN-and-Transfer commarrdwas issued), the 3ilcggA expects the Target to respordwith a Messa€p Out phase. lf the first information phaseresiost ls other than a Message o,fi regro , the33c934 will terminate the command ard generate aterminatsd' intern pt. However, when tho Targst dse€request a Message but phase, the ggcgoA will-respordby automatically serdirp an IDENTIFY lieseage.'Thlssirqle byte messagp is of tho binary form: 1o00ttt,wh€ro r*'l if ths ENABLE RESELECTTON_ b,il h fhe$ouncE lD registor is eguat to 1, and ttt is tho ermdodTa,rget LoGlcAL uNtr NUMBER @ntained in theTARGET tuN register. once thE tDENfiF/ Messagoha$ been sent, the 33cg3A wiil set tho coMurutoPHASE register to hex A0.

Folbwjq.the Messrue o.rt phase (or setection phasewhen ATN w&s not as$rted during $electbn), a corn-mard phsss is ocpected by the OgCggA. Again, ardthrougflqrt ttrc entire Select-and-Transfer mmmardexscutbfi, if lhe Target reqresils an unexp€ded irilor-mation srase type, the 33cg3A termi:nates the conr-mand ard generates a "tsrmlnated" intemrpt. lf thecomrnard phase is requested in this situation, the33C9SA will eilmct the $csl command from the inter-nal colriMAND DEScRtPToR BLocK regsters ardsend thd 6-, l0-, or l2-by{es of commard information asdetermined by its evaluation of the scsf cornrnardcode in the CDB1 regisrer. The COMMAND PHASEregister is set to hex 30 before the first command byte issent and lhen increments with each byte transferred, sothat for a 12-byte CDB command the COMMAND

FHtqlregietor udtt ffiitain, hsx gS wt*cn d byfts ofthe cDB tuva been transfoffi::

Afterthe conrnand phass, the elcg3Asxpectg eittpreData In phase, Data Out phase, Stalus phase, or M€B-sage ln phase. lf the Targpt is re$lestlng a Mms*gu tnphase, a perdirg dlmnneGbn is eezuilrgd,

-The

SscggA tfpr€fors expods b rsogFe eilhar a,sry*Dd*Pointer fiEgsagp {hex 0e} or a Diffir,nffitmossage {hex 04}, ff.gfthr nussage ls h6ns$, or il f,differers msss4p is rmelvd;,a *ts|mlnatsd Frtemrywill be sneratBd to abrt tfn processor of that f8d ardto allor the messsgF to be read frcm tha DATA Fag,issr.A "tenninated" intemrpl will arso be generated lf theTarget dismnnects before sendirq

-the Dism*ntri

message. when a conect save-Dati-pointer messagpis receivsd, a pausedlaborted Interrupt is generatgdard the setect-and-Transfer commard terminated toafturtr ther processor to save the scsl rl-ata poirrt*r.However, if a Disconnect message is received, tlecoiTMAND PHASE register wiil be updatgd to hsr 4lanq commar$ exgcrltton mntinues,

:when the ac{ual ralgetdisconnection does offir, thsOOMMAND PHASE register is updated to hex 4if ard ffthe lDl bit b ast, tho *rnggcgsAterminates ths $bd-3$-Transrep oomrl#d by gonerattng an gstf internrpt.However, fi ths lDf bit is '.r€ssl, thgn lfrstead theArn33c93A sits in an ldle Btets, wailirg for the Target toreconnect. lt a different Target devile nesete{ili thg33c93A, a terminated' intemrfl is generated. Hour-ever, it the original Target Reselects-the BtlCgSA minterrupt is generated ard th8 CoMMAND pHAsEregister is set to hex 44.

Fotbwirg the originat rarget Reselsctbn, the gilcEgAexpcts a Massage In phase rtfiicfi eturu consbt ottha Taryst scrding an tDENTtFy Meesage. Thb sirgrFbyta iTrsssqF sfioutrl bo of fu blnery,ioum: .t000Qewhere ttt ls the Target LtrN. tr ths dsta roceived by ile3ltlc93A is dlfferent or ttre Target LUN,spdtsd h $risbyte does not match the conterts of the TARGET LUNregister, a 1erminatsd" intgnupt ls genetded ard ule'Message byte may be examined Ui the prooessor. Amnect'$gNTIFY ltfsssagp In phase resulte in theCOMMAND PHASE register being updatd to hsx 45.

After the IOENTIFY Message ls recaived firorn,,ttpTargel or imrnediatety after the commard out phase(when thore is rp dlsenn6ctbn), a,Da|g tn phase, Deteqn phase, or $aUs phase shou$, osur,. lf theTRAf{SFER couNT rwbtor cofitakur any rpn-r€K}value, then the 33cg3A win, expac* a Data Transferphaso. lf Advanced Features ar6 enslsd, thsn theDPD bit will be examined to verify the cons{t datadtrection. lf the data direc{bn is irrconecl, th€n'a "temi-nated" ifiemrpt is generated. In this phase, the ggcggAwill use the TRA^ISFER couNT register to determinethe number of bytes to be transfeffed, ard all host-sldeDATA register accesses will be acconprished via tfre

Aa€Sgg* It"$S

rrptW,ssbdd by ttls B[fA'nFdg sem bJ|s ln theSOS{TROL regrister. Wten $F htemalcqrnbr reetpgrefoi tho Deta Transfer phase is mmplete and theOO[dtrtAND PHASE register is set to hex 48.

Nots thet arry nlrbsr d disconnedbrVreconnectbn6yes may o@Jr durirg ttts Dda Trarusler phase sobrrg s*they art @rnplished acmrdirg to the defindrnessagp prolscol. The COMMA|,ID PHASE reglster willcyderthru4gh ths dimonnec{ phases (41-45} wist eachdiEmnnectkln snd a$mquen resnrection ur*il all sfths daia has been treriSened and $F Data Transferphaes is conplste.

A Status phase is expcted by th€ 33c93A folbwing theData Transter phase {or instead ol the Data Transterpfrass when the TRANSFER COUNT regi$er containsa yaluo of zem). At ttm start of the Statls phase, theCQI{IiAND PHASE register is foaded with hex 47.Upan mr$etion of the $atus phase, the COMMAf{DFHASE rcgister will be Wdated to hex 50, and therecoUEd status byte b storsd in the TARGET LUNreglstor where it can be read upon corrpfEtion ol theconnnanil.

Folbwirg completbn of the status{yte transfer, a Mes-sags ln ptr*o is expectd. Tho 33C93A expects thsTs$et to send a COMMAFID COIilPLETE Message(hex 00) to irdbate u|d the scsl cornmard operatbnhas ben mmplsted. Atter the 33G93A recelyes thisCOUU*UD CQMPLETE ilessage, the COMMANDPHASE ruglster advarpes to hex 60, and ll th EDI bit isresst, a "succss$ul completion' irilemrpt is generatedThe processor shoukl then read the TARGET LUNregrbter to examine the Target status. An additbnalir,{ernlpt will then mq.lrwhsr the SC$l hls gpss to theBur Froe stats, or ryften arclher REQ is asseiled tobryin an hilormatbn transfer pfrase (as in SCSI finftedcornrnars), lf the EDI blt is set, the "sumessful com-detiorf irilernpt will be suppressed until the Targetdbconn*{s fromthe scsf ht8.

At arry tims during executbn of the Select-ard-Transfer@mmands, an abnormal or unexpected conCition willcilrse ths SilCgSA to terminate th€ cotrunard, set theapproprise da&.ts qralifiors, ard generate a "tsrmi-nated' intemr$. lf ths termination ocarned durirg anlr,*ormdbn transfsf phaee, ths 33C93A trei$ be lsft in aC'gnnst#ae-dt'lm'tiatorsteto{unleesterrdnatbnwas*re to a afikfen Taqnt dismnnsclion). Cornmardterrrdnfrtion durirg any ottur phase will result in theS{IGSSA birr€ in a Dis@rrwtad Sate. Transfer com-rmr-,S$, may be ussd to handb ths exce$bn bytranEfsrrrhu mes$agas with .tb Targqt.

ThE lohwiru table surnrnarizesths possible values thatths CoMMAND PHASE register can take durirq theSelecl-ard-Transfer mnuTrards, ard their meaningsreletive to commard terminatbn:

hb SC$l hlr devb hs born aslodcd. Th.SilCgS ie in the disonnected state.

The Targot hes,,t'ffii ssHed. The SSCO3A bnow in the onneeiled s en hitiator stde.

An Een$y mos�agp hs'been sent to $eTaqnt.Cornmand phase has start€d, no b:ftestrandenedCommand phase, x bytes have beentrandened.Save-Dda-Pointer message received.

Disconfiest msae€t roe;eived, bus not fres,

Targra has disonneded (SCSf bus free)blbwir€ a sr,lresfuf fan$sr of a Dissrnedmessag.. The 33C93A is now in lhediscsrneeted stde.

The glC93A hs,been reselgc{ed by the Ter-get,wtloee SCSf hle lD mebhs the trdus }nthe DESTINATHIilI fD ngirt*. Ths gtl0ggA btw in ths omrcc'ted.as en hitids *tdo.The 33Cg3A has rmlsad an Hentfi meesqsfrom the Targd uhose Log*lel .Unit Numbermatdns the vahn in tho TARGET LUHregisfier.The number ol bytes specified in theTRANSFER CO|JNT regista have been trans-ferred tor{rom the Targst dwing a Data Ou/fnphase.

The Targst hubsgun a Reclw Stdurdrmo.

The 33C93A has smssfully rrceiued eSatus byte from ttre Tryget end cbred il h theTARGET LUN register.

The &3Cg.3A has suceeesfully rcoeiwd a Com-mand Compldo messry from the Target.

Colrrmd.Ffter fFlmng

1 0

3x

114243

&

45

46

:l

4750

60

A "FosutTts S6lsct-an&Tran$ef esmlmrd Is aseunpdufienevsr a normal €ebct-arxC-Trandef mnunard bissued while the SSCgilA is in the Confpd€d-lnitiatorstate. When the "Resume" is issued, the 33CggAexamines the COMMAND PHASE registerto detemrirpwhre to rs$art tho Select-ar*Transler onuftarxtexocutbn. Thi$ featurs, in sniur$lon wlth ttts]NTERM EDIATE DISCONNECT ]NTERRUPT eN*H€d,allowe support ol rnrlti-lhrsaded or ovet@Fd UO onthe SCSI br.rg.

Tho lollqilirq lable briefly descrhes tlrE valH eettit€s oftho coMMAt{D PHASE Fgister when rezurnirg aSelect-and-Transter comrnarud :

*s ailfltis9llA

Sotr-,*nrml' Pfp;; : rhwtffrf

lO Berumn afierT*tg* EeMion h eornpbte.fussme dt*1 Her*lfy qnqsagsout, Cornnrsddt$q b expecred; an implbd Negate AcKo@llr&

g0' Rgsuflre when C0mrnand pharo has begunFtEci asseiled).

41 Resurne after Gommand phase or after Save-Date.Pointer message. Dat+ Stslue, oriiloceage ln phases are expeded. An implledNegrde Ag( oetrs. '

42 Resume b cornplete Dirsmnnect Message h;an lmplfied Negde ACK oocurs.

U Resume after resdectbn by a Targd.

4$ Resurne b tranefer npr€ dala in e deta tr,*ns.ferphase. M.ly:Ipect Status or Message In asrseH. An irrplied Nqate ACK osurs.

46 Reeurne after the data phas€ has beonompleted, elpeciling Status.phase or a Saye,Dda-Poidon0bconnu Message ln phme.An imdied ilqde ACK does NOT oeGUr.

SO: Rsurno b oornpfde a StA,u* phcsq; enint1$i€d Nogate ACK oqlris-

80 Resurae to ondete a Command GonrSoterftess€gs from tho Tsrg*t,ail irftsied $fry*eACK o@urs.

FESELECT-A}|STf,*$|SFEn (0* Ar{D 0B HEX}The Rgse,bct-afSTransf,sr mnsnafds inclt.ds lfpRoeobct-end-RCegfug-Dgta arxil the Res€tect-gnd-Send-Data mmrnards. Thesc oorffnands cause the3ilC93A to execute certain common SCSI tus phasesquen€o es a Target folbrring a Reoelec[bn phase.Thsss ph*ees ars detennined by whlctt commar,d iseent; ard the ssttFE d tr,r€ bits: tho EDI bit in fiFCONTfiOL reglster; and ths SCC bit lp, thgDESTINATIOf.I lD register. The SCS| bus phasesotgJsncos ars surnrnarized bebw. Refer to the 6m-mard degcrisbne of ths Ssrd-Status-and€omrnand-Conplete ard Ssrd-Disconnec{-ilileseage comrnardsfor datnlH on tlloss mqlences.

1. Reselect-ard-R€osiw comrnand, EDld), ardSCC-don't care:. Ressle$bn pfrase;. Send ldentlly Mess4e ln;-r 'P|66,;u* Dfitg,Oilt phagn;. Corplelbn interupt

2. Reselect-ard-Serd commard, EDI=0, andSCC-dbn-l care:. Resebctbn phase;. Send ldsntlly Mesaago tn;. Serud Data In phase;. Comdsrnr'-it inte mrpt.

Csr*nendPhrm ttu*lng

Ho $C$l'bu$ d€vh0 has benn r.eselectsd. Thegg0g3A b in the dismnnw{ed state.The 33Gl9ttA has sumessfully reselec'ted theInltiator; The SCOSA ic now in {to mnectudas a Targst stats.Srs,Hsntily m$ssfrgls hs beon eurcesslullyasnt to the lniliamr.The, reguortod deta trengfer has beencomplatedi

3; ,R rsWfiSffi, ESI'ol, afHSGC=0:. Resdedbn pfiasC

'. Serd klenttry Messsg,s In;. Rgcgivg Data Slt pfme;. Cluinto S€rd-Stafirs & ConWte;

4. Resetect-ar$Serd mmmanil; EDl.l, and SCC-O:. Fg,sgbc[bn 'g€; ' ]

,,tt ',. ' '

. Serd ktentis Memage ln;

. $Erd:o*ie,ln'Fll*sei

. Chain to Serxt-Stdns-anG ;5. lgryne-arxi-Reeivs @mmard, EDI-I, And

SCC*I t , ,:. Reselection phase;. Serd ldentity triesoage ln;. Receive Data Ag phase;. Chain to Sen&Dle@nnecil-Messagn;

6. Resgle€il-arild"Ssfit oorffnard, EDI'"I, erd SCC-I:. Reseft$ctbn pheee;. Serui ldentify iltessegs ln;" ' s g r . d x t . D a t , a . t n f ; ' ' ] i . , ' . . �. Ghain to Serd-Die@nne€f-t*euuege .

lf lhs resoMbn attenetllmss out d,rlng a Ressb€fi-ar-,xFTrarelsr cortnarfld, ATN :,b,Sgtt$ ard FliA**, 6,rit a parity enor b &tocild on a lrwn{r,q dda bfio {erdH$P-l or,HHP*l,n'dgp0: - Ut o$ df,ta dir,ectkln), thscommard will bo tsrnindsd,sf,ld, ttle,,Sptrffiifrts statuswill tre sst"ln tf$s €aBrB, ths GS{UAI{D, FHA$S regs+rshoukl be evaluatsd |o dstermine thE last succeesfusycompbted Bhase ..lf Fmn€ sf :$saa blp Ecctffi, sllphases eorr,plste rsrmalh ard il EDI*O, tlpn a "$$S.cesslulcorrp|sqbn'intgfruF utoufd be gsrpra.�$d at thiepoirfr. However, if EDI*I, no lnterrug ls gernretod snd@rfirnarxt shain occurs {ae descrbsd abwe}

The folbrrirq tabb sufiunarizea the posslt*e vafues thatthe,CSW{I{$D FHA$E regiser scn taks &rilg,,lheReselsfit, r co_,rffnatdg, ard thair:rrpanjryS$re&atlv,g to'@fllrryrd tstminsttuln. $se gtfisr m$n-Hffid,&scr$lons for addllbnal vafuee that can oocur whencofiunard chalning ls us6d.

rg

m

1 0

e0

4S

ffi#ffi* +57

A " Rossbct€rtsTffisf comrmtd ,ls 8s-€ilffi urtlofrover a nonnaf "Rasglect and.Transefmrunard b bsued whlfe tho 33cg3A ie in theConnscilosas-a-Targot gtate. Whon thg "Resums" is is-flIod, tho 3itc93A examines the COMMAND PHASEregtsterto &termlne wtprc to redsil the Reselect-ard-Trandsr conmand sxscnsion. This feature, in confurn-tbn 1tt{h tm capabiRy to chain to other comblnatbnootnmfiftds, albrrs tonger SCSI bus sequen€s to beeroartsd by a sirqlo command.

The loffowirq table Hlefly descrbes the msaning of theCOil|MAND PHASE register when resuming aRes6,bd-s*Tnarrcfi er mmrnan*

Oonxnrnd?hrrr filemlrXg

Resume after lniti&r reselectbn is compbte;slart with Hedlly lbeerye Qut.Resume sfter Hentrfy mess{e out; etad withdata transfer phase. ll TRANSFER COT NT iszero, rp data tander Srce oocurs. ln eithersern, a chain to Er,dhsr contbindbn 6m-mard can occur if enabled.

WAIT.FOn SE[JECT-Ail DRECEIVE trc HERThe ttYalt-for€elect-an&Rmeive causes the SCSIAto Ulo ufitil il b eebctd bV an Inrliator, et which tirTp thstrlC.93A wl$ er*er tfn Target mode and nessage ardoorrrr*nd hto{rnatbn wS autornatkral[ be reguestsd.As sr optbn, th 3tlC93A rtvy be pognarnnnd to die-oor wlmn a SGSf red @rnmand is r€c€foed wfiibexect$Fq a Wail-fof€efecil-ar$Rgcelve @mmard.Usc d ttfr oomrfiand therefore eliminates tfere irtomrptsutrddr mnr ooqrr after sebctbn ard after eachengsSrenil SGSI bt.rs $rass, ard resuftrs in very shoilhrs iFA lirrp &rirg SCSf read mmrnards.

|| mwas acsert€d by the lnitiator durirg the sebctionptrmo, ,ths 3rc93A will firlil execute aR imsiedfrscoivo lrteosaga Oi$'oommand to get the f&ntlfyrrcsry I'rom the lnitiator, before cor*inuing on witirtb ir$id fresfve Conrnanf to receive tho SCSIcofn$fiand lrilormatbn. The SCSI @rnrilard irilonmt*)ntG0ts' wifl be silored In the CDB regstors (hexArftroosatm b 0E), and lt a wlH IDENTIfV rnassageF rumfusd, ils,if bo eared in tfie TARGET LUN reglster{tpx #rese 0n. Tfp nun$er of conunard bytesf€$rs€*sd by ttp 33c93A is deterrnined by the scslgrqp oads in ttE first byte of the cDB.

Afrer ths 33C93A is sebcted ard recsives all validmmrnard ard rnessagle infonnatbn, a 'successfulmfpletbn'intem4il will nonnally be generated to albrrth hcsf procossor to read out ard interpret the SCSICU8. lbwever, by $ettirg tho EDI bil prbr to issuing aWeil-for-$ebd-arxl-Racelv€ cor,nmand, the 33CggA issr$lod b Frform an automatb disonnect when aSCSf nad oomrnand b rmeived. Therefore, whenEDI-I and the lst CDB byte recsived contain$ a S,lD, or lz-byto read oorrnand code, then the 33CggA

wilf terporarilf supp'ress the InBrnry and cfiEFr bbegin executbn d a Seru&Dlsconnecil-Messago oonr-mard. An irffem.rfl willthen be generated after conple-tbn of this conrmanC, which rprmally wlld irdlcate atransition to the bus fres corditbn. Rs,fer to the Ssnd-Dismnnect-Message comrnard descriptbn for rprgdetails.

lf durirq execution the messago or command informa-tbn received frcm the lnitiator is irrualkl, the impfiedreceive @mmard will be terminated and the appropri-ate status reported. In this cas€, the COnlirfnifOPHASE register shoutcf be red to dstsrnine whicflphase of lhe Walt-for-$eld-ard-Receiye cornrnardwas la$ completed before tha ensr condition occnrned.A COMMAND PHASE hex value of hex 10 indimtesthat the 3ilCgSAwas euccessfully selected. A hex valueof 20 indicates that a illessagB ufas recelved from theInitiator, and when th€ 3itC93A @ins receMrg com-mard $[es, the COMMAND PHASE is set to hex 30ard increrents with each h[e reeived (to a nraxinuumof 3C for a l2-byte CDB commant).

The folbwirq tab'le sumrnarlzesthe possble valuesthatthe COMMAND PHASE regbtor can take drrir€ thgWait-for-Select-ard-Rseeive cofiunard, and tfreirmeanings rehtivo to commard tennimtbn. $es:sthrcomffi&rd descridbns for #lil)nel values that canoccur when oorrrnard cfialnirq b usd.

CommaldPtlrtc Hsrrtg

1 0

t0

s

t0

2A

30

The 33GSA has not besnrebc*ed, lTietrlC93A b in the disconneded state.The 33G93A hs been guccessfrdly sebctedby rh€ krilisr. The slcg3A is rpw in theconnec{ed as a Target silate.The Hentfi me*age has hn strcessft$frrecelvsd from the Initiator-Ths *lC$fA has begun snmard phass bysstting the SCSI hs phme srtlndu w$asserting RECI.The 33C93A has transfend ono flnmandbyte from thg Initidor. The SCSI STATUSmay indi,mte the negd for the hod to bad thecommand sizo into the OtAtll lD register.The 3ilC93A hae trarpfered x ommendbytes from the hifiabr.

31

3x

A "Resume Wait-for-Select-ard-Receive' commard bassumed whenever a normal Ytfaft-lor-Sebct-ard-Receive" orrnarrd ls issued whils tho 3s0ggA is in theConnected-as-a-Target state. When the ficsufns' isissued, the 33C93A examines the COMMAND PHASEregister to determine where to restart the t/tlait-for-Select-ard- Receive commard executbn. This fsature,in conjurrction with the capabillty to chain to other com-bination commaFtds, allqffs bngpr SC$l bus sequetrcesto be executed by a single command.

{ff AmSSSA

n.-:: lH'ff i*j ' : .1'*'besthemoant'gofthe2.cDB12bit0=.1,bit1-0:ThestauuMMANu Fl-fASr regtsterwhen rasuming a Wait-for. Bsnt, fofbwed., by e Linked, (Solect-ard-Rscsive cohnrarU:

.-

Fortbn of Wait;for-$elect-and-lCormard

l i l* , qn,qo,: :?Ji l i i lT_ff i":?i l f$J10 Resume after selecilbn by the Initiator is com- COmrnand.

p{eto; start with Hernify l#essage Out if ATN b , r_h,r . ,-,^.

asseried, otherwbg, starl ,with mmmand g. CDBIA bitO--i, bifl ot: The slal

phase. 8ent, folbtrd by a Lirked-Cornilesurne after a rns'Bags our; efrpck rhe re- Flag messruE (08 hsx). A chain to the cocsived messago in the TAHGET LUN regisrer fetch Fortion of Wait-for-select-and-Recehfor a valH ldentify msssage O€Cur8 to fotcfi ths next CDB from ths I

CDBll is sent, folloered by a Command Comptetemsssage (00 hex). A isuccessful compreiionl s0 Rosume sfter status F

30 Resume aftor Hentify messqe out. Start with 3elC93A frd eregutttn pcommand phase. for that mrnmard.

31 Resumo altsr the &?CggA hes transfened 1*nt"nsun"-irdili;iti"il.'iiil;;;;; A Serd-Status'and.Cqry6nd.Compfere corpoint is uEed onff whon an unknown group may be terminatsd by ffi asserted,,wh€fi H,6de heg bsen detected in Advanoed lr,lode, when a Disconnect or ffeeet connnard b isguerand the commard size has been loaded into

The forfowing tabre summ,ariaes th, ,. th? ow! f? tg.giltet ,, ' , the co[{MAND pHAsE regreterSEI{D_STA''*.AND€O$'*AN*GOM'LETE Send-Status-ard-Comman&Com(0D HHx)

'v nrlr '�r'vr"rr''rrrv-\'t/ilrr-rr*rE thgir rrpanings relatiig to cornlni

i"ne serd.sarus-and-commard-comprere command ::Tr"ffi"#ffiS St#ffiXi:il,;is vglid in the Target rola, ard ls used to mrwete aSCSI operation by transfening the appropriate status Commandinformation to the Initiator prbr to disconnection from Phase ftharthe scsl bus. This @mmard atso supports lirs<ed scsloperatbns by optionally allowing a'rinreC co1r11xgrd: 00 l*o oB*ratlrn occut?s

found lo be a$ertsd.compfete msssage to bo sent after the status is S0 Srq$d phss'iransfar ctransfened. Linked connnand oonplete fftsssages are il comrninc Gomptrile rcorilrolled by tho CDB1Z register with Oim mat COre. r'\'

gerod.spord to the standard linked onrnand controt bits in 6t ti;k; command comthe cDB

- il;t"d:'

f,Xff:-il,T$i5ffiif,ff:l$ffi;ffyg';ltffi; A "Resume send-srarus-and-(I sraru$ byre which witf rhen be rransrened across rhe ssil:lll-ffn:ffi..k$iffi'",scsl h.rs. Also, the fink contror bits from the currentcDB mustbe badedintothecDBr2 registerto ensrrre

while the 33c93A is in the Gcrhar rhe corrqq tleyer,rco ocours" Nore rhar rhe bils il:y,ilftsJffixffii3;xi:trflused by the 33C93A ar,e idsntical in meaning to the where to restart the $end_StiSCSI slandard link controt bits. The fE${ procgls_or may Comptete ,;;;nd'- executionsimply load ths control byte from theicunent SCSI cont- confrrrstbn wittr the capability to rmand into cDBlz to grst the correct furKtbn. As lhecommand execution-prosfssses, tn,

-cdrrrilNb ffiitrfrffiftffi,:ffijPHASE register witt b€ updsted to indicate the la$t

phase completed. The {otbwing tabte brtefry descrlberhe possible sequencss caused by this comrnand are 3ffilYffi":ffitrH1lil,rf:

r , ' , l , , - t - . , t , ' ,

I , , , , -as follows:

cornmand1. CDB12 bit0*O, gitl-dont care: The status byte in phrca ile*r

tr -il :ll rf$*"*"*"Xffi ;H',f ain to

irnsitwtA /*s0

gsilsDaco-ilH$cr.$EssAcE (0E HEI(}T[g $erxt-Dbmrred-Message smmard is a Target-role coFunArd nrhbh may be used to disqonnsct lromthe SCS| bus at sny time &rrirq a SCSI comrnandEogrsnce. T.hb wrlrnard mnsists of ssrdirg a Discon-@ messagq b.yto, fosouved bV phy$cal dlsconnactbnfrom tfre bus (SCSI bus free). An internr$ b generatedonly afier tnansfrion to bus free occurs. As an optbn, aSave-Data-fuirilgr rrrss4e will automatbal$ be sentbelore tho Discormect meseagp wheneverthe lDl blt iss6t prbr to iss rg thls cornrTlard.

The COMMAND PI{ASE register b updded dldrqexocutkm of ttle Son&Dismnnoct-Messqn commsndto irdicate bus Srase gtdtrs, After a,SarrsrDataP.ointerrns$ agp b sert, thE COMMAND PHASE will be set to4lH. Aftertho tllsconnect ;ressage transfer, this rogis-ter will bs updatsd $ 4AH, ard dler disconnedbn theCOMIIAND PFIASE reglster,will cortain a 4i]H.

A Send€isosnned-4lcssap eofirrtqff rny be terilS-nated byffi asserted whsn HA'.l, orwhen a Discon-nect or Reset comrnard is issusd.

The folbwing tabls supqtadzes the poaslble vafuesthstth6 COMMAND PH SE register can take during theSsrd-Disconnscf-Messagn, ard thslr rneanings relativeto oornmad terminatbn. Sse olher consnanC de*rip-tions, for d$tbnal valuss ,that can o6ur whgncamrmrd chainlrE is used.

CotrnraldPhesc Ithnlng

00

41

42{r

No operabn occuned; beically, Iffi wasfourd to be asserted.The Saw'Date-Pointer mesage was trans-ferred.The Discqn@ messege was trensferred.The bus fre ddo oeurrd afrer the Dlscon-neci messago was trandened. The 33C93A isnow in the diwnnec*ed ltale.

ETECTR,ICAL CHARACTERISNCS

ABSOLUTE lfAxllf UM nAT|hfgSVoltage on any prin with r*pect to GND -0.5 V to +7.0 V

Qpemting temperatureStorago lenperaturefuwor dbslpatbnlnpr$ Statb Discharge Protectbn

0 to 70 deg. C-65 to +125 deg. G

5@ mllll

2000 V prn lo ptn

'#f ,iii #; X':,H#;, i'##::,ffiffiat or eblp lhesE fiitrtfs� is rrit imf,iod. *psuro to atrnllv/relmaxlnun ratirrys tar extended prbds nay atfoc/. devicnrc,i&iw.

DC OPERATING CHARACTERISTICSTa - O b 70"C, VCC - +5 Vt0.25 V, GND - 0 V

S.ymbqf chrrd|rldb

lnput Lo*age

SQSf otrqn,tt Ledc4c {lnactive}qupul Leakage (Tri-State)

lnpu Hbh Voltage

Gondltbng

VS'l -.4to \rcC

VOttT - .5 to VCO

VOtT- .4 toVCC

il) . -4t10 ttAil} - 48.0 rnA

t) - 4.0 fiiA

Ta - +?S*

0.5

0.4

20

vV

v

vvv

mA

ilSO , Am3{ffi91}A