All Channels LTE Filtering System · One of these LTE (TDD) channels is the LTE band 38 occupying from 2570 to 2620 MHz. A goal to be reached, suggested by a Portuguese mobile phone

All Channels LTE Filtering System

Miguel Pereira Leite Fragoso

Thesis to obtain the Master of Science Degree in

Electrical and Computer Engineering

Examination Committee

Chairperson: Prof. João Manuel Torres Caldinhas Simões Vaz

Supervisor: Prof. José António Beltran Gerald

Member of the Committee: Profa Maria João Ramos Marques Coelho Carillho do Rosário

October 2013

II

Acknowledgments

It is of my wholehearted will to say a big and grateful thank you to the following persons:

To my Family that always supported me.

To my Friends that were always there in the good times and in the bad times.

To my Supervisor, José Gerald, who always corrected my mistakes and taught me plenty. The

lessons learned will stay with me forever. His friendly, professional and dedicated character have truly

inspired me.

To Professor Horacio Neto for always being so kind and available with his help in making me

understand the mistakes I was making in the VHDL code of the FPGA simulation.

III

Abstract 4G is the fourth and most recent generation of mobile communications standards; LTE (Long Term

Evolution), marketed as 4G LTE, is a standard for high-speed data mobile phones and data terminals.

It uses scalable channel bandwidths of 5 to 20 MHz (optionally up to 40 MHz).

Governments of many European countries (as for instance, Portugal) are releasing (licensing)

these LTE bands to private Institutions. The exhaustive use of this spectrum makes it difficult to avoid

interference from adjacent channels, limiting the signal data rate. Very selective channel filtering is

thus mandatory and suitable filters have to be developed for that purpose.

One of these LTE (TDD) channels is the LTE band 38 occupying from 2570 to 2620 MHz.

A goal to be reached, suggested by a Portuguese mobile phone company, is to design a filter with

central frequency 2585 MHz and 20 MHz of bandwidth achieving 80 dB attenuation at 5 MHz beyond

each side of the band. This kind of very selective filter does not exist in the market today. To note that

this filter was supposed to be applied to LTE band 38.

A functional filter architecture with the previous mentioned filtering properties and suitable for being

used in almost any LTE band (not only in band 38) is proposed in this thesis. The filtering system’s

behavior is fully simulated using MATLAB and the FPGA block using ISE.

Keywords: All channels, LTE Filter, Downconversion, FPGA, Upconversion, Simulations.

IV

Resumo 4G é a quarta e mais recente geração de normas de comunicações móveis; LTE (Long Term

Evolution) comercializado como 4G LTE é uma norma de dados de alta velocidade para telefones

móveis e terminais de dados. Esta utiliza canais escaláveis com largura de banda entre 5 e 20 MHz

(opcionalmente pode subir até 40 MHz).

Governos de muitos países Europeus (como por exemplo Portugal) estão a libertar (licensiar) estas

bandas LTE para instituições privadas. O uso exaustivo do espectro torna difícil evitar a interferência

de canais adjacentes, limitando a velocidade de transferência de dados do sinal. Uma filtragem muito

selectiva de canais é então obrigatória e filtros adequados necessitam de ser desenvolvidos para

esse propósito.

Um desses canais LTE (TDD) é a banda LTE 38 que ocupa desde 2470 a 2620 MHz.

Um objectivo a ser alcançado, sugerido por uma empresa de comunicações móveis Portuguesa, é

desenhar um filtro com frequência central 2585 MHz e 20MHz de largura de banda, que alcance 80

dB de atenuação em apenas 5 MHz para além de cada um dos lados da banda. Este tipo de filtro,

muito selectivo, não existe no mercado actualmente. Note-se que é aplicar este filtro à banda LTE 38.

Uma arquitectura funcional do filtro com as propriedades previamente mencionadas e além disso

adequada para ser usada na grande maioria das bandas LTE (e não apenas na banda 38) é proposta

nesta tese.

Palavras Chave: Filtro LTE, Qualquer Canal, Downconversion, FPGA, Upconversion,

Simulações.

V

Contents Acknowledgments ...............................................................................................................................II

Abstract .............................................................................................................................................III

Resumo ............................................................................................................................................ IV

List of Figures .................................................................................................................................. VII

List of Tables .................................................................................................................................... XI

Acronyms List ................................................................................................................................. XIII

1. Introduction ............................................................................................................................. XIV

1.1 Introduction ........................................................................................................................... XIV

1.2 Filter Specifications ............................................................................................................... XIV

1.3 LTE Bands ............................................................................................................................. XV

1.3.1 Band 1 ............................................................................................................................. XV

1.3.2 Band 2 ............................................................................................................................. XV

1.3.3 Band 3 ............................................................................................................................. XV

1.3.4 Non Supported Band ....................................................................................................... XV

1.4 General Architecture .............................................................................................................. XV

1.5 Dissertation Outline ............................................................................................................... XVI

2. Downconversion ........................................................................................................................ XVII

2.1 Introduction .......................................................................................................................... XVII

2.2 Downconversion Block (Block A) ......................................................................................... XVIII

2.3 Downconversion Block SNR ................................................................................................... XX

2.3.1 Downconversion Block initial SNR ................................................................................... XX

2.3.2 Downconversion Block SNR Degradation ....................................................................... XXI

2.4 Mixers .................................................................................................................................XXIV

2.4.2 Up mixing and Down Mixing..........................................................................................XXIV

2.4.3 Mixing modes and concepts...........................................................................................XXV

2.4.5 Noise Figure ............................................................................................................... XXVIII

2.4.6 Downconversion Mixer Selection ..................................................................................XXIX

2.5 Down Conversion Process ...................................................................................................XXX

2.5.1 First Step .......................................................................................................................XXX

2.5.2 Second Step .............................................................................................................. XXXVI

2.5.3 Pre-Processing Before the Analog to Digital Conversion ........................................... XXXVII

2.5.4 Simulated range of the Attenuation filters in the Down conversion Block .......................... XL

3. FPGA Block ............................................................................................................................... XLII

3.1 Introduction .......................................................................................................................... XLII

3.2 ADC ..................................................................................................................................... XLII

3.2 Digital Filter .................................................................................................................... XLV

VI

3.2.1 Digital Filter Higher Level Design for the FPGA .............................................................. XLV

3.2.2 Digital Filter Lower Level Design for the FPGA ............................................................ XLVIII

3.3 Equalizer ....................................................................................................................... XLIX

3.4 DAC .........................................................................................................................................LI

4. Upconversion ................................................................................................................................ LII

4.1 Introduction ............................................................................................................................. LII

4.2 Upconversion Block (Block B) ........................................................................................... LIII

4.3 Upconversion Block SNR ....................................................................................................... LV

4.4 Up Conversion Process .................................................................................................. LVII

4.4.1 First Step ....................................................................................................................... LVII

4.4.2 Second Step ................................................................................................................ LVIII

5. Matlab and FPGA Simulations ................................................................................................. LXVIII

5.1 Single Run Matlab Simulation ............................................................................................ LXVIII

5.1.1 OFDM Signal generation ............................................................................................ LXVIII

5.1.2 Analog Filters Simulation .............................................................................................. LXIX

5.1.3 Matlab Simulation Results ............................................................................................ LXIX

5.2 FPGA Simulation ............................................................................................................. LXXXV

5.3 Multiple Run Matlab Simulation ...................................................................................... LXXXVI

6. Final Remarks .................................................................................................................... LXXXVIII

6.1 Future Work ................................................................................................................. LXXXVIII

6.2 Conclusions ................................................................................................................... LXXXIX

7. References .................................................................................................................................. XC

Appendix ...................................................................................................................................... XCIII

1.1 LTE Bands details ............................................................................................................... XCIII

2.1 Algorithm for SNR Degradation determination ..................................................................... XCV

2.2 Single MosFET Mixer Analysis ........................................................................................... XCVI

2.3 Tables of functional filters’ components ............................................................................ XCVIII

2.5 Filter conversion to Microstrip line technology ......................................................................... CII

3.1 ADC - Some important specifications ..................................................................................... CIV

3.2 ADC – Types of Error ............................................................................................................. CV

3.4 Study of IIR filters as the FPGA Digital Filter .................................................................. CVIII

3.5 Detailed Information of FIRs’ hardware implementation .................................................. CVIII

5.1 Recursive Calculations For Filters’ Frequency Response Matlab Simulation .......................... CIX

5.2 IP3 Error after each mixing step............................................................................................ CXII

VII

Pages

List of Figures Figure 1.1 – Ideal LTE filter specifications……………………………………………………………………………...XIV

Figure 1.2 – Filtering system’s general architecture. ………………………………………………………………….XVI Figure 2.1 – Used architecture for block A……………………………………………………………………………XVII Figure 2.2 – Scheme that exhibits the operation of block A1………………………………………………………..XVIII Figure 2.3 – A simple scheme of a downconversion mixer………………………………………………………….XXIV Figure 2.4 – A simple scheme of an upconversion mixer……………………………………………………………XXIV Figure 2.5 – Operation of an ideal downconversion mixer for a single frequency signal. ……………………….XXIV Figure 2.6 – Operation of an ideal upconversion mixer for a single frequency signal…………………………….XXV Figure 2.7 – Schematic of a simple and representative continuous non-linear mode mixer……………………...XXV Figure 2.8 – Graphical determination of the third order intercept point……………………………………………XXVII Figure 2.9 – Ring mixer waveforms…………………………………………………………………………………..XXVIII Figure 2.10 – Noise generated by a downconversion image band in the frequency domain……………………XXIX Figure 2.11 – Schema of the downconversion of the signal to 600 MHz…………………………………..............XXX Figure 2.12 – Illustration of band 1 and the matching dynamic range of the LO frequency……………………...XXXI Figure 2.13 – Highest frequency image band and LTE lower frequency band in band 1. …………………….XXXII Figure 2.14 – HP Filter Specifications to Reject the Image Band of Band 1……………………………..............XXXII Figure 2.15 – HP Filter Circuit to Reject the Image Band of Band 1……………………………………...............XXXII Figure 2.16 – Illustration of band 2 and the matching dynamic range of the LO frequency…………………….XXXIII Figure 2.17 – Highest frequency image band and respective LTE band in Band 2……………………………..XXXIII Figure 2.18 – HP Filter Specifications to Reject the Image Band of Band 2……………………………………..XXXIV Figure 2.19 – HP Filter Circuit to Reject the Image Band of Band 2……………………………………………...XXXIV Figure 2.20 – Illustration of band 3 and the matching dynamic range of the LO frequency. …………………..XXXIV Figure 2.21 – Highest frequency image band and respective LTE band in Band 3. …………………………….XXXV Figure 2.22 – High Pass Filter Specifications to Reject the Image Band of Band 3……………………………..XXXV Figure 2.23 – HP Filter Circuit to Reject the Image Band of Band 3……………………………………………...XXXVI Figure 2.24 – Schema of the downconversion from 600MHz to a 60MHz……………………………………….XXXVI Figure 2.25 – HP filter Specifications to Reject the Image Band before 2nd downconversion step…..............XXXVI Figure 2.26 – HP Filter Circuit to Reject the Image Band before 2nd dowconversion step…………………...XXXVII

VIII

Figure 2.27 – Schema of the replica generation of the signal digitalization process…………………………...XXXVII Figure 2.28 – Digitalizing a band pass signal in 60MHz with an 푓 of 250 MSPS…………………….............XXXVIII Figure 2.29 – Adjacent Replicas interference in digitalizing the band pass signal. ………………………......XXXVIII Figure 2.30 – Band pass filter for cleaning the signal spectrum of the input of the ADC……………………..XXXVIII Figure 2.31 – Low pass filter to attenuate the LO tone inserted in the second mixing step………………………...XL Figure 3.1 – Internal constitution of the FPGA block…………………………………………………………………..XLII Figure 3.2 – Magnitude response of Equiripple solution with 퐴 = 1푑퐵……………………………………..........XLVI Figure 3.3 – Simplified example of a systolic parallel FIR implementation. ……………………………………...XLVIII Figure 3.4 – Simplified example of a symmetric systolic parallel FIR implementation…………………………....XLIX Figure 3.5 – Frequency response of the FIR equalizer designed……………………………………………………….L Figure 4.1 – Architecture to be used to construct block B. …………………………………………………………….LIII Figure 4.2 – Scheme that exhibits the operation of block B1………………………………………………………….LIV Figure 4.3 – Schema of the upconversion of 60MHz to 600MHz……………………………………………............LVII Figure 4.4 – Response of Band Rejection Filter to attenuate 540 MHz LO leaked tone . ………………...........LVIII Figure 4.5 - BR Filter Circuit to attenuate the LO leaked tone in 540 MHz. ………………………………………LVIII Figure 4.6 – Schema of of upconversion from 600 MHz to LTE band chosen……………………………………...LIX Figure 4.7 – Response of HP Filter to reject the variable LO leaked tone in Band 1………………………………LXII Figure 4.8 – HP Filter Circuit to Reject the Variable LO leaked tone in Band 1…………………………………….LXII Figure 4.9 – Response of HP Filter to reject the LO leaked tone in Band 2 Sub Band 1………………………….LXII Figure 4.10 – HP Filter to reject the LO tone in in Band 2 Sub Band 1………………………………..……………LXIII Figure 4.11 – Response of HP Filter to reject the LO leaked tone in Band 2 Sub Band 2………………............LXIII Figure 4.12 – HP Filter to reject the LO leaked tone in Band 2 Sub Band 2……………………………………….LXIII Figure 4.13 – Response of HP Filter to reject the LO leaked tone in Band 2 Sub Band 3……………………….LXIV Figure 4.14 – HP Filter to reject the LO leaked tone in Band 2 Sub Band 3………………………………...........LXIV Figure 4.15 – Response of HP Filter to reject the LO leaked tone in Band 3 Sub Band 1………………………..LXV Figure 4.16 – HP Filter to reject the LO leaked tone in Band 3 Sub Band 1………………………………………..LXV Figure 4.17 – Response of HP Filter to reject the LO leaked tone in Band 3 Sub Band 2……………………......LXV Figure 4.18 – HP Filter to reject the LO leaked tone in Band 3 Sub Band 2……………………………………….LXVI Figure 5.1 – Scheme of the generation of an ofdm signal centered at frequency 푓…………………………….LXVIII Figure 5.2 – Power spectrum at the entrance of block A……………………………………………………............LXX Figure 5.3 – Zoom in of power spectrum of signal at the entrance of block A………………………...................LXX Figure 5.4 – Power spectrum after HP Band 3………………………………………………………………………..LXXI

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Figure 5.5 – Zoom in of power spectrum of the signal after HP Band 3…………………………………………..LXXI Figure 5.6 – Power spectrum after the Down Conversion first mixing step……………………………………….LXXII Figure 5.7 – Power spectrum of the LO Isolation error………………………………………………………...........LXXII Figure 5.8 – Zoom in of power spectrum of signal after DC 1st mixing step……………………………….........LXXIII Figure 5.9 – Power spectrum after second Image band Rejection Filter………………………………………….LXXIII Figure 5.10 – Zoom in of power spectrum of signal after FRI2…………………………………………………….LXXIV Figure 5.11 - Power spectrum after the Down Conversion second mixing step…………………………………LXXIV Figure 5.12 – Zoom in of power spectrum of signal after DC 2nd mixing step………………………….………LXXV Figure 5.13 - Power spectrum after the Pre Processing Band Pass Filter………………………………………..LXXV Figure 5.14 – Zoom in of power spectrum of signal after the Band Pass Filter. ……………………………….LXXVI Figure 5.15 - Power spectrum after the Pre Processing Low Pass Filter…………………………………………LXXVI Figure 5.16 – Zoom in of power spectrum of signal after the Low Pass Filter………………………................LXVII Figure 5.17 - Power spectrum after the Analog to Digital Converter………………………………………............LXVII Figure 5.18 - Power spectrum after Normalization before the FPGA Digital Filter………………………………LXVIII Figure 5.19 - Power spectrum after FPGA Digital Filter, after Renormalization. ………………………………..LXVIII Figure 5.20 - Power spectrum after FPGA Equalizer and power adaptation for 1st UC mixer………………….LXXIX Figure 5.21 - Power spectrum after Oversampling..…………………………………………………………………LXXX Figure 5.22 - Power spectrum after the Sample and Hold………………………………………………………….LXXX Figure 5.23 - Power spectrum after the DAC ideal Low Pass Filter………………………………………………..LXXX Figure 5.24 - Power spectrum after first Upconversion mixing step. ……………………………………………..LXXXI Figure 5.25 - Power spectrum after Upconversion first Image Band Rejection Filter. ………………………….LXXXI Figure 5.26 – Filter response of BR Filter, that functions as Notch at 540 MHz………………………………...LXXXII Figure 5.27 - Power spectrum after “Notch” at 540 MHz…………………………………………………….........LXXXII Figure 5.28 - Power spectrum after the Upconversion second mixing step……………………………….......LXXXIII Figure 5.29 – Zoom in of power spectrum of the signal at IF and of its respective image band……………...LXXXIII Figure 5.30 - Power spectrum after HP Band 3……………………………………………………………………LXXXIV Figure 5.31 - Power spectrum after HP filter structure to reject the variable LO tone (block B1)………........LXXXIV Figure 5.32 – Zoom in of power spectrum of signal after block B1…………………………………...………….LXXXV Figure 5.33 – Comparison between FPGA simulated in ISE and simulated in MATLAB..……………………LXXXVI Figure 5.34 - Power spectrum at end of LTE filter, Montecarlo Simulation of 15 sequential runs…………..LXXXVII Figure 5.35 – Zoom in of power spectrum of Montecarlo Simulation. See ripple and SNR………………….LXXXVII

X

Figure a2.1 – First equivalent circuit with ideal transmission lines of the LP filter…………………………………...CII Figure a2.2 – Kuroda identities. Case a)………………………………………………………………………………...CIII Figure a2.3 – Kuroda identities. Case b)……………………………………………………………………………......CIII Figure a2.4 – Transmission line filter schematic after insertion of 2 unit elements………………………...............CIII Figure a2.5 – Transmission line filter schematic after application of the Kuroda identities……………………….CIV Figure a3.1 – Graphical representation of the SFDR in dBc and dBFS……………………………………………..CV Figure a3.2 – Representation of a generic and ideal DAC transfer function…………………………………………CV Figure a3.3 – Representation of an ideal 3 bit DAC transfer function………………………………………………...CV Figure a3.4 – ADC offset error graphical example……………………………………………………………………..CVI Figure a3.5 – ADC gain error graphical example. ……………………………………………………………………..CVI Figure a3.6 – ADC DNL error graphical example………………………………………………………….................CVII Figure a3.7 – ADC INL error graphical example..……………………………………………………………………..CVII Figure a3.8 – Simplified serial FIR implementation………………………………………………………….............CVIII Figure a3.9 – Example of a transposed parallel FIR implementation………………………………………………..CIX Figure a5.1 – Ilustration of a generic lumped component filter of even order……………………………………….CIX Figure a5.2 – General representation of a lumped component filter of odd order…………………………………..CX Figure a5.3 – Capacitor and respective impedance…………………………………………………………………..CXI Figure a5.4 – Inductor and respective impedance……………………………………………………………………CXI Figure a5.5 – Inductor and capcitor in parallel and respective impedance…………………………………………CXI Figure a5.6 – Inductor and capcitor in series and respective impedance…………………………………………..CXI

Figure a5.7 – IP3 error after first downconversion mixer……………………………………………………………..CXII Figure a5.8 – IP3 error after second downconversion mixer…………………………………………………………CXII Figure a5.9 – IP3 error after first upconversion mixer………………………………………………………………..CXIII Figure a5.10 – IP3 error after second upconversion mixer. ………………………………………………………...CXIII

XI

Pages List of Tables

Table 2.1 – SNR degradations of each section of block A…………………………………………………………....XXII Table 2.2 – Most important specifications of the chosen mixer as downconverter 1 and 2……………………….XXX Table 2.3 – Attenuation of Downconversion block filters with ideal value components…………………………….XLI Table 2.4 – Attenuation of Downconversion block filters with highly biased components…………………………XLI Table 3.1 – Most important specifications of the chosen ADC……………………………………………………….XLIV Table 3.2 – Error specifications of the chosen ADC…………………………………………………………………..XLIV Table 3.3 – Minimum order FIR filters that meet the specifications using Equiripple methods…………………..XLVI Table 3.4 – Minimum order FIR filters that meet the requirements using windows………………………………..XLVI Table 3.5 – Equalizer specifications and output response……………………………………………………................L Table 3.6 – Most important datasheet characteristics of DACs working at 250 MSPS……………………...............LI Table 4.1 – SNR degradations of the first 3 sections of block B………………………………………………………LVI Table 4.2 – SNR degradations of the specific sections transversed by signals of Band 1…………………………LVI Table 4.3 – SNR degradations of the specific sections transversed by signals of Band 2………………………...LVII Table 4.4 – SNR degradations of the specific sections transversed by signals of Band 3……………………......LVII Table 4.5 – Minimum Attenuations of all Variable LO Rejection Filters……………………………………………....LXI Table 4.6 – Minimum LO attenuation required and actual LO attenuation…………………………………………LXVI Table 4.7 – Safety margins accomplished in LO attenuation………………………………………………………...LXVI Table 4.8 – Attenuation of Upconversion block filters with ideal value components……………………………...LXVII Table 4.9 – Attenuation of Upconversion block filters with much deviated value components………………….LXVII Table a1.1 – FDD Downlink LTE bands included in band 1…………………………………………………………XCIII Table a1.2 – FDD Uplink LTE bands included in band 1…………………………………………………………….XCIII Table a1.3 – FDD Downlink LTE bands included in band 2 and……………………………………………..........XCIV Table a1.4 – FDD Uplink LTE bands included in band 2……………………………………………………………XCIV Table a1.5 – TDD LTE bands included in band 2…………………………………………………………………….XCIV Table a1.6 – TDD LTE bands included in band 3…………………………………………………………………….XCIV Table a1.7 – TDD LTE bands included in the non supported band…………………………………………...........XCV Table a2.1 – Components of the Image Band Reject Filter of Band 1……………………………………………XCVIII Table a2.2 – Components of the Image Band Reject Filter of Band 2……………………………………………XCVIII Table a2.3 – Components of the Image Band Reject Filter of Band 3……………………………………………XCVIII

XII

Table a2.4 – Components of the image Band Reject Filter FRI2…………………………………………..............XCIX Table a2.5 – Components of the Band Pass Filter before the LP filter……………………………………............XCIX Table a2.6 – Components of LP Filter before the ADC………………………………………………………………XCIX Table a2.7 – Components of the BR Filter to attenuate the 540 MHz leaked LO tone…………………………...XCIX Table a2.8 – Components of the Band 1 Variable LO tone rejection filter……………………………………………..C Table a2.9 – Components of the Band 2, Sub Band 1, LO tone rejection filter………………………………………..C Table a2.10 – Components of the Band 2, Sub Band 2, LO tone rejection filter………………………………………C Table a2.11 – Components of the Band 2, Sub Band 3, LO tone rejection filter……………………………………...CI Table a2.12 – Components of the Band 3, Sub Band 1, LO tone rejection filter……………………………………...CI Table a2.13 – Components of the Band 3, Sub Band 2, LO tone rejection filter……………………………………...CI Table a3.1 – Minimum order IIR filters that meet the specifications………………………………………..............CVIII

XIII

Acronyms List

Acronyms Meaning ADC Analog to Digital Converter BW Bandwidth BP Band Pass BR Band Reject

DAC Digital to Analog Converter dBC dB Carrier

dBFS dB Full Scale DC Direct Current

DNL Differential Non linearity DPDT Double Pole Double Transfer DSP Digital Signal Processor

ENOB Effective Number Of Bits FDD Frequency Division Duplexing FIR Finite Impulse Response

FPGA Field Programmable Gate Array FSR Full Scale Ratio HP High Pass IF Intermediate Frequency

IMD Intermodulation Distortion INL Integral Non Linearity IIR Infinite Impulse Response IP3 Third Order Intermodulation Point ISE Integrated Sofware Environment LO Local Oscillator LP Low Pass

LSB Least Significant Bit LTE Long Term Evolution

MSPS Mega Samples Per Second MUX Multiplexer

Nchips Number of chips Nsc Number of sub carriers NSD Noise Spectral Density QAM Quadrature Amplitude Modulation QPSK Quadrature Phase Shift Keying OFDM Orthogonal Frequency Division Multiplexing RAM Random Access Memory RF Radio Frequency SA Sidelobe Attenuation

SFDR Spurious Free Dynamic Range SINAD Signal to Noise And Distortion Ratio SNR Signal to Noise Ratio SPDT Single Pole Double Transfer TDD Time Division Duplexing TOIP Third Order Intercept

XIV

1. Introduction

1.1 Introduction Nowadays there is a great need of available spectrum in order to satisfy the needs created by recent

technology in the communications domain. A good example is internet everywhere, which is becoming

faster and faster. Therefore, the number of allocated bands for use has increased as the pressure

increases on spectrum.

The filter system designed in this thesis is meant to help solve this very problem, enabling a very good

isolation between signals in adjacent bands. Note that 5MHz is a very short and demanding spacing

between channels to achieve attenuations higher than 60 dB of the adjacent channel to be rejected.

Attention was taken, so that the filtering, although designed to work primarily between frequencies

2575 and 2595 MHz, would work for any 20 MHz or lower bandwidth channel of the big majority of the

existent LTE bands. In this way, it is a highly flexible solution that can help to increase the data rates

and efficiency of spectrum management of most LTE bands.

The technique adopted consists of a 2 step downconversion of the signal (for instance the 2.585 GHz

TDD-LTE input signal) to a suitable IF (60 MHz), perform a bandpass digital filtering and then to

upconvert, in the same fashion, the filtered signal back to the initial band. To note that this specific

filtering system is presently a market innovation.

1.2 Filter Specifications The ideal specifications of the filter, initially requested by the Portuguese mobile phone company, are

displayed in figure 1.

Figure 1.1 – Ideal LTE filter specifications.

As one can see these specifications represent an extremely selective filtering, and surely this fact is

the reason why one can not find this product in the market today.

XV

1.3 LTE Bands LTE uses scalable channel bandwidths of 5 to 20 MHz (optionally up to 40 MHz). Currently the LTE

bands between 1 and 22 are reserved for FDD (Frequency Division Duplexing), and LTE bands

between 33 and 41 are reserved for TDD (Time Division Duplexing). [1]

For convenience, the LTE Bands researched were divided in 3 major bands, band 1, band 2 and band

3. There are downlink LTE bands, uplink LTE bands and TDD LTE bands, which are spread across

the 3 specified major bands. In the next section all these specifications are going to be presented on

tables for each major band.

It is relevant to state that, in some cases, the uplink and downlink channels in a FDD band can be

filtered and thus separated, using the developed LTE digital filter. For this to be possible, the band

gap between the uplink and the downlink bands must be at least 5 MHz. That is always the case. Also,

and more constraining, the width of the band to be filtered must be equal or less than 20MHz.

This procedure would work in all the FDD duplex bands of band 1 except 1 and in about 1/4 th (3/11)

of FDD bands in band 2. Nevertheless, the filter simulated would work in any of the bands discussed

(1,2 or 3) as long as the center frequency of the filter is chosen so that the edge frequencies in the

passband of the filter are inside the respective band (1,2 or 3).

In the following section, an overview of the LTE bands and their division through the 3 major bands

decided is given. For more information see section 1.1 in the appendix.

1.3.1 Band 1 The band 1 goes from 698 MHz to 960MHz. The LTE Bands in band 1 are the represented in tables 1

and 2 in the appendix, section 1.1.

1.3.2 Band 2 The band 2 goes from 1427.9 MHz to 2200 MHz. The LTE Bands in band 2 are exposed in tables 3, 4

and 5 in the appendix, section 1.1.

1.3.3 Band 3 The band 3 goes from 2300 MHz to 2690 MHz. LTE Bands in band 3 are presented in table6 in the

appendix, section 1.1.

1.3.4 Non Supported Band This band goes from 3400 MHz to 3800 MHz and is composed by the LTE bands exhibited in table 7

in the appendix.

1.4 General Architecture The design choice of the architecture to solve the proposed problem is depicted in figure 1.

XVI

Figure 1.2 – Filtering system’s general architecture This filtering system architecture will filter a 20MHz band centered anywhere between 708 MHz and

2680MHz. This arquitecture covers this filtering in 41 out of 43 existent LTE bands. It achieves almost

80 dB attenuation, in just 5 MHz for both sides of the band. Block A basically downconverts the signal

to a low frequency, of the order of tens of MHz. The signal is then analog to digital converted and the

FPGA block main function is to implement a FIR that digitally filters the signal with the pretended

quality. After a digital to analog conversion, B Block finally upconverts the signal to its original

frequency.

An alternative architecture using circulators was considered but its cost was excessive and it was

therefore discarded as a valid option.

1.5 Dissertation Outline In chapter 2, the downconversion block (Block A in figure 1.2) constitution is exhibited and explained.

The SNR degradation in the block is studied and a theoretical introduction to mixers is given. The

downconversion steps and principles of operation of the mixing process steps, are stated and the

preparing of the signal to be digitalized is discussed. Finally, the process of analog to digital

conversion and its impact is explained. All the equipment choices are justified.

In chapter 3, the FPGA block (in figure 1.2) is examined. The optimum digital filter to be implemented

in the most acessible FPGA possible is obtained. The equalizer that follows to dimished the signal

distortion intoduced by the LTE filtering chain is projected and studied. At last, the digital to analog

conversion of the signal after leaving the FPGA is specified.

In chapter 4, the upconversion block (Block B in figure 1.2) constitution is exposed and explained. The

SNR degradation in the block is studied. The upconversion steps and principles of operation of the

block are stated and the more complex process of rejection of variable frequency image bands and of

variable frequency local oscilator leaked tones is discussed.

In chapter 5, the OFDM signal generation in Matlab is detailed and the method of simulation in Matlab

of the fucntional analog filters used, is explained. The results of the Matlab simulation of whole LTE

filtering chain are discussed. A Monte Carlo simulation of 15 sequential runs is made and its outputs

are evaluated. A comparison between the simulation of the FPGA in Matlab (software simulation) and

in Xilinx ISE (Integrated Software Environment) (hardware simulation) is also performed.

XVII

2. Downconversion 2.1 Introduction To achieve the filter specifications presented in section 1.2, it is mandatory to downconvert the signal

coming from the antenna to a low frequency (of the order of tens of MHz). To note that the core of the

designed LTE filter is a digital filter. Aside from being a much more flexible solution, this is the best

option because to achieve 80 dB attenuation in 5 MHz of transition band is too stringent a specification

to be achieved using a bandpass analog filter.

The downconversion is done in 2 steps. In the first step there is a downconversion of the 20MHz

bandwith chosen LTE band to a center frequency of 600MHz. Finally there is a downconversion from

the 600 MHz to a center frequency of 60MHz.

In section 2.2, an overview of the downconversion block is exhibited. The most important information

of the block, architecture wise, is stated along with the explanation of some choices that were made

related to hardware, frequency, etc.

In section 2.3, the amplifications and attenuations, performed to maintain good values of SNR along

the entire downconversion chain, are explained.

In section 2.4, a theoretical explanation of mixers operation is given. Finally a mixer is selected among

many options. In sub section 2.3, the reasoning behind the presence of the analog filters in block A, is

presented along those filters required specifications.

In section 2.5, the downconversion process is described in detail. The preprocessing before the ADC

is discussed. For each filter designed, an example of its circuit is presented.

A simplified explanation for block A operation will now be given.

Block A input comes from the antenna and, depending on the LTE band to be filtered, the frequency of

the programmable local oscillator is set. We start with block A1 followed by a mixer. This mixer will

downconvert the signal to 600 MHz. A1 is basically a block that performs the image rejection

necessary before this first downconversion step. This image rejection is dependent on the major band

in which the signal is present (band 1, 2 or 3 defined in section 1.3). This block’s constitution is

represented in figure 2.2.

Figure 2.2 – Scheme that exhibits the operation of block A1 included in figure 2.1 .

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2.2 Downconversion Block (Block A)

The design of block A to solve the problem proposed is depicted in figure 2.

Figure 2.1 – Used architecture for block A exhibited in the general architecture of the LTE filtering system presented in figure 1.

XIX

The first and last muxes conduct the signal through the image rejection filter correspondent to the

band the signal is in. The 2 muxes between them, in each path, have the purpose of providing at

least 80 dB attenuation between the chosen path and the other 2 paths that stay “open”. This is

important because, even though in the signal frequency band the magnitude response of the different

HP filters is somewhat similar, the phase response differences between them could distort the signal

if the “open” paths are not sufficiently isolated.

The amplifiers and attenuators across the chain, visible in figure 2.1, are present for several reasons.

The main reason is that, despite adding noise to the system, they still considerably reduce the SNR

(thermal noise) degradation when compared to the case where they are not used.

Note that if a signal simply passes through an attenuator, the signal is attenuated but the thermal

noisefloor remains the same, thus, the SNR suffers a reduction equal to the attenuators attenuation. If,

however, an amplifier is placed before the same attenuator, both the signal and the noisefloor are

amplified and some additional noise is added in the process.

Now when the signal arrives to the attenuator both the signal and the noisefloor are attenuated. The

minimum noisefloor is the same as in the previous case, and if that noisefloor is reached, there is still

SNR degradation, but it is now potentially much lower. [2]

The attenuators are indispensable because it cannot be permitted that the mixers or the amplifiers

enter into compression. A 3 dB safety margin from the power that drives each device into a 1dB

compression was employed.

After the first mixer, there is another image rejection filter which prepares the signal to be

downconverted in the mixer ahead, this time, to 60 MHz. Next, a band pass filter is present to clean

the spectrum that will eventually be fed to the analog to digital filter before the FPGA. Lastly, the LP

filter functionality is to reject, with a desired attenation of 80 dB attenuation, the LO tone with

frequency 540 MHz inserted in the second mixer. This is important not to produce replicas of the LO

that can hamper the operation of the digital filter in the FPGA.

The choice of using 2 mixing steps was taken for the reason that if only one mixing step was used

there would be problems in the downconversion and upconversion processes. For the

downconversion, the direct “jump” from very high frequencies to 60 MHz would cause the image band

of the signal to have a spacing of only 100 MHz from the signal itself (60 MHz x 2 – BW = 120 MHz –

20 MHz = 100MHz). It would therefore be impossible to reject the image band at high frequencies,

which would be necessary whenever the frequency of the LTE band to be filtered is high itself. In the

upconversion, something similar would happen.

The chosen mixer, JYM-28H from Mini-Circuits, has good specifications but its most important feature,

which was preponderant in its choice, is its input and output bandwidth. This mixer downconverts

signals from the band 400 – 2800 MHz to 4-700 MHz or upconverts signals from the 4-700 MHz band

to 400 – 2800 MHz. The stages of upconversion and downconversion were kept exactly symmetrical,

which brings the advantages of simplicity and the fact that the filters used in the upconversion stage

(except the LO tone rejection ones), block B ,will be exactly equal to the ones in block A. To achieve

this, the first jump in frequency must be to a frequency between 400 MHz and 700 MHz because of

the mixer’s input and output bands. A higher frequency in this first step leads to more relaxed filter

XX

specifications overall in bands 2 and 3 (to note the filter was sought after to work on a sub band of

band 3). A lower frequency in this first step induces a lower sensitivity of analog filter responses to the

components tolerances and more relaxed specifications in band 1. For graphical aid related to the last

two sentences please consult figures 2.11, 2.13, 2.27 and 2.21 ahead in the next sections. So, 600

MHz, a midle high frequency, was chosen.

All the filters that are a part of block A were designed by inserting the filter specifications on the

software “AADE Filter Design V4.5”. This is done after choosing each filter’s options, namely, it’s type

and topology. [4]

The analog filters presented in this Msc thesis, in LC ladder technology, are theoretical prototypes that

serve the purpose of more easily making it possible to study the overall system proposed by us, to

address the problem of all bands high quality filtering for LTE.

These filters would not work in practice because they presuppose ideal components, that is, that the Q

factor of the capacitors and inductors used is infinite. In reality the Q factor of the capacitors on the

market, do is quite high, however for inductors the Q factor obtained is often not high enough for the

inductors to be considered ideal. The big majority of the functional filters developed will thus, probably

need to be implemented recurring to microstrip lines. It is even possible that in a few cases, resonant

cavities have to be used instead of microstrip lines. Elliptic type filters were selected because for high frequencies, high attenuation and low transition

bands, these are the types of filters with lowest order and therefore, the more accomplishable to be

obtained through the use of AADE Filter Design V4.5. This software outputs each filter’s circuit

scheme and its ideal component values, depending on the specifications and options selected, for

filters of order lower than 12.

Those circuits were manually copied to PSPICE, the same designs, and simulated in the ideal case (

ideal component values) and in a bad case, when all the capacitors and inductors had their

capacitance and inductance furthest away from their ideal values, in accordance to each component’s

tolerance. Whenever the PSPICE simulation revealed the filter didn’t answer the specifications for the

ideal case or the bad one, the requirements inserted in AAL Filter Design V4.5 were made more

stringent. This process was repeated as many times as necessary and by trial and error, filters that

fulfilled the specifications were allways obtained.

2.3 Downconversion Block SNR 2.3.1 Downconversion Block initial SNR The 1 dB compression point of the used mixers is 10dBm, so the maximum power allowed in the input

of the mixers will be considered to be 7dBm, half the power that would drive the mixer’s output into a 1

dB compression.

A power of 7dBm, which is approximately 5mW, when distributed by a 20MHz band, gives an uniform

power spectral density of

10 ∗ log 5 ∗ 1020 ∗ 10

= 10 ∗ log (2.5 ∗ 10 ) ≅ −96푑퐵

XXI

It is not known the power or power density of the signal that arrives to the antenna, but for simplicity, a

constant power spectral density is a good reference case. The signal must be attenuated or

amplificated to achieve this level of power (without exceeding it, at the entrance of the first mixer. If

amplification is required, that will probably be beneficial because it might limit the signal to noise

(thermal noise) degradation of the entire chain.

To achieve this purpose, for simulation reasons explained in chapter 5, our signal spectrum will vary

from -76.5dB to -77.4 dB at the entrance of the LTE filtering system. This is because the minimum

attenuation of block A which comprises all the components before the first mixer is equal to 19.2 dB

(6+6+0.7+0.5+6). Note that adding 19.2 dB of attenuation to the signal, it would now have values

between -95.7 and -96.6 dB. It is then determined that the minimum value of the signal spectral

density is -77.4 dB at the beginning of the downconversion block.

As for the noise, it is very important to calculate the thermal noisefloor at 25ºC which is a typical

temperature to assume the filter to be working in. [4], [5]

푆 , = 푃훥

= 퐾 푇,푆 , [푑퐵] = 10 log(푆 , )(35)

퐾 = 1.3806503 × 10−23J/K

푇 = 25º퐶 ≅ 300퐾 ⇒ 푆 , ≅ −203.8푑퐵 The initial SNR at the entrance of the circuit is simply calculated by the difference of power between

the signal and the thermal noise.

The signal to noise ratio at this point of the circuit is:

푆푁푅 = 푆 − 푁 = −77.4— 203.8 = 126.4푑퐵 = 80푑퐵 + 46.4푑퐵 =

= 푆푁푅 + 푆푁푅푑푒푔푟푎푑푎푡푖표푛 Á

To achieve the 80 dB of SNR proposed, a maximum SNR degradation of 46.4 dB must be

accomplished.

2.3.2 Downconversion Block SNR Degradation Two cases were considered: (i) the SNR degradation in an “optimum case” and (ii) an SNR

degradation in a very bad case.

The optimum case corresponds to using the lower values of insertion losses of the muxes and best

values of attenuation possibly obtained in the attenuators, so that the attenuators compensate the

amplifiers almost perfectly. The filters’ attenuations considered are the maximum attenuations they

present with their ideal component values.

For the very bad case the maximum values of attenuation of any components and minimum values of

gain of the amplifiers are used. When those two are dependent variables and the attenuation is higher

than the gain, the maximum diference from the atenuators’ attenuation and the amplifiers’ gain is used

instead.

XXII

Sections of the circuit were considered for the calculations of SNR degradations. Each middle section

begins at the start of an amplifier and ends at the start of the next amplifier. The first section starts at

the start of block A and ends at the start of the first amplifier and the last section starts at the start of

the last amplifier and ends at the end of block A.

In the downconversion block there are 4 sections. In each section the SNR degradation is calculated

taking into account the overall gain and attenuation in the section, as well as the noise figure of the

amplifiers.

The SNR degradations are calculated following the algortithm presented in the appendix, section 2.1.

[2], [6] The SNR degradation of each section and the overall SNR degradation of the downconversion

block are given in table 2.1.

SNR Degradation Attenuation Comparison

Sections Optimum Case Worst Case A max without attenuators

Section 1 28.15 dB 30.95 dB 30.95 dB Section 2 6.81 dB 7.95 dB 13.46 dB Section 3 2.3 dB 3.4 dB 8.4 dB Section 4 1.99 dB 2.3 dB 7 dB

Total 39.25 dB 44.6 dB 59.81 dB Table 2.1 – SNR degradations of each section of block A as well as total SNR degradation of block A and evaluation of the reduction in SNR degradations due to employing amplifiers+attenuators. Comparing the last 2 colums of table 2.1, it is concluded that, except in section 1 where there is no

amplification, for all other sections, the worst case SNR degradation using amplifiers is between 4.7dB

(Section 4) and 5.51 dB (Section 2) lower than if no amplifiers were used.

The SNR at the end of block A ranges between 81.8 dB ( 80 + 46.4- 44.6) and 87.15 dB (80 + 46.4-

39.25). Since the signal will then be digitalized, this SNR is simply “converted” into a very small error

in the digitalized signal that will enter the FPGA.

It is now relevant to discuss the most important specifications of the components chosen to be used

as part of the LTE filter designed.

Muxes Each time the signal has to be able to follow 1 of 3 different paths, muxes we defined as Mux 2<->4

and Mux 4<->2 are used. In reality these muxes are equal. They are GaAs (Gallium Arsenide), MMIC

(monolithic microwave integrated circuit) 4x2 switch matrixes that work between 0.2GHz and 3 GHz.

This switch matrixes are bidirectional which is why the input and output functionality may be

interchanged.

The model of the mux is the HMC276LP4 / HMC276LP4E from the Hittite Microwave Corporation. It

has an insertion loss from 6 to 7 dB. The minimum isolation it provides is 38 dB in band 1, 33dB in

band2 and 31 dB in band3. [7]

When the signal only needs to go through 2 different paths, muxes we described as Mux1<-

>2 and Mux 2<->1 are resorted upon.

Mux 1<->2 is a GaAs (Gallium Arsenide), MMIC (monolithic microwave integrated circuit) SPDT

(Single Pole Double Throw) that functions between DC and 3 GHz. The model of the Mux is the

HMC194MS8 / 194MS8E from the Hittite Microwave Corporation. It has an insertion loss from 0.7 to

XXIII

1.1 dB and the minimum isolation it provides is 48 dB in band 1, 31 dB in band 2 and 24 dB in band 3.

[8]

Finally, Mux 2<->1 is a GaAs (Gallium Arsenide), pHEMT (Pseudomorphic High Electron Mobility

Transistor) DPDT (Double Pole Double Throw) switch that operates from 0.1 to 4GHz. The model of

the mux is the SKY13395-397LF from the Skyworks. It has a minimum typical isolation of 27 dB in

band 1, 19 dB in band 2 and 15 dB in band 3.

As for the insertion loss, from 0.1 to 1GHz, it varies between 0.5 to 0.6 dB. From 1 to 2.5 GHz it is

between 0.7 and 0.75 dB. Finally, between 2.5 and 4GHz, the insertion loss goes from 1 to 1.2 dB. [9]

Attenuators The attenuators’ model used is the DAT-15R5-SP+ from the Minicircuits corporation. It is a digital step

atteduator with a serial control interface which operates from Dc to 4 GHz.

The maximum attenuation setting error of the attenuator functioning in band 1, is

0.1+0.1+0.15+0.2+0.2 = 0.75 dB for an attenuation setting of 0.5dB+1dB+2dB+4dB+8dB = 15.5dB

respectively. The typical attenuation setting error in the same conditions is

0.03+0.02+0.05+0.07+0.03= 0.2 dB. In addition to this there is a typical insertion loss of 1dB. The

maximum value possible of insertion loss is 1.2 dB.

The maximum attenuation setting error of the attenuator operating in band 2, is

0.15+0.15+0.25+0.25+0.25 = 1.05 dB for an attenuation setting of 0.5dB +1dB+2dB+4dB+8dB =

15.5dB respectively. The typical attenuation setting error in the same conditions is

0.05+0.05+0.15+0.15+0.15= 0.55 dB. Moreover, the insertion loss of the attenuator is usually 1.1 dB

and it is 2.5 dB at maximum.

The maximum attenuation setting error of the attenuator operating in band 3, is

0.3+0.3+0.45+0.45+0.8 = 2.3 dB for an attenuation setting of 0.5dB +1dB+2dB+4dB+8dB = 15.5dB

respectively. The typical attenuation setting error in the same conditions is 0.1+0.1+0.2+0.18+0.5=

1.08 dB. Besides this, the insertion loss of the attenuator is usually 3.3 dB and 4.7 dB at maximum.

[10]

Amplifiers The amplifiers’ model chosen is the PHA-1+ from the Minicircuits corporation. Its main strong points

are a high bandwidth, a maximum typical noise figure up to 3 GHz of only 2.3 dB. To note that the

amplifier functions from 50 MHz to 6 GHz and the mentioned noise figure is on par with some LNAs

(Low Noise Amplifiers) specifications. LNAs are high tech and very expensive.

A PHA-1+ amplifier costs 1.49$. Its gain can vary between minimum and maximum values that are

quite changeable with frequency. Near 50 MHz, the gain goes from 15.4 dB to 19.4 dB and has a

typical value of 17.2 dB.

In Band 1, the gain varies between 14.1 dB and 17.3 dB and is usually equal to 15.7 dB.

In Band 2, the typical gain is 13.5 dB. It was assumed it can go 1.8 dB lower and 2.2 dB higher (which

is the dynamic range around 50 MHz, where the gain is more changeable), staying between 11.7 and

15.7 dB.

XXIV

In Band 3, the typical gain is 11.8 dB. It was assumed it can go 1.8 dB lower and 2.2 dB higher (which

is the dynamic range around 50 MHz, where the gain is more changeable) , staying between 10 and

14 dB. [11]

Simulations of block A’s performance in its entirety were performed in Matlab. The input signals have

a 20 MHz bandwidth and a changeable central frequency. Snapshots of the signal spectrum across

the chain will be presented in Chapter 5 for the case in which the signal is centered on 2585 MHz.

Since several theoretical concepts shall be reviewed, a section about mixers is introduced.

2.4 Mixers 2.4.2 Up mixing and Down Mixing The process of translating a signal in frequency to a lower frequency is called downconversion

whereas the operation of translating it to a higher frequency is called upconversion. The signal with

the lowest frequency is called the intermediate frequency signal ( 푓 ). The additional signal used to

perform the translation is the local oscillator signal ( 푓 ). Finally the other signal is the radio frequency

signal (푓 ) A graphical illustration is in figures 2.3 and 2.4.

RFf

LOf

IFf

Figure 2.3 – A simple scheme of a downconversion mixer.

LOf

IFfRFf

Figure 2.4 – A simple scheme of an upconversion mixer. In a downconversion, this image frequency band can’t have any signal present. If so that signal will

also be downconverted to the same frequencies as the radio frequency signal. The desired (radio

frequency) and the image signal will overlap and the radio frequency signal will be corrupted. Figure

2.5 shows an example of a downconversio mixing for a single tone signal.

Figure 2.5 – Operation of an ideal downconversion mixer for a single frequency radio frequency signal. On the left, 푓 < 푓 and the image frequency is equal to 푓 −푓 and on the right 푓 > 푓 and the image frequency is equal to 푓 + 푓 . [12]

XXV

In an upconversion, 푓 can also be higher or lower than the input signal, which in this case is the

intermediate frequency signal (푓 ). However, in this case, that is not a choice, it is simply dictated by

the frequency band of the inputed signal 푓 and the frequency band desired for the output signal 푓 .

In figure 2.6, only the case where 푓 > 푓 is shown.

After an upconversion, a copy of the 푓 signal will appear in the image frequency band.

Figure 2.6 shows a visual example of an upconversion mixing process for a single tone signal.

Figure 2.6 – Operation of an ideal upconversion mixer for a single frequency radio frequency signal. On the left 푓 < 푓 and the image frequency is equal to 푓 −푓 (difference) and on the right푓 > 푓 and the image frequency is equal to 푓 + 푓 (sum). [12]

2.4.3 Mixing modes and concepts Mixers can be classified in two types: Those which operate in a continuous non-linear mode, or those

which operate in the switching mode. [13]

Continuous non-linear mode

Figure 2.7 – Schematic of a simple and representative continuous non-linear mode mixer [13]

Let us look carefully at figure 2.7. It is know that 푣 (푡) = 푣 cos(휔 푡) + 푣 cos(휔 푡)

An identity of the form of the expression for 푉 (푡) where Λ = a v (t) + a v (t) + a v (t) + …

can be obtained with any diode or transistor because they will exhibit non linearities in their transfer

function if subjected to sufficiently high level signals.

The analysis of the frequency response of a single Mosfet will serve as a mixer study case and will

allow us to introduce several basic concepts for mixers. This theoretical development shall be

consulted in the appendix, section 2.2.

Several new harmonics have appeared. We want to draw the attention to the

2푓 + 푓 , 2푓 −푓 , 2푓 + 푓 , 2푓 −푓 (2.1)

harmonics that constitute the third order intermodulation distortion.

XXVI

Other important harmonics generated are:

푓 + 푓 + 푓 , 푓 + 푓 − 푓 , 푓 −푓 + 푓 , 푓 −푓 − 푓 (2.2)

These are the harmonics that form the second order intermodulation shifted of ±푓 , which means

that those harmonics (second order intermodulation) were mixed.

Finally we see that other previous order harmonics were also mixed:

2푓 + 푓 , 2푓 −푓 , 2푓 + 푓 , 2푓 −푓 (2.3)

This mixing of the lower order products always occurs. Thus the 4th order non linearity would for

instance mix the third order intermodulation distortion (IMD) harmonics.

From the algebraic development of the third order non linearity performed with the aid of the binomial

theorem and trigonometric identities, the major drawbacks of this type of mixers can be detected.

Using this kind of mixers with a diode or a BJT, the amount of undesired harmonics generated is

immense. Considering from now on 푣 = 푣 = 푣 because it is usually the case and taking into

consideration the expression for 푉 (푡) until the 3rd order, many conclusions can be made. Note that the

desired harmonics are multiplied by 푣 푣 while the majority of the undesired harmonics are

multiplied by terms proportional to 푣 or 푣 . A few undesired harmonics are multiplied by terms

proportional to 푣 . This means that as 푣 rises, the unwanted harmonics will increase much faster

than the desired signal. The same happens with 푣 though not to the same extent. Finally, it is

important to state that harmonics of frequency equal to 푓 and an harmonic of frequency 푓 are also

present in the output of the mixer.

Third order intercept Because of intermodulation distortion, 푣 is usually chosen to be higher than 푣 . The undesired

harmonics we are concerned of, are always the ones whose frequency is close to that of the desired

signal, since they will be the hard ones to reject using filters.

As we already discussed, the third order products will also be mixed and thus we will have at the

mixer’s output harmonics like the following:

푓 −(2푓 − 푓 ) and 푓 −(2푓 − 푓 ) (2.4)

These harmonics will have an amplitude proportional to 푣 푣 unlike the desired signal amplitude

which is proportional to 푣 푣 . [14]

Let us provide a practical example: One of our purposes is to downconvert a radio frequency signal containing a frequency band that goes from 2575 MHz to 2595MHz, to an intermediate signal with frequencies between 50 MHz and 70MHz. In this case, it would be impossible to filter most of the third order products stated above, because they will be mixed exactly into the desired frequency band or very near to it. This is an extremely important reason why 푣 must be low. Anytime we increase the radio frequency signal (푣 ) in 10 dB, the fundamental (desired output) increases 10 dB and the third order products (distortion) increase 30 dB. The third order intercept point (TOIP) is a theoretical point where the output level of a third order intermodulation product equals the output level of the fundamental. It is often specified to define the third order intermodulation performance of a mixer. [14]

XXVII

It is emphasized that this point is theoretical and can never be achieved in practice as the mixer would be driven into compression before the point could be reached.

Figure 2.8 – Graphical determination of the third order intercept point. The figure is to be interpreted as being in a logarithmic scale. [16 ] Figure 2.8 shows a graphical determination of the TOI point. The specification of this point is useful

because the two curves (straight lines in a logarithmic scale) (fundamental and third order

intermodulation harmonic) can be reestablished from it using the linear and cube laws.

If the power at the input of the mixer is too high, the output will reach a maximum level, it will saturate,

which means both the fundamentals and the intermodulation harmonics will tend to increase very little

or remain constant as the input power increases (see figure 2.8).

The 1dB compression point is the point where the input power increases but the output power of the

fundamental is 1 dB below what it would be if the power at the input of the mixer was low enough, so

that, that device was operating in the linear region.

Switching Mode Mixers These mixers operate by switching one input signal (푓 ) between two states at each half cycle of the

second signal (푓 ).

Double-Balanced Mixers In this type of Mixer both input signals, the radio frequency signal and the local oscillator, are isolated

from the Mixer’s output.

The most common type of double-balanced mixers is the Ring Mixer. Nevertheless there are other

types of double-balanced mixers like the Star Mixer or the Gilbert cell. [12]

As for the Ring mixer, it implements the following switching function [13]:

푇 (푡) = 12

+ 2휋

cos(휔 푡) + cos(3휔 푡)

3+

cos(5휔 푡)5

+ … (2.5)

푇 (푡) = −12

+ 2휋 cos(휔 푡) +

cos(3휔 푡)3

+ cos(5휔 푡)

5+ … (2.6)

푇(푡) = 푇 (푡) + 푇 (푡) = 4휋

cos(휔 푡) + cos(3휔 푡)

3+

cos(5휔 푡)5

+ … (2.7)

XXVIII

푇 (푡) is a square wave with amplitude plus a DC offset of + and 푇 (푡) is a square wave with

amplitude plus DC offset of − . Finally, 푇(푡) is a square wave with amplitude 1. Its value jumps

between 1 and -1. It has no DC offset, and represents the LO waveform (See figure 2.9)

Figure 2.9 – Ring mixer waveforms. Adapted from [14]

The radio frequency signal (푓 ) is multiplied by the local oscillator which has a higher frequency (푓 )

and is a square wave of amplitude 1 (푇(푡) ). The product is represented in the time domain in figure

2.10 below the drawing of the local oscillator signal. The phase reversal of the radio frequency signal

at each half signal of the local oscillator square wave can thus be observed. The harmonics generated

in an ideal situation are given by

푓 ± 푛푓 , 푛 = {1,3,5,7, … }(푛 ∈ ℕ).

The radio signal feedthrough to the output was hence eliminated.

In real mixers, there is always some imbalance. Transistors and baluns are never perfectly matched or

balanced. These nonidealities will produce some LO to IF or RF to IF feedthrough

(isolation is therefore, not perfect). Also, the RF to IF path is not perfectly linear. This will lead to

intermodulation distortion. Odd-order distortion (typically third and fifth order are the most significant)

will cause spur frequencies within the IF bandwidth and cause crossmodulation when strong signals

are present. Also, the LO “switches” are not perfectly linear, especially while in the transition region.

This can add more distortion to the IF output and will increase loss due to the resistance of the

switches.

2.4.5 Noise Figure The Noise Figure is by definition the input signal to noise ratio over the output signal to noise ratio, in

linear unities, converted to dB. So, it is always ≥ 0푑퐵. Thus, it can represent a measure of the noise

added by the Mixer, noise that gets converted to the IF output. For a passive Mixer which has no gain

and only loss, the Noise Figure is approximately equal to the insertion loss.

A Mixer will convert energy in the upper or lower sidebands with equal efficiency. Consequently the

noise in the side band with no signal (the image band) will be added to the IF output. [12] For a

graphical illustration refer to figure 2.10.

XXIX

Figure 2.10 – Representation in the frequency domain of the noise of the radio signal image. This noise would be summed to the desired downconverted outputted signal. [12]

2.4.6 Downconversion Mixer Selection Several datasheets from the Mini-circuits company were consulted [14]. [20], [21]

It is important to select the most adequate mixers to perform the downconversion required. The

datasheet parameter allow us to perform a simulation of the performance of the chosen mixers.

As explained in section 2.2, the downconversion will be performed in 2 steps. Moreover, like affirmed

in section 1.1 it was our purpose that, if possible, the filter worked in most of the LTE bands. The first

mixer has therefore to have an input bandwidth that covers the frequencies from 698 MHz to 2690

MHz. To note that, the isolation between the LO and IF or RF ports and the amount of conversion

loss of a mixer are frequency dependent. It was considered that the conversion loss varies mainly with

the RF signal frequency and the LO to IF isolation (LO to RF isolation in the upconversion case) alters

primarily as the LO frequency changes. The worst case values of each parameter according to these

assumptions were inserted in table 2.2.

The mixer chosen was the JYM-28H and it fulfills the additional requirement of bandwidth coverage.

Notwithstanding, it has the highest LO to IF (and a very good LO to RF) port isolation and the highest

1 dB compression point from all the mixers searched. It also has the highest TOIP. Due to all the

reasons given, JYM-28H is by far the mixer to be used in the downconverter block, both in the first and

second step of shifting our signal to lower frequencies. (It will be seen in chapter 4, this mixer will be

used in both upconversion steps aswell.) Care has to be taken so that the IF port bandwidth of the first

mixer has always, at least a 20 MHz (some safety margin is advised) intersection with the RF port

supported frequency span of the 2nd mixer. This is also safeguarded by using 2 JYM-28H Mixers in

block A with a conjunct frequency span from 400 to 700 MHz. As already stated multiple times, the

mixer specifications to be aware of in the downconversion part of the filter are for graphical aid,

exposed in table 2.2.

XXX

Worst Case Performance Data

Mixer LO/R

F [MHz]

IF [MHz]

Conversion Loss [dB]

Isolation L-I [dB]

TOIP at center band [dBm]

1 dB Comp Point [dBm]

Max RF

Power Max IF Current

JYM-28H Level 17

Surf Mount

400 to 2800

4 to 700 7.05 38.28 23 10 200

mW 40 mA

Table 2.2 – Most important specifications of the chosen mixer as downconverter 1 and 2. [22]

For our purposes (the frequency bands used), the minimum conversion loss of the mixers used is 5.76

dB and its maximum conversion loss is 7.05 dB, the one that was presented in table 2.2.

To conclude, the advantages of the mixer chosen will be briefly reviewed. It has a high compression

point, so, the input signal can have a considerably good level of power. The Isolation between the LO

and the intermediate frequency is also large, which leads to less demanding filters to completely reject

the leaked LO tone in each mixing step.

2.5 Down Conversion Process

2.5.1 First Step Introduction The first step in the downconversion process is illustrated in figure 2.11.

Figure 2.11 – Schema of the downconversion of the chosen LTE band to that centered in 600 MHz.

When the chosen LTE band is downconverted to the represented (figure 2.13) 600MHz band, it’s

image band is also upconverted to the 600MHz band. Therefore that image band needs to be rejected

with 80 dB attenuation with respect to the chosen LTE band.

The 3 major bands are illustrated in figure 3. If the LTE band belongs to band1, then it’s image will be

in the negative frequencies, however, if the chosen LTE band is included in bands 2 or 3, it’s image

will be situated in the positive frequencies. Because the filter’s response is allways simetric there is no

difference in the filter response in the positive and negative frequencies. The stripped rectangule on

the left of figure 3 represents the rejected image band which depends on the major band where the

XXXI

chosen LTE band is present. It was chosen to reject the image band of the whole major band, instead

of rejecting the image band of the chosen LTE band, because, that way, the filter architecture turns to

be simpler (smaller order) and much more flexible. The image rejection high pass filters for each band

are exhibited in the forthcoming sub sections.

Major Number of Band and Matching Image Band Rejection Because there are 21 FDD LTE bands and a really big number of different 20 MHz bands can be

defined upon the spectrum reserved to be used by LTE, a flexible, practical and simple solution

needed to be devised to cut all the possible image bands. In other words, an alternative to the

presence of a complex and rigid structure that consisted of a huge filter bank needed to be devised.

Thus the LTE spectrum was separated in 3 as claimed in section 1.3. The anti-image filter of each

band will reject the image bands of all possible 20 MHZ bandwidth signals inside the respective major

band. The specifications demanded to those three filters are explained, sequentially, from band 1 to

band 3 in the next three subsections.

Finally, each filter’s functional circuit is given. They were obtained through the methodology described

in section 2.2.

High Pass Band 1 The band 1 goes from 698 MHz to 960MHz. The variable local oscillator frequency varies accordingly from 108MHz to 350 MHz. An illustration of this is given in figure 2.12.

Figure 2.12 – Illustration of band 1 and the matching dynamic range of the frequency of the programmable frequency local oscillator. As the frequency of the chosen LTE band in band1 increases, so does the frequency of the local

oscillator and the the frequencies covered by the image band will lower. The worst case is when the

image band has its highest frequency in band 1. If a high pass filter is used to reject such an image,

the worst case and all possible scenarios are covered.

XXXII

Figure 2.13 – Representation of the highest frequency image band in band 1 as well as the LTE lower frequency band in that major band. The HP filter required for band 1 must let pass the 698MHz frequency and attenuate 80 dB at

502MHz. This filter’s ideal response is presented in figure 2.14.

. Figure 2.14 – High Pass Filter Specifications to Reject the Image Band of Band 1. The projected filter is represented in figure 2.15.

Figure 2.15 – High Pass Filter Circuit to Reject the Image Band of Band 1, HP Band1, in figure 2.1.

In order to evaluate the filters performance (degradation) with biased parameters, market

characterisctics of their components were used in the simulations.

XXXIII

The constituent components of the filter are detailed in table a2.1 in the appendix, section 2.3.

High Pass Band 2 The band 2 goes from 1427.9 MHz to 2200 MHz. The variable local oscillator frequency varies

accordingly from 837.5 MHz to 1590 MHz. An illustration of this fact is given in figure 2.18.

Figure 2.16 – Illustration of band 2 and the matching dynamic range of the frequency of the programmable frequency local oscillator. As the frequency of the chosen LTE band in band 2 increases, so does the frequency of the local

oscillator and therefore, the frequencies covered by the image band will now increase accordingly.

The same logic of worst case engineering as for band 1 is applied. The worst case is when the image

band has its highest frequency in band 2. It is depicted in figure 8.

Figure 2.17 – Representation of the highest frequency image band in band 2 as well as the respective LTE band in that major band.

From figures 2.16 and 2.17, it is concluded that the HP filter required for band 2, must let pass the

1427.9MHz frequency and attenuate 80 dB at 1000MHz. This filter is presented in figure 2.18.

XXXIV

Figure 2.18 – High Pass Filter Specifications to Reject the Image Band of Band 2.

The projected filter is represented in figure 2.19.

Figure 2.19 – High Pass Filter Circuit to Reject the Image Band of Band 2, HP Band2 in figure 2.1.

The constituent components of the filter are detailed in table a2.2, in the appedix, section 2.3.

High Pass Band 3 The band 3 goes from 2300 MHz to 2690 MHz. The variable local oscillator frequency varies

accordingly from 1710 MHz to 2080 MHz. An illustration of this is given in figure 2.20.

Figure 2.20 – Illustration of band 3 and the matching dynamic range of the frequency of the programmable frequency local oscillator.

XXXV

As the frequency of the chosen LTE band in band 3 increases so does the frequency of the local

oscillator and therefore, the frequencies covered by the image band will again increase accordingly.

The same logic of worst case engineering as for bands 1 and 2 is applied. The worst case is when the

image band has its highest frequency in band 3. It is depicted in figure 2.21.

Figure 2.21 – Representation of the highest frequency image band in band 3 as well as the respective LTE band in that major band.

Analyzing figures 2.20 and 2.21, it is concluded that the HP filter required for band 3 is one that

passes the frequency of 2300 MHz and attenuates 80 dB in 1490 MHz. This filter is presented in figure

2.22.

Figure 2.22 – High Pass Filter Specifications to Reject the Image band of band 3. The projected filter in practice is represented in figure 2.23.

XXXVI

Figure 2.23 – High Pass Filter Circuit to Reject the Image Band of Band 3, HP Band3 in figure 2.1.

The components of the filter are detailed in table a2.3, in the appendix, section 2.3.

2.5.2 Second Step The second step in the downconversion process is illustrated in figure 2.24.

Figure 2.24 – Schema of the downconversion process of the 20MHz bandwith LTE band centered in 600MHz, to a center frequency of 60MHz. The image band is marked with a cross. The band that is to be downconverted is marked with a circle. Observing figure 2.24, it is clear that there must also be an image rejection filter for this down

conversion step. That filter response is exposed in figure 2.25.

Figure 2.25 – High pass filter Specifications required in the 2nd downconversion step, to reject the image band represented in figure 2.24.

XXXVII

The projected filter is represented in figure 2.26.

Figure 2.26 – High Pass Filter Circuit to Reject the Image Band correspondent to the second dowconversion step.

The components of the filter are detailed in table a2.4, in the appendix, section 2.3.

2.5.3 Pre-Processing Before the Analog to Digital Conversion The LTE band was already downconverted to a center frequency of 60 MHz. If that signal was going

to be digitalized by an ADC (analog to digital converter) with a sampling frequency of 250 MSPS (this

is the sampling frequency of the ADC selected, described in section 3.2), the spectra would change.

Replicas would be generated with a periodicity of 250 MHz, as illustrated in figure 2.27.

Voltage [dB]

50 70 Frequency [MHz]

60

-50 -70

-60

+ N x 250 MHz- N x 250 MHz + N x 250 MHz- N x 250 MHz

0

Figure 2.27 – Schema of the replica generation of the digitalization process of a bandpass signal centered in 60MHz with a sampling frequency of 250 MSPS (mega samples per second).

Such procedure would produce the spectrum on the positive frequencies, exhibited in figure 2.28. The

negative frequencies present an exact symmetry once V(f) = V(-f).

XXXVIII

Voltage [dB]

300 320 Frequency [MHz]

180 200

190

50 70

60 310

...

250125

Figure 2.28 – Spectrum of the positive frequencies resultant from digitalizing a band pass signal centered in 60MHz with a sampling frequency of 250 MSPS.

Band Pass Filter By looking in more detail to the band and its first replica, we obtain figure 2.29.

Figure 2.29 – Same spectrum as in figure 2.28 but only the first replica is present.

Figure 2.29 reveals the impact of one adjacent replica on another. Our purpose is that one replica does not introduce considerable noise in the adjacent one, namely that the LTE band centered in 60 MHz doesn’t get affected by a residual signal coming from the replica centered in 190 MHz. This leads to the necessity of a bandpass filter centered in 60 MHz with 20 MHz bandpass and an attenuation of 80 dB at 180 MHz, the last filter in block A. Moreover, without the existence of this filter, spectral components beyond 125 MHz in frequency that would be replicated below 125 MHz in the ADC could have enough power to significantly increase the quality requirements of the filter. The filter’s circuit is present in figure 2.30. The components of the filter are detailed in table a2.5, in the appendix, section 2.3.

Figure 2.30 – Band pass filter for cleaning the signal spectrum of the input of the ADC.

XXXIX

Low Pass Filter In each mixing step an LO tone is introduced. These, when at the entrance of the ADC, must be 80 dB

below the signal to be filtered in the FPGA. It is, then, necessary to compare the powers of the LO

tones and the signal when both have gone through the BP filter just described. It is mandatory to

design a low pass filter that helps cut the LO tones if their attenuation in the remaining

downconversion chain is not sufficient.

The lowest value possible of the level of the signal at the entrance of the low pass filter (which is

probably unreachable), corresponds to the signal passing through the maximum attenuation of all the

previous filters. Analyzing figure 2.1 in section 2.2, and page 21 in section 2.3.1, it can be seen that:

The minimum power density of the signal after the first mixer is −77.4− 30.95(7 + 7.6 + 1.1 + 1.2 +

7 + 7.05) = −108.35푑퐵푊/퐻푧

Its minimum power density before the second amplifier is −108.35+ 10.5− 7.31− 6.15 − 5.5 =

−116.81푑퐵푊/퐻푧

Finally, its minimum power density before the LP filter is −116.81− 8.4+ 5+ 15.4 = −104.81푑퐵푊/

퐻푧

LO1 The first LO tone added to the signal will be named LO1. This addition happens in the first mixer and

the tone is introduced with a power of −54.29푑퐵푊 (imposed by the mixer).

In a LTE band of band 1, LO1 has a minimum attenuation of 105.42푑퐵 in the FRI2 filter (see figure

2.1) , (in the bad case simulation). These values were found in the Matlab simulations discussed in

section 5.

The maximum power of the LO1 tone at the entrance of the second amplifier is −54.29+ 11.76−

105.42 − 5.76− 3.64 = −157.35푑퐵푊 and the maximum power of the LO1 tone at the entrance of the

LP filter is −157.35− 66.08(퐴푚푖푛,퐿푂푟푒푗푒푐푡푖표푛푏푎푛푑,퐵푃푓푖푙푡푒푟, 표푝푡푖푚푢푚푐푎푠푒) + 5 + 15.4 =

−203.03푑퐵푊 < −184.81 = −104.81− 80. There is a safety margin of −184.81 − (−203.03) =

18.22푑퐵.

For LTE bands in band 2 or 3, the band pass filter attenuates LO1 at least 120푑퐵. In that case,

the maximum power of the LO1 tone at the entrance of the the second amplifier is −54.29+ 11.76−

6.8− 5.76− 3.64 = −58.73푑퐵푊and the maximum power of the LO1 tone at the entrance of the LP

filter is

−58.73− 120(퐵푃푓푖푙푡푒푟, 퐴푚푖푛, 퐿푂푟푒푗푒푐푡푖표푛푏푎푛푑, 표푝푡푖푚푢푚푐푎푠푒) + 5+ 15.4 = −158.33푑퐵 <

−184.81. In these bands (푓 ≥ 837.9푀퐻푧), LO1 needs an attenuation greater than 184.81−

158.33 = 26.48푑퐵 to meet the requirements. To note that LO1 is not a problem since the LP filter

designed presents an attenuation bigger than 70 dB for frequencies above 800 MHz. A safety margin

around 45 dB is achieved.

XL

LO2 The second LO tone added to the signal will be named LO2. Contrary to the LO1 case where the tone

has a variable frequency, this tone has always a fixed frequency of 540 MHz. This addition happens in

the second mixer and the tone is introduced with a power of -54.29 dBW (again, required by the

mixer).

The maximum power of the LO2 tone at the entrance of the LP filter is −54.29− 5.5+ 5 −

120.24(퐵푃푓푖푙푡푒푟,퐴푎푡540푀퐻푧, 푏푎푑푐푎푠푒) + 15.4 = −159.63dB

The minimum attenuation the LP filter must present to the LO2 tone (at 540 MHz) is

−159.63 − (−184.81) = 25.18푑퐵(in comparison to the attenuation suffered by the signal).

The actual value of the LP filter attenuation in 540 MHz is, in the optimum case, of 61.79 – 6.99 = 54.8

dB which is equivalent to a safety margin of 54.8 – 26.48 = 28.32 dB.

In the worst case scenario, the actual value of the LP filter attenuation in 540 MHz is 61.44 – 6.96 =

54.48 dB which corresponds to a safety margin of 54.48 – 26.48 = 28 dB.

Once more, these numbers were taken from the Matlab Simulations performed.

The LP filter designed is represented in figure 2.31. It is a 3rd order T configuration low pass

Chebyshev filter, that mainly functions as a notch in 540 MHz. Lower order filters were tested and it is

guaranteed this is the lowest order low pass filter that achieves the specifications as a Notch in 540

MHz. Nonetheless, the safety margin reached is quite high.

Figure 2.31 – Low pass filter to conveniently attenuate the LO tone inserted in the second mixing step.

The constituent components of the filter are detailed in table a2.6, in the appendix, section 2.3.

Like stated in section 2.2 the majority of the functional filters developed will need to be converted to

microstrip lines technology. An example of such a procedure, for this relatively simple, Low Pass filter,

will be given in the appendix, section 2.5. [22], [23]

2.5.4 Simulated range of the Attenuation filters in the Down conversion Block The attenuation the signal suffers when passing through the downconversion block filters usually

increases when the filters’ components do not have ideal values. The ideal attenuation (ideal case)

and very bad case attenuation are given in tables 2.3 and 2.4, respectively. It is reminded that the

simulation components used were defined throughout section 2.4.

XLI

Downconversion – Filters Attenuation in The Signal in the Optimum case

Filter 푨풎풊풏[풅푩] 푨풎á풙[풅푩] 푨풎풆풂풏[풅푩]

HP Band 1 6 7.4 X HP Band 2 6 7 X HP Band 3 6 7 X

FRI 2 6 6.8 X BP 6 7.5 6.5 LP 6 7 6.5

Table 2.3 – Attenuation of Downconversion block filters with ideal value components. 퐴 [푑퐵] is the퐴 is the overall medium attenuation in the signal. It is only accounted for the

band pass and low pass filters because those are the filters where the ripple has a frequency that is

high enough so that 퐴 is a meaningful parameter.

The very bad case consists of using component values having the biggest deviation from the ideal.

The data presented in tables 2.3 and 2.4 was obtained in the Simulations performed in Matlab. These

attenuations take into account the limited frequency bands occupied by the signal prior to passing

through each filter.

Downconversion – Filters Attenuation in a very bad case

Filter 푨풎풊풏[풅푩] 푨풎á풙[풅푩] 푨풎풆풂풏[풅푩] HP Band 1 6 7 X HP Band 2 6 7.15 X HP Band 3 6 7.6 X

FRI 2 6 7.31 X BP 6 8.4 6.7 LP 6 6.8 6.4

Table 2.4 – Attenuation of Downconversion block filters with highly biased components.

XLII

3. FPGA Block 3.1 Introduction

The general architecture of the FPGA block is illustrated in figure 3.1.

Figure 3.1 – Internal constitution of the FPGA block.

The FPGA block behavior is now briefly explained. In order to take advantage of the full capabilities of

the analog to digital converter selected, the voltage of the signal at its input must cover the full range

of the ADC or as much close to it as possible. For that purpose a voltage level adapter is employed

before the ADC.

Next, the signal enters the FPGA as a bitstream composed of 16 bit words in rapid series. These

represent the signal values that are digitally encoded. The digital signal, first of all, passes through a

FIR (Finite Impulse Response) Digital Filter that is basically a digital band pass filter which achieves

the 80 dB attenuation in 5MHZ transition bands on both sides of the pass band. Afterwards the signal

traverses an equalizer. The signal hereafter leaves the FPGA and arrives the DAC (digital to analog

converter) where it is then again converted to an analog signal. Lastly there is a power level adapter

so that the signal that enters the Upconversion block, has the highest possible power while respecting

the minimum safety margin from saturating the first mixer ahead.

3.2 ADC The ENOB specifies the number of bits in the digitalized signal above the noise floor. [25]

퐸푁푂퐵 = 푆퐼푁퐴퐷[푑퐵] − 1.76

6.02(3.1)

Where SINAD is defined as:

푆퐼푁퐴퐷 = 푆

푁 + 퐷=

푃푃 + 푃

(3.2)

For a more detailed explanation of the SINAD parameter, consult the appendix, section 3.1.

XLIII

All real components operate under a certain amount of noise. If the converter has a sufficient

resolution to represent signal levels below the system noise floor, the lower bits of the digitalized

signal only represent system noise and do not contain useful information. ENOB specifies the number

of bits in the digitalized signal above the noise floor of the ADC.

This will be the main parameter used to select an ADC and to simulate it. A device with the biggest

ENOB possible will be chosen taking into consideration that the FPGA used after the ADC accepts up

to 18 bits. The error introduced by the ADC can simply be the error introduced by quantizing an analog

signal with the ENOB number of bits. However, this only happens if the other errors introduced by the

ADC operation only affect bits that are less significant than the ENOB more significant ones.

Another restriction in the ADC to be used is its minimum working rate, because the analog signal must

be sampled at a rate high enough so it can be digitalized and reconstituted in the analog domain

without any loss of information and a very small error introduced.

It is known that, to avoid aliasing, a band pass signal with centre frequency 푓 and bandwidth Δf must

be sampled at a frequency 푓 which meets the following specification [26], [27]:

2푁

푓 + Δf2 ≤ 푓 ≤

2푁 − 1

푓 −Δf2 , 푁 ≥ 1 ⇔ (3.3)

⇔2푁푓 ≤ 푓 ≤

2푁 − 1

푓 , 푁 ≥ 1(3.4)

A compromise must now be reached. There are two variables in equation (9), 푓 and 푓 .

A higher 푓 means the replicas are more apart (Refer to figures 17 and 18) from each other and the

digitalization will be of better quality. At the same time, it also means the speed of processing of the

FPGA ahead and the DAC that follows must be higher. A lower 푓 brings the possibility that a FIR

digital filter with a lower order will be able to address the specifications demanded.

The quality of the AD conversion was favored instead of the lower processing speed and lower order

of the digital filter. First, 푓 was maximized according to the speed of ADC processing existent on the

market. Care was taken to also obtain the highest ENOB and the smallest introduced error in the

conversion as possible. 푓 has a value of 250 MHz. Next, 푓 was chosen. The goal was to increase as

much as feasible, the frequency gap between the replicas.

We want to call the attention to the fact that several different ADCs’ were researched, through their

datasheets. Of all those, the AD9446 from Analog devices, was the one with the highest ENOB, with a

value of 12.9 at 70 MHz. It had 16 bits resolution and worked at 80 MSPS or 100 MSPS.

The ADC chosen was, however, the AD9467 from the Analog Devices corporation. This was the

industry’s fastest 16 bit ADC, running at 250 MSPS at the date of 27 September 2010. [28]

Its specifications are represented in table 3.1. There are some parameters in that table that require an

explanation. Those explanations, which are related with the ADC operating principles are given in the

appendix, section 3.1. [25]

XLIV

Table 3.1 – Most important specifications of the chosen ADC including noise and distortion but excluding error specifications [29]

The 4 types of error of an ADC are discussed in the appendix, section 3.2.

The specifications of these 4 error types for the ADC to be used, are exhibited in table 3.2. [30]

AD 9467 Minimum Typical Maximum Offset Error - 150 LSB 0 LSB 150 LSB Gain Error - 3.5 %FSR - 0.1 %FSR + 2.5% FSR DNL Error - 0.6 LSB ∓ 0.5 LSB +1.3 LSB INL Error - 11.8 LSB ∓ 3.5 LSB + 9.5 LSB

Table 3.2 – Error specifications of the chosen ADC.

The typical gain error will need to be compensated. This is because in a full scale of 2.5 V, 0.1% is

equivalent to 65.536 LSB (

= = 65.536). This affects up to the lower 7 bits of the codeword

which is unacceptable because it reduces far too much the quality of the digitalization process.

Minimum and maximum offset and gain errors shall be corrected only if their occurrence is not

sufficiently rare. These problems are, as discussed in the appendix, addressable, and therefore, do

not impose an impairment on the ADC performance.

The SFDR is a worst case harmonic characterization parameter. The SFDR of the chosen ADC is 95

dBFS for a frequency of 97 MHz, and this value is much bigger than the 80 dB required, so, undesired

harmonics are not a problem in this case.

The conclusions to be taken are therefore that the ENOB and the typical INL error are the parameters

that limit the performance of the ADC. The INL will typically interfere with the 3 bits of lower

significance of the codeword. The typical INL error is of 3.5 LSB. The 2 lower significance bits cover

up to 3 LSB difference in analog voltage and the 3 lower significant ones bits cover up to 7 LSB jumps

in voltage. As far as operation (except noise and distortion) errors are concerned, 13 bits of the ADC

are typically 100% reliable.

The ENOB is thus the bottleneck of the ADC performance. Note that none of the ADCs searched were

able to achieve or exceed an ENOB of 13 bits. The AD9467 presents a good compromise between

speed and accuracy with an ENOB of 12.3 and a sampling rate of 250 MSPS. We now know that of

the 16 bits resolution only 12 bits are totally reliable. Even though 30% of the 13th bit isn’t affected by

noise or other non correctable typical errors, this advantage will not be taken into account, since it is

statistical and hard to measure.

The ADC will inevitably impose, in the simulations performed in Matlab, a minimum signal to noise

ratio at the end of the ADC that cannot go any higher than 20푙표푔(2 ) ≅ 72.25푑퐵.

Finally to note that the input of the ADC is serial and its ouput is parallel, which means there will be a

different output pin for each bit in a given 16 bit codeword.

ADC MSPS Number of Bits ENOB SFDR Differential

Input Range Analog Devices AD 9467

250 16 12.3 (140 MHz)

95 dBFS (140 MHz) 2.5V p-p

XLV

3.2 Digital Filter 3.2.1 Digital Filter Higher Level Design for the FPGA The band pass filter to be projected has a pass band from 50 MHz to 70 MHz with a maximum

attenuation of 3dB and has attenuation bands bellow 45 MHz (inclusive) and above 75MHz

(inclusive) with a minimum attenuation of 80 dB.

From here on, the attenuation in the pass band will be designated by 퐴 and the attenuation in the

rejection band will be referred by 퐴 .

For the required filter’s implementation it is proposed the use of a FPGA of the family Spartan 3A by

Xilinx. This family presents DSP slices that work at 250 MHz, each of which contains a multiplier of

18x18 bits, a pre adder of 18 bits and an accumulator of 48 bits. The differential Input/Ouput ports run

slightly above 640 Mb/s. Because the DSP slices have parallel buses at their entrance, the minimum

I/O rate demanded is 250 Mb/s.

The most complex XC3SD3400A device of Spartan 3A family was picked. It has 126 DSP slices, 373

Kb of distributed RAM and a total block RAM of 2268 Kb. It comprises 309 I/O ports which is quite

above the minimum sought of 12. [31], [32]

It will be seen later, the minimum number of DSP slices needed is 73+41=114 with pre adder or 146 +

41 = 187 DSP slices without pre-adder. Since a pre-adder exists, the minimum number of DSP slices

necessary in the FPGA is exceeded.

Other FPGA families were considered. The second best option, found for use, is the Virtex 6 device,

XC6VLX75T [34]. This family presents DSP slices with much better specifications but which clearly

exceed the requirements. For this reason, this last device was not our first option.

It was considered that all the inputs of the FPGA are samples with magnitude between 0 and 1. It is

noted that it is possible to normalize any filter entries to a value in this range knowing the maximum

absolute value of the samples that arrive to the filter. Thus it was inserted the following data in

FDATool (Filter Design Analysis Tool), a tool from the Matlab (Matrix Laboratory) software that allows

the simulation of digital filters [35]:

The inputs and outputs of the filter have 18 bits and the coefficients are also represented with 18 bits.

The output of the multiplier is constituted of 36 bits (18 + 18) and lastly the accumulator has a capacity

for storing 48 bits.

In the next 3 sub sections, all the possible digital filter high level architectures that can accomplish the

digital filter sought will be compared. First, FIR filters will be addressed and then IIR filters will be

discussed. Finally, the filter to be implemented will be briefly discussed.

Digital Filter High Level Architecture Several techniques for projecting FIR (Finite Impulse Response) filters were considered:

Equiripple and Generalized Equiripple – These techniques produce attenuation bands with lobes of

approximately constant amplitude and pass bands with uniform ripple. See Figure 3.2.

XLVI

Filter Type 푨풑[dB] 푨풔풕풐풑 [dB] Order Equiripple 3 87 116 Equiripple 1 86 135

Generalized Equiripple 3 84 120 Generalized Equiripple 1 84 145

Table 3.3 – Characteristics of minimum order FIR filters that meet the specifications (80 dB attenuation in the quantized coefficients’ filter), obtained through Equiripple methods simulated using FDATool.

Figure 3.2 – Magnitude response of Equiripple solution with 퐴 = 1푑퐵 exposed in Table 3.3. Note that the difference in attenuation between the reference coefficients response and the 18 bits

quantized coefficients response is negligible. The difference is 1 dB attenuation maximum.

Analyzing Table 3.3, it is observed that the act of reducing 퐴 to 1 dB, improving the filter bandpass

response, requires more coefficients. In this case, additional 19 to 25 coefficients are needed

depending on the chosen solution. Results have shown that the Equiripple method spares between 4

and 10 coefficients with respect to the Generalized Equiripple solution.

Another option is resorting to window techniques, once more considering 퐴 = 3푑퐵, but now when

applied to 50 MHz and to 70 MHz. This happens because unlike the Equiripple techniques that

produce ripple in the pass band, the windows method does not generate that ripple, so the filters

obtained can attenuate up to 3 dB in the extremes of the pass band.

In Table 3.4, the results for those windows which allow us to meet the filter requirements are

presented. This procedure produces filters that have a magnitude response dependent on the window

chosen. Usually the attenuation band is composed by sidelobes. Most often, these do not have a

constant amplitude.

Window 풇풄ퟏ [MHz] 풇풄ퟐ [MHz] Additional data Order Chebyshev 49 71 SA* = 82 230

Nutall 49 71 X 215 Blackman Harris 49 71 X 220

Gaussian 49 71 α = 3,4 285 Flat Top 49 71 X 275

Table 3.4 – Characteristics of minimum order FIR filters that meet the requirements using windows. These results were obtained with FDATool. *SA – Sidelobe attenuation [dB]

It can be seen in table 3.4, that, to make it possible for the filter’s attenuation to reach 80 dB in

the 5 MHz frequency span of the transition bands, it is necessary a large number of coefficients

relatively to the Equirriple methods. This happens in all the cases presented in

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Table 3.4. To note that in the case of FIR filters, the number of coefficients corresponds to the order of

the filter added to one.

All FIR filters showed on Tables 3.3 and 3.4, have linear phase response. This implies a constant

phase delay, however, because of all the analog filters in the LTE filter chain, this is rather irrelevant,

as the total phase response of the LTE filter is very unlikely to be linear.

In the filter design, it is intended to reduce the number of filter coefficients, respecting, although, all the

specifications of the filter, because that will reduce the filters latency and diminish the hardware

required to implement it. Note that the number of coefficients is directly linked to the exact number of

DSP slices necessary to implement the digital filter, the first block inside the FPGA. In this way, the

main conclusion to take so far is that in the FIR filter case, the Equiripple method with 퐴 = 3푑퐵 is the

one that minimizes the number of DSP slices required, making the digital filter more reliable. However,

the Equiripple method with 퐴 = 1푑퐵 solution would, on the other hand, produce less ripple in the

passband, and even taking into account the equalizer that follows in the FPGA, the total ripple

produced in the whole LTE filter is significantly reduced if 퐴 = 1푑퐵. Because of this improvement in

the smoothness of the power magnitude of the signal in the passband, this is the solution to choose so

far.

Finally, it is relevant to state that if the coefficient quantization was done with 25 bits instead of 18,

using the equiripple method and 퐴 = 1푑퐵 there would be an order reduction of 2 (attenuation

required would be 2 dB lower, of 84 dB which gives an order of 132) to achieve the same quality of

digital filtering. This proves the advantage in utilizing 25 bits coefficients instead of 18 bit coefficients,

is in this case, very small. (There are other FPGAs that have DSP slices with 18x25 multipliers).

The IIR filters option was also studied. That study is shown in the appendix, section 3.3. In practice,

IIR’s are usually only used with order up to 8. The reason is the complexity of the filters and their

possible instability allied to the fact that a non linear phase response makes these solutions

unattractive compared to using FIR filters.

It can be found, observing Table a3.1 in the appendix, section 3.4, that the minimum order for an IIR

filter to successfully comply with the requirements, is, in this case, order 12, which is considerably

high.

The Equirriple method with 퐴 = 1푑퐵 does seem the best option so far, however it turns out not to be

that way. This is because the coefficients are quantized with 18 bits, and so they have minimum

resolution of 2 ≅ 7.63퐸 . Two of the coefficients obtained with this solution have lower values

than this and will be quantized to 0 which will induce an error in the FIR calculations. Because of this,

the Generalized Equirriple solution with 퐴 = 1푑퐵 was selected. (It is also important that the order of

the filter obtained is odd, because that allows us to spare half the amount of DSP slices used for its

implementation, but that also happens in the Equiripple solution with the same value of 퐴 ).

The main conclusion to take from the above results, is that FIR filters, more specifically, the

Generalized Equiripple method with 퐴 = 1푑퐵 presents the most promising solution for the designing

the filter specified.

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The filter to be implemented is therefore a FIR, projected with a Generalized Equiripple technique with

퐴 = 1푑퐵. It has an order of 145 which means it has 146 coefficients and will require the use of 73

DSP slices to be accomplished. This will be verified later.

3.2.2 Digital Filter Lower Level Design for the FPGA The general FIR filter equation is a summation of products as represented in expression 1:

푦 = 푥 ℎ (3.5)

There are several different digital circuits that can make this computation. They all have different

strengths and weaknesses and all will be studied so that the circuit that best meets our purposes can

be selected. There are serial FIRs, parallel FIRs which separate into 2 categories, transposed and

systolic filters and finally there are semi-parallel FIRs. [36]

An example of a serial FIR and an example of a transposed FIR can be viewed in the appendix,

section 3.4. The architectures selected are presented ahead.

Systolic FIRs

Figure 3.3 – Simplified example of a systolic parallel FIR implementation. B is the bus where the samples are inputted and P is the output of the digital circuit. Each DSP slice is enclosed by a dashed line. [36]

A parallel architecture was selected because those are the ones that perform faster. Contrary to

transposed FIRs architecture, in systolic filters, bus B does not have fanout problems because it never

needs to drive several gates simultaneously. In these filters, the latency increases one clock cycle per

tap/coefficient used. This is the optimum solution for parallel architectures when there is a large

number of coefficients. That is because it avoids the fan out problem. Also, the initial latency usually

does not have much an impact in the overall filter performance. Transposed architectures are more

indicated for smaller FIRs, because there will not be fan out problems and a lower initial latency will be

reached.

Symmetric Systolic FIRs

Figure 3.4 shows how to use the symmetry property of the FIR coefficients to improve the

performance of systolic FIR filters. Despite the running of the circuit represented in figure 4 being

counter intuitive, its correctness in guaranteed by the Xilinx corporation and its mathematical validity

was confirmed by us. A mathematical analysis of this circuit is presented in the appendix, section 3.4.

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The semi-parallel FIR architecture study will not be displayed because there are no hardware

restrictions, and parallel architectures perform faster.

Figure 3.4 –Parallel FIR implementation. On the top left of the picture begins the bus where the samples are inputted. P is the output of the digital circuit. Each DSP slice is enclosed by a dashed line. [36]

FIR Design in FPGA Conclusions The FIR we are implementing has 146 coefficients which have a symmetric property. With this number

of taps, even using the symmetric property of the coefficients, a serial FIR design would not be

sustainable because the input rate of the samples in the FPGA would be much higher than the output

rate of the FIR.

The number of DSP slices and the amount of RAM existent in the Spartan 3, XC3SD3400A device

(See section 3.2.1) does not seem to be a problem for a parallel implementation of this filter plus the

equalizer ahead, and since the FPGA will be used for that sole purpose, parallel FIR filters seem to be

the better choice. This is because these kinds of FIRS are the fastest. To avoid possible bus fan out

problems, the systolic architecture is going to be used for the digital filter. Despite a higher initial

latency than the transposed type FIR, this solution is very reliable.

The FPGA will have input and ouput rates of 250Mb/s, which the digital filter can handle since the

DSP slices operate at an equal frequency of 250 MHz.

In fact, a Symmetric Systolic FIR will be implemented instead. This filter has all the advantages of the

systolic FIR above, but cuts the number of DSP slices used in half. This is possible since care was

taken so that the number of coefficients of the filter designed would be even, making it possible to

implement the filter on the XC3SD3400A FPGA of the Spartan 3A family.

3.3 Equalizer The digital equalizer developed has the frequency response depicted in figure 3.5. The shape of this

response is a pre-distortion that counteracts the total distortion the signal pass band will suffer in the

entire LTE filter.

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Figure 3.5 – Frequency response of the FIR equalizer designed. It is an arbitrary magnitude equalizer of order 40 designed with an Equiripple method. The ripple introduced outside of the signal band (50 to 70 MHz) was checked to be of ∓ 0.3 dB. The design procedure is briefly explained. The attenuation specifications are given in voltage linear

units in the FDATool software in a magnitude vector aligned with a frequency vector. The order of the

equalizer is also provided to the software. The order chosen was 40. The higher the order, the better

the equalizer matches the specifications, however, the more DSP slices are used and the higher is the

latency of the equalizer. This order was a good compromise between not having too high hardware

requirements and achieving a good quality of equalizing. The specifications in frequency of the

Equiripple equalizer projected, were the ones presented in table 3.5.

Frequency [MHz]

Magnitude Vector/ Voltage

Attenuation

Ideal Power Attenuation

[dB] Actual Power

Attenuation [dB]

0 1 0 0.3 45 1 0 0.3 50 1.42 3.05 2.84 55 1.42 3.05 2.84 60 1.09 0.75 1.02 65 1.02 0.17 0.16

68.5 1 0 - 0.12 70 1 0 - 0.16 75 1 0 0.29

125 1 0 - 0.3 Table 3.5 – Equalizer specifications and output response. On the first three columns the data fed to the software along with the intended outcome is shown. On the last column, the actual power attenuation measured in the equalizer graphical response is exhibited. Other FIR equalizer types were tested like the Least Square and Generalized Equiripple Equalizers.

The least square equalizer achieves less attenuation outside of the signal band (50 to 70 MHz) but the

shape and rate of the transitions inside of the signal band, were considered, to slightly lower the

quality of the equalizing, in relation to the equalizer chosen.

If the Generalized Equiripple option is used instead the response generated is very similar. The choice

between the 2 (Generalized Equiripple and Equiripple) is not very relevant.

An equalizer designed with the method described in this section, cannot have an odd order and

therefore will never have an even number of coefficients. For that reason, the equalizer to be used, will

be implemented with a systolic parallel FIR architecture, which is the best available option according

to what was stated in section 3.2.2.

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3.4 DAC Since the ADC samples the signal at 250 MSPS, the DAC must also operate at 250 MSPS. The DAC

offset error, gain error, DNL and INL errors have the same definition that was given in the appendix,

section 3.2, for the ADC. The only difference would now be that, in figures a3.3 to a3.6 in that section,

the digital input should be displayed on the x axis and the analog output should be shown on the y

axis instead. All the other definitions given in that section, such as the SFDR and the ENOB, still

remain valid and unchanged. To note that the SFDR refers to the worst possible spur, so it is a worst

case scenario and not a typical one.

Contrary to the ADC used, the DAC has parallel inputs and a serial output. It will have as many inputs

as the number of bits in its resolution. The only DACs found that operated at 250 MSPS were the

following devices: AD9741, AD9743, AD9745, AD9746 and AD9747.

DAC Resolution [bits] INL NSD

( 61.44 MHz) SFDR

(70 MHz) IMD

(70 MHz) AD9741 8 ∓0.05LSB -162 dB/Hz 70 dBc 80 dBc AD9743 10 ∓0.10LSB -174 dB/Hz 70 dBc 80 dBc AD9745 12 ∓0.25LSB -185 dB/Hz 70 dBc 80 dBc AD9746 14 ∓1LSB -193 dB/Hz 70 dBc 80 dBc AD9747 16 ∓4LSB -195 dB/Hz 70 dBc 80 dBc

Table 3.6 – Most important datasheet characteristics of DACs working at 250 MSPS. [37]

NSD is the noise spectral density and IMD refers to the two tone third order intermodulation distortion

just like in the mixers case.

There are undesired harmonics that affect the signal. It is certain that these harmonics cause errors in

the 14th bit of the DAC (IMD) and they can possibly affect bits 13th and 12th (SFDR).

The output of the DAC has a full scale current between 8.6 mA and 31.7 mA. This current will pass

through a 50 ohm resistor and create a voltage between 430 mV (pp) and 1.585 V (pp).

An OFDM signal with 64 orthogonal sub carriers and a tension of 1.585 V (pp) has a power as low

as 0.158 mW (simulated, the signal is stochastic, maybe lower values can be obtained) which if

spread uniformly by 20MHz gives a power spectral density of −103.576푑퐵푊 ≅−104푑퐵푊. This is

possibly a good approximation of the signal present at the output of the ADC. Considering that that is

the case, from table 3.6, only the DACs with resolutions equal or above 12 bits, AD9745, AD9746 and

AD 9747, would exhibit an SNR bigger than 80 dB (NSD).

We believe the best DAC between all the options is the AD9746. It has an SNR 8 dB better than the

AD9745 and only 2 dB worse than the AD9747. Finally, with an INL of 4 LSB, the AD9747 usually has

a non linearity error that affects the 3 least significant bits of the input codeword, which means only 13

bits are completely non linearity error free.

As for the AD9746, with an INL of only 1 LSB, 13 bits are also completely non linearity error free.

The DAC to be used is then the AD9746. We will consider as a good approximation, that, of the 14 bit

codeword that is the input of the DAC, 12 bits are completely error free (unaffected by noise, distortion

or non linearity). This is important for simulation purposes, as will be verified later, in section 5.

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4. Upconversion 4.1 Introduction

Having been filtered with the demanded quality, the signal must be upconverted to its original

frequency before reaching the modem. The upconversion is the reversed process of the

downconversation already explained. It is done in 2 steps as the downconversion is, which has mainly

to do with the image bands inherent to the mixing processes.

In the first step there is an upconversion of the 20MHz bandwith from a center frequency of 60MHz, to

one of 600MHz. Finally, there is an upconversion of the 600 MHz band, to the center frequency of the

LTE band selected to be filtered.

all the components of the upconversion hardware block are present to make the upconversion as

reliable and innocuous as possible, according to the specifications of the LTE filter to design.

In section 4.2, an overview of the upconversion block is exhibited. The most important information of

the block, architecture wise, is stated along with the discussion of some choices that were made

related to hardware, frequencies, etc. In section 4.3, the amplifications and attenuations performed, to

maintain good values of SNR along the entire upconversion chain, are explained. The possible range

of SNR degradation in this part of the circuit, is calculated. The criteria for these delimiter values

estimation, is stated.

In section 4.4, the upconversion process is described in detail. The mixing steps, LO tones and image

band rejections are explained. All the new filters’ designed circuits are presented, along with the

components used to simulate them.

A simplified explanation of block B’s principle of operation will now be given.

The input of block B comes from the power adapter after the DAC.The first component is a mixer. This

mixer will upconvert the signal to 600 MHz. The amplifiers and attenuators across the chain, serve the

same purposes as in the downconversion block. These are explained in section 2.2 and have mainly

to do with avoiding SNR degradation, while not driving the mixers and amplifiers into compression.

Then, comes FRI2. This filter is the first image band rejection filter in block B and it eliminates the

unwanted replica of the desired signal that was generated in the mixing process. The replica is

100MHz apart from the signal. The filter has exactly the same circuit and components as the filter that

does the rejection of the second image band in the downconversion block, henceforth the name FRI2.

(See section 2.5.2 for its specifications).

Next, the signal encounters BR Notch, which is a band reject filter that works as a Notch filter, to reject

the LO tone of 540MHz introduced in the mixer. After this, the second step of the upconversion is

performed, and the signal is upconverted to its initial frequency, in the second mixer. The image band

and LO tone rejection must still be made, but now, their frequency is variable. This problem needs to

be addressed. For this reason, the signal goes through a 2<->4 MUX and into B block’s final block,

block B1. This is the alternative devised to implementing a huge filter bank and multiplexing system,

with the signal passing through 2 different filters for each different 20 MHz LTE band selected to be

filtered, which would be impracticable.

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4.2 Upconversion Block (Block B)

The design of block B to solve the problem proposed is depicted in figure 4.1. (See section 1.4)

Figure 4.1 – Architecture to be used to construct block B, which was exhibited in the general architecture of the LTE filter, presented in figure 1.2.

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Block B1 architecture is represented in figure 4.2.

Figure 4.2 – Scheme that exhibits the operation of block B1, that is included in figure 4.1. In the band 2 pathway, A pair consisting of Mux 1->2 followed by a Mux 2->1 is also present, both after HP Band 2 Sub Band 2 and before Mux 2->4. Another pair of muxes, exactly like the one just described, is placed after Band 2 Sub Band 3 and before Mux 2->4. These are not shown due to lack of space, because of visualization purposes.

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For the image band rejection, it is enough to take advantage of the already made division of the LTE

bands into 3 major bands, and to design an image rejection filter for each major band. These filters are

already projected, since they are exactly equal to the 3 filters inside block A1 in the down conversion

block, HP1, HP2 and HP3, respectively, by band.

However, the problem of the variable LO tone rejection is more complicated and entails a further

division of the LTE spectrum into smaller bands than the major 3 already existent.

In this way, band 2 was further divided into 3 sub bands and band 3 was split into 2 sub bands. Band

1 remained unchanged. This was necessary so the order of the LO rejection filters obtained was

reasonable and the resultant filters’ response would be stable enough, even with the possible

variations of the functional component values (capacitance, inductance).

The first and last muxes conduct the signal through the image rejection filter of the correspondent

major band the signal is in.

In band 2 and 3, a pair of muxes also lead the signal into the sub band specific LO tone rejection

filters. In band 1, the signal is directly headed to the respective LO tone rejection filter.

Just like in the downconversion block, an isolation of at least 80 dB, between any route of the chosen

path and its parallel routes, is good practice. The importance of this 80 dB isolation has mainly to do

with the filters’ different phase responses and is described in section 2.2.

In the band 1 path, a pair of muxes assures a minimum of 80 dB isolation between the band path

selected and the other 2 that remain “open”. In band 2 and in band 3 paths, there are muxes with the

objective of providing a minimum 80 dB isolation between the chosen sub band path and the other sub

band paths that stay “open”.

This level of isolation is allways achieved except, in band 3, where a minimum isolation of 78 dB is

obtained. This value is only 2 dB below the required isolation and concerns the worst typical case

scenario. It was considered to be good enough. The alternative would be to insert 4 more muxes (2 for

each sub band path) that would add a minimum isolation of 39 dB.

Lastly we would like to call to the attention, the arrow entering the block B1 and terminating right at its

entrance in figures 4.1 and 4.2. This arrow actually connects to all attenuators and muxes in block B1,

since the control unit must be in charge of the path and sub path choice decisions as well as control

the digital step atenuators to avoid the amplifiers to enter into power compression. This is not

represented for obvious reasons related to visualization purposes.

4.3 Upconversion Block SNR At the beginning of the upconversion chain, the minimum signal level in the frequency domain, found

by simulation of the entire Downconversion plus FPGA chain in Matlab was -99.97 dB dBW/Hz (LTE

signal initially centered in 2350 MHz, filters’ components with maximum deviation from ideal values).

The simulation was run for the frequencies of 800MHz, 1500MHz, 1800 MHz, 2350 MHz and

2585MHz. The maximum level of the signal was -94.64 dB/Hz (LTE band initially centered in 2350

MHz. components with ideal values).

Note that in the simulation performed, it was chosen a fixed digital gain in the FPGA block and

because of the fact that the attenuation of the analog filters is changeable with frequency, the signal

LVI

present at the start of the Upconversion block, is also variable with frequency. Different power

spectrums and signal ripples are obtained by varying the center frequency of the 20 MHz LTE band.

Nevertheless, it was guaranteed that the total power of such signal is always below -7 dBm to not

drive the first mixer of the Upconversion circuit into compression. If a new simulation yields a smaller

minimum value for the signal level at block B’s entry, that difference has to be taken into account in

the signal to noise ratio degradation in the upconversion block.

The noisefloor was already calculated in section 2.3 and has the value of ≅ −203,8푑퐵.

The initial SNR at the entrance of block B is: 푆푁푅 = 푆 − 푁 = −99.97— 203.8 =

= 103.83푑퐵 = 80푑퐵 + 23.83푑퐵 = 푆푁푅 + 푆푁푅푑푒푔푟푎푑푎푡푖표푛 Á

To achieve the 80 dB of SNR sought, the maximum SNR degradation must be of 23.83 dB.

Two cases were considered: (i) the SNR degradation in an “optimum case” and (ii) an SNR

degradation in a very bad case. These are defined in section 2.3.2.

Again, sections of the circuit were considered for the calculations of the SNR degradation. Those

sections are defined exactly as in section 2.2 of the thesis and the same parameters are taken into

account to calculate each section’s SNR degradation.

In the upconversion block, the number of sections varies with the band path followed. The first 3

sections are independent of the band in which the signal initially was.

The SNR degradations of these 3 sections and the overall SNR degradation, at this point in the circuit,

are shown in table 4.1

SNR Degradation Attenuation Comparison

Sections Optimum Case Worst Case A max without

attenuators Section 1 7.45 dB 8.05 dB 8.05 dB Section 2 2.3 dB 2.3 dB 7 dB Section 3 1.82 dB 5.55 dB 14.95 dB

Accumulated 11.57 dB 15.9 dB 30 dB Table 4.1 – SNR degradations of the first 3 sections of block B as well as accumulated SNR degradation . The attenuations on the right are present, so the reduction in SNR degradations due to employing amplifiers+attenuators can be evaluated. The next sections are dependent on the LTE band chosen and correspondent path that is followed.

They will be presented in the following order, Band 1 signals, Band 2 signals and Band 3 signals,

repectively in tables 4.2, 4.3 and 4.4.

SNR Degradation Attenuation Comparison Sections Optimum Case Worst Case A max without attenuators Section 4 1.92 dB 8.3 dB 14.4 dB Section 5 1.96 dB 2.3 dB 15.7 dB

Total 15.55 dB 26.5 dB 58.4 dB Table 4.2 – SNR degradations of the specific sections transversed by signals belonging to Band 1, as well as the total SNR degradation in block B for those types of signals. The attenuations on the right are present, so the reduction in SNR degradations due to employing amplifiers+attenuators can be evaluated. The SNR at the end of block B, for signals in band 1, ranges between 77.98 dB (80 + 24.48 - 26.5)

and 88.93 dB (80 +24.48–15.55).

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SNR Degradation Attenuation Comparison Sections Optimum Case Worst Case A max without attenuators Section 4 1.92 dB 9.45 dB 21.15 dB Section 5 2.09 dB 4.9 dB 7.6 dB Section 6 1.23 dB 8.15 dB 16.45 dB Section 7 1.87 dB 2.3 dB 7 dB

Total 18.68 dB 40.7 dB 82.2 dB Table 4.3 – SNR degradations of the specific sections transversed by signals belonging to Band 2, as well as the total SNR degradation in block B for those types of signals. The values correspond to the pathway of band 2, sub band 3, where the SNR degradation is maximized. The attenuations on the right are present, so the reduction in SNR degradations due to using amplifiers+attenuators can be evaluated. The SNR at the end of block B, for signals in band 2, at worse, range between 63.68 dB (80 + 24.48 -

40.8) and 85.8 dB (80 +24.48–18.68). Like already stated, this values correspond to sub band 3 of

band 2. In sub band 2, the SNR degradation is slighly lower. In sub band 1, despite existing one less

section, the SNR improvement at the end of the chain is just, between 1.29 dB in the optimum case

and 4.36 dB in the worst case, which is a notable but small, improvement.

SNR Degradation Attenuation Comparison Sections Optimum Case Worst Case A max without attenuators Section 4 6.86 dB 13.96 dB 23.96 dB Section 5 2.3 dB 2.3 dB 17.11 dB Section 6 0.57dB 2.1 dB 7 dB

Total 21.3 dB 34.26 dB 78.07 dB Table 4.4 – SNR degradations of the specific sections transversed by signals belonging to Band 3 as well as the total SNR degradation in block B for those types of signals. The values correspond to the pathway of band 3, sub band 2, where the SNR degradation is maximized. The attenuations on the right are present so the reduction in SNR degradations due to using amplifiers+attenuators can be evaluated. The SNR at the end of block B, for signals in band 3, at worse, range between 69.57 dB (80 + 23.83 -

34.26) and 82.53 dB (80 +23.83–21.3).

4.4 Up Conversion Process 4.4.1 First Step The first step in the upconversion process is represented in figure 4.3.

Figure 4.3 – Schema of the process of upconversion of the 20MHz bandwith LTE band from 60MHz to a center frequency of 600MHz. The image band produced is marked with a cross. The intended upconverted band is marked with a circle.

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From figure 4.3, it is made clear that a high pass filter is going to be needed; this filter has the same

exact response, as depicted in figure 2.25. The bands are the ones in figure 2.24.

The 540MHz local oscillator tone inserted in the process must also be rejected at this stage. This way

the tone is rejected always at the same frequency which is low enough to allow the minimum desired

attenuation of 80 dB to be possible. For simulation purposes, a band reject chebyshev filter is used to

simulate a Notch at 540 MHz. The filter response is in figure 4.4.

Figure 4.4 – Ideal reponse of Band Rejection Filter to attenuate the LO leaked tone in 540 MHz.

The filter actually projected is shown in figure 4.5.

Figure 4.5 - Band Rejection Filter to attenuate the LO leaked tone in 540 MHz. The constituent components of the filter are detailed in table a2.7 in the appendix, section 2.3.

4.4.2 Second Step The second step in the upconversion process is represented in figure 4.6.

Image Bands Rejection The image bands generated in this upconversion step depend on the LTE band chosen. Then again,

to accomplish simplicity of the system architecture and to gain flexibility, the image band of the whole

major bands was taken into account. The image band to consider is, therefore, only dependent, on if

the LTE band selected is within band 1, band 2 or band 3.

The necessary HP filters (one for each of the 3 bands), required to filter out the image bands

produced, are exactly the same as the ones exhibited in figures 2.14, 2.18 and 2.22 for band 1, band 2

and band 3 respectively. See section 2.5.1.

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Figure 4.6 – Schema of the process of upconversion from the 600 MHz centered, 20MHz bandwidth band, back to the higher frequency that varies with the LTE band chosen.

Variable LO tone Rejection After having mixed the signal back to its final frequency and having rejected the image of the signal,

generated in the last upconversion step, there is a final problem to address. This is the rejection of the

variable LO tone. In the downconversion block, the correspondent problem was solved on its own by

the conjunction of the BP filter and the LP filter prior to the FPGA. In the upconversion block, at a

much higher frequency, a different solution must be devised.

See figures 4.1 and 4.2.The minimum power density of the signal at the output of the 2nd mixer is:

−99.97− 6.15− 1.9 + 5− 7 + 14.1 − 7.9− 5− 7.05 = −115.87dBW/Hz

The minimum signal power density at the entrance of the sub band filters is, in band 1: −115.87 +

14.1 − 7 − 7.4 − 8+ 14.1 = −115.87 + 5.8 = −110.07dBW/Hz. The LO tones maximum power

must be equal or lower than −110.07− 80 = −190.07dBW at the entrance of HP Band 1 SB11, to

respect, at that point, the 80 dB attenuation specification.

The minimum signal power density at the entrance of the sub band filters is in Band 2: −115.87 +

11.7 − 7 − 7.15 − 7 + 11.7 = −115.87 + 2.25 = −113.62dBW/Hz. The LO tones maximum power

must be equal or lower than −113.62− 80 = −193.62dBW at the entrance of HP Band 2 Sub Band

1,2 and 3, to respect, at that point, the 80 dB attenuation specification.

The minimum signal power density at the entrance of the sub band filters is in Band 3: −115.87 +

10 − 7 − 7.6 − 1.1 = −115.87− 5.7 = −121.57dBW/Hz

The LO tones maximum power must be equal or lower than −121.57− 80 = −201.57dBW at the

entrance of HP Band 3 Sub Band 1 and 2, to respect, at that point, the 80 dB attenuation specification.

Note that the attenuators’ and the muxes’ insertion loss increases with frequency and the gain of the

amplifiers decreases with frequency. This means the higher a frequency is, the more attenuated or

less amplified the power in it will be. Both LO1 and LO2 usually have a considerably lower frequency

than the signal (the difference is not always big enough to be relevant), therefore, good safety margins

for the variable frequency LO tone required attenuations, are recommended.

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A tangent topic will now be touched upon, the absence of the need to further attenuate the LO tone

introduced in the first upconversion step, will now be proved. The LO tone introduced in the first

upconversion mixing step will be called LO1 exactly as was done for the downconversion process. It is

inserted with an amplitude of -49.41 dB. It has a frequency of 540 MHz. The maximum LO1 power, in

the conditions where the signal level is at its minimum, at the output of the 2nd mixer, is approximately

equal to: −49.41− 1.9 + 5 − 54(퐹푅퐼2) + 14.1− 107.05(퐵푅푁표푡푐ℎ)− 5− 7.05 = −205.31푑퐵푊

The band 3 pathway is the one where the signal power level is lowest. In that worst case scenario, the

80 dB of LO1 tone level attenuation in relation to the signal is exceeded. It is concluded LO1 doesn’t

need any additional attenuation. The safety margin achieved is of −201.57 − (−205.31) = 3.74푑퐵

Let us return to the rejection of the variable LO tone added in the second upconversion step.

Again, the LO tone introduced in the second mixer will be called LO2. It is inserted with an amplitude

of -49.41 dB and a variable frequency that depends on the LTE band to filter. Several filters have to be

designed to reject the variable LO tone. Each filter will reject the tone in a certain band of frequencies.

Note that the highest order filter until this point is FRI2, an 11th order filter. It reaches 80 dB attenuation

in a 100 MHz transition band that goes approximately between 500 and 600 MHz.

In the variable LO rejection case, the filters’ transition band is very often situated at a much higher

frequency, and the filter will need to have a considerably larger transition band to compensate (order

<11). A transition band of approximately 300 MHz or higher will be used in all these types of filters.

To make it possible for the filters to have transition bands of that size, band 2 will be subdivided in 3

sub bands and band 3 is going to be subdivided in 2 sub bands. The sub bands of all respective

bands are described in the following sub section.

Bands and Sub Bands Band 1 – The signal goes from 698 to 960 MHz. The LO tone goes from 108 a 350 MHz.

Band 2 – The signal goes from 1427.9 to 2200 MHz. The LO tone goes from 837.9 to 1590 MHz.

Band 2 Sub Band 1 - The signal goes from 1427.9 to 1700 MHz. The LO from 837.9 to 1090 MHz.

Band 2 Sub Band 2 – The signal goes from 1700 to 2000 MHz. The LO goes from 1090 to 1390 MHz.

Band 2 Sub Band 3 – The signal goes from 2000 to 2200. The LO tone goes from 1390 to 1590 MHz

Band 3 – The signal goes from 2300 to 2690 MHz. The LO tone goes from 1710 to 2080 MHz.

Band 3 Sub Band 1 – The signal goes from 2300 to 2500 MHz. The LO from 1710 MHz to 1890 MHz.

Band 3 Sub Band 2 – The signal goes from 2500 to 2690 MHz. The LO from 1890 MHz to 2080 MHz.

It is demanded for the LO tone to be 80 dB below the signal level at the entrance of the modem. In the

next sub section, the calculations of the minimum attenuation needed, for the LO tone rejection filter(s)

of each sub band, to comply with this specification, is computed.

Calculations of the minimum attenuations required for the several LO rejection filters In the case where the signal power density is lowest, the power of the LO2 at the entrance of the sub

band filters is band dependent.

In Band 1 it is around −49.41+ 14.1 − 7(푀푈푋)− 105.58(퐻푃퐵푎푛푑1)− 8+ 14.1 =

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= −36.21– 105.58 = −141.79푑퐵푊

105.58 dB is the minimum attenuation presented by HP Band 1 to the LO tone, which frequency, goes

from 108 to 350 MHz. Optimum and worst cases were simulated so the minimum value was selected.

The minimum additional attenuation, required to accomplish the 80 dB attenuation of LO2 in

comparison with the signal in band 1 is: −141.79푑퐵– (−190.07dB) = 48.28dB

In Band 2 it is near −49.41+ 11.7 − 7(푀푈푋)−퐴(퐻푃퐵푎푛푑2)− 7(푀푈푋) + 11.7 =

= (−40.01–퐴)푑퐵

A is the minimum attenuation of the HP band 2 filter in each sub band. In sub band 1, LO2 goes from

837.9 MHz to 1090 MHz. In sub band 2, it is between 1090 and 1390 MHz. Finally in sub band 3, it

goes from 1390 to 1590 MHz. Both the optimum and worst cases were simulated and the minimum

values were selected. In sub band 1, A = 70 dB, and therefore 퐿푂2 == −40.01− 72.2 =

−112.21푑퐵푊. The minimum additional attenuation required to accomplish the 80 dB attenuation of

LO2 in comparison with the signal, in band 2, sub band 1 is −112.21— 193.62 = 81.41푑퐵.As for sub

band 2, A = 9.02 dB and so 퐿푂2 = −40.01

−9.02 = −49.03푑퐵. The additional attenuation required is of −49.03— 193.62 = 144.59푑퐵. Finally

in sub band 3, A = 6 dB, which means 퐿푂2 = −40.01− 6 =

= −46.01푑퐵. The additional attenuation required is of −46.01− (−193.62) = 147.61푑퐵.

In Band 3 it is approximately −49.41+ 10 − 7(푀푈푋)−퐴(퐻푃퐵푎푛푑3) − 1.1(푀푈푋) =

= −47.51–퐴 푑퐵. As for sub band 1, A = 45.12 dB, which leads to 퐿푂2 = −47.51

−45.12 = −92.63푑퐵. The minimum additional attenuation required to accomplish the 80 dB

attenuation of LO2 in comparison with the signal, in band 3, sub band 1 is equal to −92.63−

(−201.57) = 108.94푑퐵. Finally in sub band 2, A = 27.71 dB, therefore, 퐿푂2 = −47.51− 27.71 =

−75.22푑퐵. The additional attenuation required is of −75.22− (−201.57) = 126.35푑퐵.

The following subsection will consist first, of a summary of the calculated specifications of the LO

rejection filters and then, of a display of the filters (the ones that answer to the specifications) actual

circuits.

Summary of Specifications and Filters Actually Projected Sub Bands A min required [dB]

SB1 48.28 SB21 81.41 SB22 144.59 SB23 147.61 SB31 108.94 SB32 126.35

Table 4.5 – Minimum attenuations required of each LO rejection filter to achieve the sought after 80 dB LO tone attenuation in relation to the signal. The filters are identified by the respective sub band where they function. The implementation of these filters will consist of either a high pass T configuration elliptic filter or a

series of 2 such filters. The goal is to obtain minimum order filters that answer, to the specifications

condensed in table 4.5 (without using too many filters). The ideal responses of the filters that meet the

requirements and those filters’ actual circuits and simulation components, will now be presented.

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Band 1 To reject the LO tone, the ideal filter response represented in figure 4.7 can be used.

Figure 4.7 – Ideal response of high pass filter to reject the variable oscilator leaked tone in Band 1. The filter projected in practice is exposed in figure 4.8.

Figure 4.8 – High pass filter to reject the variable frequency oscilator leaked tone in Band 1. The constituent components of the filter are detailed in table a2.8 in the appendix, section 2.3.

Band 2 Sub Band 1 To reject the LO tone, the ideal filter response presented in figure 4.9 can be used.

Figure 4.9 – Ideal response of high pass filter to reject the LO leaked tone in Band 2 Sub Band 1.

The filter projected in practice is exhibited in figure 4.10.

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Figure 4.10 – High pass filter to reject the variable frequency oscilator tone in Band 2 Sub Band 1.

The constituent components of the filter are detailed in table a2.9 in the appendix, section 2.3. Band 2 Sub Band 2 To reject the LO tone, the ideal filter response presented in figure 4.11 can be used.

Figure 4.11 – Ideal response of HP Filter to reject the LO leaked tone in Band 2 Sub Band 2. The filter projected in practice is shown in figure 4.12.

Figure 4.12 – High pass filter to reject the variable oscilator leaked tone in in Band 2 Sub Band 2. The signal must pass through 2 of these filters to achieve the minimum attenuation required. If only one filter was to be used, its order would need to be, mandatorily higher than 11.

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The components of the filter are detailed in table a2.10 in the appendix, section 2.3. Band 2 Sub Band 3 To reject the LO tone, the ideal filter response presented in figure 4.13 can be used.

Figure 4.13 – Ideal response of the high pass filter to reject the variable frequency oscilator tone in Band 2 Sub Band 3. The filter projected in practice is exposed in figure 4.14.

Figure 4.14 – High pass filter to reject the variable oscilator leaked tone in Band 2 Sub Band 3. The signal must pass through 2 of these filters to achieve the minimum attenuation required. If only one filter was to be used, its order would need to be higher than 11. The components of the filter are detailed in table a2.11 in the appendix, section 2.3. Band 3 Sub Band 1 To reject the LO tone, the ideal filter response presented in figure 4.15 can be used.

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Figure 4.15 – Ideal response of the high pass filter to reject the variable frequency oscilator leaked tone in Band 3 Sub Band 1. The filter projected in practice is exhibited in figure 4.16.

Figure 4.16 – High pass filter to reject the variable frequency oscilator in Band 3 Sub Band 1. The signal must pass through 2 of these filters to achieve the minimum attenuation required. The components of the filter are detailed in table a2.12 in the appendix, section 2.3.

Band 3 Sub Band 2 To reject the LO tone, the ideal filter response presented in figure 4.17 can be used.

Figure 4.17 – Ideal response of the high pass filter to reject the variable frequency oscilator leaked tone in Band 3 Sub Band 2. The filter projected in practice is shown in figure 4.18.

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Figure 4.18 – High pass filter to reject the variable frequency oscilator tone in Band 3 Sub Band 2. The signal must pass through 2 of these filters to achieve the minimum attenuation required. If only one filter was to be used, its order would need to be higher than 11.

The components of the filter are detailed in table a2.13 in the appendix, section 2.3. The next subsection will display a comparison between the specifications to be met and the

attenuations actually attained. The safety margins will be analyzed and commented on.

Comparisons between specifications and results Once more, the filters were simulated according to the simulation components selected and their

respective specifications’ tolerances. The optimum case where the values of the components are

closer to the ideal values and the very bad case where the components values are furthest apart from

the ideal were the two delimiter case studies. The attenuation accomplished was, in both cases, identified and those values were always compared

with the minimum attenuation required. These results are specified in table 4.6.

Bands A min required [dB] A min real A max real SB1 48.28 65.77 66.22

SB21 81.41 89.24 89.44 SB22 144.59 2x79.31 = 158.62 2x82.28 = 164.56 SB23 147.61 2x85.46 = 170.92 2x87.39 = 174.78 SB31 108.94 2x60.34 = 120.68 2x= 61.35 = 122.7 SB32 126.35 2x75.59 = 151.18 2x77.67 = 155.34

Table 4.6 – Minimum LO attenuation required and actual LO attenuation reached in the optimum and very bad case scenarios.

In order to make it easier to analyze the results present in table 4.6, the differences between the

minimum and maximum attenuations attained and the minimum attenuation required was calculated.

The values are exposed in table 4.7.

Bands Min Margin Max Margin Difference Order SB1 17.49 17.94 0.45 5 SB21 7.83 8.03 0.2 9 SB22 14.03 19.97 5.94 9 SB23 23.31 27.17 3.86 9 SB31 11.74 13.76 2.02 7 SB32 24.83 28.99 4.16 9

Table 4.7 – Safety margins accomplished in relation to the minimum LO attenuation required. Also, comparison between optimum and very bad case and display of the order of the filters designed.

LXVII

Note that the attenuators’ and the muxes’ insertion loss increase with frequency and the gain of the

amplifiers decrease with frequency. This phenomenon was not taken into account into the calculations

performed and it must now be considered. Both LO1 and LO2 usually have a substantially lower

frequency than the signal. The margin for LO1 is quite high so it shall not be a problem. As for LO2, it

always has a frequency 600 MHz lower than the center frequency of the signal. A good safety margin

is recommended. Observing table 4.7, it is concluded, that the minimum safety margin achieved

varies between 8.48 and 25.48 dB. A value of approximately 8.5 dB or higher, is a considerable

safety margin which is thought to be enough to compensate the effect of bigger gain and smaller

attenuation of the LO in comparison with the ones of the signal, due to a 600 MHz gap in frequency.

The following subsection will exhibit the attenuation that all the new filters (upconversion block only),

present to the signal, instead of the attenuation they pose to the LO tones. This is relevant to perform

the calculations on section 4.3 that treats the issue of the SNR degradation in the upconverson block.

This information is also very important to gain a notion of the quality of filtering achieved by each filter.

Simulation range of Attenuation of the filters designed The values of attenuation the signal suffers, when it passes through filters in the upconversion block,

which are made of components that happen to have no deviation (or the least amount of deviation,

when it is inevitable) from their ideal values of capacitance or inductance, are given in table 4.8. It is

reminded that the components used were defined along section 4.4.

Upconversion – Filters Attenuation in The Signal in the Optimum case

Filter 푨풎풊풏[풅푩] 푨풎á풙[풅푩] Notch 540 MHz (BR) 6.05 7.1

HP Sub Band 11 6 7 HP Sub Band 21 6 7.32 HP Sub Band 22 6 7.04 HP Sub Band 23 6 7.14 HP Sub Band 31 6 7 HP Sub Band 32 6 7.06

Table 4.8 – Attenuation of Upconversion block exclusive, filters, with ideal value components.

The values of attenuation the signal withstands when it passes through filters in the upconversion

block when these are made of components which happen to have the biggest amount of deviation

from their ideal values (capacitance, inductance) are given in table 4.9. It is reminded that the

components used were defined throughout section 4.4.

Downconversion – Filters Attenuation in The Signal in the Worst Case

Filter 푨풎풊풏[풅푩] 푨풎á풙[풅푩] Notch 540 MHz (BR) 6.2 7.9

HP Sub Band 11 6 7 HP Sub Band 21 6 8.14 HP Sub Band 22 6 7.31 HP Sub Band 23 6 7.6 HP Sub Band 31 6 8 HP Sub Band 32 6.17 8.26

Table 4.9 – Attenuation of Upconversion block exclusive, filters, with furthest from ideal value components.

LXVIII

5. Matlab and FPGA Simulations 5.1 Single Run Matlab Simulation 5.1.1 OFDM Signal generation To simulate the LTE filter projected, in Matlab, an input digital signal that most resembles a typical

LTE received signal, must be used. LTE technology uses OFDM (orthogonal frequency division

multiplexing) and so, for simplicity, an ofdm signal carrying 4-QPSK symbols was selected. Note that

this way all symbols have the same power and the signal power density will therefore, in theory, be

uniform.

The ofdm signal is generated in the way depicted in figure 5.1.

0S

1S

1NscS

)2cos( tf c

)2sin( tf c

}{e

}{m

Figure 5.1 – Scheme of the generation of an ofdm signal centered at frequency 푓 .

The generation of the signal happens as follows. An array of random bits is generated recurring to the

rand function. That function generates random numbers with a uniform distribution between 0 and 1. If

the number generated is less than 0.5 it is converted in a 0, otherwise, it is converted in a 1. Next,

those bits are grouped in pairs and mapped to QPSK symbols with a real and an imaginary part. A

vector having the size of the number of carriers,푁 , is formed with the symbols. To note that, in each

ofdm symbol, each carrier will carry one QPSK symbol. Once the symbols to be transmitted and the

number of sub carriers to be used are selected, an IFFT is performed to determine the correspondent

time samples. These samples are complex, in other words, they have a real and an imaginary part.

Because OFDM is a digital modulation method, the power spectrum of an OFDM signal is periodic in

frequency, that is, it has infinite replicas. These replicas are centered in frequencies multiples of BW

(Bandwidth), showing themselves as rectangles contiguous in frequency. This arises problems

because we will need to filter our signal with filters accomplishable in practice. If the replicas continue

right next to the signal, the filter will not be able to reject them in a satisfactory way and there will be

distortion in the signal. To solve this problem, zero padding in the frequency domain will be used. This

technique consists in having subcarriers with zero amplitude in frequencies more negative and more

positive than the signal.

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Next the real and imaginary part of the time samples of the signal are each fed to a DAC (Digital to

Analog Converter). This component was modeled by an ideal sample & hold block, followed by an

ideal low pass filter.

The sample and hold is equivalent to a convolution by a comb of discrete dirac deltas (in other words,

a discrete rect), and so it will be a filter which in the frequency domain has a sinc shape.

It is implemented in the following way: A number of zeros given by the variable Nchips is inserted

between samples. Then the convolution is performed with an array of ones of size equal to the

number of zeros between samples (Nchips). The output is then limited to the first Nsc*Nchips points

since the convolution will generate some surplus points at the end of the output array. The low pass

filter follows the sample and hold and it will produce an analog signal that will ideally pass through the

samples at the middle of the holding intervals. This will in fact happen, but just because the LP filter

simulated was an ideal rectangular filter that only let pass the baseband OFDM signal and perfectly

rejected all its replicas in frequency.

The final step of the process is to modulate both analog signals obtained in a quadrature modulation

(QAM, to be more specific). This is so that both signals can be transmitted at the same time (the real

part signal and the imaginary part signal). In this way, an ofdm signal is generated and its real and

imaginary parts can be obtained through the adequate signal processing procedures. Having finished

the explanation of the ofdm signal generation, a few ofdm simulation concepts will be explained so

that the simulation procedure can be understood and adapted to different cases.

5.1.2 Analog Filters Simulation The analog filters, required for the implementation of the LTE filter architecture, showed in figure 1.1,

were projected in the software “AADE Filter Design V4.5” and simulated in PSPICE taking into

account the components’ value tolerance. The simulation capacitors chosen were always tunable and

for simulating inductors, fixed inductors were used. All the components were searched on

www.digikey.com .

To simulate these filters in Matlab, it was imperative to obtain the value of their transfer function on

every frequency that is part of the frequency simulation array (frequency domain window with

frequency intervals of a certain precision, used in the Matlab simulation).

This array usually (Nsc = 64), has values from -3.9997 GHz to 4 GHz with a spacing of 312.5KHz in a

total of 25600 points.

In order to tackle this problem, a systematic method was developed, which is presented in appendix,

in section 5.1.

5.1.3 Matlab Simulation Results The Matlab simulation was performed. The most important data present in the datasheets of the

components that were used, namely, mixers, muxes, attenuators and amplifiers, was inserted on the

Matlab script developed. The whole LTE filter chain has been simulated. The biggest values of

attenuation possible were considered (minimum gains and maximum values of attenuation in the

attenuators). The analog filters were simulated as having their optimum case component values. The

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signal was selected to be centered at 2585 MHz. Snapshots of the signal along the entire

downconcersion, FPGA and upconversion chains will now be displayed sequentially. Those will be

commented upon. It is advised that, for visualization purposes, the reader consults figures 2.1, 2.2, in

section 2 and figures 4 and 4.1 in section 4. At the beginning of block A the signal assumed to be

received by the antenna has a power spectrum resembling the one present in figure 5.2.

Figure 5.2 – Power spectrum at the entrance of block A. White noise was generated with such a power that it’s spectral power density is similar (but slighly

lower for visualization purposes) to that of the signal. The goal is to simulate an unknown spectra

except for the signal to be filtered. The spectra might be filled by all sort of signal types in all kinds of

frequency bands and to emulate this, white gaussian noise was generated in the fashion just

illustrated.

The signal is centered on ∓2585MHz and can be spotted by the vertical traces below the noise. The

sinc shaped spectra of the signal power density rises above the noise. A zoom of figure 5.2 is

exhibited in figure 5.3. The sinc shape can be identified in that last picture.

Figure 5.3 – Zoom in of power spectrum of signal at the entrance of block A.

-3000 -2000 -1000 0 1000 2000 3000

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Signal Received By The Antennafc=2585 MHZ, LB=20MHz

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The signal power density varies between -76.5dBW and -77.4 dBW. The signal then passes through

a Mux 2<->4 and encounters HP Band 3. The results are exposed in figure 5.4.

Figure 5.4 – Power spectrum after HP Band 3. Again the signal can be identified by the vertical traces in the picture. Once more, a zoom in of the

signal is presented, this time in figure 5.5.

Figure 5.5 – Zoom in of power spectrum of the signal after HP Band 3. Note that the maximum power of the signal is around -90 dBW. This equates to -76.5dBW – 7dB from

the Mux – 6.5 dB from HP Band 3. Next, after Mux 1->2, Mux 2->1 and Mux 4<->2, the first Down

conversion step is performed. The results are displayed in figure 5.6.

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Power Spectrum after FRI1fc=2585 MHZ, LB=20MHz

Frequency [MHz]

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Figure 5.6 – Power spectrum after the Down Conversion first mixing step. It is apparent the leaked LO tone power is way higher than the signal power density level. The signal

can be spotted by the vertical traces in the bottom of the picture and is predictably centered at 600

MHz. It still rises slightly above the white noise.

A zoom in of the LO leaked tone is illustrated in figure 5.7.

Figure 5.7 – Power spectrum of the LO Isolation error after the 1st mixing step of the Downconversion.

The LO leaked tone has a power around -54.29 dBW. It has a frequency of 1985 MHz.

A zoom in of the signal at the IF is shown in figure 5.8.

To note that the IP3 error after each downconversion or upconversion step is displayed and discussed

in the appendix, section 5.3.

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Power Spectrum after Down Conversion to 600 MHzfc=2585 MHZ, LB=20MHz

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-55

-54.5

-54

LO Isolation error after Down Conversion to 600MHz

Frequency [MHz]

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Figure 5.8 – Zoom in of power spectrum of the signal after Down Conversion 1st mixing step.

The maximum power density of the signal is near -106 dBW/Hz. This is approximately equal to -90

dBW/Hz – 9 dB of insertion losses from the muxes and -7dB from the mixer’s insertion loss.

Then the signal goes through an amplifier and reaches FRI2. The power spectrum after this is

exposed in figure 5.9.

Figure 5.9 – Power spectrum after second Image band Rejection Filter , FRI2. The signal can be spotted at the edges right before the filter starts to increase its attenuation in a very

steep fashion. The LO tone power is still very high and and it (LO) is thus, easily identifiable. A zoom

in of the signal is presented in figure 5.10.

400 450 500 550 600 650 700 750 800-150

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Signal at IF after Down Conversion to 600 MHzfc=2585 MHZ, LB=20MHz

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Power Spectrum after FRI2Downconversion, fc=2585 MHZ, LB=20MHz

Frequency [MHz]

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Figure 5.10 – Zoom in of power spectrum of the signal after FRI2.

The signal has a maximum power density of -96.75 dBW/Hz. This is equal to -106dBW/Hz +15.7dB of

the gain of the amplifier minus 6.45 dB of attenuation in FRI2. There is a 0.7 dB (−97.3푑퐵 −

(−98)푑퐵 ) deformation that happens in the left side of the spectrum of signal. This is very hard to

avoid. Note that this filter is the most stringent of the entire chain, having an order of 11, whereas the

most demanding filters excluding this one, have an order of 9.

After this, the signal encounters an attenuator followed by a mixer that will execute the second mixing

step of the down conversion. The spectrum after this is exhibited in figure 5.11.

Figure 5.11 - Power spectrum after the Down Conversion second mixing step.

The previous LO tone, LO1, got mixed, which gave origin to two LO tones instead of one. These have

a spectral power density of -56.4 dB. The frequencies are 1985 ∓ 540푀퐻푧 which means, 1445 MHz

and 2525 MHz.

Note that -56.4 dBW = -54.29 dBW + 15.7 dBW from the amplifier – 6.46 dB from FRI2 – 5.2 dB from

the attenuator – 6.15 dB from the insertion loss of the mixer.

200 400 600 800 1000 1200-150

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Power Spectrum after FRI2Downconversion, fc=2585 MHZ, LB=20MHz

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Power Spectrum after Down Conversion to 60 MHzfc=2585 MHZ, LB=20MHz

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A new leaked LO tone, LO2, is introduced with a frequency of 540 MHz. It has a power of -54.29

dBW, as was to be expected. The signal is centered at 60 MHz and is near the gap around DC (0 Hz),

caused by FRI2. A zoom in of the signal is depicted in figure 5.12.

Figure 5.12 – Zoom in of power spectrum of the signal after Down Conversion 2nd mixing step.

The maximum power density of the signal is near -108 dBW. This is approximately equal to -

96.75 dBW – 5.2 dB from the attenuator – 6.15 dB from the insertion loss of the mixer.

Next, the signal passes through an attenuator (with 5.5 dB attenuation) and an amplifier (with a gain of

17.4 dB) and arrives at the Band Pass Filter.

Figure 5.13 - Power spectrum after the Pre Processing Band Pass Filter.

The signal power density varies between -104.6 dBW/Hz and -102.4 dBW/Hz. This can be seen in

figure 5.14 where there is a zoom in view of the signal spectra. The LO in 540 MHz has a power of -

162.8 dBW and it is 58.2 dB below the signal. The LO at 1445 MHz has a power of -170.6 dBW

and is thus 66 dB below the signal. Finally the LO tone at 2525 MHz has a power of -175.2 dBW and

is 70.6 dB more attenuated than the signal.

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Figure 5.14 – Zoom in of the power spectrum of the signal after the Band Pass Filter.

Once again the signal traverses an attenuator (with 12.4 dB attenuation) and then an amplifier (with a

gain of 15.4 dB) and then finds the Low Pass Filter, the last filter in the Downconversion Block. The

resultant spectra can be consulted in figure 5.15.

Figure 5.15 - Power spectrum after the Pre Processing Low Pass Filter.

The signal power density varies between -108.3 dBW/Hz and -105.45 dBW/Hz.

This can be seen in figure 5.24 where there is a zoom in view of the signal spectrum. The LO at 540

MHz has a power of -221.59 dBW and is therefore 113.29 dB more attenuated than the signal.

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Power Spectrum after Band Pass Filterfc=2585 MHZ, LB=20MHz

Frequency [MHz]

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Figure 5.16 – Zoom in of power spectrum of the signal after the Low Pass Filter.

Considering that the signal that leaves the LP filter is exactly the one that enters the ADC, the output

of the frequency domain simulation of the signal after the ADC, is exhibited in figure 5.17.

Figure 5.17 - Power spectrum after the Analog to Digital Converter.

The signal power density varies approximately between -138.65 dBW/Hz and -136 dBW/Hz. The

signal went down roughly 30 dB by the ADC (analog to digital converting) process. This was due to

the time sampling of 250 MSPS (mega samples per second). Now, on 45 MHz the power spectrum is

around -147.7 dBW and on 75 MHz it is around -145.5 dB.

After the time sampling, the absolute values of the samples are taken. Those are normalized to an

interval from 0 to 0.857. This is due to the FPGA digital filter + equalizer that will amplify the values of

some samples. The samples’ values are mandatory to be between 0 and 1, at any point inside the

FPGA. The power spectrum after this procedure can be consulted in figure 5.18.

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Figure 5.18 - Power spectrum after Normalization and before the FPGA Digital Filter. The signal power density goes nearly between 6 dBW/Hz and 8.9 dBW/Hz, which shows a jump of

about 130 dB in the signal power density due to the normalization procedure alone.

What follows is the crossing of this signal with the FPGA Digital Filter. The frequency domain output of

that filter, after a renormalization, is presented in figure 5.25.

Figure 5.19 - Power spectrum after FPGA Digital Filter, after Renormalization.

After the signal being digitally filtered in the FPGA, it is renormalized back to its original value range so

that it can be compared with the signal present before the ADC. The signal now varies between -

138.86 dBW and -135.44 dBW. The 1 dB ripple introduced clearly took its toll.

This figure (5.19) must be compared with figure 5.18. Note the impact of the filtering. The edges on

the outer frequencies of the signal band are now much steeper, smoother and thinner. For instance,

on 45 MHz or below the power spectrum density is now, at maximum, -234.2 dBW and on 75

MHz or above, the power spectrum density is always equal or below of -227.9 dBW. This means, 95

dB attenuation on the left edge of the signal and 88.7 dB attenuation on the right edge of the signal,

were reached, after the respective 5 MHz transition bands. The 80 dB attenuation intended was

exceeded and the digital filtering was a success. The noisefloor is sensitively around -245 dB.

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After passing through the FPGA digital filter, the signal is going to be equalized. This is to nullify the

effect of a big part of the ripple induced in the signal in the whole Downconversion and Upconversion

chains. Finally, a simulation gain is applied to the signal, to simulate the power level adapter that

exists after the DAC. The resultant power spectrum is exposed in figure 5.20.

Figure 5.20 - Power spectrum after FPGA Equalizer and after power adaptation before the signal encounters the first Upconversion mixer.

The signal power density has values roughly between -95.54 and -93.38 dBW/Hz. To note that the

spectrum of the signal is evidently higher on the lower frequencies. This is to counter the effects of the

filters ahead that attenuate more the lower frequencies than the higher ones.

It is of the utmost importance to call the reader’s attention to something that has happened. After the

equalization was performed, all the samples were rounded so that only the 12 most significant bits of

each sample were used to represent them. This is because, after the DAC, only the 12 most

significant bits will be error free from the DAC operation itself.

The noisefloor has consequentially gone up a lot, being now around -167 dB. The SNR is now near

71.25 dB. This is the single bottleneck of the system performance. If a better, accessible DAC, is put

on the market, it shall be used instead. The signal to noise ratio, will, at this stage in the chain,

increase 6.02 dB (20 log 2) if one error free bit added in the resolution the DAC can handle. If 2

additional error free resolution bits are available, the DAC will no longer be an impairment to the

minimum quality of filtering of 80 dB guaranteed by the remaining system developed.

Next, the signal crosses the DAC. The DAC is simulated just as explained in the OFDM signal

generation sub section (sub section 5.1.1). It is therefore, an ideal DAC, comprised of an

oversampling, a sample and hold and finally an ideal low pass filter. The spectrum after each of these

three phases of the digital to analog conversion is shown respectively in figures 5.21, 5.22 and 5.23.

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Figure 5.21 - Power spectrum after Oversampling. The replicas have appeared exactly as expected. See figure 2.28 in section 2.5.3. The signal power density is the same as in figure 5.20 (last figure).

Figure 5.22 - Power spectrum after the Sample and Hold. The replicas have been multiplied by a sinc shape. The signal power density has slighly changed. This is better visible in the next figure, figure 5.23, where only the 60 MHz replica remains, all other replicas having been rejected by the ideal low pass filter.

Figure 5.23 - Power spectrum after DAC ideal Low Pass Filter. The signal power density varies approximately between -97.58 dBW/Hz and -94.88 dBW/Hz. At this stage, there is, thus, a temporary ripple of around 2.7 dB in the signal.

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This noise (in the worst case, lower frequencies than the signal spectra) is frequently composed of

tones with a power of -169 dBW, which is only 71.42 dB below the signal minimum level of power

spectral density. This can be observed in figure 5.22.

Then the signal goes into the mixer that performs the first upconversion step. It can be inspected in

figure 5.23 that the power density average, of the signal spectra delivered to the mixer, is below -96

dBm. This means, said signal has a power under 7 dBm, which is 3dB away from saturating the mixer.

The output spectrum after the first upconversion step is completed, is displayed on figure 5.24.

Figure 5.24 - Power spectrum after first Upconversion mixing step.

A LO tone with a power density of -49.41 dBW was introduced with a frequency of 540 MHz.

The signal is now centered at 600 MHz and its image band, centered in 480 MHz, has appeared with

the same power density. In comparison with last figure, the signal has just suffered the effect of a 6.15

dB conversion loss, its power density being now between -103.73 and -101.03 dBW. Next, the signal

faces an attenuator (with attenuation equal to 1.9 dB), then an amplifier (with a gain of 15.7 dB) and

after that, it crosses FRI2, that will filter the undesired image band created in this upconversion first

mixing step. The resulting power spectrum is presented in figure 5.25.

Figure 5.25 - Power spectrum after Upconversion first Image Band Rejection Filter, FRI2.

The signal power density varies between -95.97 and -93.90 dBW/Hz. To note that -93.90 dBW/Hz is

equal to -101.03 dBW/Hz – 1.9dB from the attenuator + 15.7 dB from the amplifier

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– 6.67 dB from the FRI2. The ripple in the signal is now only slightly above 2 dB.

The image band of the signal has a maximum power density of -191.35 dBW/Hz. The rejection of the

image band was thus successful, since it is now more than 90 dB more attenuated than the signal.

After this, the signal goes through an attenuator (with an attenuation of 10.7 dB), an amplifier (of gain

equal to 14.1 dB) and finds a Band Reject Filter that works as a notch to cut the leaked LO tone of

frequency 540 MHz. This filter’s response is illustrated in figure 5.26. The power spectrum after

crossing this filter, is exhibited in figure 5.27.

Figure 5.26 – Filter response of an order 6, Chebyshev, Band Reject Filter, that functions as a Notch to the 540 MHz frequency. The attenuation provided by this notch is quite high, exceeding 250 dB in 540 MHz. The result is this

good only because closest to ideal component values were used.

Figure 5.27 - Power spectrum after “Notch” at 540 MHz (the filter response is shown in figure 5.26)

The signal power density varies between -99.17 and -97.29 dBW/Hz. -99.17 dBW/Hz is equal to -

95.97 dBW/Hz – 10.7 dB from the attenuator + 14.1 dB from the amplifier – 6.6 dB from the “Notch”.

The ripple in the signal is, at this point in the circuit, slightly below 2 dB.

It is observed in figure 5.27 that the leaked LO tone is more than 120 dB

more attenuated than the minimum power density of the signal.

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After the “Notch”, the signal encounters an attenuator (with an attenuation of 5 dB) and then enters the

mixer that will perform the upconversion second mixing step. The output spectrum of that mixer, is

depicted on figure 5.28.

Figure 5.28 - Power spectrum after the Upconversion second mixing step.

A new LO tone, LO2, with a frequency of 2585 – 600 = 1985 MHz, was leaked. The power of LO2 is -

49.41 dBW, as was prospective. The signal power density stands approximately between -111.22 and

-109.34 dBW/Hz. This is better observed on figure 5.29 that shows a zoomed in view of just the signal

and its image band on the positive frequency side of the spectrum.

Figure 5.29 – Zoom in of power spectrum of, signal at IF and respective image band.

Comparing with figure 5.28, it is visible that the signal suffered the effect of the 5 dB attenuation in the

attenuator plus 7.05 dB attenuation due to the insertion loss of the mixer.

The signal has already returned to its original center frequency, 2585 MHz.

The image band and leaked LO tone, present in the power spectrum, still have to be rejected in

comparison with the signal. The image band issue is tackled first. For this purpose the signal goes

through an amplifier (with a gain of 10 dB), a 2<->4 Mux (with an insertion loss of 7 dB) and finally

reaches HP Band 3 filter that attenuates the image band of the signal. The output power spectrum is

presented on figure 5.30.

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Figure 5.30 - Power spectrum after the HP Band 3 filter.

The signal power density is now between -114.55 and -112.63 dBW/Hz. -114.55 dBW/Hz is equal to -

111.22 dBW/Hz – 7 dB from the mux + 10 dB from the amplifier – 6.33 dB from the HP Band 3 Filter.

The image band has now a maximum value of power density of -211.40 dBW/Hz. It is then, at least

96.85 dB more attenuated than the signal and it has thus been, sufficiently rejected.

Finally, only the LO tone at 1985 MHz remains to be rejected. To address this, the signal traverses

a Mux 1->2 (with insertion loss of 1.1 dB), a first HP Band 3 Sub Band 2 Filter, an amplifier (with a

gain of 10 dB), a second HP Band 3 Sub Band 2 Filter, a Mux 1->2 (with insertion loss of 1.1 dB), a

Mux 2->1 (with 1.2 dB attenuation) and another Mux 2->1 (with insertion loss of 1.2 dB). Finally, the

signal still crosses a second amplifier (with a gain of 10 dB) and a last Mux 4->2 (with an insertion loss

of 7 dB) and at last, leaves block B1 to enter the modem. With the exception of the attenuation

suffered in both of the two HP Band 3 Sub Band 2 Filters, in this whole path the signal suffers an

amplification of 8.4 dB. The power spectrum at the end of block B1 is displayed in figure 5.31.

Figure 5.31 - Power spectrum after HP filter structure to reject the variable LO tone (block B1).

The signal power density now goes nearly, from -119.00 to -116.92 dBW/Hz. This is better

distinguishable in figure 5.32. To note -119.00 dBW/Hz is equal to -114.55 dBW/Hz + 8.4 dB of overall

derived from all the Amplifiers’ gains and the Muxes’ insertion losses – 6.425 dB attenuation from

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each of the two HP Band 3 Sub Band 2 Filters. In this random simulation ran, the DAC originated

noise composed of tones with a frequent power density of, at least, -191 dBW/Hz. It is then concluded,

that the overall signal to noise ratio of the filter is around 72 dB, which represents 72 dB of filtering

quality reached.

As a consequence of these last filters, the leaked LO tone at 1985 MHz, LO2, now renders a power of

-262.16 dBW. It is 143.16 dB attenuated in relation to the signal.

Figure 5.32 – Zoom in of power spectrum of the signal after HP filter structure to reject the variable LO tone (block B1).

The final ripple of the signal is of 2.19 dB, which is inferior to the maximum ripple acceptable of 3 dB.

If, instead of using optimum case components’ values, the components’ values furthest from the ideal

were employed, the ripple attained would be of (–121.92 – (–124.77)) 2.85 dB. Also, a random SNR

attained would be of (–124.77 – (–195)) 70.23 dB. Note that this very bad case scenario is highly more

improbable than the optimum one, since the components’ values tolerance follows a Gaussian shape

probability function and the ideal values are much closer to the expected value of the Gaussian(휇),

than the referred bad case values.

5.2 FPGA Simulation The FPGA code for the digital filter in series with the equalizer was written in VHDL and the FPGA

performance was simulated in Xilinx ISE Design Suite. [33]

The entry signal in the FPGA was originated in Matlab and was applied to the ISE simulation of the

FPGA and also, to a Matlab simulation of the FPGA. This input sequence is normalized so that its

values are always somewhere between 0 and 1. The difference between the output samples of the

FPGA simulator in ISE and of the FPGA simulator in Matlab code are given in figure 5.33.

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Figure 5.33 – Difference between the output samples of the FPGA (time domain) simulated in ISE and the ouptut samples of the FPGA simulated in MATLAB. In the simulations performed, there are 800 time samples that compose the output of the FPGA when its input is one OFDM symbol.

The difference in the value of the samples from the two simulators has only 2 possible values: 0 and approximately 4.883 × 10 . To note that 2 ≅ 4.883 × 10 which is exactly the deviation obtained when it is not equal to 0. The reason for this is that the only difference in both simulators is how the output samples rounding is performed. In the ISE simulator, emulating hardware, the output value is truncated from 36 bits to 12 bits (one bit is the signal bit). On the other hand in the Matlab Simulator (that consists basically of software computations), a rounding to the nearest 12 bit word, is made, and a bit of accuracy is gained in the output values obtained. In this way, it is only natural for the Matlab values to be 0 or 1 LSB (Least Significant Bit) higher, which is equivalent to 0 and 4.883 × 10 respectively in a sample amplitude range that goes from 0 to 1. Both simulations agree completely with one another and, in this way, the correctness of both is verified.

5.3 Multiple Run Matlab Simulation Because of the random nature of each matlab simulation run, an average of 15 sequential random simulations was performed to better access the quality (SNR) of the signal delivered to the modem (see figure 1.1).

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Figure 5.34 - Power spectrum at the end of the LTE functional filter developed. The results consist of a Monte Carlo Simulation of 15 sequential runs.

Figure 5.35 – Zoom in of power spectrum of figure 5.34, for ripple and SNR visualization purposes.

The signal power density varies between -117.60 dBW/Hz and -115.52 dBW/Hz. The DAC generated noise, as can be verified in figure 5.35 above, is frequent to have a value below -190 dBW. Nevertheless, that noise power density might go up, occasionally, to a maximum of -188.16 dBW. The SNR has, therefore, an usual value of 72.4 dB and a minimum value of 70.56 dB.

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6. Final Remarks

6.1 Future Work To be able to develop this product and deliver it into the market, several issues have to be studied. The realizability of the lower frequency functional filters (lower in terms of cutoff frequency) in lumped element analog technology shall be studied. For this aim, filter simulations using the models of real components with finite Q factors, must be done. [38] The higher frequency filters (in terms of cutoff frequency) have to be converted to microstrip line technology. In some cases this may not be straightforward and may require some research/development. Firstly, a conversion of the filters to ones consisting of ideal transmission lines would be performed. These filters would be simulated. After that, a commercial simulator would need to be employed, to, according to the substrate chosen, give the dimensions of the stubs in microstrip technology. There is the possibility that some of the filters are not accomplishable in microstrip technology, in which case, resonant cavities filters must be studied and resonant cavities technology has to be used. Finally, the entire control unit of the filter must be projected. This is the unit that sends binary words to the muxes and attenuators in the filter chain. Note that some sensors have to be present, as the signal level must be monitored, so it is possible to adjust conveniently the level of attenuation of the attenuators in the filtering system. These sensors must be chosen and integrated in the filter chain. The pathway followed by the signal is LTE band dependant and is controlled by the several muxes in the LTE filtering chain. This choice may also be automated as a control unit automatic activity.

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6.2 Conclusions The main conclusion to take is that the functional filter developed functions quite well. An usual filtering quality of 72.4 dB is attained and in the worst typical case, a 70.56 dB quality is obtained (Monte Carlo simulation results). In a very bad case, the typical quality of filtering is 70.23 dB. The ripple of the filter designed is always between 2.19 and 2.85 dB, which is inferior to the ceiling established of 3 dB. All the components except for the DAC, supply the opportunity of achieving the minimum quality sought of 80 dB. All the analog filters, ADC and FPGA digital filter and equalizer are prepared for providing the 80 dB quality mark. However, to achieve that, the SNR must be closely controlled, and the attenuation of the attenuators must be rigorously monitored and promptly and dynamically changed so that close to optimum SNR degradations can be reached. Nevertheless, the quality of filtering achieved is between 8 to 10 dB below the 80 dB attenuation mark after as small as 5MHz transition bands. The bottleneck of the system performance is the DAC. When a DAC with the same INL, higher ENOB and a sample rate of 250 MSPS is put on the market, the system performance will improve accordingly, 6.02 dB of improvement for one additional error free bit added in the resolution the DAC can handle. If 2 additional error free resolution bits are available, the DAC will no longer be an impairment to the minimum quality of filtering of 80 dB guaranteed by the remaining system developed. The second very important conclusion to take is that this filtering system is probably going to be very difficult to actually produce. Although it is outside of the scope of this first approach to the problem proposed by a Portuguese Telecommunications Company, the research done, implies that most of the functional filters will need to be, in practice, implemented in microstrip lines or even resonant cavities technology. There are some problems that might arise in the remaining studies to perform, to make possible the development of the functional LTE filter discussed. These will now be stated. The conversion of some LC ladder type filters to microstrip technology may not be straightforward and that process may need to be further researched/developed. The attenuations needed of 80 dB in most of the functional analog filters simulated, may be simply too high to be able to be accomplished without equivalent chains of filters in the microstrip/cavities technology. Finally, the periodicity of 4 푓 (cutoff frequency) of the filter responses designed with microstrip lines, may also present a problem, because that will cause the spectra at the entrance of the ADC, not to be as clean. Note that the transition bands of the functional filters of the system developed are relatively small in comparison with their cuttoff frequencies. That is very advantageous, since the periodicity of the response will probably not hamper the quality of the filtering achieved. However, higher frequencies, unexpected “pass bands“, will be present in the several filters’ frequency responses. These will usually be attenuated (since in real transmission lines implemented in microstrip technology, there is an attenuation that increases with frequency), but may still be an impairment to the LTE filtering system overall performance.

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7. References

[1] (September 2013) “LTE Frequency Bands and Spectrum Allocations :: Radio- Electronics.Com ” [Online] Available: http://www.radio-electronics.com/info/cellulartelecomms/lte-long-term-evolution/lte-frequency-spectrum.php [2] (September 2013) “Understanding Noise Figure”, Iulian Rosu, YO3DAC / VA3IUL [Online] Available: http://www.qsl.net/va3iul/Noise/Understanding%20Noise%20Figure.pdf [3] (September 2013) “FREE filter design and analysys program” [Online] Available: http://aade.com/filter32/download.htm#download [4] (September 2013) “Johnson-Nyquist Noise - Wikipedia, the free encyclopedia” [Online] Available: http://en.wikipedia.org/wiki/Johnson%E2%80%93Nyquist_noise [5] D.M.Pozar, “Microwave Engineering”, Ed. USA: Addison Wesley, pp. 582-594 (Section 11.1: Noise In Microwave Systems) [6] A. Cartaxo “Capítulo 1 – Introdução aos Sistemas de Telecomunicações por Fibra Óptica”, pp 16-36 (Factor de Ruído, Temperatura Equivalente de Ruído, Cadeia de Sistemas) , Secção de Folhas, IST, 2012 [7] (September 2013) HMC276LP4 / HMC276LP4E Mux Datasheet, Hittite Microwave Corporation. Available:http://www.hittite.com/content/documents/data_sheet/hmc276lp4.pdf [8] (September 2013) HMC194MS8 / 194MS8E Mux Datasheet, Hittite Microwave Corporation. Available:http://www.hittite.com/content/documents/data_sheet/hmc194ms8.pdf [9] (September 2013) SKY13395-397LF DPDT Datasheet, Skyworks. Available: http://www.skyworksinc.com/uploads/documents/201385A.pdf [10] (September 2013) Dat-15R5-SP+ Attenuator Datasheet, Mini-Circuits [Online] Available: http://217.34.103.131/pdfs/DAT-15R5-SP+.pdf [11] (September 2013) PHA-1+ Amplifier Datasheet, Mini-Circuits [Online] Available: http://217.34.103.131/pdfs/PHA-1+.pdf [12] (September 2013) “RF MIxers” ,Iulian Rosu, YO3DAC / VA3IUL [Online] Available: www.qsl.net/va3iul/RF%20Mixers/RF_Mixers.pdf [13] (September 2013) “Agilent EEsof EDA– Presentation on Fundamentals of Mixer Design” [Online].

Available: http://cp.literature.agilent.com/litweb/pdf/5989-9102EN.pdf [14] (September 2013) “A discussion on Mixers” [Online] Available: http://users.tpg.com.au/users/ldbutler/MixerTheory.htm [15] (September 2013), Mini-Circuits, White Paper, “Improve Two Tone, Third-Order Intermodulation Testing” [Online] Available: http://217.34.103.131/app/AN00-008.pdf [16] (October 2012) “Glossary of RF & Microwave terms | API Technologiese” [Online] Available: http://www.spectrummicrowave.com/glossary.aspx

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[17] (September 2013) “FM/PM Demodulation Double Balanced Mixer The Phase Lock Loop” [Online]. Available: : http://www.st-andrews.ac.uk/~www_pa/Scots_Guide/RadCom/part13/page1.html [18] R.Gilmore, L.Besser, “Practical RF Circuit Design for Modern Wireless Systems, Volume 2: Active Circuits and Systems ”, 2003, Artech House Inc, pp 451- 455 (Section 7.2.3 Double Balanced Mixers) [19] (September 2013) “Taking the mystery out of double-balanced mixers” , Shankar Joshi, Chief

Engineer Synergy Microwave [Online] Available:http://www.robkalmeijer.nl/techniek/electronica/radiotechniek/hambladen/qst/1993/12/page32/index.html [20] (September 2013) “Mini-Circuits Frequency Mixers” [Online] Available: http://217.34.103.131/products/Mixers.shtml [21] (September 2013)”Mini-Circuits”, Company Overview [Online] Available: http://217.34.103.131/aboutus/overview.html [22] (September 2013) JYM-28H Mixer Datasheet [Online] Available: http://217.34.103.131/pdfs/JYM-28H.pdf [23] D.M.Pozar, “Microwave Engineering”, Ed. USA: Addison Wesley, pp. 455-528 (Chapter 9: Microwave Filters) [24] M.A.Uslu, L.Sevgi, “A MATLAB-Based Filter-Design Program: From Lumped Elements to Microstrip Lines”, IEEE Antennas and Propagation Mag., Vol.53, Nº1, February 2011 [25] Understand SINAD, ENOB, SNR, THD, THD + N, and SFDR so You Don't Get Lost in the Noise Floor, Walt Kester, Analog Devices [Online] Available: http://www.analog.com/static/imported-files/tutorials/MT-003.pdf [26] R.G.Lyons “Understanding Digital Signal Processing”, 2001, Prentice Hall PTR, pp 32-42 (Section

2.3 – Sampling Bandpass Signals) [27] G. Tavares, “SinaisAmostragem.pdf”, Sitemas Electrómicos de Processamento de Sinal, 2011,

IST, slides 21-26 [Online] Available: https://dspace.ist.utl.pt/bitstream/2295/903233/1/SinaisAmostragem.pdf

[28] (September 2013) “Analog Devices Announces Industry’s Fastest 16 bit – ADC at 250 MSPS” [Online] Available: http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad9467/products/9_27_10_ADI_Announces_Industrys_Fatest_16bit_ADC_a/press.html [29] (September 2013) AD9487 ADC Datasheet, Analog Devices [Online] Available: http://www.analog.com/static/imported-files/data_sheets/AD9467.pdf [30] (September 2013) “ADC Errors”[Online] Available:http://www.cypress.com/?docID=32695 [31] (September 2013), “Buy Xilinx FPGA Spartan-3A DSP Family 3.4M Gates”, Avnet Express [Online] Available:http://avnetexpress.avnet.com/1/1/4642771-xilinx-fpga-spartan-3a-dsp-family-3-4m-gates-53712-cells-667mhz-90nm-technology-1-2v-484-pin-lcsbga-xc3sd3400a-4cs484i.html [32] (September 2013), “Extended Spartan-3A Family Overview”, Product Specifications, Xilinx [Online] Available: http://www.xilinx.com/support/documentation/data_sheets/ds706.pdf

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[33] V.A. Pedroni, “Circuit Design with VHDL“, MIT Press, 2004, pp. 13-158, pp. 233-271 and pp. 285-293 (Introduction, Code Structure, Data Types, Operators and Attributes, Concurrent Code, Sequential Code, Signals and Variables, Packages and Components, Functions and Procedures, Multiply-Accumulate Circuits, Digital Filters) [34] (September 2013) [Online] “Virtex6-Family Overview”, Product Specifications, Xilinx [Online] Available: http://www.xilinx.com/support/documentation/data_sheets/ds150.pdf [35] (September 2013) [Online] “Filter Design Toolbox Users Guide ”, Mathworks, Version 2 (Chapter 1 – Filter Design Toolbox Overview and Chapter10 – Using FDATool with the Filter Design Toolbox) [Online] Available: http://www.busim.ee.boun.edu.tr/~resources/fdq.pdf [36] “XtremeDSP for Virtex-4 FPGAs”, User Guide, Xilinx [Online] Available: http://www.xilinx.com/support/documentation/user_guides/ug073.pdf [37] (September 2013) “AD9741, AD9743, AD9745, AD9746 and AD9747 Datasheet”, Analog Devices, [Online] Available: http://www.analog.com/static/imported files/data_sheets/AD9741_9743_9745_9746_9747.pdf [38] L. Wanhammar, “Analog Filters Using MATLAB”, Springer, 2009, pp 77-79 (Section 3.2.1 – “Q Factor Of Coils” and Section 3.2.2 – “Q factor for Capacitors”)

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Appendix 1.1 LTE Bands details The LTE bands respective information is presented from band 1 to band 3, and can be consulted

between table a1.1 and table a1.7. In that last table, the LTE bands in which the filter studied would

not work are exposed. The parameter band gap in tables a1.1 to a1.4 is the frequency gap between

the downlink and uplink FDD bands. As for the duplex spacing in those same tables, it is the

frequency span between the start of the FDD uplink band and the start of the FDD downlink band or

vice versa.

Band 1 Downlink

LTE Band Number

Allocation [MHz]

Width of

Band [MHz]

Band Gap

[MHz]

Duplex Spacing [MHz]

12 728 – 746 18 12 30 17 734 – 746 12 18 30 13 746 – 756 10 21 31 14 758 – 768 10 20 30 20 791 – 821 30 11 41 18 860 – 875 15 30 45 5 869 – 894 25 20 45 6 875 – 885 10 25 35

19 875 – 890 15 30 45 8 925 – 960 35 10 45

Table a1.1 – FDD Downlink LTE bands included in band 1 and their correspondent characteristics.

Band 1 Uplink

LTE Band Number

Allocation [MHz]

Width of

Band [MHz]

Band Gap

[MHz]

Duplex Spacing [MHz]

12 698 – 716 18 12 30 17 704 – 716 12 18 30 13 777 – 787 10 21 31 14 788 – 798 10 20 30 18 815 – 830 15 30 45 5 824 – 849 25 20 45 6 830 – 840 10 25 35

19 830 – 845 15 30 45 20 832 – 862 30 11 41 8 880 – 915 35 10 45

Table a1.2 – FDD Uplink LTE bands included in band 1 and their correspondent characteristics.

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Band 2 Downlink

LTE Band Number Allocation [MHz] Width of

Band [MHz] Band Gap

[MHz] Duplex Spacing

[MHz]

11 1475.9 – 1500.9 20 28 48 21 1495.5 – 1510.9 15 33 48 24 1525 – 1559 34 66.5 100.5 3 1805 – 1880 75 20 95 9 1844.9 – 1879.9 35 60 95 2 1930 – 1990 60 20 80

25 1930 – 1995 65 15 80 4 2110 – 2155 45 355 400 1 2110 – 2170 60 130 190

10 2110 – 2170 60 340 400 23 2180 – 2200 20 160 180

Table a1.3 – FDD Downlink LTE bands included in band 2 and their respective characteristics.

Band 2 Uplink LTE Band Number Allocation [MHz] Width of

Band [MHz] Band Gap

[MHz] Duplex Spacing

[MHz] 11 1427.9 – 1452.9 20 28 48 21 1447.9 – 1462.9 15 33 48 24 1625.5 – 1660.5 34 66.5 100.5 4 1710 – 1755 45 355 400

10 1710 – 1770 60 340 400 3 1710 – 1785 75 20 95 9 1749.9 – 1784.9 35 60 95 2 1850 – 1910 60 20 80

25 1850 – 1915 65 15 80 15 1900 – 1920 20 680 700 1 1920 – 1980 60 130 190

23 2000 – 2020 20 160 180 Table a1.4 – FDD Uplink LTE bands included in band 2 and their respective characteristics.

Band 2 TDD

LTE Band Number Allocation [MHz] Width of Band [MHz]

35 1850 – 1910 60 39 1880 – 1920 40 33 1900 – 1920 20 36 1930 – 1990 60 34 2010 – 2025 15

Table a1.5 – TDD LTE bands included in band 2 and their respective characteristics.

Band 3 TDD LTE Band Number Allocation [MHz] Width of Band [MHz]

40 2300 – 2400 100 41 2496 – 2690 194 38 2570 – 2620 50

Table a1.6 – TDD LTE bands included in band 3 and their matching characteristics.

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Non Supported Bands TDD LTE Band Number Allocation [MHz] Width of Band [MHz]

42 3400 – 3600 200 43 3600 – 3800 200

Table a1.7 – TDD LTE bands included in the non supported band and their matching characteristics.

2.1 Algorithm for SNR Degradation determination

푆푁푅_푑푒푔 _ = 퐴 − 퐺

퐼푓푆푁푅_푑푒푔 _ < 0 ⇔푆푁푅_푑푒푔 = 푁퐹

and in the next section, 퐺 = 퐺 + 푆푁푅_푑푒푔 _ and 퐴 = 퐴 − 푁퐹

If퐴 < 0푑퐵,퐴 = 퐴 − |퐴 |, 퐴 = 0푑퐵, If퐴 < 0푑퐵,퐴 = 퐴 − |퐴 |, 퐴 = 0푑퐵

And so on until 퐴 ≥ 0

퐼푓푆푁푅_푑푒푔 > 푁퐹 ⇔푆푁푅_푑푒푔 = 푆푁푅_푑푒푔 _

(+푁퐹 −푁퐹 ) 퐼푓푆푁푅 _ < 푁퐹 ∩푆푁푅 _ ≥ 0 ⇔푆푁푅_푑푒푔 = 푁퐹

and in the next section 퐴 = 퐴 − 푁퐹 – 푆푁푅

If퐴 < 0푑퐵,퐴 = 퐴 − |퐴 |, 퐴 = 0푑퐵, If퐴 < 0푑퐵,퐴 = 퐴 − |퐴 |, 퐴 = 0푑퐵

Note that in our case, 푁퐹 is usually equal to 2.3 dB. When the thermal noisefloor is at its minimum,

which is 퐾 (Boltzman constant) times T (temperature in Kelvins), the NF is given by expression

(a2.1).

푁퐹 = 10 log 1 +푛푔푛

(푎2.1)

Where g is the gain of the amplifier, 푛 is the noise added by the amplifier and 푛 = 퐾 푇. However,

if the thermal noisefloor is amplificated when the signal arrives at the entrance of the amplifier, 푁퐹

is going to be lower than 2.3 dB. It is calculated as illustrated in expression a2.2.

푁퐹 = 10 log 1 +푛

푛 × 푔푛(푎2.2)

Where 푛 is the noisefloor amplification in linear units.

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2.2 Single MosFET Mixer Analysis In the saturation zone, when 푣 > 푣 −푉 the current from the drain to the source in a MosFET is

푖 = 푘(푣 − 푉푡) . In this case 푣 = 푣 (푡) = 푣 cos(휔 푡) + 푣 cos(휔 푡)

푣 (푡) = 푉퐷퐷 −푖 푅

푖 = 푘(푣 cos(휔 푡) + 푣 cos(휔 푡) −푉 ) = = 푘((푣 cos(휔 푡) + 푣 cos(휔 푡)) + 푉 − 2푉 (푣 cos(휔 푡) + 푣 cos(휔 푡)))

= 푘(푣 cos (휔 푡) + 푣 cos (휔 푡) + 2푣 푣 cos(휔 푡) cos(휔 푡) + −2푉 푣 cos(휔 푡) + 푣 cos(휔 푡)) + 푉

= 푘(푣

2(1 + cos(2휔 푡)) +

푣2

(1 + cos(2휔 푡)) + 푣 푣 cos((휔 +휔 )푡) +

+푣 푣 cos((휔 −휔 )푡) − 2푉 (푣 cos(휔 푡) + 푣 cos(휔 푡))+ 푉 )(푎2.3)

The square law characteristic of the MosFET is particularly good for mixing purposes because

harmonic generation is theoretically limited to second order. Also because of its high gate impedance,

it requires little power to drive it.

However there’s yet another problem. The radio frequency signal in most real applications is not a

single tone signal but encompasses an entire frequency band. We shall then analyze the case of the

radio frequency signal being a two tone generator because that will allow us to understand the

frequency band case.

We will return to the more general expression and consider

푉 (푡) = a + a v (t) + a v (t) + a v (t) + … (푎2.4) with 푣 (푡) = 푣 cos(휔 푡) + 푣 cos(휔 푡) + 푣 cos(휔 푡)(푎2.5)

Developing the second order term in (푎2.4) in order to observe the generated harmonics:

푣 (푡) = (푣 cos(휔 푡) + 푣 cos(휔 푡)) + 푣

2(1 + cos(2휔 푡)) +

+푣 푣 (cos((휔 + 휔 )푡) + 푣 푣 (cos((휔 − 휔 )푡) + +푣 푣 (cos((휔 +휔 )푡) + 푣 푣 (cos((휔 −휔 )푡) (푎2.6)

With

(푣 cos(휔 푡) + 푣 cos(휔 푡)) = 푣

2(1 + cos(2휔 푡)) +

+푣

2(1 + cos(2휔 푡)) + 푣 푣 (cos((휔 −휔 )푡) +

+푣 푣 (cos((휔 +휔 )푡) (푎2.7)

From (푎2.7) we can see that harmonics with frequency 푓 + 푓 and 푓 −푓 are generated, which means there is inter modulation, more specifically there is second order inter-modulation distortion. Finally let’s analyze the third order term in (푎2.4) again to observe the generated harmonics:

푣 (푡) = (푣 cos(휔 푡) + 푣 cos(휔 푡) + 푣 cos(휔 푡)) = = (푣 cos(휔 푡) + 푣 cos(휔 푡)) + 푣 cos (휔 푡) +

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+3(푣 cos(휔 푡) + 푣 cos(휔 푡)) 푣 cos(휔 푡) +

+3(푣 cos(휔 푡) + 푣 cos(휔 푡)) 푣

2(1 + cos(2휔 푡))(푎2.8)

With

(푣 cos(휔 푡) + 푣 cos(휔 푡)) = 푣 cos (휔 푡) + 푣 cos (휔 푡) +

+3푣

2(1 + cos(2휔 푡))푣 cos(휔 푡) +

3푣

2(1 + cos(2휔 푡))푣 cos(휔 푡) (푎2.9)

A mathematical identity is that

cos (푥) = cos(3푥) + 3cos(푥)

4(푎2.10)

So, from (푎2.8), (푎2.9) and (푎2.10):

푣 (푡) = 푣

4(cos(3휔 푡) + 3cos(휔 푡)) +

푣4

(cos(3휔 푡) + 3cos(휔 푡))

+3푣

2푣 cos(휔 푡) + 3

푣2

푣 cos(휔 푡) +

3푣

4푣 ((cos((2휔 + 휔 )푡) + (cos((2휔 −휔 )푡) +

+3푣

4푣 ((cos((2휔 + 휔 )푡) + (cos((2휔 − 휔 )푡) +

푣4

(cos(3휔 푡) + 3cos(휔 푡)) + 3 푣

2+ 푣

2 푣 cos(휔 푡) +

+3푣

4푣 (cos((2휔 +휔 )푡) + cos((2휔 −휔 )푡)) +

+3푣

4푣 (cos((2휔 +휔 )푡) + cos((2휔 −휔 )푡)) +

+3푣 푣 푣

2(cos((휔 −휔 + 휔 )푡) +

+3푣 푣 푣

2(cos((휔 −휔 −휔 )푡) +

+3푣 푣 푣

2(cos((휔 +휔 + 휔 )푡) +

+ 푣 푣 푣

2(cos((휔 +휔 −휔 )푡) +

+3푣

2(푣 cos(휔 푡) + 푣 cos(휔 푡)) +

+3푣

4푣 (cos((2휔 +휔 )푡) + cos((2휔 −휔 )푡)) +

+3푣

4푣 (cos((2휔 + 휔 )푡) + cos((2휔 −휔 )푡))(푎2.11)

The conclusions taken from the expression obtained ( (푎2.11) ) are made in the Continuous non-linear part of section 2.4.3 – Mixer Modes.

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2.3 Tables of functional filters’ components Component Type SubType DigiKey Part Number Value Tolerance

C1 Capacitor Variable SG2018TR-ND 2.19 pF 0.5 to 4.5 pF C2 Capacitor Variable 490-1957-ND 55.41 pF 10 to 120 pF L2 Inductor Fixed P14860TR-ND 11 nH ±2% C3 Capacitor Variable SG2018TR-ND 1.75 pF 0.5 to 4.5 pF C4 Capacitor Variable 490-1982-2-ND 9.03 pF 7 to 50 pF L4 Inductor Fixed P14862TR-ND 13 nH ±2% C5 Capacitor Variable SG2018TR-ND 2.06 pF 0.5 to 4.5 pF C6 Capacitor Variable SG2017TR-ND 6.89 pF 0.6 to 9 pF L6 Inductor Fixed 535-10413-2-ND 15 nH ±1% C7 Capacitor Variable SG2018TR-ND 1.95 pF 0.5 to 4.5 pF C8 Capacitor Variable 490-1957-ND 15.40 pF 10 to 120 pF L8 Inductor Fixed 478-7176-2-ND 12.5 nH ±2% C9 Capacitor Variable SG2018TR-ND 2.49 pF 0.5 to 4.5 pF

Table a2.1 – Components characteristics of the image reject filter of Band 1.

Component Type SubType DigiKey Part Number Value Tolerance C1 Capacitor Variable SG2018TR-ND 1.07 pF 0,5 to 4,5 pF C2 Capacitor Variable 490-1957-ND 32.11 pF 10 to 120 pF L2 Inductor Fixed 478-7173-2-ND 5.45 nH ±2% C3 Capacitor Variable SG2018TR-ND 0.84 pF 0.5 to 4.5 pF C4 Capacitor Variable SG2017TR-ND 5.25 pF 0.6 to 9 pF L4 Inductor Fixed 490-6759-2-ND 6.2 nH ± 0.1 nH C5 Capacitor Variable SG2018TR-ND 0.96 pF 0.5 to 4.5 pF C6 Capacitor Variable SG2018TR-ND 4.02 pF 0.5 to 4.5 pF L6 Inductor Fixed 535-10384-2-ND 6.8 nH ±0.1 nH C7 Capacitor Variable SG2018TR-ND 1.95 pF 0.5 to 4.5 pF C8 Capacitor Variable 490-1957-ND 32.11 pF 10 to 120 pF L8 Inductor Fixed 535-10383-2-ND 5.9 nH ± 0.1 nH C9 Capacitor Variable SG2018TR-ND 1.16 pF 0.5 to 4.5 pF


Component Type SubType DigiKey Part Number Value Tolerance C1 Capacitor Variable SG2018TR-ND 0.80 pF 0,5 to 4,5 pF C2 Capacitor Variable 490-1957-ND 13.34 pF 10 to 120 pF L2 Inductor Fixed 732-2917-2-ND 2.7 nH ±0.1 nH C3 Capacitor Variable SG2018TR-ND 0.74 pF 0,5 to 4,5 pF C4 Capacitor Variable SG2017TR-ND 5.02 pF 0.6 to 9 pF L4 Inductor Fixed 535-10366-2-ND 2.5 nH ± 0.1 nH C5 Capacitor Variable SG2018TR-ND 0.94 pF 0.5 to 4.5 pF C6 Capacitor Variable SG2017TR-ND 8.55 pF 0.6 to 9 pF L6 Inductor Fixed 535-10360-2-ND 1.9 nH ±0.1 nH C7 Capacitor Variable SG2018TR-ND 1.09 pF 0.5 to 4.5 pF L8 Inductor Fixed 535-10360-2-ND 1.9 nH ± 0.1 nH


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Component Type SubType DigiKey Part Number Value Tolerance C1 Capacitor Variable SG2018TR-ND 2.61 pF 0,5 to 4,5 pF C2 Capacitor Variable 490-1957-ND 56.05 pF 10 to 120 pF L2 Inductor Fixed P14862TR-ND 13 nH ±2% C3 Capacitor Variable SG2018TR-ND 2.17 pF 0.5 to 4.5 pF C4 Capacitor Variable SG2017TR-ND 8.15 pF 0.6 to 9 pF L4 Inductor Fixed 535-10393-2-ND 17 nH ±2% C5 Capacitor Variable SG2018TR-ND 2.91 pF 0.5 to 4.5 pF C6 Capacitor Variable SG2017TR-ND 4.54 pF 0.6 to 9 pF L6 Inductor Fixed 535-10415-2-ND 22 nH ±1% C7 Capacitor Variable SG2018TR-ND 3.20 pF 0.5 to 4.5 pF C8 Capacitor Variable 490-1957-ND 15.40 pF 10 to 120 pF L8 Inductor Fixed 535-10395-2-ND 20.8 nH ±2% C9 Capacitor Variable SG2018TR-ND 2.56 pF 0.5 to 4.5 pF

C10 Capacitor Variable 490-1957-ND 14.92 pF 10 to 120 pF L10 Inductor Fixed 535-10413-1-ND 15 nH ±1% C11 Capacitor Variable SG2018TR-ND 2.61 pF 0,5 to 4,5 pF

Table a2.4 – Components characteristics of the image reject filter FRI2 in figures 2.1 and 4.1.

Component Type SubType DigiKey Part Number Value Tolerance C1 Capacitor Variable GMC30600-ND 218.9 pF 56 to 250 pF L1 Inductor Fixed ATFC-0603-33N-FT 33 nH ± 1% C2 Capacitor Variable SG2018TR-ND 1.23 pF 0.5 to 4.5 pF L2 Inductor Fixed AISC-0805-R27G-TTR-ND 270 nH ± 2%

C2a Capacitor Variable SG3027-ND 29.61 pF 3 to 40 pF L2a Inductor Fixed DN2279CT-ND 6.2 uH ± 5% C3 Capacitor Variable GMC31100-ND 314.77 pF 150 to 500 pF L3 Inductor Fixed P14868TR-ND 24nH ± 2% C4 Capacitor Variable SG2018TR-ND 3.41 pF 0.5 to 4.5 pF L4 Inductor Fixed PCD2018TR-ND 220 nH ± 2%

C4a Capacitor Variable SG3027-ND 35.44 pF 3 to 40 pF L4a Inductor Fixed SG2018TR-ND 2.2 uH 0.5 to 4.5 pF C5 Capacitor Variable GMC30600-ND 218.9 pF 56 to 250 pF L5 Inductor Fixed ATFC-0603-33N-FT 33 nH ± 1%

Table a2.5 – Components characteristics of the band pass filter in the pre-processing before the ADC.

Component Type SubType DigiKey Part Number Value Tolerance L1 Inductor Fixed 490-6929-2-ND 200 nH ± 2% C2 Capacitor Variable 490-1957-ND 40 pF 10 to 120 pF L3 Inductor Fixed 490-6929-2-ND 200 nH ± 2%

Table a2.6 – Components characteristics of the low pass filter in the pre processing before the ADC.

Component Type SubType DigiKey Part Number Value Tolerance C1 Capacitor Variable SG2018TR-ND 1.42 pF 0.5 to 4.5 pF L1 Inductor Fixed 490-6836-2-ND 62 nH ± 2% C2 Capacitor Variable 490-1957-ND 47.73 pF 10 to 120 pF L2 Inductor Fixed 732-2915-2-ND 1.8 nH ± 0.1 nH C3 Capacitor Variable SG2018TR-ND 2.03 pF 0.5 to 4.5 pF L3 Inductor Fixed PCD2367TR-ND 43 nH ± 2% C4 Capacitor Variable 490-1957-ND 45.21 pF 10 to 120 pF

C

L4 Inductor Fixed ATFC-0402-1N9-BT 1.9 nH ± 0.1 nH C5 Capacitor Variable SG2018TR-ND 2.03 pF 0.5 to 4.5 pF L5 Inductor Fixed PCD2367TR-ND 43 nH ± 2% C6 Capacitor Variable 490-1957-ND 47.73 pF 10 to 120 pF L6 Inductor Fixed 732-2915-2-ND 1.8 nH ± 0.1 nH C7 Capacitor Variable SG2018TR-ND 1.42 pF 0.5 to 4.5 pF L7 Inductor Fixed 490-6836-2-ND 62 nH ± 2%

Table a2.7 – Components characteristics of the Band Rejection filter to attenuate the LO leaked tone in 540 MHz after first upconversion step.

Component Type SubType DigiKey Part Number Value Tolerance C1 Capacitor Variable SG2018TR-ND 2.25 pF 0.5 to 4.5 pF L1 Inductor Fixed P14860TR-ND 11 nH ± 2% C2 Capacitor Variable 490-1957-ND 45.61 pF 10 to 120 pF L2 Inductor Fixed 732-2915-2-ND 1.8 nH ± 0.1 nH C3 Capacitor Variable SG2018TR-ND 2.03 pF 0.5 to 4.5 pF L3 Inductor Fixed PCD2367TR-ND 43 nH ± 2% C4 Capacitor Variable 490-1957-ND 17 pF 10 to 120 pF L4 Inductor Fixed 478-7176-2-ND 12.5 nH ± 2% C5 Capacitor Variable SG2018TR-ND 2.43 pF 0.5 to 4.5 pF

Table a2.8 – Components characteristics of the band 1 variable LO tone rejection filter.

Component Type SubType DigiKey Part Number Value Tolerance C1 Capacitor Variable SG2018TR-ND 1.09 pF 0.5 to 4.5 pF C2 Capacitor Variable 490-1957-ND 21.52 pF 10 to 120 pF L2 Inductor Fixed 478-7173-2-ND 5.45 nH ±2% C3 Capacitor Variable SG2018TR-ND 0.91 pF 0.5 to 4.5 pF C4 Capacitor Variable SG2018TR-ND 3.48 pF 0.5 to 4.5 pF L4 Inductor Fixed 535-10385-2-ND 7.2 nH ± 0.1 nH C5 Capacitor Variable SG2018TR-ND 1.12 pF 0.5 to 4.5 pF C6 Capacitor Variable SG2018TR-ND 2.63 pF 0.5 to 4.5 pF L6 Inductor Fixed 535-10386-2-ND 8 nH ±0.1 nH C7 Capacitor Variable SG2018TR-ND 1.04 pF 0.5 to 4.5 pF C8 Capacitor Variable SG2017TR-ND 5.94 pF 0.6 to 9 pF L8 Inductor Fixed 490-6759-2-ND 6.2 nH ± 0.1 nH C9 Capacitor Variable SG2018TR-ND 1.16 pF 0.5 to 4.5 pF

Table a2.9 – Components characteristics of the band 2, sub band 1, variable LO tone rejection filter.

Component Type SubType DigiKey Part Number Value Tolerance C1 Capacitor Variable SG2018TR-ND 0.91 pF 0.5 to 4.5 pF C2 Capacitor Variable 490-1957-ND 14.90 pF 10 to 120 pF L2 Inductor Fixed 535-10381-2-ND 4.7 nH ±0.1 nH C3 Capacitor Variable SG2018TR-ND 0.78 pF 0.5 to 4.5 pF C4 Capacitor Variable SG2018TR-ND 2.39 pF 0.5 to 4.5 pF L4 Inductor Fixed 490-6759-2-ND 6.2 nH ±0.1 nH C5 Capacitor Variable SG2018TR-ND 1 pF 0.5 to 4.5 pF C6 Capacitor Variable SG2018TR-ND 1.79 pF 0.5 to 4.5 pF L6 Inductor Fixed 535-10385-2-ND 7.2 nH ±0.1 nH C7 Capacitor Variable SG2018TR-ND 0.91 pF 0.5 to 4.5 pF C8 Capacitor Variable SG2018TR-ND 4.09 pF 0.5 to 4.5 pF

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L8 Inductor Fixed 535-10382-2-ND 5.6 nH ±0.1 nH C9 Capacitor Variable SG2018TR-ND 1.05 pF 0.5 to 4.5 pF

Table a2.10 – Components characteristics of the band 2, sub band 2, LO tone rejection filter.

Component Type SubType DigiKey Part Number Value Tolerance C1 Capacitor Variable SG2018TR-ND 0.77 pF 0.5 to 4.5 pF C2 Capacitor Variable 490-1957-ND 14.12 pF 10 to 120 pF L2 Inductor Fixed 535-10379-2-ND 3.8 nH ±0.1 nH C3 Capacitor Variable SG2018TR-ND 0.65 pF 0.5 to 4.5 pF C4 Capacitor Variable SG2018TR-ND 2.28 pF 0.5 to 4.5 pF L4 Inductor Fixed 490-6758-2-ND 5.1 nH ±0.1 nH C5 Capacitor Variable SG2018TR-ND 0.81 pF 0.5 to 4.5 pF C6 Capacitor Variable SG2018TR-ND 1.72 pF 0.5 to 4.5 pF L6 Inductor Fixed 490-6835-2-ND 5.8 nH ±0.1 nH C7 Capacitor Variable SG2018TR-ND 0.75 pF 0.5 to 4.5 pF C8 Capacitor Variable SG2018TR-ND 3.89 pF 0.5 to 4.5 pF L8 Inductor Fixed 732-2920-2-ND 4.7 nH ±0.1 nH C9 Capacitor Variable SG2018TR-ND 0.88 pF 0.5 to 4.5 pF


Component Type SubType DigiKey Part Number Value Tolerance C1 Capacitor Variable SG2018TR-ND 0.70 pF 0.5 to 4.5 pF C2 Capacitor Variable SG2017TR-ND 6.78 pF 0.6 to 9 pF L2 Inductor Fixed 535-10376-2-ND 3.5 nH ±0.1 nH C3 Capacitor Variable SG2018TR-ND 0.62 pF 0.5 to 4.5 pF C4 Capacitor Variable SG2018TR-ND 1.32 pF 0.5 to 4.5 pF L4 Inductor Fixed 478-7173-2-ND 5.45 nH ±2% C5 Capacitor Variable SG2018TR-ND 0.72 pF 0.5 to 4.5 pF C6 Capacitor Variable SG2018TR-ND 1.96 pF 0.5 to 4.5 pF L6 Inductor Fixed 535-10381-2-ND 4.7 nH ±0.1 nH C7 Capacitor Variable SG2018TR-ND 0.91 pF 0.5 to 4.5 pF


Component Type SubType DigiKey Part Number Value Tolerance C1 Capacitor Variable SG2018TR-ND 0.64 pF 0.5 to 4.5 pF C2 Capacitor Variable SG2017TR-ND 8.88 pF 0.6 to 9 pF L2 Inductor Fixed 535-10373-2-ND 3.2 nH ±0.1 nH C3 Capacitor Variable SG2018TR-ND 0.56 pF 0.5 to 4.5 pF C4 Capacitor Variable SG2018TR-ND 1.41 pF 0.5 to 4.5 pF L4 Inductor Fixed 535-10381-2-ND 4.7 nH ±0.1 nH C5 Capacitor Variable SG2018TR-ND 0.75 pF 0.5 to 4.5 pF C6 Capacitor Variable SG2018TR-ND 1.05 pF 0.5 to 4.5 pF L6 Inductor Fixed 478-7173-2-ND 5.45 nH ±2% C7 Capacitor Variable SG2018TR-ND 0.67 pF 0.5 to 4.5 pF C8 Capacitor Variable SG2018TR-ND 2.43 pF 0.5 to 4.5 pF L8 Inductor Fixed 732-2919-2-ND 3.9 nH ±0.1 nH C9 Capacitor Variable SG2018TR-ND 0.75 pF 0.5 to 4.5 pF

Table a2.13 – Components characteristics of the band 3, sub band 2, variable LO tone rejection filter.

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2.5 Filter conversion to Microstrip line technology In any ideal transmission line terminated in a short circuit, the input impedance is equal to

푍 = 푗푍 tan(휃 ) If however the same line is terminated in an open circuit, the line input impedance becomes

푍 = −푗푍 cot(휃 )

Where in both cases 푍 is the characteristic impedance of the line and 휃 is its electrical angle.

Choosing the length of the lines to be 휆/8, implies that 휃 = 훽푙 = . = 휋/4 and therefore

tan(휃 ) = cot(휃 ) = 1. The equations become 푍 = 푗푍 and 푍 = −푗푍 .

Inductors and capacitors can be replaced by stubs since a short circuit stub functions as an inductor

and an open circuit stub operates as a capacitor.

푍 = 푗푍 = 푗휔퐿 ⇔푍 = 휔퐿 = 2휋푓퐿 and 푍 = −푗푍 = −푗 ⇔푍 = =

In both cases, it is applied the identity 푓 = 푓 , 푓 being the frequency where the filter’s frequency

response has started to decay and is 3 dB attenuated from the pass band. The filter produced in this

fashion, is periodic in frequency with a period of 4푓 Hz. [23], [24]

Figure a2.1 – First equivalent circuit of the filter presented in figure 2.31 in section 2.5.3, using just ideal transmission lines.

The cutoff frequency chosen was in this case, of 85 MHz. The filter response will repeat itself in

4x85MHz = 340 MHz. Observe the filter in figure 2.40 in section 2.5.3.2. According to the procedure

explained, the equivalent circuit of that filter, recurring to ideal transmission lines, is depicted in figure

a2.1 below. Nevertheless, the circuit obtained has short circuit stubs which degrade the filters

frequency response when compared to open circuit stubs. To address this problem, and achieve a

circuit that only uses open circuit stubs, the well known Kuroda identities are used. [23], [24]

These are presented in figures a2.2 and a2.3.

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푍 =푍

푍 + 푍, 푍 =

푍 푍푍 + 푍

푍 = 푍 + 푍 , 푍퐵 = 푍 푍푍

Figure a2.2 – Kuroda identities. Case a) where 푍 is a s.c. stub and 푍 is an o.c stub. Adapted from [24].

푍 = 푍 푍푍 + 푍

,푍 =푍

푍 + 푍푍 =

푍 푍푍

, 푍 = 푍 + 푍

Figure a2.3 – Kuroda identities. Case b) where 푍 is a s.c. stub and 푍 is an o.c stub. [24]

We now add two lines of λ/8, of 50 Ω (unit elements), one after the source resistance and one before

the load resistance. Note that the source and load resistances of the filter are also of 50 Ω. These

additional impedances added, will theoretically not alter the frequency response of the filter. The

resultant circuit is shown in figure a2.4.

Figure a2.4 – Transmission line filter, schematic, after insertion of 2 unit elements in the circuit. The Kuroda identities are applied, identity b) on the left side of the filter and identity a) to the right side

of the circuit. Thus, the short circuit stubs gave place to open circuit stubs. The filter’s performance is

now greatly improved. Figure a2.5. shows the final form of the filter.

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Figure a2.5 – Transmission line filter, schematic, after application of the Kuroda identities. This filter that works as a Notch, achieves an attenuation of 44.65 dB in 540 MHz (in comparison with

the attenuation in the passband). According to section 2.5.3.2, the minimum attenuation required at

540 MHz is of 34.27 dB. Therefore a safety margin of 10.38 dB is reached. This is a quite high safety

margin. To note that there is software that recursively applies well known equations that make it

possible to produce ideal transmission lines in microstrip technology. The characteristic impedance of

the line 푍 was already calculated and having chosen the material, 휀 , the relative permitivity of the

material is known. With these inputs (휀 , 푍 ), combinations of substrate thickness (h), strip width (W)

and strip thickness (t), that present the intended 푍 (characteristic impedance), can be obtained. This

is done through software, that for instance, applies equations (17) to (24) in [24].

3.1 ADC - Some important specifications The most important data on the ADC datasheets is now promptly explained.

The most frequent way to make comparisons between ADCs is through the SINAD parameter.

SINAD stands for Signal-to-Noise and Distortion Ratio. It is a measure of the quality of a communications device, defined as:

푆퐼푁퐴퐷 = 푆

푁 + 퐷=

푃푃 + 푃

(푎3.1)

Where P stands for average power. SINAD is the ratio of the rms signal amplitude to the mean of the

rss (root sum square) of all other spectral components, including harmonics, but excluding dc. It is a

good indication of the overall dynamic performance of an ADC because it includes all components

which make up noise and distortion. [25]

The SFDR (Spurious Free Dynamic Range) is a measure of the power of the strongest spurious tone

created in the operation of the device in question. If it is measured in relation to the full power

representable by the device, its units are dBFS (dB full scale). If, however, the reference point is the

power of the biggest tone of the input signal, its units are dBc (dB carrier). These reference points and

units apply to any other power measures for ADCs and DACs. The SFDR is depicted in both units in

figure a3.1. [25]

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Figure a3.1 – Graphical representation of the SFDR in dBc and dBFS. [25]

3.2 ADC – Types of Error In an ideal ADC, the signal input is quantized in uniform steps. Uniting the middle points of all steps, a

line representing this ideal response of the ADC, is traced in figure a3.2.

Figure a3.2 – Representation of a generic and ideal DAC transfer function. [30]

For a better, understanding and visualization, an ideal, 3 bit example is shown in figure a3.3.

Figure a3.3 – Representation of an ideal 3 bit DAC transfer function [30]

There are 4 types of error specifications in an ADC (excluding the ENOB already discussed). They are

the offset error, the gain error, the differential non linearity error and the integral non linearity error. All

these error types will now be discussed. [30]

The impact of the offset error in the ADC response is illustrated in figure a3.4.

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Figure a3.4 – ADC offset error graphical example. The line that represents the ADC ideal response is on blue and the transfer function subjected to the offset error is on black. [30] This error is a constant vertical difference between the ideal ADC response and the ADC response

that includes the offset error.

It basically means, the ADC transfer function does have uniform steps of the right size, but the

transitions are done later or earlier than what should ideally happen. The first transition (lowest voltage

one) of the response is misaligned by a constant value, which means all transitions are misaligned by

a constant offset. This can lead to an error in the output codewords expressed in number of LSBs.

The offset error can be removed by measuring the point on which the first transition occurs (reference)

and comparing it to the ideal value, correcting that difference in all future samples.

As for the gain error, its’ consequences in the ADC’s response are illustrated in figure a3.5.

Figure a3.5 – ADC gain error graphical example. The line that represents the ADC ideal response is on blue and the transfer function subjected to the gain error is on black. [30]

This type of error refers to a change of slope in the line representing the DAC response when

compared to the ideal response. A change of slope is due to a change of the quantization intervals

length (which ideally would be equal to q). The ADC transfer function still has uniform steps, but now

they are all bigger or all smaller than what was expected, which leads to errors. The gain error can

also be removed. This is done by, after having eliminated the offset error, measuring a second

reference point (or points) and again “pre-distorting the analog signal”, multiplying it by a gain factor

(inversely proportional to the change in slope) that will counter the slope difference in the ADC. In

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other words, what is being done is adapting the input signal to the ADC full scale, taking into account

the fact that its actual response is now characterized by a line with a new slope that needs to be

determined (reference points).

Regarding the DNL (Differential Non Linearity) error, an example is exposed in figure a3.6.

Figure a3.6 – ADC DNL error graphical example. The line that represents the ADC ideal response is on blue and the transfer function subjected to the DNL error is on black. [30] In figure a3.6, the real ADC transfer function is on black. The area of the ADC response where the

DNL error is introduced is surrounded by a dashed red circle. Notice the variability of the size of the

steps enclosed in the red circle. [30] The DNL error introduces a non linearity in the ADC response.

What happens is, the quantization intervals can now be non uniform and be of the wrong size. This

means the transitions between codewords have a random element to them. The DNL expresses the

limits of that randomness in any transition. The quantization interval size should be q, which is the

analog level input difference that if covered would result in a transition of 1LSB. However, each

transition will possibly happen in a smaller or higher gap in tension. This difference in step length is

called DNL and it is given in LSBs. The DNL error is a function of each ADC’s particular architecture

and its effects are not possible to be removed.

Lastly, the impact of an INL (Integral Non Linearity) error in an ADC’s response is on figure a3.7.

Figure a3.7 – ADC INL error graphical example. Ideal response is on blue and real one is on black.

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The arrow in figure a3.7 points towards the middle of the step in the response that is furthest away

from the ideal ADC response. The INL, at that point, is the horizontal gap between the blue line and a

parallel line that passes through the point indicated by the arrow. The INL error is the most important

ADC error of all the 4 error types presented. In reality INL error is just the name given to the

accumulation of DNL errors. Note, however, that depending on the DNL errors, the total error

introduced by these, in the ADC ideal response, called INL, can actually magnify or decrease as the

accumulation takes place. DNL errors with the same sign add up and DNL errors with opposite signs

mitigate or cancel out. The INL is thus defined as the maximum deviation from the ideal line. In other

words, thinking about a transition between codewords, it is the maximum difference between the

analog tension that should trigger that transition and the one that actually does due to the

accumulation of DNL errors.

3.4 Study of IIR filters as the FPGA Digital Filter Through simulations in FDATool, the IIR (Infinite Impulse Response) filters that achieved the

specifications required were obtained. The results are presented in Table a3.1.

Filter Type 푨풑[dB] 푨풔풕풐풑 [dB] Order Nº of Biquadratic Sections |풛| Butterworth 3 83 46 23 0,9838 Chebyshev

type 1 3 83 22 11 0,9973

Table a3.1 – Characteristics of minimum order IIR filters that meet the specifications. These results were obtained with FDATool. It is very important to state that, unlike the FIR filters case, there is a probability of instability of this

type of filters. This results from the fact that IIRs have poles, or, saying it in a different way, they are

implemented with feedback of the previous outputs.

The absolute value of the higher modulus complex conjugate poles in the Z domain of each IIR is

exposed in table 3. They are approximated to the 4th decimal case. The higher its absolute value and

closer to 1 (but minor than 1), the harder it will be to realize the filter. If the complex conjugate poles’

absolute value is bigger than 1, the filter will be unstable.

For instance, it can be seen that with a |푧| of 0,9973 and 0,9838, respectively, for the Butterworth and

Chebyshev type 1 IIRs, it would be hard to make those filters operate reliably.

3.5 Detailed Information of FIRs’ hardware implementation

Serial FIRs

Figure a3.8 – Simplified serial FIR implementation. Uses only one DSP slice which is enclosed by a dashed line. A and B are the inputs and P is the output of the digital circuit. [36]

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Transposed FIRs

Figure a3.9 – Example of a transposed parallel FIR implementation. B is the bus where the samples are inputted and P is the output of the digital circuit. Each DSP slice is enclosed by a dashed line. [36] Symmetric Systollic FIRs Mathematical analysis

푃(푛) = ℎ (푥 + 푥 )푧 + ℎ (푥 + 푥 )푧 + ℎ (푥 + 푥 )푧+ ℎ (푥 + 푥 )푧 ⇔

⇔푃(푛) = 푧 [ℎ (푥 + 푥 )푧 + ℎ (푥 + 푥 )푧 + ℎ (푥 + 푥 )푧

+ ℎ (푥 + 푥 )] ⇔

To note that 푧 is multiplied by all terms in the summation and so represents part of an initial

latency (4 clock cycles).The 푧 is converted in the following change of variables: 푛′ = 푛 − 4.

The next step is to multiply the remaining 푧 terms as time domain delays:

푃(푛′) = ℎ (푥 + 푥 ) + ℎ (푥 + 푥 ) + ℎ (푥 + 푥 ) + ℎ (푥 + 푥 ) The initial latency is the time we have to wait for the circuit to begin generating its valid outputs (start

of the transient regime). Making yet another change of variable: 푛′′ = 푛′ − 4 = 푛 − 8

which in this context means an initial latency of 8 clock cycles, finally yields: 푃(푛′′) = ℎ (푥 + 푥 ) + ℎ (푥 + 푥 ) + ℎ (푥 + 푥 ) + ℎ (푥 + 푥 )

This is exactly the expected summation and so, the correct operation of the design presented in figure

3.4, in section 3.2.2, is proved.

5.1 Recursive Calculations For Filters’ Frequency Response Matlab Simulation First we begin by drawing the possible generic schemes of a typical lumped component analog filter.

Those are depicted in figures a5.1 and a5.2.

1NZ1Z

LR2ZNZSR

'1Z'1NZ

'2Z'NZ

OUTVINV

Figure a5.1 – Ilustration of a generic lumped component filter of even order.

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1Z

LR2Z

NZ'1Z

'2Z

'NZ

1NZ

'1NZ

OUTVSRINV

Figure a5.2 – General representation of a lumped component filter of odd order.

Analyzing figures a5.1 and a5.2, a solution was devised to calculate the transfer function of a filter in

each of the mentioned frequencies.

The filters are created in Matlab. It is require the specification of the values of their load resistance,

푅 , source resistance, 푅 , and a variant of their order, which in this case is the N present in 푍 , in

figures 29 and 30. The values of 푅 and 푅 used are always 50 Ω.

The filters’ components are inserted in matlab from right to left (figures a5.1 and a5.2), with the

possibility of having any impedance equal to 0. As each component is added the software routine

developed will recursively make calculations. When the component of order N is inserted is

calculated for all the frequencies in the array.

The algorithm developed uses just 2 simple concepts, voltage divisors analysis and equivalent

impedances calculations with pairs of impedances in series or in parallel to each other.

At the start, some initiations are made in the program.

푍 = 푅 (a5.1) 푍 = 푅 (a5.2) 푉 = 1 (a5.3)

The calculations are different if 푍 is odd or if it is even. If 푍 is odd, (a5.4) and (a5.5) are calculated.

푍 = 푍 + 푍 (a5.4)

푉 = 푉 × (a5.5)

If 푍 is even, (a5.6) and (a5.7) verify.

푍 = × (a5.6)

푉 = 푉 (a5.7)

When the last component is added, the transfer function values are determined by:

푉푉

= 푉 × 푍

푍 + 푅 (a5.8)

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Finally, the way the components are added, shall be discussed. There is a specific number of

impedance configurations accepted by software developed. The type of impedance to be inserted is

identifiable by a character string. The type and values of the components are inputs in the call of a sub

routine that generates an output which consists of an array with the numeric impedance value

presented to every frequency of the frequency domain window. This array is itself, an input in the call

of the software routine that “adds” the components to the filter. At its completion, it is accessible to

obtain the transfer function value in every frequency.

The next subsection will display the accepted impedance configurations.

Impedances Any impedance, for instance, 푍 , may have many configurations. These are presented below from

figures 31 to 34. The impedance is always converted to an imaginary number푗푏.

푍 = 푗 × 푍 = 푗 × 휔퐿

푍 = 푗 × 휔퐿

1−휔 퐿퐶 푍 = 푗 × 휔퐿 −

1휔퐶

A resistor mat be added in series to all the combinations displayed resulting in a complex number

푎 + 푗푏.

The main issues with the analog functional filters’ simulation have been explained.

Figure a5.4 – Inductor and respective impedance

Figure a5.3 – Capacitor and respective impedance

Figure a5.5 – Inductor and capcitor in parallel and respective impedance

Figure a5.6 – Inductor and capcitor in series and respective impedance

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5.2 IP3 Error after each mixing step

Figure a5.7 – IP3 error after first downconversion mixer. The IP3 error after the first mixing step consists of one 60 MHz bandwidth band centered in 600 MHz.

It has a maximum power density of -250.98 dBW/Hz and the signal, at this point in the chain, has a

minimum power density of -107.06 dBW/Hz.

Figure a5.8 – IP3 error after second downconversion mixer. After the second downconversion step, the maximum IP3 error power density is now of 250.08

dBW/Hz and the minimum power density of the signal is of -109.33 dBW/Hz . There have appeared

several IP3 intermodulation bands, of bandwidth 60 MHz, 40MHz and 20 MHz. The center frequencies

are of 60MHz and 1140MHz (60MHz), 785 MHz and 1325 MHz (40 MHz) and finally of 2830 MHz and

3910 MHz (20 MHz). This is in accordance to calculations made.

-1000 -500 0 500 1000

-290

-280

-270

-260

-250

-240

IP3 Error after Down Conversion to 600 MHzfc=2585 MHz, LB=20MHz, Nsc=64

Frequency [MHz]

Pow

er S

pect

rum

[dB

W]

-4000 -3000 -2000 -1000 0 1000 2000 3000 4000

-310

-300

-290

-280

-270

-260

-250

-240

IP3 Error after Down Conversion to 60 MHzfc=2585 MHz, LB=20MHz, Nsc=64

Frequency [MHz]

Pow

er S

pect

rum

[dBW

]

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Figure a5.9 – IP3 error after first upconversion mixer. The IP3 error after the first upconversion mixer consists of one 60 MHz wide, band, centered in 480

MHz and another centered in 600 MHz. The maximum power density is of -250.08 dBW/Hz and the

signal, at this point, has a minimum power density of -103.73 dBW/Hz.

Figure a5.10 – IP3 error after second upconversion mixer. After the second upconversion mixer, the maximum IP3 error power density is now of -250.98 dBW/Hz

and the minimum power density of the signal is of -111.22 dBW/Hz. The center frequencies and

respective bandwidths in parentheses, of the bands that appeared, are, in this case, of, 60MHz and

1140MHz (60MHz), 1385 MHz and 2585 MHz (40 MHz) and finally, of 1505 MHz and 2465 MHz (20

MHz). Again, this is in accordance to calculations made.

The maximum difference in all 4 cases, between the IP3 error power density and the signal power

density is around 140 dB, which is 60 dB higher than 80 dB. The conclusion is that the IP3 error is, in

this case, not a problem. To note, however, that the IP3 error power density raises 6.02 dBW each

time the number of subcarriers of the ofdm signal (Nsc), at the input of the filtering system, is doubled.

-800 -600 -400 -200 0 200 400 600 800

-290

-280

-270

-260

-250

-240

IP3 Error after Up Conversion From 60 MHzfc=2585 MHz, LB=20MHz, Nsc=64

Frequency [MHz]

Pow

er S

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rum

[dB

W]

-3000 -2000 -1000 0 1000 2000 3000

-310

-300

-290

-280

-270

-260

-250

-240

IP3 Error after Up Conversion From 600 MHzfc=2585 MHz, LB=20MHz, Nsc=64

Frequency [MHz]

Pow

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[dB

]

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