PDP4216M Monitor

Model:

SERVICE MANUAL

Safety Precaution

Technical Specifications

Block Diagram

Circuit Diagram

Basic Operations & Circuit Description

Main IC Specifications

Trouble Shooting Manual of PDP Module

Spare Part list

Exploded View

If You Forget Your V-CHIP Password

Software Upgrade

This manual is the latest at the time of printing, and does notinclude the modification which may be made after the printing,by the constant improvement of product.

Safety Precaution

PRECAUTIONS DURINGSERVICING

1. In addition to safety, other parts and

assemblies are specified for conformance with

such regulations as those applying to spurious

radiation. These must also be replaced only

with specified replacements.

Examples: RF converters, tuner units, antenna

selection switches, RF cables, noise-blocking

capacitors, noise-blocking filters, etc.

2. Use specified internal Wiring. Note especially:

1) Wires covered with PVC tubing

2) Double insulated wires

3) High voltage leads

3. Use specified insulating materials for hazardous

live parts. Note especially:

1) Insulating Tape

2) PVC tubing

3) Spacers (insulating barriers)

4) Insulating sheets for transistors

5) Plastic screws for fixing micro switches

4. When replacing AC primary side components

(transformers, power cords, noise blocking

capacitors, etc.), wrap ends of wires securely

about the terminals before soldering.

5. Make sure that wires do not contact heat

generating parts (heat sinks, oxide metal film

resistors, fusible resistors, etc.)

6. Check if replaced wires do not contact sharply

edged or pointed parts.

7. Make sure that foreign objects (screws, solder

droplets, etc.) do not remain inside the set.

The lightning flash with arrowhead symbol,within an equilateral triangle, is intended toalert the user to the presence of uninsulated“dangerous voltage” within the product’s enclosure that may be of sufficient magnitude toconstitute a risk of electric shock to persons.

The exclamation point within an equilateraltriangle is intended to alert the user to thepresence of important operating andmaintenance (servicing) instructions in theliterature accompanying the appliance.

CAUTION: TO REDUCE THE RISK OFELECTRIC SHOCK, DO NOT REMOVE COVER(OR BACK). NO USER-SERVICEABLE PARTSINSIDE. REFER SERVICING TO QUALIFIEDSERVICE PERSONNEL ONLY.

CAUTION

RISK OF ELECTRIC SHOCKDO NOT OPEN

MAKE YOUR CONTRIBUTIONTO PROTECT THE

ENVIRONMENTUsed batteries with the ISO symbol

for recycling as well as small accumulators

(rechargeable batteries), mini-batteries (cells) and

starter batteries should not be thrown into the

garbage can.

Please leave them at an appropriate depot.

WARNING:

Before servicing this TV receiver, read the

SAFETY INSTRUCTION and PRODUCT

SAFETY NOTICE.

SAFETY INSTRUCTIONThe service should not be attempted by anyone

unfamiliar with the necessary instructions on this

apparatus. The following are the necessary

instructions to be observed before servicing.

1. An isolation transformer should be connected in

the power line between the receiver and the

AC line when a service is performed on the

primary of the converter transformer of the set.

2. Comply with all caution and safety related

provided on the back of the cabinet, inside the

cabinet, on the chassis or picture tube.

3. To avoid a shock hazard, always discharge the

picture tube's anode to the chassis ground

before removing the anode cap.

4. Completely discharge the high potential voltage

of the picture tube before handling. The picture

tube is a vacuum and if broken, the glass will

explode.

PRODUCT SAFETY NOTICE

Many electrical and mechanical parts in this

apparatus have special safety-related

characteristics.

These characteristics are offer passed

unnoticed by visual spection and the protection

afforded by them cannot necessarily be obtained

by using replacement components rates for a

higher voltage, wattage, etc.

The replacement parts which have these

special safety characteristics are identified by

marks on the schematic diagram and on the parts

list.

Before replacing any of these components,

read the parts list in this manual carefully. The

use of substitute replacement parts which do not

have the same safety characteristics as specified

in the parts list may create shock, fire, or other

hazards.

9. Must be sure that the ground wire of the AC

inlet is connected with the ground of the

apparatus properly.

5. When replacing a MAIN PCB in the cabinet,

always be certain that all protective are

installed properly such as control knobs,

adjustment covers or shields, barriers, isolation

resistor networks etc.

6. When servicing is required, observe the original

lead dressing. Extra precaution should be given

to assure correct lead dressing in the high

voltage area.

7. Keep wires away from high voltage or high

tempera ture components.

8. Before returning the set to the customer,

always perform an AC leakage current check

on the exposed metallic parts of the cabinet,

such as antennas, terminals, screwheads,metal

overlay, control shafts, etc., to be sure the set

is safe to operate without danger of electrical

shock. Plug the AC line cord directly to the

AC outlet (do not use a line isolation

transformer during this check). Use an AC

voltmeter having 5K ohms volt sensitivity or

more in the following manner.

Connect a 1.5K ohm 10 watt resistor paralleled

by a 0.15µF AC type capacitor, between a

good earth ground (water pipe, conductor etc.,)

and the exposed metallic parts, one at a time.

Measure the AC voltage across the combination

of the 1.5K ohm resistor and 0.15 uF

capacitor. Reverse the AC plug at the AC

outlet and repeat the AC voltage measurements

for each exposed metallic part.

The measured voltage must not exceed 0.3V

RMS.

This corresponds to 0.5mA AC. Any value

exceeding this limit constitutes a potential

shock hazard and must be corrected

immediately.

The resistance measurement should be done

between accessible exposed metal parts and

power cord plug prongs with the power switch

"ON". The resistance should be more than

6M ohms.

Good earth groundsuch as the waterpipe, conductor,etc.

Place this probeon each exposedmetallic part

AC VOLTMETER

AC Leakage Current Check

Technical Specifications

MODEL : PDP4216M Monitor

42” Plasma Display

DATE FIRST ISSUED

ISSUE

1

RAISED BY

CHECKED BY

NUMBER OF PAGE

10

REVISIONS ISSUED DATE DESCRIPTION RAISED BY :

SPECIFICATION AGREED : SIGNATURE DATE

R & D DEPARTMENT

COMMERCIAL DEPARTMENT

PRODUCTION DEPARTMENT

Q/A DEPARTMENT

CUSTOMER

......................................................................................

......

............................................................................................

.............................................................................................

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SPECIFICATION APPROVED : .

SIGNATURE :

DATE :

NOTE : Only documents stamped “Controlled Document” to be used for manufacture of production parts.

Technical Specifications

PDP4216M

CONTINUATION PAGE

NUMBER 2 OF 10 PAGES

1. Standard Test Conditions All tests shall be performed under the following conditions, unless otherwise specified. 1.1 Ambient light : 150ux (When measuring IB, the ambient luminance ≦0.1Cd/m2)

1.2 Viewing distance : 50cm in front of PDP

1.3 Warm up time : 30 minutes 1.4 PDP Panel facing : no restricted 1.5 Measuring Equipment : PC, Chroma 2225 signal generator (with Chroma digital additional card) or equivalent, Minolta CA100 photometer 1.6 Magnetic field : no restricted 1.7 Control settings : Brightness, Contrast, Tint, Color set at Center(50) 1.8 Power input : 100~120Vac 60Hz 1.9 Ambient temperature : 20°C ± 5°C (68°F ± 9°F) 1.10 Display mode : Resolution 1024 x 768 1.11 Other conditions : 1.11.1 With image sticking protection of PDP module, the luminance will descend

by time on a same still screen and rapidly go down in 5 minutes. When measuring the color tracking and luminance of a same still screen, be sure t o accomplish the measurement in one minute to ensure its accuracy. 1.11.2 Due to the structure of PDP, the extra-high-bright same screen should not hold over 5 minutes for fear of branding on the panel.

Technical Specifications

PDP4216M

CONTINUATION PAGE

NUMBER 3 OF 10 PAGES

ELECTRICAL CHARACTERISTICS 2. Power Input 2.1 Voltage : 100 ~120VAC 60Hz 2.2 Input Current : 5.0 /2.5A 2.3 Maximum Inrush Current : <30 A (FOR AC110V ONLY) Test condition : Measured when switched off for at least 20 mins 2.4 Frequency : 50Hz to 60Hz(±3Hz) 2.5 Power Consumption : 330W Typical Test condition : full white display with maximum brightness and contrast 2.6 Power Factor : Meets IEC1000-3-2 2.7 Withstanding voltage : 1.5kVac or 2.2kVdc for 1 sec 3. Display

3.1 Screen Size : 42” Plasma display 3.2 Aspect Ratio : 16:9 3.3 Pixel Resolution : 1024x768 3.4 Peak Brightness : 1000 cd/m² (Typical, Panel only) 3.5 Contrast Ratio (Dark room) : 5000:1 (Ratio, Typical, in a dark room, Panel only) 3.6 Viewing Angle : Over 160° 3.7 OSD language : English,Spanish,French

4. Signal 4.1 AV & Graphic input 4.1.1 Composite signal : CVBS 4.1.2 Y,C Signal : S-Video 4.1.3 Component signal : YPbPr x 2, HDMI,VGA compatible 4.1.4 Graphic I/P : Analog: D-sub 15pin detachable cable Digital:HDMI 4.1.5EDID compatibility : DDC 1.3

4.1.6 I/P frequency : fH: 31.5kHz to 60kHz/fV: 56.25Hz to 75Hz(1024x768 recommended)

Technical Specifications

PDP4216M

CONTINUATION PAGE

NUMBER 4 OF 10 PAGES

PIP/POP/PBP, Picture size, Picture Still, Sound mode,Last memory, Timer, MTS5. Environment 5.1 Operating environment 5.1.1 Temperature : 5º to 33°C 5.1.2 Relative humidity: 20% to 85%(non-condensing) 5.2 Storage and Transport 5.2.1 Temperature : -20°C to 60°C(-4º to 140°F) 5.2.2 Relative humidity: 5% to 95% 6. Panel Characteristics 6.1 Type : LGX2A 6.2 Size : 42”,1106.5mm(W)X622.1mm(H) (W/Ostand) 6.3 Aspect ratio : 16:9 6.4 Viewing angle : Over 160° 6.5 Resolution : 1024X768 6.6 Weight : 22.0kg ±0.5 kg (Net) 6.7 Color : 16.7 millions of colors (R/G/B each 256 scales)

6.8 Contrast : Average 60:1 (In a bright room with 150Lux at center) Typical 5000:1 (In a dark room 1/100 White Window

pattern at center). 6.9 Peak brightness : Typical 1000cd/ (1/25 White Window) 6.10 Color Coordinate Uniformity : Contrast; Brightness and Color control at normal

setting Test Pattern : Full white pattern Average of point A,B,C,D and E +/- 0.01

4.2 Audio input VGA(D-Sub 15 Pin Type)×1 D-Sub 9 Pin (RS-232 Input) × 1 HDMI (Ver. 1.1) connector × 1 S-Video (Mini Din 4 Pin) × 1 C V B I n p u t (RCA Type) × 1 Y P b P r × 2 Stereo/Audio × 6 4.3 Audio output Audio&Video Output (RCA Type) × 1 SPDIF (Optical) × 1

Technical Specifications

PDP4216M

CONTINUATION PAGE

NUMBER 5 OF 10 PAGES

6.11 Color temperature : Contrast at center (50); Brightness center (50); Color temperature set at Natural x=0.285±0.02 y=0.290±0.02

6.12 Cell Defect Specifications Subject to Panel supplier specification as appends. 7. Front Panel Control Button 7.1 SEL. Up / Down Button : Push the key to select Item up or down. When selecting the item on OSD menu. VOL. Left/Right Button : Push the key to increase the volume left or right. When selecting the adjusting item on OSD menu increase or decrease the data-bar.

MENU Button : Display or Exit the OSD menu. Source Select Button : Press this button and use up/down button to sellect

the signal sources. AV, S-Video, YPbPr1,YPbPr2 VGA or HDMI.

7.2 STANDBY Button : Switch on main power, or switch off to enter power Saving modes. 7.3 Main Power Switch : Turn on or off the unit. 8. OSD Function

8.1 Picture : Brightness; Contrast; Saturation; Phase; Frequency; Picture Mode (Normal, Bright, Cinema, User); Color Temp (Warm, Normal, Cool); etc. 8.2 Window : Image Size (Fill All, Force 4:3, Letter Box, Wide, Anamorphic, etc); H Position; V Position; Freeze Window (Off, On) 8.3 Audio : Balance; Audio Mode (SRS TSXT, Cinema, Music, News, User) Speaker (Internal, External); AVC (Off, On) Equalizer (120Hz, 200Hz, 500Hz, 1.2kHz, 3kHz, 7.5kHz, 12kHz) 8.4 Options : Osd Timeout (5 Sec, 15 Sec, 60 Sec); Menu Background (Opaque, Translucent); Language (English, French, Spanish); Default Setting; Close Caption Mode (CC1, CC2, T1, T2, Xds); Close Caption (Off, On, On Mute); Content Blocking; Timer 8.5 Layout : Full Screen; PIP; Split Screen

Technical Specifications

PDP4216M

CONTINUATION PAGE

NUMBER 6 OF 10 PAGES

9. Agency Approvals Safety UL/FCC/cUL Emissions FCC class B 10. Reliability

11.1 MTBF : 20,000 hours(Use moving picture signal at 25°C ambient) 11. Accessories : User manual x1, Remote control x1,

Stand x 1, Battery x 2, AC Cable x 1

12. Support the Signal Mode A. HDMI Mode / D-Sub Mode (VGA or DVI) / HDTV Mode (YpbPr1 or YpbPr2)

No Mode Resolution Horizontal

Frequency (KHz)

Vertical Frequency

(KHz)

Dot Clock Frequency

(MHz) 1 640x400 31.47 70.08 25.17 2 640x480 31.50 60.00 25.18 3 640x480 35.00 67.00 30.24 4 640x480 37.50 75.00 31.50 5 640x480 37.86 72.81 31.50 6 720x400 31.47 70.08 28.32 7 800x600 31.56 56.25 36.00 8 800x600 37.90 60.32 40.00 9 800x600 46.90 75.00 49.50 10 800x600 48.08 72.19 50.00 11 832x624 49.00 74.00 57.27 12 1024x768 48.84 60.00 65.00 13 1024x768 56.50 70.00 75.00 14 1024x768 60.00 75.00 78.75 15 1152x864 54.53 61.13 80.37 16 1152x864 63.86 70.02 94.51 17 1152x864 67.52 75.02 108.03 18 1280x960 60.02 60.02 108.04 19

D-Sub Mode

(VGA or DVI)

1280x1024 64.00 60.01 108.00 20 1080i (1920x1080) 33.75 60.00 74.25 21 1080i (1920x1080) 28.125 50.00 74.25 22 720P (1280x720) 45.00 60.00 74.25 23 720P (1280x720) 37.50 50.00 74.25 24 576p (720x576) 31.25 50.00 27.00 25 480p (720x480) 31.468 59.94 27.00 26 576i 15.625 50.00 13.50 27

HDMI Mode

HDTV Mode

(YpbPr1/ YpbPr2)

480i 15.734 59.94 13.50

Technical Specifications

PDP4216M

CONTINUATION PAGE

NUMBER 7 OF 10 PAGES

4.4 Remote Control

1 POWER( ): Press this button to turn off to standby and turn on from standby. 2 MUTE( ): Press this button to quiet the sound system. Press again to reactivate the sound system. 3 P.STILL: Press this button to hold on the screen. Press again to normal. 4 P.SIZE: When the input source is YPbPr 1, YPbPr 2, VGA or HDMI, press this button, the picture will change according to Fill All, Force 4:3, Letter Box, Wide or Anamorphic. When the input source is AV or S-Video, press this button, the picture will change according to Fill All, 4:3, Letter Box, Wide or Anamorphic. 5 S.SELE: Press this button to select the sound output from Main Window or Sub Window. 6 P.MODE : Press the button to select different picture effect. 7 TIME: Press this button to pop up the “Clock Set” menu. 8 SLEEP: Press this button to select the sleep time. 9 INFO: Press the button to display the source information.10 AUTO: The Display automatically adjusts the phase, vertical / horizontal position when pressing this button in VGA mode.11 LAYOUT: Press this button to pop up Layout menu.12 C/C: Press this button to enter the Closed Caption Function. (Only for AV or S-Video)13 V-CHIP: Press this button to enter the V-Chip Function. (Only for AV or S-Video)14 Number buttons: Use these buttons to enter the password.

(Continued on next page)

CONTINUATION PAGE

Technical Specifications PDP4216M NUMBER 8 OF 10 PAGES

15 SWAP: Press this button to switch the Main window or Sub window pictures in PIP and Split Screen.16 F.WHITE: Press this button to show a full white picture.17 PIP POS. : Press the button to select different Image Position in PIP Mode.18 PIP SIZE : Press the button to select different Image Size in PIP Mode.19 SPEAKER: Press this button to pop up the “Speaker” menu, use the / button to select “Internal” or “External”.20 SOUND: Press the button to select different sound effect.21 W.SELE: Press this button to select the Main Window or Sub Window.22 SOURCE: Press this button and use / button to select the signal sources. AV, S-Video, YPbPr 1, YPbPr 2, VGA or HDMI.23 PIP: Press this button to change different Picture Mode.24 MENU: Press this button to pop up the OSD Menu and press it again to exit the OSD Menu.25 OK : Press to enter or confirm.26 / : They are used as / buttons in the OSD Menu screen and they can be used for the adjustment of volume when the OSD Menu is not shown on the screen. / : They are used as / buttons in the OSD Menu screen. They also can be used for the selection of the program when the OSD Menu is not shown on the screen, but only for the Model with Tuner.

CONTINUATION PAGE

Technical Specifications PDP4216M NUMBER 9 OF 10 PAGES

CONTINUATION PAGE

Technical Specifications PDP4216M NUMBER 10 OF 10 PAGES

PHYSICAL CHARACTERISTICS

14. Power Cord

Length : 1.8m nominal

Type : optional

15. Cabinet

15.1 Color : black colour as defined by colour plaque reference number

15.2 Weight(W/Ostand)

Net weight : 34kg Gross weight :

15.3 Dimensions (W/O stand&speak)

Width : 1024mm Height : 692mm Depth : 286mm

Product Specification of PDP Module

Color Plasma Display Panel1366 X 768 pixels

Address Driver

Scan

Driv

er

Com

mon

sust

ain

driv

er

Display data, Driver timing

MemoryController

DriverTimingController

InputInterfaceController Vcc(+5V)

Va(55V~65V)

Vs(180V~190V)

Control Signal (Serial Interface)

APL Data

LVDS Input

Applied Voltage level is specified at the time when Full-White pattern is displayed on the panel.

Block Diagram

Block Diagram MAIN / AUDIO BOARD

Stereo Audio Input

Speaker

Video Input

S-Video Input

MSP44XXG Audio

decoder

TDA 2616 Audio Amp

HDMI Input

HD1 Input

HD2 Input

D-Sub15

VPC3230D

Video decoder

VPC3230D Video decoder

286229V-Chip /

CCD

SAA5316 TV TEXTPRO

LP262S20480T SRAM

PI5V330 Switch

AD9880 ADC & HDMIReceive

PW1231

De-Interlace

PW181 Image

Processor

D-SUB9

Max232RS232C

1R

Keypad

AT24C32EEPROM

HT48R06Amcu

THc63LVDM83 LVDS Transmitter

LVDS Header

Circuit Diagram - Power supply board of Audio Amplifier, MPT012A - Main (Video) board - Audio/Tuner board - Keypad board - Remote control receiver board - Remote control board

1 2 3 4 5 6

A

B

C

D

654321

D

C

B

A

Title

Number RevisionSize

B

Date: 14-Oct-2005 Sheet of File: F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:

OG

ND

11

G7 2

G6 3

G5 4

G4 5

G3 6

G2 7

G1 8

G0 9

OV

DD

110

OG

ND

211

B7 12

B6 13

B5 14

B4 15

B3 16

B2 17

B1 18

B0 19

MCLKIN 20

MCLKOUT 21

SCLK 22

LRCLK 23

I2S3 24I2S2 25I2S1 26I2S0 27

S/PDIF 28

DG

ND

129

DV

DD

30

CG

ND

131

CV

DD

132

TVD

D1

33

RX0-34

RX0+35

TGN

D1

36

RX1-37

RX1+38

TGN

D2

39

RX2-40

RX2+41

TGN

D3

42

RXC+43

RXC-44

TVD

D2

45

RTERM46

CG

ND

247

CV

DD

248

DDC_SCL49

DDC_SDA50

MCL51

MDA52

ALG

ND

53A

LVD

D54

PGN

D1

55

FILT57

PGN

D2

58PV

DD

259

VS160

VS061

COAST/EXTCK62

HS163

HS064

AG

ND

269

BAIN166

AV

DD

167

BAIN068

SOG170 GAIN171

AV

DD

272

SOG073 GAIN074

AG

ND

375

AV

DD

376

RAIN177

AG

ND

478

RAIN079

AV

DD

480

PWRDN 81

SCL82

SDA83

FIELD 84VSOUT/A0 85SOGOUT 86HSOUT 87DE 88

DCLK 89

OV

DD

290

OG

ND

391

R7 92

R6 93

R5 94

R4 95

R3 96

R2 97

R1 98

R0 99

OV

DD

310

0

PVD

D1

56

AG

ND

165

U901

DATA2+ 1

DATA2S 2

DATA2- 3

DATA1+ 4

DATA1S 5

DATA1- 6

DATA0+ 7

DATA0S 8

DATA0- 9

CLK+ 10

CLKS 11

CLK- 12

CEC 13

NC 14

SCL 15

SDA 16

CEC/GND 17

+5V 18

HPDET 19

T120

T221

T322

T423

JP901

GBE0GBE1GBE2GBE3GBE4GBE5GBE6GBE7

GGE0GGE1GGE2GGE3GGE4GGE5GGE6GGE7

GRE0GRE1GRE2GRE3GRE4GRE5GRE6GRE7 GRE[7..0]

GGE[7..0]

GBE[7..0]RP901

RP902

RP903

RP904

RP905

RP906

VCLK7

SCL6

SDA5

GND4

NC1 1

NC2 2

NC3 3

VCC 8U905

R903

C929

DDC5V

DDC5V5V

1

2

3

D911

HDMI_D2+HDMI_D2-HDMI_D1+HDMI_D1-HDMI_D0+HDMI_D0-

HDMI_CK+HDMI_CK-

R925

R919

R920 G

SD

Q902

R924

G

SD

Q901

R923

DDC5V

DDC_SCL5

DDC_SDA5

DDC_SCL3

DDC_SDA3

TVDD3.3V

R921

R922

HDMI_5V

PLL1.8V

R904C936

C935

SCL_H5VSDA_H5V

R906

R905

C938 C937

R907

PLL1.8VDVDD1.8VCVDD1.8V

HD1_R/Pr

HD1_G/Y

HD1_B/Pb

C939

C940

C941

C942

C943

C944

C945

C946

R909

R910

DDC_SDA3DDC_SCL3

R918R917

HDCP_SDAHDCP_SCL

SGND

R914

AVDD3.3V

RP909

RP908

ADCR0ADCR1ADCR2ADCR3ADCR4ADCR5ADCR6ADCR7

ADCG0ADCG1ADCG2ADCG3ADCG4ADCG5ADCG6ADCG7

ADCB0ADCB1ADCB2ADCB3ADCB4ADCB5ADCB6ADCB7

RP907

I2S_SCLKI2S_LRCLKI2S_DATA

ADC_DEADC_HSADC_SOGADC_VSADC_FIELDADC_DCLK

VCLK7

SCL6

SDA5

GND4

NC1 1

NC2 2

NC3 3

VCC 8

U906

C934

TVDD3.3VR912

R913

HDMI_D2+HDMI_D2-

HDMI_D1+HDMI_D1-

HDMI_D0+HDMI_D0-

HDMI_CK+HDMI_CK-

HPD_DET

HD2_CrHD2_Y

HD2_Cb

C902

C911

SGND

C913

C901C910

5V

C912

5V

INPUT3

GN

D1

OUTPUT 2

TAB 4

U902

INPUT3

GN

D1

OUTPUT 2

TAB 4

U903AVDD3.3V#

C926

L904

C908

C903 C915

D3V3B

C914

HDMI-1.8V

INPUT3

GN

D1

OUTPUT 2

TAB 4

U904

C924

L903

C907

OVDD3.3V

TVDD3.3V

C917C916

L900 PLL1.8V

C904

C918

OVDD3.3V# OVDD3.3V#

C920C919

L901 CVDD1.8V

C905

C921

C922

L902 DVDD1.8V

C906

C923

C2V2Y2

R928R927R926

GHSGVS

GPEN

GCLK

GCOASTR908

GSOG

C925

C927 C928

Using digital interface: DVdd (1.8V) (DVdd+CVdd) 130mA 234mW PVd (1.8V) (PVd+ALVdd) 30mA 54mW Vd (3.3V) (Avdd+TVdd) 80mA 264mW Vdd (3.3V) (Ovdd) 10-120mA, 30mA typical 99mW Using analog interface: DVdd 60mA 108mW PVd 20mA 36mW Vd 270mA 891mW

DDC_SCL5DDC_SDA5

DDC_SCL5DDC_SDA5

D901 D902

GYCbCr_Cb

GYCbCr_Cr

GYCbCr_Y

HD1_B/Pb

HD1_R/Pr

HD1_G/Y

VGA_HSVGA_VS

9-HDMI-R

GPEN

GHS

FIELD

C930

L913

GSOG

GVSFIELDGCLK

HPD_DET

C947C948

L914

C909C950C949 C951 C952

AVDD3.3V#AVDD3.3V

R915

R930

1 2

714

U907A

3 4

U907B

OVDD3.3V

R932

R933

C953R931 R934

S/PDIF

SPDIFOUT

5V

R929

VIN1

VCC2

GND3

JP902

L915C954

SPDIFOUT

HDMI_D2+

HDMI_D2-

HDMI_D1+

HDMI_D1-

HDMI_D0+

HDMI_D0-

HDMI_CK+

HDMI_CK-

GYCbCr_Cr

GYCbCr_Y

GYCbCr_Cb

R941

R942

R943

R944

R945

R946 GYCbCr_Cb

HD1_R/Pr

HD1_G/Y

HD1_B/Pb

GYCbCr_Cr

GYCbCr_Y

SGND

GFBK

R916

GFBK

C955

C956

D903

D904

D905

D906

D907

D908

D909

D910

DDC5V DDC5V

R947

SCL#SOSDA#SO

123

JP903

DDC_SCL5DDC_SDA5

1 2 3 4 5 6

A

B

C

D

654321

D

C

B

A

Title

Number RevisionSize

B

Date: 14-Oct-2005 Sheet of File: F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:

15_TELETEXT_DECODER

SCL_NVRAM

SDA_NVRAM

CV

BS

0

CV

BS

1

SCL_S3V

SDA_S3V

/RD_SRAM

/WR_SRAM

D7

_S

RA

M

D6

_S

RA

M

D5

_S

RA

M

D4

_S

RA

M

D3

_S

RA

M

D2

_S

RA

M

D1

_S

RA

M

D0

_S

RA

M

R_

OU

T

G_

OU

T

B_

OU

T

XTALIN

XTALOUT

/WR_SRAM

/RD_SRAM

A17_SRAM

A16_SRAM

A15_SRAM

A14_SRAM

A13_SRAM

A12_SRAM

A11_SRAM

A10_SRAM

A9_SRAM

A8_SRAM

A7_SRAM

A6_SRAM

A5_SRAM

A4_SRAM

A3_SRAM

A2_SRAM

A1_SRAM

A0_SRAMP2.71

P3.02

A17_LN3

P3.14

P3.25

P3.36

A15_LN7

A148

/RD9

/WR10

VSSC11

VSSP12

P0.513

NC14

A715

SCL_NVRAM16

SDA_NVRAM17

P0.218

NC19

NC20

VPE21

P0.322

A623

P0.424

P3.725

A5

26

A4

27

P0.6

28

P0.7

29

VSS

A30

CV

BS0

31

CV

BS1

32

A15

_BK

33

SYN

C_F

ILTE

R34

IREF

35

A13

36

A12

37

A3

38

A2

39

A1

40

FRA

ME

41

VPE

42

/CO

R43

P3.4

44

VD

DA

45

B46

G47

R48

A0

49

RA

MB

K1

50

RAMBANK0 51VDS 52HSYNC 53P3.5 54VSYNC 55NC 56NC 57NC 58P3.6 59VSSP 60NC 61VSSC 62VDDC 63A11 64A10 65A9 66A8 67NC 68OSCGND 69XTALIN 70XTALOUT 71/RESET 72RESET 73NC 74VDDP 75

P1.0

76A

16_L

N77

P1.1

78P1

.279

P1.3

80SC

L81

SDA

82P1

.483

P1.5

84A

D0

85A

D1

86A

D2

87A

D3

88A

D4

89A

D5

90A

D6

91A

D7

92P2

.193

P2.2

94P2

.395

P2.4

96P2

.597

P2.6

98V

SSC

99P2

.010

0

U1501

I/O829

I/O728

I/O627

I/O526

I/O425

I/O323

I/O222

I/O121

/WE5

/CE130

CE26

GN

D24

/OE32

A17 9

A16 10

A15 7

A14 11

A13 4

A12 12

A11 1

A10 31

A9 2

A8 3

A7 13

A6 14

A5 15

A4 16

A3 17

A2 18

A1 19

A0 20

VC

C8U1502

RP1502RP1501

RP1503

RP1504

RP1505

RP1506

R1508R1509

D7_SRAM

D6_SRAM

D5_SRAM

D4_SRAM

D3_SRAM

D2_SRAM

D1_SRAM

D0_SRAM

R1506

R1507

D3V3D

D3V3D

C1505C1504

R1505

X1501

A1

7_

SR

AM

A1

6_

SR

AM

A15_SRAM

A14_SRAM

A1

3_

SR

AM

A1

2_

SR

AM

A11_SRAM

A10_SRAM

A9_SRAM

A8_SRAM

A7_SRAM

A6_SRAM

A5

_S

RA

M

A4

_S

RA

M

A3

_S

RA

M

A2

_S

RA

M

A1

_S

RA

M

A0

_S

RA

MD3V3D

D3V3D

D3V3_TT_A

3450_rest

TT_R

TT_G

TT_B

TT_FSO

SCL_S3V

SDA_S3V

TT_VVVS

TT_VVHS

TV_CVBS_S#

C15

01

R15

01

C1502

R15

02

R15

03

R15

04

TV_CVBS_M# C1503

C1506 C1507 C1508

C1510

D3V3D

GPIO_P30GPIO_P31

GPIO_P33GPIO_P32

TT_SEL

R1510

R1511

R1512

C1511

R1513

R1514

R1515

C1513C1512

C1514

C15

15

SGND SGND

SGND

SGND

Q1502

R1520

R1519

D1502

D3V3D

SC1_

SW0

SC1_

SW1

SC2_

SW0

SC2_

SW1

SC1_SW0SC1_SW1

SC2_SW0SC2_SW1

SC1_SW

Q1504

R1526

R1525

D1504

D3V3D

Q1501

R1517

R1516

D1501

D3V3D

SC2_SW

Q1503

R1523

R1522

D1503

D3V3D

NC0 1

NC1 2

NC2 3

GND 4SDA5

SCL6

WP7

VCC8

U1503

D3V3D

SCL_NVRAM

SDA_NVRAM

R1527 D3V3DR

1521

R1528

C15

16

C15

17

C15

18C1519

SGND

R1529

1 2 3 4 5 6

A

B

C

D

654321

D

C

B

A

Title

Number RevisionSize

B

Date: 14-Oct-2005 Sheet of File: F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:

11-DECODERV

VIN475

VIN374

VIN273

VIN172

CIN71

Y1/G12

U1/B11

V1/R13

FBIN179

Y2/G25

U2/B24

V2/R26

XTALI62

XTALO63

VO

UT

70

VRT 66VREF 78

VG

AV

17

Y7 31

Y6 32

Y5 33

Y4 34

Y3 37

Y2 38

Y1 39

Y0 40

UV7 41

UV6 42

UV5 43

UV4 44

UV3 47

UV2 48

UV1 49

UV0 50

LLC2 27

LLC 28

AVO 54

HCLP 55

HS 56

VS 57

INTLC 53

OE#

18

FFIE

19

FFW

E20

FFR

ST21

FFR

E22

FFO

E23

TEST

16

SCL

13

SDA

14

RST

#15

VD

D10

VD

DC

AP

9

GN

DC

AP

12

PLV

DD

29

YV

DD

36

CV

DD

45

SPV

DD

52

AFV

DD

69

ISV

DD

76

VST

BY

59

CLK

560

FPD

AT

58

CLK

2024

ASG

ND

7

ASG

ND

64

GN

D11

APG

ND

25

APV

DD

26

PLG

ND

30

YG

ND

35

CG

ND

46

SPG

ND

51

AFG

ND

65

ISG

ND

68

ISG

ND

77

ISG

ND

80

I2C

SEL

67

U1102

5VVV

VV33

C1134

C1133C1132

C1123

RP1101RP1102RP1103RP1104

VY[7..0]

VUV[7..0]

VY0VY1VY2VY3VY4VY5VY6VY7

VUV0VUV1VUV2VUV3VUV4VUV5VUV6VUV7

VVVS

VVHS

R1109

VVCLK

C1137 C1135 C1138 C1136

SGND SGND

V_SVideo_Y

V_SVideo_C

VYCbCr_Cb

VYCbCr_Cr

VYCbCr_Y

SCL_S3V

SDA_S3V

C11

25

C11

26

C11

27

L1106

C1122

L1105

C1121

L1104

C1120

SGND

C1118

C1119

C1131C1130

C1115

R1102

R1101

REF_V

V_AVCVBS

V_TVCVBS C1117L1108

C1116

R1103

C11

24

MREST

5V L1101

C1103 C1104C1106C1107

5VVV

SGND

C1141 C1142 C1143 C1144C1145C1146

C1147C1148

VV33

C1105

C11

09

C11

10

C11

11

C11

12

C11

13

C11

14C1108

5V

INPUT3

GN

D1

OUTPUT 2

TAB 4

U1101

C1140

C1150 C1151

ADR:0x88

SGND

R1110

R1105

SGND

SGND

5VVV

C1160

L1107

C1159

C1139C1128

L1102

C1149

SGND

C1154

L1111

C1156

SGND

X1101

R1115

R1116

R11

17

R1118

SGND

SGND

V_TT_R

V_TT_G

V_TT_B

SGND

3230_VO

V_TT_FSO

C1166

C1167

C1168

CVBS_O

C1171

SGND

C11

72 C11

73

C11

74

SGND

Q1101 R1104

R1112

R1113 R1106

C1164

C1163

3230_VO

R1119

R1126R1125R1124

R1107

R1108

TT_VVHS

TT_VVVS

R1121TV_CVBS_M#

A5V

RP1105

RP1106

RP1107

RP1108

RP1109

VB0VB1VB2VB3

VB4VB5VB6VB7

VG0VG1VG2VG3

VG4VG5VG6VG7

VB[7..0]

VG[7..0]

VVCLK

VCLK

VVSVHSVVCLK

VVHS

VVVS

VVHSVVVS

#VPEN

#VPEN VPEN

R1123 Install RP1105~RP1109 if cancel deinterlace IC

L1112

R1114

VY0VY1VY2VY3

VY4VY5VY6VY7

VUV0VUV1VUV2VUV3

VUV4VUV5VUV6VUV7

R1127 L1103A5V

1 2 3 4 5 6

A

B

C

D

654321

D

C

B

A

Title

Number RevisionSize

B

Date: 14-Oct-2005 Sheet of File: F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:

14-DECODER_G

VIN475

VIN374

VIN273

VIN172

CIN71

Y1/G12

U1/B11

V1/R13

FBIN179

Y2/G25

U2/B24

V2/R26

XTALI62

XTALO63

VO

UT

70

VRT 66VREF 78

VG

AV

17

Y7 31

Y6 32

Y5 33

Y4 34

Y3 37

Y2 38

Y1 39

Y0 40

UV7 41

UV6 42

UV5 43

UV4 44

UV3 47

UV2 48

UV1 49

UV0 50

LLC2 27

LLC 28

AVO 54

HCLP 55

HS 56

VS 57

INTLC 53

OE#

18

FFIE

19

FFW

E20

FFR

ST21

FFR

E22

FFO

E23

TEST

16

SCL

13

SDA

14

RST

#15

VD

D10

VD

DC

AP

9

GN

DC

AP

12

PLV

DD

29

YV

DD

36

CV

DD

45

SPV

DD

52

AFV

DD

69

ISV

DD

76

VST

BY

59

CLK

560

FPD

AT

58

CLK

2024

ASG

ND

7

ASG

ND

64

GN

D11

APG

ND

25

APV

DD

26

PLG

ND

30

YG

ND

35

CG

ND

46

SPG

ND

51

AFG

ND

65

ISG

ND

68

ISG

ND

77

ISG

ND

80

I2C

SEL

67

U1402

5VVG

GV33

C1434

C1433C1432

C1423

RP1401

RP1402

RP1403

RP1404

R1409

C1437 C1435 C1438 C1436

SGND SGND

SCL_S3V

SDA_S3V

C1431C1430

R1402

R1401

REF_G

G_TVCVBSC1417

L1408

R1403

C1424

MREST

5V L1401

C1403 C1404C1406C1407

5VVG

SGND

C1441 C1442 C1443 C1444C1445C1446

C1447C1448

GV33

C1405

C14

09

C14

10

C14

11

C14

12

C14

13

C14

14

5V

INPUT3

GN

D1

OUTPUT 2

TAB 4

U1401

C1440

C1450 C1451

ADR:0x8E

SGND

R1410

R1405

SGND

SGND

5VVG

C1439

X1401

R1416

SGND

G_TT_R

G_TT_G

G_TT_B

SGND

G_TT_FSO

C1466

C1467

C1468

GGE[7..0]

GBE[7..0]

GPEN

GVS

GHSGCLK

FIELDR1408R1407

R1419

R14205VVG

G_SVideo_C

G_SVideo_Y

C1418

C1419

C1416

G_AVCVBS

GGE0GGE1GGE2GGE3GGE4GGE5GGE6GGE7

GBE0GBE1GBE2GBE3GBE4GBE5GBE6GBE7

TV_CVBS_S

CVBS_S_O

C1471

SGND

Q1401

R1404

R1412

R1413

R1406

C1464C1463

TV_CVBS_S

C1422

C1421

C1420

C1415

GYCbCr_Cb

GYCbCr_Cr

GYCbCr_Y

C14

25

C14

26

C14

27

L1406

L1405

L1404

SGND

C14

72 C14

73

C14

74

SGND

L1402

C1428 C1449

SGNDL1411

C1454 C1456

SGND

R1417

R1418

R1426R1425R1424

L1407

C1460 C1459 R1415

SGND

R1421TV_CVBS_S#

A5V

G_AVCVBS

GYCbCr_Y

GYCbCr_Cb

GYCbCr_Cr

R1422 TT-GHSTT-GHS

GHS

R1423GHS

L1412

R1414

SGND

R1427

1 2 3 4

A

B

C

D

4321

D

C

B

A Title

Number RevisionSize

A4

Date: 14-Oct-2005 Sheet of File: F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:

8-CCD_DECODER

A5VL801

C803C804 C806C807

SGND

Vin/INTRO13

SDA14

SCK15

SEN4

SMS6

HIN5

VIDEO7

CSYNC8

LPF9 VSS(A) 11

RREF 10

VDD 12

BOX 17

SDO 16

I2C/SEL 1

G 2

B 3

R 18

U803

R855

R859

R856

SCL_S5V

SDA_S5V

C855

C856

R857

C858 C859

R858

C857

R860

R861

R862

R863

R86

4

R86

5

R86

6

R86

7

SGND

V_TT_R

V_TT_G

V_TT_B

V_TT_FSO

3230_VO

V_TT_R

V_TT_G

V_TT_B

V_TT_FSO

SGND

C860 C861

A5VL802

C801C802 C805C808

SGND

Vin/INTRO13

SDA14

SCK15

SEN4

SMS6

HIN5

VIDEO7

CSYNC8

LPF9 VSS(A) 11

RREF 10

VDD 12

BOX 17

SDO 16

I2C/SEL 1

G 2

B 3

R 18

U802

R801

R805

R802

GVS

TT-GHS

C809

C810

R803

C812 C813

R804

C811

R806

R807

R808

R809

R81

0

R81

1

R81

2

R81

3

SGND

TV_CVBS_S

G_TT_R

G_TT_G

G_TT_B

G_TT_FSO

SGND

C814 C815

5V_V_CCD

5V_G_CCD

G_TT_R

G_TT_G

G_TT_B

G_TT_FSO

C86

2

C86

3

C86

4

C86

5

C81

7

C81

8

C81

9

C82

0

5V_G_CCD

5V_V_CCD

R852

V33SWR854

R853

5V

SCL_S3V

SDA_S3V

SCL_S5V

SDA_S5V

SCL_S5V

SDA_S5V

SCL_S5V

SDA_S5V

SGND

SGND

SGND

TT_VVHS

TT_VVVS

G

SD

Q802

R814

G

SD

Q801

R815

1 2 3 4 5 6 7 8

A

B

C

D

87654321

D

C

B

A

Title

Number RevisionSize

A3

Date: 14-Oct-2005 Sheet of File: F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:

GSOGB10

GRE0E4

GRE1C3

GRE2B1

GRE3F4

GRE4C2

GRE5C1

GRE6D3

GRE7D2

GGE0C11

GGE1B12

GGE2B11

GGE3A8

GGE4B8

GGE5C8

GGE6A7

GGE7B7

GBE0B18

GBE1A20

GBE2B17

GBE3A19

GBE4B16

GBE5A17

GBE6A16

GBE7A15

GRO0A6

GRO1C7

GRO2B6

GRO3A5

GRO4D7

GRO5B5

GRO6C6

GRO7A4

GFBK A11

GGO0C13

GGO1B15

GGO2A14

GGO3B14

GGO4A13

GGO5C12

GGO6B13

GGO7A12

GBO0C18

GBO1E17

GBO2C17

GBO3B19

GBO4E16

GBO5C16

GBO6C15

GBO7D14

GHSC10 GVSA9 GPENB9 GCLKA10

GREF D10

GBLKSPL C14

GCOAST A18

GHSFOUT C9

PW181 Graphics Port

U1301A

GCLKGPENGVSGHS

GFBKGBLKSPLGCOAST

GRE[7..0] GRE0GRE1GRE2GRE3GRE4GRE5GRE6GRE7

GGE[7..0] GGE0GGE1GGE2GGE3GGE4GGE5GGE6GGE7

GBE[7..0] GBE0GBE1GBE2GBE3GBE4GBE5GBE6GBE7

GRO[7..0] GRO0GRO1GRO2GRO3GRO4GRO5GRO6GRO7

GGO[7..0] GGO0GGO1GGO2GGO3GGO4GGO5GGO6GGO7

GBO[7..0] GBO0GBO1GBO2GBO3GBO4GBO5GBO6GBO7

VB[7..0] VB0VB1VB2VB3VB4VB5VB6VB7

VG[7..0] VG0VG1VG2VG3VG4VG5VG6VG7

VR[7..0] VR0VR1VR2VR3VR4VR5VR6VR7

VCLKVVSVHS

DCLKDVSDHSDEN

RP1302

RP1303

DRE[7..0]

DRE0

DRE1

DRE2DRE3

DRE4

DRE5DRE6

DRE7

RP1304

RP1305

DGE[7..0]

DGE0DGE1

DGE2

DGE4DGE5

DGE7

RP1306

RP1307

DBE[7..0]DBE0

DBE1DBE2

DBE4

DBE5DBE6DBE7

VCLKE1

VVSE3

VHSF3

FIELDD1

VPENN2

VR0E2

VR1F1

VR2F2

VR3G3

VR4G2

VR5H3

VR6H2

VR7G1

VG0J4

VG1H1

VG2J3

VG3J2

VG4J1

VG5K3

VG6K2

VG7K1

VB0L2

VB1L1

VB2L3

VB3L4

VB4M3

VB5M1

VB6N1

VB7M2

PW181 Video Port

U1301B

DCLK J17

DVS C20

DHS D18

DEN N19

DRE0 V19

DRE7 U20

DRE6 V20DRE5 W20

DRE4 R18

DRE3 U19

DRE2 R16

DRE1 Y20

DGE7 P20

DGE6 P19

DGE5 P18

DGE4 M18

DGE3 R20

DGE2 R19

DGE1 T20

DGE0 T19

DBE7 L20

DBE6 L19

DBE5 K17

DBE4 M19

DBE3 L17

DBE2 M20DBE1 N20

DBE0 M17

DRO7 H19DRO6 H20DRO5 J19DRO4 J18

DRO2 K18

DRO3 J20

DRO1 K20DRO0 K19

DGO0 H18

DGO1 H17

DGO2 G20

DGO3 G19

DGO4 G18

DGO5 F20

DGO6 F19

DGO7 F18

DBO0 E20

DBO1 E19

DBO2 E18

DBO3 F17

DBO4 D20

DBO5 D19

DBO6 D16

DBO7 D17

PW181 Display Port

U1301C

RESETY11

MCKEXTE5

DCKEXTD6

XIA3

XOC5

RXDY12

TXDV12

IRRCVR0V11

IRRCVR1W11

PORTA0V13

PORTA1W13

PORTA2Y13

PORTA3Y14

PORTA4W14

PORTA5Y15

PORTA6W15

PORTA7V15

PORTB0R17

PORTB1W18

PORTB2V18

PORTB3Y18

PORTB4U18

PORTB5Y19

PORTB6W19

PORTB7T18

PORTC0T17

PORTC1V16

PORTC2W16

PORTC3Y16

PORTC5U17 PORTC4V17

PORTC6W17

PORTC7Y17

CPUTMSP1

CPUTCKY2

CPUDIM4

CPUDON3

MODE0U16

MODE1N4

MODE2T5

MODE3P2

ADR24BU15

A0 U4

A1 T4

A2 V3

A3 U3

A4 Y1

A5 W2

A6 T3

A7 V2

A8 U2

A9 W1

A10 R4

A11 V1

A12 P4

A13 R3

A14 T2

A15 U1

A16 T1

A17 R2

A18 R1

A19 P3

D0 V10

D1 Y10

D2 Y9

D3 W9

D4 V9

D5 Y8

D6 W8

D7 V8

D8 W7

D9 U8

D10 V7

D11 W6

D12 Y6

D13 V6

D14 U7

D15 U6

RD W3

WR Y3

BHEN W12

ROMOE V5

ROMWE W4

RAMOE W5

RAMWE Y5

CS1 Y4

CS0 V4

EXTINT U10

NMI W10

DNC1 B20

DNC2 C19

DNC3 V14

PW181 MISC

U1301D

VD

D1

E7V

DD

2E9

VD

D3

E10

VD

D4

E11

VD

D5

E12

VD

D6

E13

VD

D7

E14

VD

D8

E15

VD

D9

F16

VD

D10

H5

VD

D11

H16

VD

D12

J5V

DD

13K

5V

DD

14K

16V

DD

15L5

VD

D16

N5

VD

D17

N6

VD

D18

N15

VD

D19

N16

VD

D20

P5V

DD

21P6

VD

D22

P15

VD

D23

P16

VD

D24

R13

VD

D25

R14

VD

D26

R15

VD

D27

T6V

DD

28T7

VD

D29

T9V

DD

30T1

0V

DD

31T1

1V

DD

32T1

2V

DD

33T1

3V

DD

34T1

4V

DD

35T1

5

VPP

1B

4V

PP2

C4

VC

C1

A2

VC

C2

T16

VC

C3

U5

VC

C4

U9

VC

C5

U11

VC

C6

U13

VIO

1E6

VIO

2E8

VIO

3F5

VIO

4F6

VIO

5F7

VIO

6F1

4V

IO7

F15

VIO

8G

5V

IO9

G6

VIO

10G

15V

IO11

G16

VIO

12J1

6V

IO13

L16

VIO

14M

5V

IO15

M16

VIO

16R

6V

IO17

R7

VIO

18R

8V

IO19

T8

GN

D1

A1

GN

D2

B2

GN

D3

B3

GN

D4

D4

GN

D5

D5

GN

D6

D8

GN

D7

D9

GN

D8

D11

GN

D9

D12

GN

D10

D13

GN

D11

D15

GN

D12

G4

GN

D13

G17

GN

D14

H4

GN

D15

H8

GN

D16

H9

GN

D17

H10

GN

D18

H11

GN

D19

H12

GN

D20

H13

GN

D21

J8G

ND

22J9

GN

D23

J10

GN

D24

J11

GN

D25

J12

GN

D26

J13

GN

D27

K4

GN

D28

K8

GN

D29

K9

GN

D30

K10

GN

D31

K11

GN

D32

K12

GN

D33

K13

GN

D34

L8G

ND

35L9

GN

D36

L10

GN

D37

L11

GN

D38

L12

GN

D39

L13

GN

D40

L18

GN

D41

M8

GN

D42

M9

GN

D43

M10

GN

D44

M11

GN

D45

M12

GN

D46

M13

GN

D47

N8

GN

D48

N9

GN

D49

N10

GN

D50

N11

GN

D51

N12

GN

D52

N13

GN

D53

N17

GN

D54

N18

GN

D55

P17

GN

D56

R5

GN

D57

U12

GN

D58

U14

GN

D59

Y7

PW818 POWER AND GROUND

U1301E

A[19..1]A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17

D0

A18A19

D[15..0]

D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15

ROMOEnROMWEn

RESET

C1302C1301

RXDTXD

IR_181NMI

SDA_H3VSCL_H3VSDA_S3VSCL_S3V

D3V3B

MUTE

VGASEL

KEY0KEY1

COMMUNIC

SEL1

HPD_DET

MREST

D3V3B

RNMI2

V15V15pV25D3V3B

C1324C1303

INPUT3

GN

D1

OUTPUT 2

TAB 4

U13025V

C1325C1304 C1305 C1306 C1307 C1308 C1309

V25

C1315C1314C1313

D3V3B

C1322 C1321 C1320 C1319 C1318 C1317 C1316INPUT3

GN

D1

OUTPUT 2

TAB 4

U1303

C1344

C1331

D3V3B

C1333 C1334 C1335 C1336 C1337 C1338 C1339 C1340 C1341 C1342 C1343

C1330 C1329 C1328

V15

V15

12

C1346 C1349 C1350

L1301

C1332 C1351 C1352 C1353

V15p

R1301

R1304

R1303

R1308

R1307

R1306

R1305

R1313

R1311R1312

13-SCALER

GAFEOE

R1316

D3V3CR1314

R1315

SCL_H5V

SDA_H5V

KEY3

Q1303

R1309

R1310

D3V3B

SDA_H3VSCL_H3V

SCL_H3V

SDA_H3V

KEY6

KEY2

KEY4KEY5

R1317R1318R1319R1320

C1354

SP_RELAY

DBE3

DGE6

DGE3

X1301

R1323

R1322

R1321

D3V3B

R1325

R1324

R1326

D3V3B

D3V3B

P_SLE

P_SCLKP_SDATA

R1329

R1331

3450_rest

R1332

HARDWARE I2C: SDA1 SCL1SOFTWARE I2C: VSDA VSCL

REMARK:

V15

R1333

SEL0

L1302

C1355

L1304

C1357

DTXON

D1302

FIELD

C1326

C1312

SCL_H5V

SDA_H5V

5Vstby

G

SD

Q1302

R1335

G

SD

Q1301

R1334

VPEN

DR0

DR1

DR2DR3

DR4

DR5DR6

DR7

DG0DG1

DG2

DG4DG5

DG7

DB0

DB1DB2

DB4

DB5DB6DB7

DB3

DG6

DG3

RP1308

RP1309

RP1310

RP1311

RP1312

RP1313

DR0

DR1

DR2DR3

DR4

DR5DR6

DR7

DG0DG1

DG2

DG4DG5

DG7

DB0

DB1DB2

DB4

DB5DB6DB7

DB3

DG6

DG3

DRE[7..0]

DRE6

DRE7DRE0

DRE1

DRE2

DRE3

DRE4DRE5

DGE[7..0]

DGE6DGE7DGE0

DGE2DGE3

DGE5

DBE[7..0]

DBE6

DBE7DBE0

DBE2

DBE3DBE4

DBE5

DBE1

DGE4

DGE1

R0R1R2R3R4R5R6R7For Samsung/Formosa panel

2005.05.22

181 LVDS

R0R1R2R3R4R5

R6R7

GSOG

1 2 3 4 5 6

A

B

C

D

654321

D

C

B

A

Title

Number RevisionSize

B

Date: 14-Oct-2005 Sheet of File: F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:

VY[7..0]

VUV[7..0]

VVCLK

VVVSVVHS

VY0VY1VY2VY3VY4VY5VY6VY7

VUV0VUV1VUV2VUV3VUV4VUV5VUV6VUV7

RP1201

RP1202

RP1203

RP1204

RP1205

RP1206

VCLKVVSVHS

VR[7..0]

VG[7..0]

VB[7..0]

VG0VG1VG2VG3VG4VG5VG6VG7

VR0VR1VR2VR3VR4VR5VR6VR7

VB0VB1VB2VB3VB4VB5VB6VB7

AV331

V33SW

SCL_S3VSDA_S3V

C1218C1241

MREST

V33SW

31RAMD1531RAMD1431RAMD1331RAMD1231RAMD1131RAMD1031RAMD931RAMD831RAMD731RAMD631RAMD531RAMD431RAMD331RAMD231RAMD131RAMD0

31RAMA031RAMA131RAMA231RAMA331RAMA431RAMA531RAMA631RAMA731RAMA831RAMA931RAMA1031RAMA1131RAMA1231RAMA13

V33SW

V25SW

V33SW1

AV25p1

AV25p2

AV25a

AV331

AV25A

AV25P1

Vdd

1

DQ0 2

Vdd

Q3

DQ1 4

DQ2 5

Vss

Q6

DQ3 7

DQ4 8

Vdd

Q9

DQ5 10

DQ6 11

Vss

Q12

DQ7 13

Vdd

14

DQ

ML

15

CAS 17

RAS 18

/CS

19

BA121 BA020

A1022

A023

A124

A225

A326

Vdd

27

Vss

28

A429

A530

A631

A732

A833

A934

A1135

NC

36

CKE 37

CLK38

DQ

MH

39

NC

40

Vss

41

DQ8 42

Vdd

Q43

DQ9 44

DQ10 45

Vss

Q46

DQ11 47

DQ12 48

Vdd

Q49

DQ13 50

DQ14 51

Vss

Q52

DQ15 53

Vss

54

WE 16

U1203

V33SW

31RAMD1531RAMD1431RAMD1331RAMD1231RAMD1131RAMD1031RAMD931RAMD831RAMD731RAMD631RAMD531RAMD431RAMD331RAMD231RAMD131RAMD0

31RAMA031RAMA131RAMA231RAMA331RAMA431RAMA531RAMA631RAMA731RAMA831RAMA931RAMA1031RAMA11

31RAMA1231RAMA13

31RASn31CASn31WEn

V33SW

VB082

VB183

VB284

VB385

VB486

VB587

VB688

VB789

COMP 25

SVHS92

SVVS93

SVCLK94

PVHS108

VG095

VG196

VG297

VG398

VG499

VG5100

PVVS107

VG6101

VG7102

CREF106

VR0109

VR1110

VR2111

VR3112

VR4113

VR5114

VR6115

VR7116

PVCLK105

RSET 24

VREFOUT 27VREFIN 26

ADB 15ADG 18ADR 21ADSVM 12

DR4 3

DHS 138DVS 137DCLK 136

DB7 148DB6 145DB5 144DB4 143DB3 142DB2 141DB1 140DB0 139

DG7 156DG6 155DG5 154DG4 153DG3 152DG2 151DG1 150DG0 149

DR3 2DR2 159DR1 158DR0 157

DR6 5DR5 4

DR7 6

PW1231 VIDEO BLOCK

U1201A

TDO127

TCK128

TDI129

TMS130

TRST131

I2CA1119

I2CA2120

SCL125

SDA126

XTALI117

XTALO118

RESET132

DEN73

TESTCLK72

TEST135

CGMS74

MACRO81

PW1231 HOST IF BLOCK

U1201B

MA040

MA138

MA236

MA334

MA433

MA535

MA739 MA637

MA841

MA943

MA1042

MA1145

MA1246

MA1344

MCLKFB47

MCLK51

MD15 68

MD14 66

MD13 64

MD12 62

MD11 60

MD10 58

MD9 56

MD8 54

MD7 55

MD6 57

MD5 59

MD4 61

MD3 63

MD2 65

MD1 67

MD0 69

MRAS 48

MCAS 49

MWE 50

PW1231 MEMORY BLOCK

U1201C

VSS08

VSS171

VSS2104

VSS3134

PVSS01

PVSS19

PVSS253

PVSS379

PVSS491

PVSS5122

PVSS6147

DPAVSS78

DPDVSS76

MPAVSS123

ADDVSS11

ADAVSS29

ADGVSS32

AVS33B17

AVS33G20

AVS33R23

AVS33SVM14

VDD0 7

VDD1 70

VDD2 103

VDD3 133

PVDD0 30

PVDD1 52

PVDD2 80

PVDD3 90

PVDD4 121

PVDD5 146

PVDD6 160

DPAVDD 77

DPDVDD 75

MPAVDD 124

ADDVDD 10

ADAVDD 28

ADGVDD 31

AVD33B 16

AVD33G 19

AVD33R 22

AVD33SVM 13

PW1231 POWER AND GROUND

U1201D

12-DEINTERLACE

AV331V33SW

C1250

C1237 C1238 C1239 C1240

V33SW1V33SW

C1247

C1227 C1228 C1229 C1230 C1231 C1232 C1233

INPUT3

GN

D1

OUTPUT 2

TAB 4

U1202

C1242

5V V25SW

C1205 C1206 C1207 C1208 C1209

V25SW

C1249

C1219 C1220 C1221 C1223

V25SW

C1248

C1234 C1235 C1236

AV25P2V25SW

C1246

C1224 C1225

V33SW

C1210 C1212 C1213 C1214 C1215 C1216 C1217

C1226

R1209 R1210

C1204

C1243

C1211

R1214

C1203

R1212R1211R1213

R1204R1205R1206R1207R1208

R1202R1201

R1215

5V

C1245 C1222INPUT3

GN

D1

OUTPUT 2

TAB 4

U1204V33SW

C1244

R1203

L1201

L1202

L1205

L1204L1203

ADR:0x64

C1251

R1216R1217R1218

X1201

C1201 C1202

1 2 3 4

A

B

C

D

4321

D

C

B

A Title

Number RevisionSize

A4

Date: 14-Oct-2005 Sheet of File: F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:

S1A2

S2A3

S1B5

S2B6

S1C11

S2C10

S1D14

S2D13

IN1

EN15

GN

D8

VC

C16

DA 4

DB 7

DC 9

DD 12

U1004

VGASEL

SGND

A5V

YPbPr_Y

YPbPr_Pr

YPbPr_Pb

R1005

R1006

10-PROGRESSIVE_ADC

1 27

14

U1007A3 4

U1007B

11 10

U1007C

13 12

U1007D

TVDD3.3V

R1007 R1009

R1008 R1010

C1042R1016

C1041R1015

C1026L1004

SGND

51049382716

15

14

13

12

11

1617

JP1001

5V

VGAVS

VGAHS

VGAVS

VGAHS

VCLK7

SCL6

SDA5

GND4

NC1 1

NC2 2

NC3 3

VCC 8U1008

R1021

C1003

R1020R1019

5V

L1001

R1011 R1012 R1013

L1002

L1003

SGND

5V

VGA B

VGA G

VGA R

VGA R

VGA G

VGA B

DDCD

DDCC

DDCDDDCC

VGA5V5V

SGND

VGA5V

1 2

3

D1015

VGASEL

5V5V

YPbPr_Pb

YPbPr_Pr

YPbPr_Y AGND

SC101 SC103 SC104SC102

VGA_HS

VGA_VS

HD1_B/Pb

HD1_R/Pr

HD1_G/Y

VGA_HS

VGA_VS

HD1_R/Pr

HD1_G/Y

HD1_B/Pb

D1001 D1002D1003 D1004 D1005

D1006 D1007

R1022

1 2 3 4 5 6 7 8

A

B

C

D

87654321

D

C

B

A

Title

Number RevisionSize

A3

Date: 14-Oct-2005 Sheet of File: F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:

4-FLASH

A151 A142 A133 A124 A115 A106 A97 A88

A19 9

NC 10

WE11

RESET12

NC 13

NC14

RY/BY 15

A1816 A1717

A718 A619 A520 A421 A322 A223 A124 A025

CE26

Vss 27

OE28

DQ0 29

DQ8 30

DQ1 31

DQ9 32

DQ2 33

DQ10 34

DQ3 35

DQ11 36

Vdd 37

DQ4 38

DQ12 39

DQ5 40

DQ13 41

DQ6 42

DQ14 43

DQ7 44

DQ15 45

Vss 46

BYTE47

A1648

FLASH_8M

U401

1 23 4

JP401

A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18A19

D9D8

A[19..1]

D[15..0]

D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15

A14

A17A19

D14D15

D3V3B

ROMOEnROMWEn

D3V3B

C401

D3V3B

CT3

CONTROL1

RESin2

GND 4

Vdd 8

RESET 5

RESET 6

SENCE7U403

C405

D3V3B

C407

TLCCT

RSTINn

RESET

C406

D3V3B

NMI

R409 R410

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 5051 5253 5455 5657 5859 60

JP402A1A2A3A4A5A6A7A8A9A10A11

A12

R411

A13A15A16A18

R413R412

D7D6D13D12

D10D11

D0D1

D3V3B

D2D3

D4D5

R404

R405

R414

SCL_H5V

SDA_H5V

RESETn

R402

RESETnR401D3V3B

R407

R408

R406

R415

1 2

SW402

1 2

SW401

ADR:0xA0/MEMORYADR:0xD0/COMPANION

C408

NC0 1

NC1 2

NC2 3

GND 4SDA5

SCL6

WP7

VCC8

U402

C402

5Vstby

C1+1

C1-3

C2+4

C2-5

T1_IN11

T2_IN10

R1_OUT12

R2_OUT9

T1_OUT 14

T2_OUT 7

R1_IN 13

R2_IN 8

V- 6

V+ 2VC

C16

GN

D15

U404

5V#

TXD

RXD

162738495

1011

JP403

232_OUT

232_IN

R416

R417

C411

L401

C412

L402

L403

C414C413

5V

C416 C415

RXD

TXD

C409

C410

C419C418

C417

L404

C420

R418

L405

5V

1234

JP404

TXDRXD

5V

RESET

R420

R419

R422

R421SDA#SOSCL#SOSCL#SO

SDA#SO

1 2 3 4

A

B

C

D

4321

D

C

B

A Title

Number RevisionSize

A4

Date: 14-Oct-2005 Sheet of File: F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:

5-LVDS&TMDS

VC

C1

TxIN52

TxIN63

TxIN74

GN

D5

TxIN86

TxIN97

TxIN108

VC

C9

TxIN1110

TxIN1211

TxIN1312

GN

D13

TxIN1414

TxIN1515

TxIN1616

R_FB 17

TxIN1718

TxIN1819

TxIN1920

GN

D21

TxIN2022

TxIN2123

TxIN2224

TxIN2325

VC

C26

TxIN2427

TxIN2528

GN

D29

TxIN2630

TxCLK_IN31

PWR_DWN 32

PLL_GND 33

PLL_

VC

C34

PLL_GND 35

LVDS_GND 36

TxOUT3+ 37TxOUT3- 38

TxCLKOUT+ 39TxCLKOUT- 40

TxOUT2+ 41TxOUT2- 42

LVDS_GND 43

LVD

S_V

CC

44

TxOUT1+ 45TxOUT1- 46TxOUT0+ 47TxOUT0- 48

LVDS_GND 49

TxIN2750

TxIN051

TxIN152

GN

D53

TxIN254

TxIN355

TxIN456

U501

DRE0DRE1

DRE2DRE3DRE4DRE5DRE6DRE7

DGE0DGE1

DGE2DGE3DGE4DGE5DGE6DGE7

DBE0DBE1

DBE2DBE3DBE4DBE5DBE6DBE7

DRE[7..0]

DGE[7..0]

DBE[7..0]

DCLK

DENDVSDHS

DTXON

TX0-TX0+TX1-TX1+TX2-TX2+TX3-TX3+CK-CK+

5V

C506C507

INPUT3

GN

D1

OUTPUT 2

TAB 4

U502LVD33

DHSDVSDEN

DCLK

DTXON

ANDY

00

DRE0DRE1DRE2DRE3DRE4DRE5DRE6DRE7DGE0DGE1DGE2DGE3DGE4DGE5DGE6DGE7DBE0DBE1DBE2DBE3DBE4DBE5DBE6DBE7

For sumsung panel

For LG panel

/ DS90C385AMTD

C520

L501

C510

LVD33

C521

L502

R501

R502

C522

C523

C502C501

LVD_VCC

LVD_PLL33

RS

C524

C525

SGND

12345678910111213141516171819202122232425262728293031

TX0+TX0-

TX1-

TX2-TX2+

TX1+

TX3+TX3-

CK-CK+

For sumsung panel standard LVDS jack

R510

R511

P_SLE

P_SCLK

P_SDATA

P_DISPEN

R508

R509

LVD33

L503

C526

L504

C527

L505

C528

L506

C529

P_DISPEN

P_SDATA

P_SCLK

P_SLE

C505

NC

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

19 20

21

22

JP501

TX0-

TX0+

TX1-

TX1+

TX2-

TX2+

TX3-

TX3+

CK-

CK+

P_DISPEN#

P_SDATA#

P_SCLK#

P_SLE#

SGND

12345678910111213141516171819202122232425262728293031

TX0+TX0-

TX1-

TX2-TX2+

TX1+

TX3+TX3-

CK-CK+

For LG panel standard LVDS jack

NC

p_dispen#p_sdata#p_sclk#p_sle#

SCL_S3V

SDA_S3V

R503

R504

Formosa panel CPUGOR512

R513VS_ON#

RELAY_ON#

Formosa panel PDPGO

CPUGO

PDPGO

IRQ

PDWN

1 2 3 4 5 6

A

B

C

D

654321

D

C

B

A

Title

Number RevisionSize

B

Date: 14-Oct-2005 Sheet of File: F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:

6-POWER MANAGER604

D3V3B

R603

IR_181

KEY1

KEY4KEY3

KEY0

To Key Board

KEY5KEY6

R605

R602

R601

RELAY_ONR606

KEY2

R60

8

R60

9

R61

0

R61

1

R61

2

R61

3

R61

4

D3V3B

Q602

Q601

RELAY_ON

VS_ON5VDetect

123456789

1011

JP6075VSC

C613C622

D3V3B

C655C654

L606

C614C623

L607

C624

D3V3C

C617C625

5V

L608

C618C626

R607

L621

C63

3

C63

4

C63

5

C63

6

C63

7

C63

8

C63

9C

640

C63

2

From

pan

nel

L623

L624

L625C648C649 C650

123456789

10111213

JP604

L620

L601

C651

R63

5

R631

R632

D601 MUTE

IR_mcu

5Vstby#

INPUT 3

GN

D1

OUTPUT2

TAB4

U6045V

C64

1

5Vstby

C629

C628

D3V3DL628

C630C631

PA31

PA22

PA04

PA13

PB0/BZ7

PB1/_BZ6

PB25

VSS8

PC0/_INT9 PC1/TMR 10

/RES 11

VDD 12

OSCI 13

OSCO 14

PA4 18

PA5 17

PA6 16

PA7 15

U601

C611C610

R625

X601

R626

C609

P_DISPEN

R64

1

R64

2

R64

3

IR_mcu

key_stby

P_ON/SLEEP

P_ON/SLEEP

5VDetect

VS_ON

R63

9

R64

0

5V_mcu

5V_mcu

V+V-

MENU

P+P-

INPUT

STANDBY

P_DISPEN OSCO

OSCI

RST

IR_mcu

P_ON/SLEEP

5VDetect

VS_ON

P_DISPEN

mut#

SB_5VCN key_stby

5V_mcu

OSCO

OSCI

RST

mut#PA31

PA22

PA04

PA13

PB0/BZ7

PB1/_BZ6

PB25

VSS8

PC0/_INT9 PC1/TMR 10

/RES 11

VDD 12

OSCI 13

OSCO 14

PA4 18

PA5 17

PA6 16

PA7 15

U602

R617

R618

SDA#

SCL#

SDA#

SCL#

COMMUNIC COMMUNIC

R616 C608

L612L611

L614L613

L616L615

L622

L617

Q605 Q606

R621 R623

Q607

R620

R619

D3V3B 5Vstby

R622

D602D603D604

5Vstby

R633

R624

R61

5

D3V3B

SCL_H5V

SDA_H5V

D3V3_TT_AL629

C642C643

L602

R627

R628

Q6035Vstby

5Vstby

LED_R

LED_G

R629

D610

5V

IR_5V

C64

4

SGND

COMMUNIC

5Vstby

C612 C602

L605

123456789

JP608

VS_ON#

RELAY_ON#

VS_ON#

RELAY_ON#

D6VD3V3#

D3V3#

5Vstby#

RELAY_ON#C603C601

INPUT 3

GN

D1

OUTPUT2

TAB4

U603

5VSC

C621

For SDI V3 HD Panel2005.06.14

D605

R630

1 2 3 4 5 6 7 8

A

B

C

D

87654321

D

C

B

A

Title

Number RevisionSize

A3

Date: 14-Oct-2005 Sheet of File: F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:

7-VIDEO&AUDIO IN

VYCbCr_Cr

5V

SGND

L750

L751

L752

VYCbCr_Y

SGND

R750

R751

SGND

R752

SGND

SGND

SGND

L753

L754

L755

R753

R754

R755

V_AVCVBS

V_SVideo_YV_SVideo_C

YPbPr_Pr

YPbPr_Pb

YPbPr_Y

Cb_in

Cr_in

YUV_Y_in

C740

C742

C744

C746

C748

C750

Pb_in

Pr_in

HD_Y_in

SCL_S5V

SDA_S5V

C787

AGND

C790C789

R780

C73

2

R781

C73

3

R782

C73

4

R783

C73

5

R776

C72

8

R777

C72

9

R778

C73

0

R779

C73

1

AGND

+8VL756

Y2B2

Y0B1

Y2A15

Y1B5

Y3B4 E 6VEE

7V

SS8

A1 9

A0 10

Y3A11

Y0A12

Y1A14 ZA 13

ZB 3VD

D16

U701

SEL1 SEL0

AGND

C719

C722

AGND

VGA_L4

DVI_L_IN

VGA_R4

DVI_R_IN

C720

C723

C721

C724 AV_R1AV_R2AV_R3

AV_L1AV_L2AV_L3

L_O

R_O

SEL1 SEL0

3

1

42

JP707

AGND

DVI_L_IN#

DVI_R_IN#

DVI_L_IN#

DVI_R_IN#

VGA_L4#

VGA_R4#

VGA_L4#

VGA_R4#

YUV_L_IN#

YUV_R_IN#

YPbPr_L_IN#

YPbPr_R_IN#

YPbPr_L_IN#

YPbPr_R_IN#

YUV_L_IN#

YUV_R_IN#

C725

R756

R757

AGND

C726

R758

R759

AGND

AV_R4

AV_L4

3450_restMUTE

SP_RELAY

+8V

AV_LOUTAV_ROUT

AGND SGND

C713C714

8V_4052

L_O

R_O

MUTE

C715 C716 C718

SGND

5V

V_TVCVBS

TV_M

V_AVCVBS

SP_RELAY

3450_rest

V_SVideo_CV_SVideo_Y

SCL_S5V

SDA_S5V

VIN1

ENABLE2

RFC3

VCC4 GND 5

VOUT 6

VF 7

GSEL 8U702

C701

L748

C702R701

Cutoff requency : 6.4MHz

R705

C704

R702

SGND

C703

R703

R704

A5V

V_TVCVBS

TV_M

G_TVCVBS

VIN1

ENABLE2

RFC3

VCC4 GND 5

VOUT 6

VF 7

GSEL 8U703

C705

L749

C706R706

Cutoff frequency : 6.4MHz

R710

C708

R707

SGND

C707

R708

R709

A5V

G_TVCVBS

TV_S

TV_S

S1A2

S2A3

S1B5

S2B6

S1C11

S2C10

S1D14

S2D13

IN1

EN15

GN

D8

VC

C16

DA 4

DB 7

DC 9

DD 12

U704

TT_SEL

SGND

A5V

C709

L739

SGND

TT_SEL

SC1_BOXSC1_RSC1_GSC1_B

SC1_BOX

SC1_R

SC1_G

SC1_B

TT_R

TT_G

TT_B

TT_FSO

TT_R

TT_G

TT_B

TT_FSO

V_TT_R

V_TT_G

V_TT_B

V_TT_FSO

V_TT_G

V_TT_B

V_TT_R

V_TT_FSO

1

2

3

JP705

3

4

1

2

5 6

JP704

YUV_L_IN

YUV_R_IN

YPbPr_L_IN

YPbPr_R_IN

2

4

1

3

87

6

5

9

JP701

Pr_in

Pb_in

HD_Y_in

Cr_in

Cb_in

YUV_Y_in

SGND

R71

2

R71

1

R71

4

R71

3R

718

R71

7

R71

6

R71

5

SGND

Q701

R719

R720 R722 C737

C736

5V_E

VYCbCr_Cb

C710 C711

SGND

A5V

SGND

Q702

R723

R724 R726C739

R725

C738

5V_E

SGND

Q703

R727

R728 R788C752

R729

C751

5V_E

L738

G_SVideo_C

G_SVideo_Y

G_AVCVBS

GYCbCr_Cb

GYCbCr_Cr

GYCbCr_Y

R730

R731

R732

R733

R734

R735

R736

R737

R738

C753

C754

C755

GPIO_P33GPIO_P32

GPIO_P30GPIO_P31

3230_VO

C757

C756

AV_LOUT

AV_ROUT

C741C743

R739R740

R741

R742

SGND AGND

1 23 45 67 89 10

11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 50

JP703

SC1_SW

SC2_BOXSC2_RSC2_GSC2_B

SC2_SWSC2_SW

SC1_SW

GPIO_P33GPIO_P32

GPIO_P31GPIO_P30

3230_VO

G_AVCVBS R743

R744

R745

G_SVideo_C

G_SVideo_Y

V_AVCVBS

V_SVideo_C

V_SVideo_Y

SGND

Q733

R749C759

R748

5V_E

C760

SGND

GYCbCr_Cb

Cb_in#

Q734

R763C762

R761

5V_E

C763

SGND

GYCbCr_CrQ735

R767C765

R765

5V_E

C766

SGND

GYCbCr_Y

Cr_in#

YUV_Y_in#

R768R769R770R771

G_TT_RG_TT_GG_TT_B

G_TT_FSO

R772

R773

R774

R775

SGND

SC2_BOX

SC2_R

SC2_G

SC2_B

R784

R785

R786

SGND

Y2C2V2

Y2

C2

V2

Cb

Cb

Cr

Cr

Y

Y

R787

R790

R721

IN ENS1A S1B S1C S1D

ON Switch0 0

S2A S2B S2C S2D1 0x 1 Disabled

P15V330 Truth Table

A5VA5V

A5V

R791

R792 R793

Q704 Q705

8V_4052

R794

C2V2Y2

D701

5V

D702

5V

D703

5V

D704

5V

D705

5V

D706

R70

R71

R73

R74

R75

R76

R77

R78

R79

R72

AGND

8V_4052

AV_R1

AV_R2

AV_R3

AV_L1

AV_L2

AV_L3

AV_R4

AV_L4 C78

0

C78

1

Audio.Board.BH(M-CH).05.06.14.sch-1 - Tue Aug 16 22:15:14 2005

DUBHE OSD Ver1.1_NAKS.sch-1 - Mon Oct 18 11:47:11 2004

0025.sch-1 - Mon May 16 09:25:50 2005

Basic Operations & Circuit Description

MODULE There are 1 pc. panel and 12 pc.s PCB including 2 pc.s Y/Z Sustainer board, 2 pc.s Y Driveboard, 6 pc.s X Extension boards, 1 pc. Control (Signal Input) and 1 pc. Powerboard in the Module.

SET There are 6 pc.s PCBs including 1 pc. AUX. PSU Board, 1 pc. Keypad board, 1 pc.Remote Control Receiver board, 1 pc. L/R Speakers and 1 pc. Main (Video) board in the SET.

PCB function1. Power:

(1). Input voltage: AC 100V~120V, 45Hz~60Hz.Input range: AC 90V(Min)~265V(Max) auto regulation.

(2). To provide power for PCBs.2. Main (Video InterFace) board: To converter TV signals, S signals, AV signals, Y Pb/

Cb Pr/Cr signals, DVI signals and D-SUB signals to digital ones and to transmit toControl board.

3. Control board: Dealing with the digital signal for output to panel.4. Y-Sustainer / Z-Sustainer board:

(1). Receiving the signals from Control and high voltage supply.(2). Output scanning waveform for Module.

5. Y-Drive board: Receive signal from Y sustainer, output horizontal scanning wave-form to the panel.

6. X extension board (6pcs): Output addressing signals.7. Tuner/Audio Board: : : : : Process and Amplifying the audio signal to speakers and

convert TV RF signal to video/audio signal and send to Main board.

PCB failure analysis

1. CONTROL : a. Abnormal noise on screen. b. No picture.2. MAIN (video) : a. Lacking color, Bad color scale.

b. No voice. c. No picture but with signals output, OSD and back light. d. Abnormal noise on screen.

3. POWER : No picture, no power output.4. Z - Sustainer : a. No picture.

b. Color not enough. c. Flash on screen.

5. Y - Sustainer : Darker picture with signals.

6. X - Extension : Abormal vertical noise on screen. 7. Audio Board or AUX PSU: a. No voice. (Make sure Mute/OFF) .

b. Noise.

Basic operation of Plasma Display 1. After turning on power switch, power board sends 5Vst-by Volt to Micro Processor

2. The micro Processor memorize the last state of Power, When the last state of

power is on or receive power on signal from local Key or Remote control, Micro

Processor will send on control signal to power. Then Power sends (5Vsc, 9Vsc,

24V and RLYON, Vs ON) to PCBs working. This time VIF will send signals to

display Image, OSD on the panel and start to search available signal sources.

If the audio signals input, them will be amplified by Audio AMP and transmitted to

Speakers.

3. If some abnormal signals are detected (for example: over volts, over current, over

temperature and under volts), the system will be shut down by Power off.

Main IC Specifications

- PW181 Image Processor, Scaler - PW1231 Digital Video Signal Processor - VPC 323XD Comb-filter Video Processor - Z86229 NTSC Line 21 CCD decorder - MSP34x0G Multistandard Sound Processor -AD9880 Analog/HDMI Dual Display Interface -PI5V330 Wideband/Video Quad 2-Channel MUX/DEMUX -SM5304AV Video Buffer with Built-in Analog LPF -TDA2616 2 X 12 W hi-fi audio power amplifier with mute -SAA5360 Multi page intelligent teletext decoder -AT24C32 Z-Wire Serial EEPROM -HT48R06A-1 8-Bit Cost-Effective I/O Type MCU

PRELIMINARY / CONFIDENTIAL

PW181Product Specification

General Description The PW181 ImageProcessor is a highly integrated “system-on-a-chip” that interfaces computer graphics and video inputs in virtually any format to a fixed-frequency flat panel display.

Computer and video images from NTSC/PAL to WUXGA at virtually any refresh rate can be resized to fit on a fixed-frequency target display device with any resolution up to WUXGA. Video data from 4:3 aspect ratio NTSC or PAL and 16:9 aspect ratio HDTV or SDTV is supported. Multi-region, nonlinear scaling allows these inputs to be resized optimally for the native resolution of the display.

Advanced scaling techniques are supported, such as format conversion using multiple programmable regions. Three independent image scalers coupled with frame locking circuitry and dual programmable color lookup tables create sharp images in multiple windows, without user intervention.

Embedded SDRAM frame buffers and memory controllers perform frame rate conversion and enhanced video processing completely on-chip. A separate memory is dedicated to storage of on-screen display images and CPU general purpose use.

Advanced video processing techniques are supported using the internal frame buffer, including motion adaptive, temporal deinterlacing with film mode detection. When used in combination with the new third-generation scaler, this advanced video processing technology delivers the highest quality video for advanced displays.

Both input ports support integrated DVI 1.0 content protection using standard DVI receivers.

A new advanced OSD Generator with more colors and larger sizes supports more demanding OSD applications, such as on-screen programming guides. When coupled with the new, faster, integrated microprocessor, this OSD Generator supports advanced OSD animation techniques.

Programmable features include the user interface, custom start-up screen, all automatic imaging features, and special screen effects.

Features• Third-generation, two-dimensional filtering techniques• Third-generation, advanced scaling techniques • Second-generation Automatic Image Optimization• Frame rate conversion• Video processing• On-Screen Display (OSD)• On-chip microprocessor• JTAG debugger and boundary scan • Picture-in-picture (PIP)• Multi-region, non-linear scaling• Hardware 2-wire serial bus support

Applications• Multimedia Displays• Plasma Displays• Digital Television

Device Application PackagePW181-10V Up to XGA Displays

352 PBGAPW181-20V Up to UXGA Displays

Crystal

ROM

DisplayPW181

VideoInput

ADC/TMDS

VideoDecoder

Computer

TV TunerTVSignal

TVSignal ADC/

TMDSComputer

VideoInput

TV Tuner

VideoDecoder

PW181 System Block Diagram

REV. A

Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third parties thatmay result from its use. No license is granted by implication or otherwiseunder any patent or patent rights of Analog Devices.

aAD9883A

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel:

Fax:

110 MSPS/140 MSPS Analog Interface for Flat Panel Displays

FUNCTIONAL BLOCK DIAGRAM

RAIN ROUTA

GAIN GOUTA

BAIN BOUTA

MIDSCV

SYNCPROCESSINGAND CLOCKGENERATION

HSYNC

COAST

CLAMP

FILT

DTACK

HSOUT

VSOUT

SOGOUT

REF REFBYPASS

SERIAL REGISTERAND

POWER MANAGEMENT

SCL

SDA

A0AD9883A

CLAMP8

A/D

CLAMP8

A/D

CLAMP8

A/D

FEATURES

140 MSPS Maximum Conversion Rate

300 MHz Analog Bandwidth

0.5 V to 1.0 V Analog Input Range

500 ps p-p PLL Clock Jitter at 110 MSPS

3.3 V Power Supply

Full Sync Processing

Sync Detect for “Hot Plugging”Midscale Clamping

Power-Down Mode

Low Power: 500 mW Typical

4:2:2 Output Format Mode

APPLICATIONS

RGB Graphics Processing

LCD Monitors and Projectors

Plasma Display Panels

Scan Converters

Microdisplays

Digital TV

GENERAL DESCRIPTIONThe AD9883A is a complete 8-bit, 140 MSPS monolithic analoginterface optimized for capturing RGB graphics signals frompersonal computers and workstations. Its 140 MSPS encoderate capability and full power analog bandwidth of 300 MHzsupports resolutions up to SXGA (1280 × 1024 at 75 Hz).

The AD9883A includes a 140 MHz triple ADC with internal1.25 V reference, a PLL, and programmable gain, offset, andclamp control. The user provides only a 3.3 V power supply,analog input, and Hsync and COAST signals. Three-stateCMOS outputs may be powered from 2.5 V to 3.3 V.

The AD9883A’s on-chip PLL generates a pixel clock from theHsync input. Pixel clock output frequencies range from 12 MHz to

140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS.When the COAST signal is presented, the PLL maintains itsoutput frequency in the absence of Hsync. A sampling phaseadjustment is provided. Data, Hsync, and clock output phaserelationships are maintained. The AD9883A also offers full syncprocessing for composite sync and sync-on-green applications.

A clamp signal is generated internally or may be provided bythe user through the CLAMP input pin. This interface is fullyprogrammable via a 2-wire serial interface.

Fabricated in an advanced CMOS process, the AD9883A isprovided in a space-saving 80-lead LQFP surface-mount plasticpackage and is specified over the 0°C to 70°C temperature range.

8100 SW Nyberg Road

Tualatin, OR 97062 USA

Telephone: 503.612.6700

FAX: 503.612.6713

www.pixelworks.com

PW1231AProduct Specification

GeneralThe PW1231A is a high-quality, digital video signal processor that incorporates Pixelworks’ patented deinterlacing, scaling, and video enhancement algorithms. The PW1231A accepts industry-standard video formats and resolutions, and converts the input into many desired output formats.The highly efficient video algorithms result in excellent quality video.

The PW1231A combines many functions into a single device, including a memory controller, auto-configuration, and others. This high level of integration enables simple, flexible, cost-effective solutions that require fewer components.

Features• Built-In Memory Controller • Motion-Adaptive Deinterlace Processor • Intelligent Edge Deinterlacing • Digital Color/Luminance Transient Improvement (DCTI/DLTI)• Interlaced Video Input Options, including NTSC and PAL • Independent horizontal and vertical scaling• Copy Protection • Two-Wire Serial Interface

Applications: For use with Digital Displays• Flat-Panel (LCD, DLP) TVs• Rear Projection TVs• Plasma Displays• LCD Multimedia Monitors• Multimedia Projectors

NOTE: “L” denotes lead (Pb) free

Device Application PackagePW1231A

PW1231AL Up to XGA 160-pin PQF

PW1231APW1231AL

Crystal

PW1231ASystem Block Diagram SDRAM

VideoDecoderVideo Digital

Output

P/N 001-0097-00 Rev BJuly 2003

PRELIMINARY—CONFIDENTIAL

a

Analog/HDMI Dual Display Interface

Preliminary Datasheet 3/26/2004 AD9880

AD9880 Preliminary Technical Information Analog Devices, Inc., 2004

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O Box 9106, Norwood, MA 02062–9106, USA Tel: 617/329–4700 Fax: 617–326–8703

FEATURES Analog/HDMI Dual Interface Supports High-Bandwidth Digital Content Protection RGB to YCbCr two-way color conversion Automated clamping level adjustment 1.8/3.3V Power Supply 100-pin LQFP Pb-Free Package RGB and YCbCr Output Formats

Analog Interface 8-bit Triple Analog to Digital Converters 150 MSPS Maximum Conversion Rate Macrovision Detection 2:1 Input Mux Full Sync Processing Sync Detect for “Hot Plugging” Mid-Scale Clamping

Digital Video Interface HDMI 1.0, DVI 1.0 150 MHz HDMI Receiver Supports High-Bandwidth Digital Content Protection (HDCP 1.1)

Digital Audio Interface HDMI 1.0 compatible audio interface S/PDIF (IEC90658 compatible) digital audio output Multi-channel I2S audio output (up to 8 channels)

APPLICATIONS Advanced TV HDTV Projectors LCD Monitor

FUNCTIONAL BLOCK DIAGRAM

DATACKDE

VsyncHsync

SyncProcessing and

ClockGeneration

DATACK2

Serial Register andPower Management

Ref

HSOUTVSOUTSOGOUT

HDMI Receiver

RX0+RX0-RX1+RX1-RX2+RX2-

RXC+RXC-RTERM

SCLSDA

Analog Interface

Digital Interface

REFOUTREFIN

Clamp A/DR/G/B or YPbPrIN0 2:1

MUXR/G/B or YPbPrIN1

COASTCLAMPCKINVCKEXTFILT

HSYNC 0HSYNC 1

2:1MUX2:1

MUX

SOGIN 1SOGIN 0

HSYNC 0HSYNC 1

2:1MUX

SPDIF OUT8 ChannelI2S OUT

2

MCLKLRCLK

HDCP

MCLMDA

DDCSCLDDCSDA

2 DATACK

HSOUTVSOUT

SOGOUTDE

MU

XES

RG

BYC

bCrM

atrix

R/G/B 8X3or YCbCr

R/G/B 8X3or YCbCr

R/G/B 8X3YCbCr (4:2:2or 4:4:4)

AD9880

/A0

GENERAL DESCRIPTION The AD9880 offers designers the flexibility of an analog interface and High-Definition Multimedia Interface (HDMI) receiver integrated on a single chip. Also included is support for High bandwidth Digital Content Protection (HDCP). Analog Interface The AD9880 is a complete 8-bit 150 MSPS monolithic analog interface optimized for capturing Component Video (YPbPr) and RGB graphics signals. Its 150 MSPS encode rate capability and full power analog bandwidth of 300 MHz supports all HDTV formats (up to 1080p) and FPD resolutions up to SXGA (1280 x 1024 at 75 Hz). The analog interface includes a 150 MHz triple ADC with internal 1.25V reference, a Phase Locked Loop (PLL), and programmable gain, offset, and clamp control. The user provides only 1.8V and 3.3V power supply, analog input, and Hsync. Three-state CMOS outputs may be powered from 1.8V to 3.3V. The AD9880’s on-chip PLL generates a pixel clock from Hsync. Pixel clock output frequencies range from 12 MHz to 150 MHz.

PLL clock jitter is typically less than 500 ps p-p at 150 MHz. The AD9880 also offers full sync processing for composite sync and Sync-on-Green (SOG) applications. Digital Interface The AD9880 contains a HDMI 1.0 compatible receiver and supports all HDTV formats (up to 1080p) and display resolutions up to SXGA (1280 x 1024 at 75 Hz). The receiver features an intra-pair skew tolerance of up to one full clock cycle. With the inclusion of HDCP, displays may now receive encrypted video content. The AD9880 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission as specified by the HDCP 1.1 protocol. Fabricated in an advanced CMOS process, the AD9880 is provided in a space-saving 100-lead LQFP surface-mount plastic package and is specified over the 0 ºC to 70 ºC temperature range.

PRELIMINARY DATA SHEET VPC 323xD

Micronas

Comb Filter Video Processor

1. Introduction

The VPC 323xD is a high-quality, single-chip videofront-end, which is targeted for 4:3 and 16:9, 50/60-Hzand 100/120 Hz TV sets. It can be combined with othermembers of the DIGIT3000 IC family (such asDDP 331x) and/or it can be used with 3rd-party prod-ucts.

The main features of the VPC 323xD are

– high-performance adaptive 4H comb filter Y/C sepa-rator with adjustable vertical peaking

– multi-standard color decoder PAL/NTSC/SECAM including all substandards

– four CVBS, one S-VHS input, one CVBS output

– two RGB/YCrCb component inputs, one Fast Blank (FB) input

– integrated high-quality A/D converters and associ-ated clamp and AGC circuits

– multi-standard sync processing

– linear horizontal scaling (0.25 ... 4), as well as non-linear horizontal scaling ‘Panoramavision’

– PAL+ preprocessing

– line-locked clock, data and sync, or 656-output interface

– peaking, contrast, brightness, color saturation and tint for RGB/ YCrCb and CVBS/S-VHS

– high-quality soft mixer controlled by Fast Blank

– PIP processing for four picture sizes ( , or of normal size) with 8-bit resolution

– 15 predefined PIP display configurations and expert mode (fully programmable)

– control interface for external field memory

– I2C-bus interface

– one 20.25-MHz crystal, few external components

– 80-pin PQFP package

1.1. System Architecture

Fig.1–1 shows the block diagram of the video proces-sor

Fig. 1–1: Block diagram of the VPC 323xD

14---

19---

116------, ,

136---

MixerCIN

VIN1

VIN2

VIN3

VIN4

VOUT

AdaptiveComb

ColorDecoder

OutputFormatter

Matrix

Filter

2D Scaler

PanoramaMode

PIP

ITU-R 656ITU-R 601

MemoryControl

Sync

AGC

ContrastSaturationBrightness

Tint

NTSCPAL

NTSCPAL

SECAM

+ Clock

Generation

CrCbOUT

Y OUT

YCOE

FIFOCNTL

H Sync

V Sync

AVO

I2C Bus20.25 MHz

RGB/

FB

Y

Cb

Cr

Y

Cb

Cr

Y/G

U/B

Y

Cb

Cr

LL Clock

SaturationTint

AnalogFront-end

ContrastBrightnessPeaking

ClockGen.

I2C Bus

V/R

FB FB

YCrCb

RGB/YCrCb

2×ADC

AnalogComponentFront-End

4 x ADC

Processing

• Complete Stand-Alone Line 21 Decoder for Closed-Captioned and Extended Data Services (XDS)

• Preprogrammed to Provide Full Compliance withEIA–608 Specifications for Extended Data Services

• Automatic Extraction and Serial Output of SpecialXDS Packets (Time of Day, Local Time Zone, andProgram Blocking)

• Programmable XDS Filter for a Specific XDS Packet

• Cost-Effective Solution for NTSC Violence Blockinginside Picture-in-Picture (PiP) Windows

• Minimal Communications and Control Overhead Pro-vide Simple Implementation of Violence Blocking,Closed Captioning, and Auto Clock Set Features

• Programmable, On-Screen Display (OSD) for Creat-ing Full Screen OSD or Captions inside a Picture-in-Picture (PiP) Window

• User-Programmable Horizontal Display Position foreasy OSD Centering and Adjustment

• I2C Serial Data and Control Communication

• Supports 2 Selectable I2C Addresses

Capable of processing Vertical Blanking Interval (VBI)data from both fields of the video frame in data, the Z86229Line 21 Decoder offers a feature-rich solution for any tele-vision or set-top application. The robust nature of theZ86229 helps the device conform to the transmission formatdefined in the Television Decoder Circuits Act of 1990, andin accordance with the Electronics Industry Associationspecification 608 (EIA–608).

The Line 21 data stream can consistof data from several datachannels multiplexed together. Field 1 consists of four datachannels: two Captions and two Texts. Field 2 consists offive additional data channels: two Captions, two Texts, andExtended Data Services (XDS). The XDS data structure is

defined in EIA–608. The Z86229 can recover and displaydata transmitted on any of these nine data channels.

The Z86229 can recover and output to a host processor viathe I2C serial bus. The recovered XDS data packet is furtherdefined in the EIA–608 specification. The on-chip XDS fil-ters in the Z86229 are fully programmable, enabling recov-ery of only those XDS data packets selected by the user. Thisfunctionality allows the device to extract the required XDSinformation with proper XDS filter setup for compatibilityin a variety of TVs, VCRs, and Set-Top boxes.

In addition, the Z86229 is ideally suited to monitor Line 21video displayed in a PiP window for violence blocking,CCD, and other XDS data services. A block diagram of theZ86229 is illustrated in Figure 1.

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PRELIMINARY DATA SHEET MSP 34x0G

Micronas

Multistandard Sound Processor Family

Release Note: Revision bars indicate significantchanges to the previous edition. The hardware andsoftware description in this document is valid forthe MSP 34x0G version B8 and following versions.

1. Introduction

The MSP 34x0G family of single-chip MultistandardSound Processors covers the sound processing of allanalog TV-Standards worldwide, as well as the NICAMdigital sound standards. The full TV sound processing,starting with analog sound IF signal-in, down to pro-cessed analog AF-out, is performed on a single chip.Figure 1–1 shows a simplified functional block diagramof the MSP 34x0G.

This new generation of TV sound processing ICs nowincludes versions for processing the multichannel tele-vision sound (MTS) signal conforming to the standardrecommended by the Broadcast Television SystemsCommittee (BTSC). The DBX noise reduction, or alter-natively, Micronas Noise Reduction (MNR) is per-formed alignment free.

Other processed standards are the Japanese FM-FMmultiplex standard (EIA-J) and the FM Stereo Radiostandard.

Current ICs have to perform adjustment procedures inorder to achieve good stereo separation for BTSC andEIA-J. The MSP 34x0G has optimum stereo perfor-mance without any adjustments.

All MSP 34xxG versions are pin compatible to theMSP 34xxD. Only minor modifications are necessaryto adapt a MSP 34xxD controlling software to theMSP 34xxG. The MSP 34x0G further simplifies con-trolling software. Standard selection requires a singleI2C transmission only.

The MSP 34x0G has built-in automatic functions: TheIC is able to detect the actual sound standard automat-ically (Automatic Standard Detection). Furthermore,pilot levels and identification signals can be evaluatedinternally with subsequent switching between mono/stereo/bilingual; no I2C interaction is necessary (Auto-matic Sound Selection).

The MSP 34x0G can handle very high FM deviationseven in conjunction with NICAM processing. This isespecially important for the introduction of NICAM inChina.

The ICs are produced in submicron CMOS technology.The MSP 34x0G is available in the following packages:PLCC68 (not intended for new design), PSDIP64,PSDIP52, PQFP80, and PLQFP64.

Fig. 1–1: Simplified functional block diagram of the MSP 34x0G

So

urc

e S

elec

t

Loud-

SCART1

SCART2

SCART1

SCART2

SCART4

SCART3

MONO

De-modulator

HeadphoneHeadphone

I2S

SoundProcessing

speakerSound

Processing

DAC

DAC

ADC

Loud-

DAC

DACADC

Subwoofer

SCARTDSP Input Select

Pre-processing

SCART Output Select

Prescale

PrescaleI2S1

I2S2

Sound IF1

Sound IF2

speaker

PS7032C 08/07/971

Functional Block Diagram

1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012

Product Features:• High-performance, low-cost solution to switch

between video sources• Wide bandwidth: 200 MHz• Low ON-resistance: 3Ω• Low crosstalk at 10 MHz: –58 dB• Ultra-low quiescent power (0.1 µA typical)• Single supply operation: +5.0V• Fast switching: 10 ns• High-current output: 100 mA• Packages available:

– 16-pin 300-mil wide plastic SOIC (S)– 16-pin 150-mil wide plastic SOIC (W)– 16-pin 150-mil wide plastic QSOP (Q)

PI5V330

Low ON Resistance Wideband/VideoQuad 2-Channel MUX/DEMUX

Product Description:Pericom Semiconductor’s PI5V series of mixed signal videocircuits are produced in the Company’s advanced CMOSlow-power technology, achieving industry leading perfor-mance.

The PI5V330 is a true bidirectional Quad 2-channelmultiplexer/demultiplexer that is recommended for bothRGB and composite video switching applications. TheVideoSwitch™ can be driven from a current outputRAMDAC or voltage output composite video source.

Low ON-resistance and wide bandwidth make it ideal forvideo and other applications. Also this device has exception-ally high current capability which is far greater than mostanalog switches offered today. A single 5V supply is all thatis required for operation.

The PI5V330 offers a high-performance, low-cost solutionto switch between video sources. The application sectiondescribes the PI5V330 replacing the HC4053 multiplier andbuffer/amplifier.

EN IN ON Switch

0 0 S1A, S1B, S1C, S1D

0 1 S2A, S2B, S2C, S2D

1 X Disabled

Truth Table

Pin Name Description

S1A, S2A Analog Video I/OS1B, S2B

S1C, S2C

S1D, S2D

IN Select Input

EN Enable

DA, DB, Analog Video I/ODC, DD

GND Ground

VCC Power

Product Pin Description

16-Pin Product Configuration

IN

S1A

S2A

DA

S1B

S2B

DB

GND

VCC

EN

S1D

S2D

DD

S1C

S2C

DC

12345678

161514131211109

16-PINQ16S16W16

DAS1A

S2A

DBS1B

S2B

DCS1C

S2C

DDS1D

S2D

DECODER/DRIVERS

EN IN

ethabella

Text Box

ethabella

Text Box

ethabella

Text Box

ethabella

Text Box

1

Features• Low-Voltage and Standard-Voltage Operation

– 5.0 (VCC = 4.5V to 5.5V)– 2.7 (VCC = 2.7V to 5.5V)– 2.5 (VCC = 2.5V to 5.5V)– 1.8 (VCC = 1.8V to 5.5V)

• Low-Power Devices (ISB = 2=µA @ 5.5V) Available• Internally Organized 4096 x 8, 8192 x 8• 2-Wire Serial Interface• Schmitt Trigger, Filtered Inputs for Noise Suppression• Bidirectional Data Transfer Protocol • 100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Clock Rate• Write Protect Pin for Hardware Data Protection• 32-Byte Page Write Mode (Partial Page Writes Allowed)• Self-Timed Write Cycle (10 ms max)• High Reliability

– Endurance: 1 Million Write Cycles – Data Retention: 100 Years– ESD Protection: >3,000V

• Automotive Grade and Extended Temperature Devices Available• 8-Pin JEDEC PDIP, 8-Pin JEDEC SOIC, 8-Pin EIAJ SOIC,

and 8-pin TSSOP Packages

DescriptionThe AT24C32/64 provides 32,768/65,536 bits of serial electrically erasable and pro-grammable read only memory (EEPROM) organized as 4096/8192 words of 8 bitseach. The device’s cascadable feature allows up to 8 devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applica-tions where low power and low voltage operation are essential. The AT24C32/64 isavailable in space saving 8-pin JEDEC PDIP, 8-pin JEDEC SOIC, 8-pin EIAJ SOIC,and 8-pin TSSOP (AT24C64) packages and is accessed via a 2-wire serial interface.In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V),2.5V (2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions.

2-WireSerial EEPROM32K (4096 x 8)

64K (8192 x 8)

AT24C32AT24C64

Rev. 0336G–04/01

2-Wire, 32K Serial E2PROM

Pin ConfigurationsPin Name Function

A0 - A2 Address Inputs

SDA Serial Data

SCL Serial Clock Input

WP Write Protect

8-Pin PDIP

1234

8765

A0A1A2

GND

VCCWPSCLSDA

8-Pin SOIC

1234

8765

A0A1A2

GND

VCCWPSCLSDA

8-Pin TSSOP

1234

8765

A0A1A2

GND

VCCWPSCLSDA

AT24C32/642

Block Diagram

Pin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positiveedge clock data into each EEPROM device and negativeedge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional forserial data transfer. This pin is open-drain driven and maybe wire-ORed with any number of other open-drain or opencollector devices.

DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1and A0 pins are device address inputs that are hard wiredor left not connected for hardware compatibility withAT24C16. When the pins are hardwired, as many as eight32K/64K devices may be addressed on a single bus sys-tem (device addressing is discussed in detail under the

Device Addressing section). When the pins are not hard-wired, the default A2, A1, and A0 are zero.

WRITE PROTECT (WP): The write protect input, when tiedto GND, allows normal write operations. When WP is tiedhigh to VCC, all write operations to the upper quandrant(8/16K bits) of memory are inhibited. If left unconnected,WP is internally pulled down to GND.

Memory OrganizationAT24C32/64, 32K/64K SERIAL EEPROM: The 32K/64K isinternally organized as 256 pages of 32 bytes each. Ran-dom word addressing requires a 12/13 bit data wordaddress.

Absolute Maximum Ratings*Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Storage Temperature ..................................... -65°C to +150°C

Voltage on Any Pinwith Respect to Ground .....................................-1.0V to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

HT48R06A-1/HT48C06

8-Bit Cost-Effective I/O Type MCU

Block Diagram

Rev. 1.30 1 August 7, 2003

General Description

The HT48R06A-1/HT48C06 are 8-bit high perfor-

mance, RISC architecture microcontroller devices spe-

cifically designed for cost-effective multiple I/O control

product applications. The mask version HT48C06 is

fully pin and functionally compatible with the OTP ver-

sion HT48R06A-1 device.

The advantages of low power consumption, I/O flexibil-

ity, timer functions, oscillator options, HALT and

wake-up functions, watchdog timer, buzzer driver, as

well as low cost, enhance the versatility of these devices

to suit a wide range of application possibilities such as

industrial control, consumer products, subsystem con-

trollers, etc.

Features

Operating voltage:

fSYS=4MHz: 2.2V~5.5V

fSYS=8MHz: 3.3V~5.5V

13 bidirectional I/O lines

An interrupt input shared with an I/O line

8-bit programmable timer/event counter with over-

flow interrupt and 8-stage prescaler

On-chip crystal and RC oscillator

Watchdog Timer

102414 program memory ROM

648 data memory RAM

Buzzer driving pair and PFD supported

HALT function and wake-up feature reduce power

consumption

Up to 0.5s instruction cycle with 8MHz system clock

at VDD=5V

Allinstructionsinoneortwomachinecycles

14-bit table read instruction

Two-level subroutine nesting

Bit manipulation instruction

63 powerful instructions

Low voltage reset function

16-pin SSOP package

18-pin DIP/SOP package

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Pin Assignment

Pad Assignment

HT48C06

* The IC substrate should be connected to VSS in the PCB layout artwork.

HT48R06A-1/HT48C06

Rev. 1.30 2 August 7, 2003

1

2

3

"

"

4

2

1

3

3

1

2

4

5

2

1

3

5

3

1

2

4

1

2

3

"

6 7 8

3

1 2 4 5

3 1 2 4

"

"

2

1

3

Pad Description

Pad Name I/O Options Description

PA0~PA7 I/OPull-high*

Wake-up

Bidirectional 8-bit input/output port. Each bit can be configured as wake-up

input by options. Software instructions determine the CMOS output or

Schmitt trigger input with a pull-high resistor (determined by pull-high op-

tions).

PB0/BZ

PB1/BZ

PB2

I/OPull-high*

I/O or BZ/BZ

Bidirectional 3-bit input/output port. Software instructions determine the

CMOS output or Schmitt trigger input with a pull-high resistor (determined by

pull-high options).

The PB0 and PB1 are pin-shared with the BZ and BZ, respectively. Once the

PB0 and PB1 are selected as buzzer driving outputs, the output signals come

from an internal PFD generator (shared with a timer/event counter).

VSS Negative power supply, ground

PC0/INT

PC1/TMRI/O Pull-high*

Bidirectional I/O lines. Software instructions determine the CMOS output or

Schmitt trigger input with a pull-high resistor (determined by pull-high op-

tions). The external interrupt and timer input are pin-shared with the PC0 and

PC1, respectively. The external interrupt input is activated on a high to low

transition.

RES I Schmitt trigger reset input. Active low

VDD Positive power supply

OSC1

OSC2

I

O

Crystal

or RC

OSC1, OSC2 are connected to an RC network or Crystal (determined by op-

tions) for the internal system clock. In the case of RC operation, OSC2 is the

output terminal for 1/4 system clock.

* All pull-high resistors are controlled by an option bit.

Absolute Maximum Ratings

Supply Voltage ...........................VSS0.3V to VSS+6.0V Storage Temperature ............................50C to 125C

Input Voltage..............................VSS0.3V to VDD+0.3V Operating Temperature...........................40C to 85C

Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those

listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-

ity.

HT48R06A-1/HT48C06

Rev. 1.30 3 August 7, 2003

D.C. Characteristics Ta=25C

Symbol ParameterTest Conditions

Min. Typ. Max. UnitVDD Conditions

VDD Operating Voltage fSYS=4MHz 2.2 5.5 V

fSYS=8MHz 3.3 5.5 V

IDD1 Operating Current (Crystal OSC)3V

No load, fSYS=4MHz 0.6 1.5 mA

5V 2 4 mA

IDD2 Operating Current (RC OSC)3V

No load, fSYS=4MHz 0.8 1.5 mA

5V 2.5 4 mA

IDD3 Operating Current (Crystal OSC) 5V No load, fSYS=8MHz 3 5 mA

ISTB1 Standby Current (WDT Enabled)3V

No load, system HALT 5 A

5V 10 A

ISTB2 Standby Current (WDT Disabled)3V

No load, system HALT 1 A

5V 2 A

VIL1Input Low Voltage for I/O Ports,

TMR and INT 0 0.3VDD V

VIH1Input High Voltage for I/O Ports,

TMR and INT 0.7VDD VDD V

VIL2 Input Low Voltage (RES) 0 0.4VDD V

VIH2 Input High Voltage (RES) 0.9VDD VDD V

VLVR Low Voltage Reset LVRenabled 2.7 3.0 3.3 V

IOL I/O Port Sink Current3V

VOL=0.1VDD

4 8 mA

5V 10 20 mA

IOH I/O Port Source Current3V

VOH=0.9VDD

2 4 mA

5V 5 10 mA

RPH Pull-high Resistance3V 40 60 80 k

5V 10 30 50 k

HT48R06A-1/HT48C06

Rev. 1.30 4 August 7, 2003

PDP PANELCAUTION1. BEFORE SERVICING THE PDP MODULE,

READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

2. WHEN REPLACEMENT PARTS ARE REQUIRED, BE SURE TO USEREPLACEMENT PARTS SPECIFIED BY THE MANUFACTURER..

MODEL : PDP42X2####

Eng

lish

ConfidentialPage 0/40Revision No. 00 10 /OCT / 2004

SPECIFICATIONFOR

APPROVAL

( ) Preliminary Specification( ) Final Specification

Title PDP42X2#### (42” PDP MODULE)

Please return 1 copy with your signature and comments for our confirmation.

Customer NAKS

Model Name

Part No.

Signature Date

Approved by

Reviewed by

Prepared by

Supplier LG Electronics Inc.

Model Name PDP42X2#000

Part No.

Signature Date

PDP Engineering DepartmentPDP Division LG Electronics Inc.

Approved byG.S. Lim/G.Manager

Agreed byJ.Y.Kim

/

/

/

Reviewed byJ.S. Lee

Prepared byJ.H.Yeom

Reviewed byTed. Lee /

ConfidentialPage 7/40Revision No. 00 10 /OCT / 2004

1. GENERAL DESCRIPTION

DESCRIPTIONThe PDP42X2#### 42-inch 16:9 color plasma display module with resolution of 1024(H)× 768(V) pixels.This is the display device which offers vivid colors with adopting AC plasma technology by LG Electronics Inc.

FEARURESHigh peak brightness (1000cd/m2 Typical) and high contrast ratio (5000:1 Typical) enables user to create high performance PDP SETs.

APPLICATIONS

General television systemsPublic information displayVideo conference systemsEducation and training systems

ConfidentialPage 8/40Revision No. 00 10 /OCT / 2004

ELECTRICAL INTERFACE OF PLASMA DISPLAYThe PDP42X2#### requires 8bits or 10bits of digital video signals for each RGB color. In addition to the video signals, six different DC voltages are required to operate the display. The PDP42X2#### is equipped with P-CUBE function which analyzes display signals to optimize system control factor for showing the best display performance.

2ndpixelcolumn

GENERAL SPECFICATIONS

Model NameNumber of PixelsPixel PitchCell PitchDisplay Area Outline Dimension Pixel Type Number of Gradations Weight

Aspect RatioPeak BrightnessContrast Ratio

Power ConsumptionExpected Life-time

: PDP42X2#### (42X2#### Model): 1024(H) × 768(V) (1pixel=3 RGB cells) : 900 (H) × 676 (V): 300 (H) × 676 (V) (Green Cell basis): 920.1(H) × 518.4(V) ±0.5mm: 1005(H) × 597(V) × 61.2(D)±1mm: RGB Closed type : (R)1024 × (G)1024 × (B)1024 : 16.1 Kg ± 0.5 Kg (Net 1EA)

109 Kg ± 5 Kg (5EA/1BOX): 16:9: Typical 1000cd/ (1/100 White Window): Average 60:1 (In a bright room with 150Lux at center): Typical 5000:1 (In a dark room 1/100 White Window pattern at center): Typical 300 W (Full White), Max.330W: more than 60,000 Hours of continuous operation

Life-time is defined as the time when the brightness level becomes half of its initial value.

Pixel Pitch(width) Cell Widthpixel

cell

1stpixelcolumn

1023thpixelcolumn

1024thpixelcolumn

pitc

h(he

ight

)

1st pixelrow2nd pixelrow

3rd pixelrow

767th pixelrow

768th pixelrow

R:0.28G:0.30B:0.32

0..900

0.67

6

BGR BGR

BGR BGR

BGR BGR

BGR BGR

BGR BGR

BGR BGR

BGR BGR

BGR BGR

BGR BGR

BGR BGR

Display Dot Diagram

NO

1

2

3

4

5

6

7

Part No.

6871QCH038A

6871QDH068A

6871QDH069A

6871QYH030A

6871QZH034A

6871QLH037A

6871QRH043A

PWB(PCB) ASSY

PWB(PCB) ASSY

PWB(PCB) ASSY

PWB(PCB) ASSY

PWB(PCB) ASSY

PWB(PCB) ASSY

PWB(PCB) ASSY

Description

LVDS CTRL B/D ASSY

Y DRV UPPER B/D ASSY

Y DRV LOWER B/D ASSY

Y SUS B/D ASSY

Z SUS B/D ASSY

X LEFT B/D ASSY

X RIGHT B/D ASSY

En

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Ⅰ. Formation and Specification of Module

- 5 -

External Cable Connection

NO

1

2

3

4

Connector

P151[Z SUS B/D]

P151[Y SUS B/D]

P300[CTRL B/D]

P201[CTRL B/D]

Input Voltage & Signal

5V, Va, Vs

5V, Va, Vs

5V

Video Signal

En

glis

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- 19 -

Ⅳ. Block Diagram

Input Signal: Full WhiteCurrent(typ.): rms

En

glis

h

- 9 -

1. Checking for no Picture

A screen doesn’t display at all and condition of black pattern or power off.

(1) Check whether the CTRL B/D LED(D1, D14) is turned on or not.(2) Check the power and signal cable of CTRL B/D.(3) X B/D, Y B/D, Z B/D is well plugged in.(4) Check the connection of X B/D, Y B/D and Z B/D to CTRL B/D. (5) Measure the output wave of X, Y, Z B/D with oscilloscope(more than 200MHz)

and find the trouble of B/D by comparing the output wave with below figure.- Measure Point fo Y B/D : TP(Bead B1) - Measure Point fo Z B/D : TP(Bead B1)

(6) Check the SCAN(Y side) IC(7) Check the DATA(X side) TCP IC(8) Replace the CTRL B/D.

Ⅲ. Trouble Shooting

<A: Y B/D Output wave - 1 FRAME>

<B: Y B/D Output wave - 1 SF>

<A: Y B/D Output wave - 1 FRAME>

<B: Y B/D Output wave - 2, 3, 4 SF>

- 10 -

<A: Y B/D Output wave - 1Frame>

<B: Y B/D Output wave - 5~10 SF>

<A: Z B/D Output wave - 1Frame>

<B: Z B/D Output wave - 1~10 SF>

<X B/D Output wave - 1 FRAME>

<X B/D Output wave - 1 SF>

<X B/D Output wave - Enlargement>

En

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h

2. Hitch Diagnosis FollowingDisplay Condition

2-1. 1/2 of the screen is not turned on

(1) Confirm the power connection of X B/D is well plugged inwhich is correspond to not showing screen.

(2) Confirm the power connector that is connected betweenCTRL B/D and X B/D correspond to not showing part.

(3) Replace relevant X B/D. When replace X B/D, TCP shouldhave been connected accurately, it confirms certainly.

[[ Relationship between screen and X B/D

Screen X B/D Left of the Screen 1/2 <--> Right X B/DRight of the Screen 1/2 <--> Left X B/D

[[ Screen Display Form

[[ 1/4 of the screen doesn’t be shownEquality with 2-1

2-2. The screen doesn’t be shown as DataTCP

(Include not be shown part of Data COF quantity or a part)

(1) Replace the cable between the CTRL B/D and X B/D,when there is not change, replace the CTRL B/D.

(2) Check the Data TCP of point screen does not come out isfail and when it is not problem, connect again withcorrespondence TCP.

(3) In case of fail the correspondence Data TCP, replace theModule.

[[ Example of the screen display form(Anything of the 16 Data TCP can be shown beside belowpictures)

- 11 -

Left of the Screen(1/2) Right of the Screen(1/2)

Display

Not display

: All : Partial : not at all

2-3. It Generates Unusual Pattern of DataTCP IC unit

(1) In case of line shape or dotted line occurs, check the screwon X B/D and make sure it is tight. When the there is notchange, replace the X B/D.

(2) In case of <case 1>- confirm the connection of Data TCP connector - Replace relevant XB/D or CTRL B/D

(3) In case of <case 2, 3> - confirm the connector that is connected from CTRL B/D torelevant X B/D - Replace relevant XB/D or CTRL B/D

[[ Screen Display Form

2-4. The screen display has a problem for Scan FPC.

(1) It may be a problem between Scan FPC and Y DRVB/D.(2) Check the connection of Y DRV B/D and Scan FPC.(3) If the Scan IC is failed, replace the Y DRV B/D.

(Check the compatibility)

[[ Screen Display Form

[[ Check a method of SCAN IC

Change the Vpp Pin into ANODE and GND Pin into CATHODand then test the Diode with forward or reverse direction.

- 12 -

Unusual screen comes out about one IC quantity in one COF

Unusual screen comes out as a unit of Data COF IC through one X B/D

Unusual screen comes out as a unit of Data COF IC through Top or Bottom screen

<Case 1>

<Case 2>

<Case 3>

1/12 of screen

The screen display is very good

The screen display is poor

En

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2-5. The screen has a vertical line withregular gap.

(A vertical stripe flash at especial color)

(1) This problem comes from Control B/D.(2) Replace Control B/D.

[[ Screen Display Form

2-6. A data copy is happened into vertical direction

(1) In this case, it’s due to incorrect marking of scan wave. (2) Replace a Y DRV B/D or Y SUS B/D.

[[ Screen Display Form

2-7. The screen has one or several verticalline

(1) In this case, It isn’t a problem about controller B/D or XB/D.

(2) It may cause followings. - It’s out of order a panel- Open or short of DATA TCP FPC attached panel- DATA TCP attached on panel is out of order

(3) Replace Module.

[[ Screen Display Form

2- 8. The screen has one or several horizontal line

(1) In this case, it isn’t a problem about controller B/D or XB/D.

(2) It may cause followings. - It’s out of order a panel- Open or short of SCAN FPC attached panel- SCAN FPC attached on panel is out of order.

(3) Replace Module.

[[ Screen Display Form

- 13 -

The screen has a vertical line with regular gap

<Case 1 : Entire Copy><Display Pattern>

<Case 2 : Top Copy> <Case 3 : Bottom Copy> <Case 4 : Entire Copy>

It may show several vertical lines in a quarter or other division part of screen including left case.

It may be shown on several horizontal lines including left case.

※Vsetup = 80±1V @42X2##2# Module

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3-2. FET Ass’y(Y B/D: HS11, 51, 91) damage

(1) When Set_Up FET is damaged, screen doesn’t be shown O Test Point: Enlarge the after measuring GND~B1(Y B/D) O Waveform state: As shown (Fig. 2)

(2) When Set_Down FET/Pass_Top FET is damaged, misdischarge of entire screen is generated. O Test Point: Enlarge the after measuring GND~B1(Y B/D) O Waveform state: As shown (Fig. 3)

(3) When Ramp FET is damaged O Test Point: Enlarge the after measuring GND~B1(Y B/D) O Waveform state: As shown (Fig. 4)

O Measurement position: Reset section enlargement waveof TP B1(Y B/D) (Full White Pattern)

Set Up waveformdoes not come out

- 15 -

(Fig. 2) When the Set_Up FET is damaged

Set Down waveformdoes not come out

(Fig. 3) When the Set_Down FET is damaged

(Fig. 4) When the Ramp FET is damaged

<FET Ass’y Normal Output Waveform >

※Vsc = 120V @ 42X2##2# Moduel

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- 17 -

3-4. TCP damage

(1) In case of shorting or opening of IC output of TCP severalvertical lines occured.O Test Point: Enlarge the after measuring output TP of

GND~TCP.O Waveform state: As shown Output of (Fig. 8)

In case of normal wave output, when STB signal isapplied, STB signal remains High. And when STB signalis applied again, it must be fall Low.But when TCP IC is bad, even STB signal is notgenerated, Output falls to Low.

[ Since the output TP of TCP is covered with SR, whenmeasurement is needed, remove the SR, measures. Andafter measuring insulates TCP leads with insulation tape.

(2) In case of being damaged on TCP IC, the screen doesn’tbe shown or happens discharge partially. When IC failoccurs, it will be able to discover the trace which is burned.O Test Point: Enlarge the after measuring output TP of

GND~TCPO Waveform state: Output wave doesn’t come out

O Measurement position: Enlarge the after measuringoutput TP of TCP (Full White Pattern)

3-5. Crystal(CTRL B/D: X2) damage

(1) When Crystal is damaged, the screen doesn’t be turnedon.O Test Point: Measuring 3pin of GND~Crystal(Ctrl B/D: X2)O Waveform state: Output wave doesn’t come out

(2) In case of unusual launch of the Crystal, it may blink thescreen.O Waveform state: As shown (Fig. 9)

O Measurement position: Measuring output 3pin ofCrystal(X2: 100MHz) on Ctrl B/D (Full White Pattern)

(Fig. 8) When IC output of TCP is poor

<TCP Normal Output Wave >

Output voltage of the signal is dropped

(Fig. 9) When Crystal is bad

<Crystal Normal Output Waveform >

Use B/D applicated SN755870 TOP:6871QDH090BBTM:6871QDH091B

Digital PDP Division, LG Electronics Inc. NO : P04#C-###

Product Specification of PDP Module

ConfidentialPage 33/40Revision No. 00 10 /OCT / 2004

6. OUTLINE DRAWINGFront View

ConfidentialPage 34/40Revision No. 00 10 /OCT / 2004

Rear View

PDP42X2##4#

For gap+pad apply Model6871QZH047CZ B/D ASSY2005.05.2517

PDP42X2##3#

For Ctrl LVDS out Model6871QZH071CCTRL B/D ASSY(LVDS Out)2005.06.2218

PDP42X2##4#

For gap+pad apply Model6871QYH042CY SUS B/D ASSY2005.05.2516

Initial Product6871QGH037AX LEFT B/D ASSY2004.06.177

Initial Product6871QDH068AYDRV UPPER B/D ASSY2004.06.172

To improve the EMI6871QZH034CZ B/D ASSY2004.12.0510

PDP42X2##2#

42X2A initial Product6871QDH091BYDRV LOWER B/D ASSY2005.03.0713

Initial Product6871QCH038ACTRL B/D ASSY(LVDS)2004.06.171

PDP42X2##2#

42X2A initial Product6871QYH042BY SUS B/D ASSY2005.03.0714

PDP42X2##2#

42X2A initial Product6871QZH047BZ B/D ASSY2005.03.0715

PDP42X2##2#

42X2A initial Product6871QDH090BYDRV UPPER B/D ASSY2005.03.0712

Initial Product6871QZH034AZ B/D ASSY2004.06.175

Initial Product6871QDH069AYDRV LOWER B/D ASSY2004.06.173

PDP42X2##2#

42X2A initial Product6871QCH060BCTRL B/D ASSY(LVDS)2005.01.1811

To improve the EMI6871QYH030CY SUS B/D ASSY2004.12.059

To improve the Scan Noise

6871QDH068BYDRV UPPER B/D ASSY2004.12.058

Initial Product6871QRH043AX RIGHT B/D ASSY2004.06.176

Initial Product6871QYH030AY SUS B/D ASSY2004.06.174

NotePart NumberBoardDateNo.

- 20 -

Ⅴ. Records of Revision for Boards,components and ROM DATA

1. Boards

Apply to 42X2A Model

0ILNRTI020BScan IC(SN755870)2005.06.2213

Apply to 42X2A Model

6007QD0018BTCP_13Pf(NEC160300)2005.06.2212

For Pb_free4921QP1027PY IPM (IC81)2005.06.2210

For Pb_free4921QP1028PZ IPM (IC81)2005.06.2211

Initial Product6007QD0007ATCP2004.06.176

Initial Product4921QP1028AZ IPM (IC81)2004.06.172

Apply to 42X2A Model

4921QF2002BY Vsetup Fet Assy(HS51)2005.05.179

Initial Product4921QP1027AY IPM (IC81)2004.06.171

Initial Product0ILNRDI001ACrystal2004.06.175

Initial Product4921QF3002AY Path FET Ass’y(HS91)2004.06.173

Apply to 42X2A Model

4921QF1009BY Setdn Fet Assy(HS11)2005.05.178

Apply to 42X2A Model

4921QF3005AY Path FET Ass’y(HS91)2005.05.177

Initial Product0ILNRTI020AScan IC2004.06.174

NotePart NumberComponentDateNo.

- 22 -

2. Component

ROM to improve high temp. miswriting(after august)

(42X2####, 42X2)

42X2DN03A2004.09.087

ROM to improve miswriting

(after august)(42X2####, 42X2)42X2DN03B2004.09.088

ROM to improve miswriting & afterglow (after august)(42X2####, 42X2)

42X2DN03C2004.10.049

ROM to improve white_blinking

(after august) (42X2####, 42X2)42X2DN03D2004.10.0410

Temporary ROM to improve R-miswriting (for october,november)

(42X2####, 42X2)

42X2DN03E2004.11.1811

ROM to improve R_margin(for november)

(42X2####, 42X2)42X2DN03G2004.12.0112

initial ROM Data

(42X2####. 42X2)42X2DN012004.06.301

Temporary ROM to improve white_blinking-afterglow

(42X2####, 42X2)

42X2DN03L2004.12.2713

Temporary ROM to improve miswriting(for July)(42X2####, 42X2)

42X2DN02B2004.08.105

Rom to improve contrast_ratio (tojanuary for defect_module)

(42X2####, 42X2)

42X2DN03P2004.12.3115

Temporary ROM to improve white_blinking-afterglow

(42X2####, 42X2)

42X2DN03M2004.12.2714

ROM to improve the Flicker, afterglow and miswriting (42X2####, 42X2)

42X2DN032004.08.106

Temporary ROM to improve high&low Temp. miswriting(42X2####, 42X2)

42X2DN02A2004.07.284

ROM to improve

the EMI,contournoise(42X2####, 42X2)42X2DN022004.07.233

Temporary ROM to improve

the afterglow in Peak P/T

(42X2####, 42X2)

42X2DN01A2004.07.072

ContentsROM data VersionDateNo.

- 23 -

3. ROM DATA

Temporary ROM to improve high temp. miswriting (April)

(42X2##22, 42X2A B_Dielec)

42X2A_DNA062005.04.2822

ROM to improve 50 Peak Brightness

(42X2##22, 42X2A B_Dielec) 42X2A_DNA06A2005.04.2723

42X2A Initial ROM for T_Dielec

(42X2#522, 42X2A T_Dielec)42X2A_TD02B2005.05.1124

ROM to improve Low Temp. Miswriting&White_Blinking

(42X2#522, 42X2A T_Dielec)

42X2A_TD02C2005.05.2825

ROM to improve afterglow-white-blinking

(42X2##22, 42X2A B_Dilect)

42X2A_DNA7A2005.07.0126

ROM to improve afterglow-white-blinking

(42X2#522, 42X2A T_Dielec)

42X2A_TD032005.07.1427

ROM to improve high temp. miswriting(to january for defect

module)(42X2####, 42X2)42X2_DN03N2005.01.0516

ROM to improve High Temp. miswriting

(42X2#522, 42X2A T_Dielec)42X2A_TD03A2005.07.2828

42X2A initial ROM DATA

(42X2##2#,42X2A B_Dielec.)42X2A_DNA032005.03.1620

ROM to improve afterglow-white-blinking

(42X2####, 42X2)

42X2DN05B2005.07.2929

Temporary ROM to improve white_blinking(April,May)

(42X2####, 42X2)

42X2DN04B2005.04.2821

ROM to improve afterglow & white_blinking (42X2####, 42X2)

42X2DN04A2005.03.0219

Temporary ROM to improve white_blinking( for february & march)

(42X2####. 42X2)

42X2DN03T2005.02.2218

ROM to improve Data_Noise & Peaking

(42X2####, 42X2)42X2_DN03R2005.01.2417

ContentsROM data VersionDateNo.

- 24-

B_Dielec. : Blue dielectric Substance

T_Dielec : Transparency dielectric Substance

PD42HAASUSXS1-A01 AKAI R&D SA PDP4216M

Item Component Description/Country Origin Unit Quantity

一, ELECT PART

1 771-42AB01-01 KEY PCB ASSY SET 12 771-42AB01-05 SPK JACK PCB ASSY SET 13 771-42D110-01 IR RECEIVE PCB ASSY SET 14 771E42AA02-01 MAIN PCB ASSY SET 15 771L42AA01-01 AUDIO PCB ASSY SET 16 774P42AB01-01 POWER ASSY SET 17 77M42D103-02 MECH CHASSIS ASSY SET 18 786-SPA103-01 INT. SPK ASSY SET 19 E3403-004001 TUBE SUMITUBE D5.0 BLK 600V M 0.35

10 E3421-926007 WIRE ASSY 1H2.5-2H2.5 L330 31P (LV PCS 111 E3421-926045 WIRE ASSY 6P/4P+2P 2.54MM L=200MM PCS 112 E3421-926046 WIRE ASSY 2.54MM 11P/12P+7P L=220MM PCS 113 E6205-001004 DISPLAY PDP 42" LG-42X2 (XGA) 107CM PCS 1.00006

二, MECH PART

1 200-42D121-25A CABINET FRONT BLACK AKAI PD42HAA USA PCS 12 244-34B811-01 GIFT BOX HANDLE 34B8 PCS 23 248-46D201-01 HANDLE FOR PLASMA PCS 24 263-42D101-01S POWER LENS 42D1 PCS 15 269-42D101-01L REMOTE LENS 42D1 PCS 16 329-053010-70 SPONGE 530X10X7.0MM W/ADHESIVE PCS 27 329-095510-70 SPONGE 955X10X7.0MM W/ADHESIVE PCS 28 361-101261-01 CABLE TIE PCS 249 384-42D103-08H PVC SHEET FOR AKAI PCB PD42HAA USA PCS 1

10 387-42D101-13H MODEL PLATE AKAI ENG PD42HAA USA H PCS 111 388-42D102-01 PC SHEET FOR REMOTE PCB42D1 94V0 0.3 PCS 112 388-42D103-01H CAUTION PLATE ENG 42D1 H PCS 113 388-42SB04-01H POWER PLATE SANSUI 42SB PCS 114 388-50AD01-01H SPEAKER PLATE FOR PDP50HAD PCS 115 402-42D114-01S BACK COVER W/O SWITCH HOLE S PCS 116 423-42D117-01S PANEL PATCH V6 42D1 PCS 417 423-42D11C-01S SUPPORT FOR PW BKT 42D1 S PCS 118 423-42D11E-01S POWER BKT FOR E-ROOM 42D1 S PCS 119 423-42D122-01S FILTER SUPPORT L&R 42D1 PCS 220 423-42D12D-01S MAIN BKT FOR HOME CHASSIS 42D1 S PCS 221 423-42SD12-01S FILTER SUPPORT TOP 42SD PCS 122 423-42SD21-01S FILTER SUPPORT BOTTOM 42SD PCS 123 457-42D101-01 CLAMP ID=4.3MM L=46MM PCS 724 553-002007-40A SHIELD GASKET 20X7X4.0MM W/CONDUCTIV PCS 425 553-002509-25A SHIELD GASKET 25X9X2.5MM W/CONDUCTIV PCS 2

26 553-004009-40A SHIELD GASKET 40X9X4.0MM W/CONDUCTIV PCS 127 553-005009-25A SHIELD GASKET 50X9X2.5MM W/CONDUCTIV PCS 128 553-012509-40A SHIELD GASKET 125X9X4.0MM W/CONDUCTI PCS 1129 553-020009-40A SHIELD GASKET 200X9X4.0MM W/CONDUCTI PCS 430 553-024509-40A SHIELD GASKET 245X9X4.0MM W/CONDUCTI PCS 231 553-056009-40A SHIELD GASKET 560X9X4.0 W/CONDUCTIVE PCS 232 553-095009-40A SHIELD GASKET 950X9X4.0 W/CONDUCTIVE PCS 233 554-080030-01 SHIELD CLOTH 80X30MM W/CONDUCTIVE AD PCS 134 563-119- SERIAL NO. LABEL PCS 135 568-P46T02-02 WARNING LB ENG 42SF NIL PCS 136 579-42D102-09 SERIAL NO/BAR CODE LABEL 42D1 PCS 137 579-42D102-16 BAR CODE LABEL AKAI PD42HAA USA PCS 238 579-42D103-02 ON/OFF LB ENG 42D1 NIL PCS 139 579-42D105-01 PROTECTIVE EARTH LABEL FOR ESA 42TD1 PCS 140 580-P42AAHS-MU01L IB E FOR AKAI PD42HAA MONITOR LGX2A PCS 141 590-42D101-07 WARRANTY CARD AKAI PD42HAA USA PCS 142 593-42D101-01 INSERTION CARD AKAI PDP4216M MONITOR PCS 143 599-BM0902-01 IB SHEET E OF TEARDOWN FOR BM09 42AA PCS 144 601-305008-00 MACH.SCREW CTS 3X8 BZN + PCS 245 602-305006-00 MACH. SCREW PAN-WASHER 3X6 B ZNP +H PCS 1646 602-305006-10 MACH.SCREW WHR 3X6 NIP + PCS 1147 604-601020-00 MACHINE SCREW BINDING M6X1.0PX20MM B PCS 648 60D-407010-40 MACH. SCREW W/SPRING WASHER M4.0X0.7 PCS 2149 610-300210-00 S-TAP.SCREW RND 3X10 A BZN + PCS 250 614-260208-10 S-TAP.SCREW BID 2.6X8 A NIP + PCS 251 614-400408-10 S-TAP.SCREW BID 4X8 D NIP + PCS 252 614-400412-00 S-TAP.SCREW BID 4X12 T BZN + PCS 3453 615-400214-00 SELF-TAPPING SCREW W/BIG WASHER PCS 154 619-300210-10 SPECIAL SCREW 3X10 NP "+" PCS 2355 634-100050-20 PLANE WASHER 10X5.0X2.0MM PCS 456 734-BM0903-01 STAND BM09 PCS 157 790-002517-A1 REMOTE CONTROL 0025 PCS 158 844-42D101-01 WOODEN PALLET 1160X940X104 PCS 0.142859 844-42D102-01 WOODEN PALLET 1160X1250X104 PCS 0.142860 900-420103-01B DISPLAY FILTER 42" OPTIMAX FOR LG (9 PCS 1

三, PACKING

1 300-42D105-02C POLYFAM FOR MAIN UNIT+BM09 BTM PCS 12 300-42D106-02C POLYFOAM FOR MAIN UNIT+BM09 TOP PCS 13 300-42D107-01C POLYFOAM SHEET 42D1 PCS 24 300-42D118-01C POLYFOAM LEFT 42TD1 PCS 15 310-111404-07V POLYBAG 11"X14"X0.04 PCS 16 310-504004-01 POLYBAG EPF 50"X40"X0.04 PCS 17 510-42D101-20K GIFT BOX AKAI ENG PD42HAA USA K PCS 18 511-42D111-01K BOTTOM BOX 42D1 PCS 19 512-42D101-01 SHEET 1160X1160 42D1 PCS 0.2857

10 512-42D102-01 SHEET 1160X1480 42D1 PCS 0.285711 E3404-157004 AC CORD UL 1.88M (YY-3/ST3 YUNBIAO) PCS 112 E7301-011002 BATTERY AA R6P1.5V <2> PCS 2

If you forget your V-Chip Password - Omnipotence V-Chip Password: 5898.

- Press MENU button. - Press Up, Down and CH+, CH-buttons to highlight "V-Chip" Control. - Press OK button to pop up "INPUT PASSWORD".

- Use the Number buttons (0~9) to enter the omnipotence Password 1234. - Press Down to highlight "Password change" Control. - Press OK button to confirm and will pop up "Password Change" item.- Change to your familiar Password again.

Software upgrade - Connect the RS-232C input jack to an external control device (such as a computer) and software upgrade.

Type of connector; D-Sub 9-pin male 1

No. Pin name 5 1 No connection2 RXD (Receive data)3 TXD (Transmit data)4 DTR (DTE side ready)5 GND

96 DSR (DCE side ready)7 RTS (Ready to send)

68 CTS (Clear to send)9 No Connection

RS-232C configurations

7-wire configuration 3-wire configuration (Standard RS-232C cable) (Not standard)

PC PDP PC PDP

2 3 5 4 6 7 8

3 2 5 6 4 8 7

TXD TXD RXD TXD RXD 2

3 5 4 6 7 8

3 2 5 4 6 7 8

RXD GND

RXD TXD GND

DTR GND GND

DTR DSR

DSR DTR DSR

RTS DTR DSR

RTS CTS

CTS RTS CTSRTS CTS

D-Sub 9 D-Sub 9 D-Sub 9 D-Sub 9

Software upgrade Process - Power Switch OFF.

- Connect the serial port of the control device to the RS-232 jack on the PDP back panel.

RS-232C connection cables are not supplied with the PDP.

- Power Switch ON. The power indicator on the front of the panel should now display red, means

that the PDP is in standby mode.

- Copy the software (Flash Upgrader) to the computer.

- Open the software (Flash Upgrader.exe)

- Point "Flash" on the interface of the Flash Upgrader.exe.

- Press STANDBY button on the front panel or POWER button of Remote control, Power indicator

green, the PDP is in power ON mode, software start upgrader immediately.

- Waiting for the upgrader programing, when it is finished, the PDP will auto power on.

- After the upgrader is finished, shut down the power switch, take out the RS-232C connection

after the power indicator is extinguished.

Note: The computer and PDP must be keep Power ON in the software upgrade processing.