Master Solution

Master Solution / Analog Integrated Circuit Design WS 09/10 10.3.2010 1/16

Technische Universität Darmstadt

FB Elektrotechnik und Informationstechnik

FG Integrierte Elektronische Systeme

Prof. Dr.-Ing. Klaus Hofmann

Examination

of the lecture

Analog Integrated Circuit Design

(former: Microelectronic Circuits) WS 2009/2010 March 10 2010

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Section Task1 Task2 Task3 Task4 Maximum 12 18 20 10 Achieved

Time allowed: 90min Allowed: Writing material, 1 A4 sheet of formula collection (double sided), non-

programmable calculator All sheets of this exam must be returned

On multiple choice questions: Equal penalty applies for wrong answers

Master Solution

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Task 1-1 (2P): The following feedback system is given, whereby the frequency response (gain (solid line) and phase (dotted line)) of G(s) are known:

You are allowed to choose the amplification factor Kp. What is the maximum value of Kp (real value or dB), so the feedback system is still stable? Kp(max.)=18 dB. The magnitude response can shift up by maximum of 18dB before the system becomes unstable. (For Kp any positive value in between 17dB and 18dB is accepted)

Master Solution

Master Solution / Analog Integrated Circuit Design WS 09/10 10.3.2010 3/16

Task 1-2 (3P): The following Nyquist plot of a systems transfer function is given below (left the full plot, right the “zoom in” close to the center of the plot). Please answer the following questions: 1-2a: Is this system stable? No 1-2b: What is the (positive for stable, or negative for an instable) gain margin (either absolute value or dB)? Gain Margin = 1/|T(jw)| = 1/1.25 (For |T(jw)| any value between 1.2 and 1.3 is accepted) 1-2c: What is the (positive or negative) phase margin? Phase Margin = -8° approximately (For phase margin any negative value between –7° and –9° is accepted)

Master Solution

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Task 1-3 – 1-9 (7P): Read the statements below and check the corresponding box if you think the statement is true or false. If you do not know the answer, leave the corresponding boxes unchecked. Equal penalty applies if you check the wrong answer. Minimum number of points for tasks 1-3 to 1-7 is 0P. Question TRUE FALSE Statement 1-3 An ideal Transconductance Amplifier has

an infinite input resistance, and a zero output resistance.

1-4 A cascode amplifier consisting of two npn-transistors behaves like a single npn-transistor with a very high current amplification factor β

1-5 The emitter (or source) node of a symmetrical differential amplifier represents a virtual ground node for differential input signals.

1-6 The common-mode rejection ratio (CMRR) characterizes the ability of an amplifier to amplify the desired differential-mode input signal and reject undesired common-mode input signals

1-7 Adding a common-drain output stage to an operational amplifier implementation increases the small signal voltage gain.

1-8 Adding a common-drain output stage to an operational amplifier implementation results in a low small signal output resistance

1-9 Internal frequency compensation aims to increase the phase margin of the amplifier.

Master Solution

Master Solution / Analog Integrated Circuit Design WS 09/10 10.3.2010 5/16

Task 2.1 (3+2P): Draw the small signal model for the circuit given below and identify the type of the two stages. Assume channel length modulation is neglected Channel length modulation λ=0, ro=infinite

Both the amplifier stages are common source.

VDD=10V

M1Vtn = 2V,

Kn = 0.1mA/V2

vovi

M2Vtp = -2V,

Kp = 1mA/V2

R1 RD1 RS2 = 0.5K

R2 Rs = 1K C1 RD2 = 2K

C3C2

Rin

ID1 ID2

G

D

S

S

D

G

VDD=10V

M1Vtn = 2V,

Kn = 0.1mA/V2

vovi

M2Vtp = -2V,

Kp = 1mA/V2

R1 RD1 RS2 = 0.5K

R2 Rs = 1K C1 RD2 = 2K

C3C2

Rin

ID1 ID2

G

D

S

S

D

G

Master Solution

Master Solution / Analog Integrated Circuit Design WS 09/10 10.3.2010 6/16

Task 2.2 (10P): Design the circuit (find R1, R2, RD1) such that ID1=0.4mA, Rin=200K, and VSD2=5V. What are the values for ID2, VDS1? Assume transistors are biased in saturation region.

Hints for easier calculation: )232.25,414.12,732.13,828.28( ====

Master Solution

Master Solution / Analog Integrated Circuit Design WS 09/10 10.3.2010 7/16

Master Solution

Master Solution / Analog Integrated Circuit Design WS 09/10 10.3.2010 8/16

Task 2.3 (3P): Calculate the resulting small signal voltage gain AV=vo/vi. (Hint: If you can not find correct values from Task 2.2, assume ID2=1mA, RD1=5K, R2=250K, R1=350K)

Master Solution

Master Solution / Analog Integrated Circuit Design WS 09/10 10.3.2010 9/16

Task 3: Assume the following parameters for the given circuits below.

== ''pn KK 40µA/V2, λ = 0.01 V-1, Vtn = -Vtp = 1V

Task 3.1 (3P): Given IQ=1mA, determine the voltage gain Av=vo/vi . The voltage VB is a DC voltage for biasing the M9 transistor. Assume that the channel length modulation effects

can not neglected and λVDS<<1 Hints for easier calculation: )232.25,414.12,732.13,828.28( ====

VCC=5V

IQ

M9W/L=15

M8W/L=100

vo

vi

VB

VCC=5V

IQ

M9W/L=15

M8W/L=100

vo

vi

VB

Master Solution

Master Solution / Analog Integrated Circuit Design WS 09/10 10.3.2010 10/16

Task 3.2 (5P): Determine the current IQ for the circuit given below. Assume that the channel length modulation effects can be neglected and transistors are biased in saturation region.

VCC=5V

M1W/L=10

M2W/L=5

M3W/L=15

IQ

VCC=5V

M1W/L=10

M2W/L=5

M3W/L=15

IQVx

Master Solution

Master Solution / Analog Integrated Circuit Design WS 09/10 10.3.2010 11/16

Task 3.3 (5P): Given IQ=1mA, determine the differential gain Av=vo/(v1-v2) using virtual ground concept. Assume the following: load resistance connected to the output port v0 is infinite channel length modulation effects should not be neglected A purely differential signal vid is applied across the input

terminal v1,v2

om

rg

<<1

, λVDS<<1 Transistors M6,M7 and M4,M5 are perfectly matched. That is

ro6=ro7=ros, ro4=ro5=rod, gm6=gm7=gms, gm4=gm5=gmd.

v1 = vid/2 and v2 = -vid/2

VCC=5V

M6W/L=10

IQ

M4W/L=50

M5W/L=50

M7W/L=10

vo

v2v1

VCC=5V

M6W/L=10

IQ

M4W/L=50

M5W/L=50

M7W/L=10

vo

v2v1

Master Solution

Master Solution / Analog Integrated Circuit Design WS 09/10 10.3.2010 12/16

(Calculations done assuming that v1 = -vid/2 and v2 = vid/2 is also accepted. In this case the gain will be -140)

Master Solution

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Task 3.4 (2+2+3P): Construct an OPAMP using the three circuits before (Task 3-1, 3-2 and 3-3) and determine overall differential gain of the complete circuit. Explain in your own words the function and type of each stage.

Task 3.1: Common source amplifier stage for improving the overall gain of the OPAMP Task 3.2: Current mirror with the NMOS transistor M1 acting as load resistor. Provides the biasing current IQ for the differential amplifier. Task 3.3: NMOS differential amplifier with current mirror load to amplify the differential signals v1 and v2.

Master Solution

Master Solution / Analog Integrated Circuit Design WS 09/10 10.3.2010 14/16

Task 4.1 (3+1P): Draw the small signal model for the given circuit and identify the type of the amplifier stage. Assume that early effect can be neglected. Early effect neglected, ro=infinite

 

vin

vout

RinRout

 

vin

vout

RinRout

Master Solution

Master Solution / Analog Integrated Circuit Design WS 09/10 10.3.2010 15/16

Task 4.2 (2+2+2P): Determine the lower 3dB frequency (fL1, fL2, fL3) due to each capacitor Cs, CE, and CL separately using the SCTC method. You may assume ßO=100, IC=1mA, VT=26mV. What is the approximate lower 3dB frequency of the amplifier?

Master Solution

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