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VHDL-AMS modelling and simulation of dualphase-locked loop based frequency synthesiser

CONFERENCE PAPER AUGUST 2006

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5 AUTHORS, INCLUDING:

A.A. Abdeltawab Telba

King Saud University

27PUBLICATIONS 39CITATIONS

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Syed Manzoor Qasim

Rizvi Consultancy


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J.M. Noras

University of Bradford


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Mohamed abdelmonem Abouelela

Future University in Egypt


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VHDL-AMS MODELING AND SIMULATION OF DUAL PHASE LOCKED

LOOP BASED FREQUENCY SYNTHESIZER

A. Telba1*, S. M. Qasim

2, J. M. Noras

1, M. A. El Ela

2, and B. Almashary

2

1School of Engineering, Design and Technology,

University of BradfordBradford, West Yorkshire, UK

BD7 1DP*[email protected]

2College of Engineering, Electrical Engineering Department,

King Saud University

Riyadh 11421

Saudi Arabia

Abstract Phase Locked Loop (PLL) based frequency

synthesizers are the key components of the vast

majority of modern communication systems. In this

paper we describe Very High Speed Integrated

Circuit Hardware Description Language-Analog

Mixed Signal (VHDL-AMS) model of a dual PLL

based frequency synthesizer using SystemVision

Software available from Mentor Graphics. The first

one is a low jitter PLL which uses a Voltage

Controlled Crystal Oscillator (VCXO) and the second

one is a wideband PLL with a normal Voltage

Controlled Oscillator (VCO). The advantage of using

dual PLL configuration is that it reduces the jitter at

the output. Important simulation results for the

frequency synthesizer are presented. The results

match well with the theoretical calculations.

Keywords: VHDL-AMS, Modeling, Simulation, PLL,

Frequency Synthesizer, SystemVision, Mentor

Graphics

I. INTRODUCTION

Phase Locked Loop (PLL) is one of the most versatile

building blocks and lies at the heart of many circuits and

systems [1,2]. The property of making its outputfrequency an exact multiple of reference frequency makes

the PLL the circuit of choice for frequency synthesizers.

The common method for frequency synthesis is to lock aPLL to a multiple of some reference frequency. PLL

based frequency synthesizers are used in wide range of

telecommunication circuits.

Behavioral modeling and simulation is more time

efficient than full circuit level simulation and is useful forverification purposes. Behavioral modeling is commonly

performed with high level hardware description

languages (HDLs) such as Very High Speed IntegratedCircuit Hardware Description Language-Analog Mixed

Signal (VHDL-AMS) [3,4].

A straight forward implementation of PLL basedfrequency synthesizer consists of the following basic

building blocks: phase detector (PD), loop filter, voltage

controlled oscillator (VCO) and a frequency divider [5].To the best of our knowledge there has been no

previous work dealing with modeling and simulation of

frequency synthesizer using dual PLLs. Researchers have

modeled and simulated frequency synthesizer using a

single PLL. In this paper we describe a dual PLL basedfrequency synthesizer using VHDL-AMS which provides

a low jitter output as compared to single PLL based

synthesizer.The remainder of the paper is organized as follows. In

section II we describe a dual PLL based frequency

synthesizer. Each component of the PLL is modeledbehaviourally in section III. Section IV gives a brief idea

about SystemVision Software. The simulation results ofthe proposed circuit are discussed in section V. Finallysection VI ends the paper with some concluding remarks.

II. DUAL PLL FREQUENCY SYNTHESIZER

The block diagram of a dual PLL frequency

Synthesizer is shown in Fig. 1. The circuit consists of twoPLL connected in cascade i.e., the output generated by

the first one is supplied as an input to the second PLL.

The first one is a PLL which uses a Voltage ControlledCrystal Oscillator (VCXO) with a centre frequency of fx

not necessarily equal tofinand the second one is a narrow

band PLL with a wide sweep range [6,7].Bandwidths of

the two PLL are carefully selected to minimize the overalloutput jitter.

The VCXO produces a low jitter output signal. Afrequency divider producing a divide-by-N, allow the

VCXO to operate at Nmultiples of the reference clock

provided by an oscillator running at T1 carrier (1.544

MHz). The divider output signal is compared to that of

the oscillator by a PD. A Digital-to-Analog Converter(DAC) is used to convert the digital output of the PD into
https://www.researchgate.net/publication/244438231_Phase_Locked_Loop_Circuit_Design?el=1_x_8&enrichId=rgreq-1c0677a6-acd6-48d5-a07e-045c2b4508dc&enrichSource=Y292ZXJQYWdlOzIzNTM1NTM2MjtBUzo5OTExNzk0MjQ0NDA0NkAxNDAwNjQyOTY3NTY4https://www.researchgate.net/publication/3225063_Behavioral_modeling_for_high-level_synthesis_of_analog_and_mixed-signal_systems_from_VHDL-AMS?el=1_x_8&enrichId=rgreq-1c0677a6-acd6-48d5-a07e-045c2b4508dc&enrichSource=Y292ZXJQYWdlOzIzNTM1NTM2MjtBUzo5OTExNzk0MjQ0NDA0NkAxNDAwNjQyOTY3NTY4https://www.researchgate.net/publication/4145696_Simulation_technique_for_noise_and_timing_jitter_in_phase_locked_loop?el=1_x_8&enrichId=rgreq-1c0677a6-acd6-48d5-a07e-045c2b4508dc&enrichSource=Y292ZXJQYWdlOzIzNTM1NTM2MjtBUzo5OTExNzk0MjQ0NDA0NkAxNDAwNjQyOTY3NTY4https://www.researchgate.net/publication/244438231_Phase_Locked_Loop_Circuit_Design?el=1_x_8&enrichId=rgreq-1c0677a6-acd6-48d5-a07e-045c2b4508dc&enrichSource=Y292ZXJQYWdlOzIzNTM1NTM2MjtBUzo5OTExNzk0MjQ0NDA0NkAxNDAwNjQyOTY3NTY4https://www.researchgate.net/publication/3225063_Behavioral_modeling_for_high-level_synthesis_of_analog_and_mixed-signal_systems_from_VHDL-AMS?el=1_x_8&enrichId=rgreq-1c0677a6-acd6-48d5-a07e-045c2b4508dc&enrichSource=Y292ZXJQYWdlOzIzNTM1NTM2MjtBUzo5OTExNzk0MjQ0NDA0NkAxNDAwNjQyOTY3NTY4https://www.researchgate.net/publication/4145696_Simulation_technique_for_noise_and_timing_jitter_in_phase_locked_loop?el=1_x_8&enrichId=rgreq-1c0677a6-acd6-48d5-a07e-045c2b4508dc&enrichSource=Y292ZXJQYWdlOzIzNTM1NTM2MjtBUzo5OTExNzk0MjQ0NDA0NkAxNDAwNjQyOTY3NTY4https://www.researchgate.net/publication/4220614_Jitter_minimization_in_Digital_Transmission_using_dual_phase_locked_loops?el=1_x_8&enrichId=rgreq-1c0677a6-acd6-48d5-a07e-045c2b4508dc&enrichSource=Y292ZXJQYWdlOzIzNTM1NTM2MjtBUzo5OTExNzk0MjQ0NDA0NkAxNDAwNjQyOTY3NTY4


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an analog signal which is fed to the VCXO after being

filtered by a Low Pass Filter (LPF).The analog VCO output is passed through an Analog-

to-Digital Converter (ADC) before being passed to thePD through the divider.

With the first loop in lock condition [6],

11 N

f

M

fxin

= (1)

Similarly, for the second loop in lock condition

22 M

f

N

f xout= (2)

Using (1) and (2), we get

)(21

21

MM

NNff

inout= (3)

III. VHDL-AMSBEHAVIORAL MODELS

A. Phase Detector (PD)

The heart of a PLL based frequency synthesizer is PD.

The PD shown in Fig. 2 is a circuit that produces an

output signal that is proportional to the phase differencebetween two input signals. The library model chosen for a

PD is a simple Exclusive OR (EXOR) gate. This is a

purely digital VHDL model. ADC and DAC are inserted

at the interfaces.

B. Low Pass Filter (LPF)

LPF allows only the low frequency part of the phase

difference to pass to the VCO. The high frequency part isfiltered out. As a result, the PLL only tracks the low

frequency variation and does not allow the high

frequency variation.Listing 1 depicts a portion of the VHDL-AMS code

for LPF using the transfer function given in 4.

22

2

)(

p

pws

Q

ws

wKsH p

++

= (4)

where,

ppfw 2= (5)

The same LPF is used for both PLLs but with different

specifications. The first PLL uses pf = 5 KHz, K= 1.0

and Q = 1.0, whereas the second PLL has the following

design criteria: pf = 10 KHz, K= 1.0 and Q = 1.0,

C. Voltage Controlled Oscillator (VCO)

VCO is a voltage controlled Oscillator whose output

frequency is linearly proportional to the control voltage

Listing 1: VHDL-AMS Code for LPF

Architecture ideal of LowPassFilter isquantity vin across input to electrical_ref;

quantity vout across iout through output to electrical_ref;

constant wp : real := math_2_pi*Fp;constant num : real_vector := (wp*wp, 0.0);

constant den : real_vector := (wp*wp, wp/Q, 1.0);

begin

vout == K * vin'ltf(num, den);end architecture ideal;

Fig. 1: Dual PLL based frequency Synthesizer

Fig. 2: Phase Detection using an EXOR gate
https://www.researchgate.net/publication/4220614_Jitter_minimization_in_Digital_Transmission_using_dual_phase_locked_loops?el=1_x_8&enrichId=rgreq-1c0677a6-acd6-48d5-a07e-045c2b4508dc&enrichSource=Y292ZXJQYWdlOzIzNTM1NTM2MjtBUzo5OTExNzk0MjQ0NDA0NkAxNDAwNjQyOTY3NTY4https://www.researchgate.net/publication/4220614_Jitter_minimization_in_Digital_Transmission_using_dual_phase_locked_loops?el=1_x_8&enrichId=rgreq-1c0677a6-acd6-48d5-a07e-045c2b4508dc&enrichSource=Y292ZXJQYWdlOzIzNTM1NTM2MjtBUzo5OTExNzk0MjQ0NDA0NkAxNDAwNjQyOTY3NTY4


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VC generated by the PD. The library model chosen for a

VCO uses the following relationship

invcoutVKff += (5)

The behavioral model of VCO is described in VHDL-AMS as shown in listing 2. The first VCO uses the

following design values: vK = 1 KHz and cf = 1.544

MHz and the second VCO uses vK = 200 KHz and cf =

6.0 MHz. A VCO initially runs at a frequency close to theexpected data rate. Listing 2 depicts a portion of the

VHDL-AMS code for VCO.

D. Frequency Divider

PLL used in frequency synthesis often use a frequency

divider. Fig. 3 illustrates a simple divide by four circuitimplemented using two D Flip-flops. The circuit can be

extended for different values of N. The frequency divider

is another purely digital block which was describedcompletely in VHDL.

It was simply implemented as a divide by four counter.

Fig.4 shows the simulation results for the frequency

divider block.

IV. SYSTEMVISION SOFTWARE

SystemVision is Mentor Graphics powerful mixed

signal modeling and simulation [8] environment that

provides a virtual lab for creating and analyzing analog,

digital and mixed signal systems. It provides simulation

of the complete system before prototype and shows adramatic improvement in simulation time for the VHDL-

AMS module.

V. SIMULATION RESULTS

A complete dual PLL frequency synthesizer wasimplemented in Mentor Graphics SystemVision

environment [8] using VHDL-AMS language.

Simulations were carried out on a Windows XP Platform

with Pentium IV 3.4 GHz processor and 2 GB RAM.

(a) PD Output

(b) LPF Output

(c) VCO Outputs

Fig.5: Simulation Results of Frequency Synthesizer

Listing 2: VHDL-AMS Code for VCO

Architecture behavioral of VCOAnalog is

quantity vout across iout through v_outp to v_outm;

quantity vctrl across v_inp to v_inm;

quantity phi : real;quantity vtmp : real;

constant Kv_w : real := math_2_pi*Kv;constant wc : real := math_2_pi*Fc;

begin

if vctrl > Vcmax usevtmp == Vcmax;

elsif vctrl < Vcmin use

vtmp == Vcmin;

elsevtmp == vctrl;

end use;

if domain = quiescent_domain use

phi == 0.0;

else

phi'dot == Fc + Kv*(vtmp-Vc);end use;

vout == Vout_offset + Vout_ampl*cos(math_2_pi*phi);

end architecture behavioral;

Fig. 4: Frequency Divider Simulation Result

Fig. 3: Frequency Divider (Divide by 4) Circuit


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Fig. 5(a) shows the output of the PD whereas figs. 5(b)

and 5(c) depicts the output of the LPF and the VCOanalog outputs of the first PLL and second PLL

respectively. As can be seen in fig. 5(c), the output

frequency is 6 MHz, which is four times the T1 carrierfrequency of 1.544 MHz. The simulated output frequency

is very close to the theoretical value of 6.176 MHz.

The eye diagram is a useful tool for the qualitativeanalysis of signal used in digital transmission [9]. It gives

an approximation of the timing jitter in the signal.

Fig. 6 (a) and (b) illustrates the eye diagram of VCO at

the output of the first and second PLL respectively. It isclear from the figure that the jitter is drastically reduced

at the final output.

VI. CONCLUSION

This paper describes the modeling and successfulsimulation of a dual PLL based frequency synthesizer.

Top-down design methodology is adopted for mixed

(a) PLL-1

(a) PLL-2

Fig.6: Eye Diagrams


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signal design using VHDL-AMS as the modeling

language. In this paper we used two PLLs connected incascade for the frequency synthesizer application as it

provides low jitter output. Eye diagrams are used for the

analysis of jitter in digital transmission.

REFERENCES

[1] D. H. Wolaver, Phase-locked Loop Circuit Design,Prentice Hall, USA: 1991.

[2] R. E. Best, Phase Locked Loops: Design,

Simulation, and Applications, McGraw-Hill, NewYork: 1999.

[3] A. Doboli and R. Vemuri, Behavioral modeling forhigh-level synthesis of analog and mixed-signal

systems from VHDL-AMS, IEEE Transactions on

CAD of Integrated Circuits and Systems, Vol. 11,November 2003, pp. 15041520.

[4] E. Christen and K. Bakalar, VHDL-AMS a

hardware description language for analog andmixed-signal applications, IEEE Transactions on

Circuits and Systems, Vol. 46, October 1999, pp.12631272.

[5] P. J. Ashenden, G. D. Peterson, and D. A.

Teegarden, The System designer's guide to VHDL-AMS: Analog, Mixed-signal, and Mixed-technology

Modeling, Morgan Kaufmann, USA: 2003.

[6] A. Telba, J. M. Noras, M. A. El Ela, and B.

AlMashary, Jitter Minimization in Digital

Transmission using Dual Phase locked Loops,

Proceedings of the 17thInternational Conference onMicro Electronics (ICM) 2005, Pakistan, pp. 270

273.

[7] A. Telba, J. M. Noras, M. A. El Ela, and B. Al-Mashary, Simulation Technique for Noise and

Timing Jitter in Phase Locked Loop, Proceedings

of the 16th International Conference on Micro

Electronics (ICM) 2004, Tunisia, pp. 501504.

[8] 1stMarch 2006, Mentor Graphics Corporation,

SystemVision 4.2 Manual,www.mentor.com/products/sm/systemvision/

[9] G. Breed, Analyzing Signals Using the EyeDiagram, High Frequency Electronics Magazine,

November 2005, pp. 50-53.

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Ahmed Conf 2006 Modified