Agenda - University of California, Berkeley

4/21/11

1

CS 61C: Great Ideas in Computer Architecture (Machine Structures) Traps, Excep,ons, Virtual Machines

Instructors: Randy H. Katz

David A. PaGerson hGp://inst.eecs.Berkeley.edu/~cs61c/Sp11

4/21/11 1 Spring 2011 -‐-‐ Lecture #25 4/21/11 Spring 2011 -‐-‐ Lecture #25 2

New-‐School Machine Structures Big Idea: Memory Hierarchy

•  Parallel Requests Assigned to computer e.g., Search “Katz”

•  Parallel Threads Assigned to core e.g., Lookup, Ads

•  Parallel InstrucYons >1 instrucYon @ one Yme e.g., 5 pipelined instrucYons

•  Parallel Data >1 data item @ one Yme e.g., Add of 4 pairs of words

•  Hardware descripYons All gates @ one Yme

Smart Phone

Warehouse Scale

Computer

So?ware Hardware

Harness Parallelism & Achieve High Performance

Logic Gates

Core Core …

Memory (Cache)

Input/Output

Computer

Main Memory

Core

InstrucYon Unit(s) FuncYonal Unit(s)

A3+B3 A2+B2 A1+B1 A0+B0

Today’s Lecture

4/21/11 3 Spring 2011 -‐-‐ Lecture #25

Virtual Memory

New-‐School Machine Structures

•  Parallel Requests Assigned to computer e.g., Search “Katz”

•  Parallel Threads Assigned to core e.g., Lookup, Ads

•  Parallel InstrucYons >1 instrucYon @ one Yme e.g., 5 pipelined instrucYons

•  Parallel Data >1 data item @ one Yme e.g., Add of 4 pairs of words

•  Hardware descripYons All gates @ one Yme

Smart Phone

Warehouse Scale

Computer

So?ware Hardware

Harness Parallelism & Achieve High Performance

Logic Gates

Core Core …

Memory (Cache)

Input/Output

Computer

Main Memory

Core

InstrucYon Unit(s) FuncYonal Unit(s)

A3+B3 A2+B2 A1+B1 A0+B0

Today’s Lecture

4/21/11 4 Spring 2011 -‐-‐ Lecture #25

Traps

Virtual Machines

Agenda

•  Virtual Memory Revisted •  Administrivia

•  Demand Paging

•  ExcepYons, Traps, Interrupts •  Technology Break •  Virtual Machines

•  Summary

4/21/11 5 Spring 2011 -‐-‐ Lecture #25

Agenda




•  Summary

4/21/11 6 Spring 2011 -‐-‐ Lecture #25

4/21/11

2

ProtecYon + IndirecYon = Virtual Address Space

4/21/11 Spring 2011 -‐-‐ Lecture #25 7

code

staYc data

heap

stack ~ FFFF FFFFhex

~ 0hex

ApplicaYon 1 Virtual Memory


code

staYc data

heap


~ 0hex

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

Page Table

Page Table

Physical Memory


4/21/11 Spring 2011 -‐-‐ Lecture #25 8

code

staYc data

heap


~ 0hex



code

staYc data

heap


~ 0hex

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

Page Table

Page Table

Code 1 StaYc 1 Heap 1 Stack 1

Physical Memory


4/21/11 Spring 2011 -‐-‐ Lecture #25 9

code

staYc data

heap


~ 0hex



code

staYc data

heap


~ 0hex

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

Page Table

Page Table

Code 1 StaYc 1 Heap 1 Stack 1 Code 2 StaYc 2 Heap 2 Stack 2

Physical Memory

ProtecYon + IndirecYon = Dynamic Memory AllocaYon

4/21/11 Spring 2011 -‐-‐ Lecture #25 10



code

staYc data

heap


~ 0hex

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

Page Table

Page Table

Code 1 StaYc 1 Heap 1 Stack 1 Code 2 StaYc 2 Heap 2 Stack 2 Heap’ 1

Physical Memory malloc(4097)

code

staYc data

heap


~ 0hex

ProtecYon + IndirecYon = Dynamic Memory AllocaYon

4/21/11 Spring 2011 -‐-‐ Lecture #25 11

code

staYc data

heap


~ 0hex



code

staYc data

heap


~ 0hex

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

Page Table

Page Table

Code 1 StaYc 1 Heap 1 Stack 1 Code 2 StaYc 2 Heap 2 Stack 2 Heap’ 1 Stack’ 2

Physical Memory malloc(4097) Recursive func,on call

ProtecYon + IndirecYon = Controlled Sharing

4/21/11 Spring 2011 -‐-‐ Lecture #25 12

code

staYc data

heap


~ 0hex



code

staYc data

heap


~ 0hex

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

Page Table

Page Table

Code StaYc 1 Heap 1 Stack 1 StaYc 2 Heap 2 Stack 2

Physical Memory Shared Code Page “X” Protec5on Bit

4/21/11

3

ProtecYon + IndirecYon = Controlled Sharing

4/21/11 Spring 2011 -‐-‐ Lecture #25 13

code

staYc data

heap


~ 0hex



code

staYc data

heap


~ 0hex

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

Page Table

Page Table

Code Sta7c Heap 1 Stack 1 Heap 2 Stack 2

Physical Memory Shared Code Page “X” Protec5on Bit

Shared Globals “RW” Protec5on Bits

Day in the Life of an (InstrucYon) Address

4/21/11 Spring 2011 -‐-‐ Lecture #25 14

PC MEM PA PA

InstrucYon

No Cache, No Virtual Memory


4/21/11 Spring 2011 -‐-‐ Lecture #25 15

PC

MEM

VA (VPN, Offset)

PA

InstrucYon

TLB Hit

No Cache, Virtual Memory, TLB Hit—Very Fast! If locality works, this is the most common case!

PA (PPN, Offset)

PA (@Page Table Entry)


4/21/11 Spring 2011 -‐-‐ Lecture #25 16

PC

MEM

VA (VPN, Offset)

PA

InstrucYon

No Cache, Virtual Memory, TLB Miss, Page Table Access NOTE: Virtual Memory implemented before caches

PTBR

Page Table Base Register +

TLB

VPN

MEM PA (PPN, Offset)

Miss



4/21/11 Spring 2011 -‐-‐ Lecture #25 17

PC

MEM

VA (VPN, Offset)

PA

InstrucYon

Physical Data Cache, Virtual Memory, TLB Miss, Page Table Access VA caches are possible, but it’s complicated: see CS 162

PTBR


TLB

VPN

D$ PA (PPN, Offset)

Miss

Hit



4/21/11 Spring 2011 -‐-‐ Lecture #25 18

PC

MEM

VA (VPN, Offset)

PA

InstrucYon Physical Data Cache, Virtual Memory, TLB Miss, Page Table Access VA caches are possible, but it’s complicated: see CS 162

PTBR


TLB

VPN

D$

Miss

Miss

MEM PA (PPN, Offset) PA

(@Page Table Entry)

4/21/11

4

VPN PA (@Page Table Entry)


4/21/11 Spring 2011 -‐-‐ Lecture #25 19

PC VA (VPN, Offset)

InstrucYon

Physical Data & InstrucYon Cache, Virtual Memory, TLB Miss, Page Table Access VA caches are possible, but it’s complicated: see CS 162

PTBR


TLB

D$

Miss

Miss



I$ Hit

VPN PA (@Page Table Entry)


4/21/11 Spring 2011 -‐-‐ Lecture #25 20

PC VA (VPN, Offset)

Day in the life of a data access is not too different Physical Data & InstrucYon Cache, Virtual Memory, TLB Miss, Page Table Access

PTBR


TLB

D$

Miss

Miss



I$ Miss

MEM PA

InstrucYon

Agenda




•  Summary

4/21/11 21 Spring 2011 -‐-‐ Lecture #25

Administrivia

•  Extra Credit due 4/24 – Fastest Matrix MulYply •  F2F “Grading” of Project 4 in Lab this week •  Final Review: Mon 5/2, 5 – 8PM, 2050 VLSB •  Final Exam: Mon 5/9, 11:30-‐2:30PM, 100 Haas Pavilion – Designed for 90 minutes, you will have 3 hours –  Comprehensive (parYcularly problem areas on midterm), but focused on course since midterm: lecture, lab, hws, and projects are fair game

–  8 ½ inch x 11 inch crib sheet like midterm

4/21/11 22 Spring 2011 -‐-‐ Lecture #25

CS61c in the News! •  NVIDIA Tegra 2 Processor with

1GHz Dual-‐core ARM Processor •  1080p MPEG-‐4/H.264 Recording

and Playback •  HDMI mirroring •  4-‐inch WVGA screen •  8-‐megapixel rear camera / 1.3-‐

megapixel front camera •  7.1 mulY-‐channel virtual surround

sound •  8GB memory •  microSD memory expandability •  (up to 32GB) •  Micro-‐USB connecYvity •  1,500 mAh baGery •  Supports Adobe Flash Player 10.1

4/21/11 Spring 2011 -‐-‐ Lecture #25 23

LG OpYmus 2X Smart Phone Theater-‐quality entertainment on a mobile device “It’s Game Over for Single-‐core Smartphones.”

President Obama @ FB Yesterday!

4/21/11 Spring 2011 -‐-‐ Lecture #25 24 hGp://www.theonion.com/video/cias-‐facebook-‐program-‐dramaYcally-‐cut-‐agencys-‐cos,19753/

4/21/11

5

Agenda




•  Summary

4/21/11 25 Spring 2011 -‐-‐ Lecture #25

Historical RetrospecYve: 1960 versus 2010

•  Memory used to be very expensive, and amount available to the processor was highly limited –  Now memory is cheap: approx $20 per GByte in April 2011

•  Many apps’ data could not fit in main memory, e.g., payroll –  Paged memory system reduced fragmentaYon but sYll required whole program to be resident in the main memory

–  For good performance, buy enough memory to hold your apps

•  Programmers moved the data back and forth from the diskstore by overlaying it repeatedly on the primary store –  Programmers no longer need to worry about this level of detail anymore

4/21/11 Spring 2011 -‐-‐ Lecture #24 26

27

Demand Paging in Atlas (1962)

Secondary (~disk) 32x6 pages

Primary 32 Pages 512 words/page

Central Memory User sees 32 x 6 x 512 words

of storage

“A page from secondary storage is brought into the primary storage whenever it is (implicitly) demanded by the processor.”

Tom Kilburn

Primary memory as a cache for secondary memory

4/21/11 Spring 2011 -‐-‐ Lecture #24 28

Demand Paging Scheme

•  On a page fault: –  Input transfer into a free page is iniYated –  If no free page available, a page is selected to be replaced (based on usage)

–  Replaced page is wriGen on the disk •  To minimize disk latency effect, the first empty page on the disk was selected

–  Page table is updated to point to the new locaYon of the page on the disk

4/21/11 Spring 2011 -‐-‐ Lecture #24

Impact on TLB

•  Keep track of whether page needs to be wriGen back to disk if it has been modified

•  Set “Page Dirty Bit” in TLB when any data in page is wriGen

•  When TLB entry replaced, corresponding Page Dirty Bit is set in Page Table Entry

4/21/11 Spring 2011 -‐-‐ Lecture #24 29

Address TranslaYon: Puxng it all Together

4/21/11 Spring 2011 -‐-‐ Lecture #24 30

Virtual Address

TLB Lookup

Page Table Walk

Update TLB Page Fault (OS loads page)

ProtecYon Check

Physical Address (to cache)

miss hit

the page is ∉ Memory ∈ memory denied permiGed

ProtecYon Fault

hardware hardware or soyware soyware

SEGFAULT

Restart instrucYon

4/21/11

6

31

Address TranslaYon in CPU Pipeline

• Soyware handlers need restartable excepYon on TLB fault • Handling a TLB miss needs a hardware or so?ware mechanism to refill TLB • Need mechanisms to cope with the addiYonal latency of a TLB: –  Slow down the clock –  Pipeline the TLB and cache access –  Virtual address caches (indexed with virtual addresses) –  Parallel TLB/cache access

PC Inst TLB

Inst. Cache D Decode E M

Data TLB

Data Cache W +

TLB miss? Page Fault? Protec,on viola,on?

TLB miss? Page Fault? Protec,on viola,on?

4/21/11 Spring 2011 -‐-‐ Lecture #24

Concurrent Access to TLB & Cache

4/20/11 Spring 2011 -‐-‐ Lecture #24 32

Index L is available without consulYng the TLB ⇒ cache and TLB accesses can begin simultaneously

Tag comparison is made ayer both accesses are completed

Cases: L + b = k L + b < k L + b > k

VPN L b

TLB Direct-‐map Cache 2L blocks 2b-‐byte block

PPN Page Offset

= hit?

Data Physical Tag

Tag

VA

PA

Virtual Index

k

Impact of Paging on AMAT

•  Memory Parameters: –  L1 cache hit = 1 clock cycles, hit 95% of accesses –  L2 cache hit = 10 clock cycles, hit 60% of L1 misses

– DRAM = 200 clock cycles (~100 nanoseconds) – Disk = 20,000,000 clock cycles (~ 10 milliseconds)

•  Average Memory Access Time (with no paging): –  1 + 5%*10 + 5%*40%*200 = 5.5 clock cycles

•  Average Memory Access Time (with paging) = – AMAT (with no paging) + ? –  5.5 + ?

4/21/11 Spring 2011 -‐-‐ Lecture #24 33 Student RouleGe?

Impact of Paging on AMAT •  Memory Parameters: –  L1 cache hit = 1 clock cycles, hit 95% of accesses –  L2 cache hit = 10 clock cycles, hit 60% of L1 misses – DRAM = 200 clock cycles (~100 nanoseconds) – Disk = 20,000,000 clock cycles (~ 10 milliseconds)

•  Average Memory Access Time (with paging) = –  5.5 + 5%*40%*(1-‐HitMemory)*20,000,000

•  AMAT if HitMemory = 99.9%? –  5.5 + 0.02 * .001 * 20,000,000 = 405.5

•  AMAT if HitMemory = 99.9999% –  5.5 + 0.02 * .000001 * 20,000,000 = 5.9

4/21/11 Spring 2011 -‐-‐ Lecture #24 34

Agenda




•  Summary

4/21/11 35 Spring 2011 -‐-‐ Lecture #25 4/21/11 Spring 2011 -‐-‐ Lecture #25

ExcepYons and Interrupts

•  “Unexpected” events requiring change in flow of control –  Different ISAs use the terms differently

•  ExcepYon –  Arises within the CPU

•  e.g., Undefined opcode, overflow, syscall, … •  Interrupt –  From an external I/O controller

•  Dealing with them without sacrificing performance is difficult

§4.9 ExcepYons

36

4/21/11

7

4/21/11 Spring 2011 -‐-‐ Lecture #25

Handling ExcepYons

•  In MIPS, excepYons managed by a System Control Coprocessor (CP0)

•  Save PC of offending (or interrupted) instrucYon –  In MIPS: save in special register called Excep,on Program Counter (EPC)

•  Save indicaYon of the problem –  In MIPS: saved in special register called Cause register – We’ll assume 1-‐bit

•  0 for undefined opcode, 1 for overflow

•  Jump to excepYon handler code at address 8000 0180hex

37 4/21/11 Spring 2011 -‐-‐ Lecture #25

ExcepYon ProperYes

•  Restartable excepYons – Pipeline can flush the instrucYon – Handler executes, then returns to the instrucYon •  Refetched and executed from scratch

•  PC saved in EPC register –  IdenYfies causing instrucYon – Actually PC + 4 is saved because of pipelined implementaYon •  Handler must adjust PC to get right address

38

4/21/11 Spring 2011 -‐-‐ Lecture #25

Handler AcYons

•  Read Cause register, and transfer to relevant handler

•  Determine acYon required •  If restartable excepYon – Take correcYve acYon – use EPC to return to program

•  Otherwise – Terminate program – Report error using EPC, cause, …

39 Spring 2011 -‐-‐ Lecture #25

ExcepYons in a Pipeline

•  Another kind of control hazard •  Consider overflow on add in EX stage

add $1, $2, $1 – Prevent $1 from being clobbered – Complete previous instrucYons – Flush add and subsequent instrucYons – Set Cause and EPC register values – Transfer control to handler

•  Similar to mispredicted branch – Use much of the same hardware

4/21/11 40

4/21/11 Spring 2011 -‐-‐ Lecture #25

ExcepYon Example

•  ExcepYon on add in 40 sub $11, $2, $4 44 and $12, $2, $5 48 or $13, $2, $6 4C add $1, $2, $1 50 slt $15, $6, $7 54 lw $16, 50($7)

58 lui $14, 1000 …

•  Handler 80000180 sw $25, 1000($0) 80000184 sw $26, 1004($0) …

41

ExcepYon Example

I$

and

or

add

slt

lw

ALU

I$ Reg D$ Reg

ALU

I$ Reg D$ Reg

ALU

I$ Reg D$ Reg

ALU

Reg D$ Reg

ALU

I$ Reg D$ Reg

I n s t r.

O r d e r

Time (clock cycles)

ALU

I$ Reg D$ Reg lui 4/21/11 42 Spring 2011 -‐-‐ Lecture #25

4/21/11

8

ExcepYon Example

I$

and

or

(bubble)

(bubble)

(bubble)

ALU

I$ Reg D$ Reg

ALU

I$ Reg D$ Reg

ALU

I$ Reg D$ Reg

ALU

Reg D$ Reg

ALU

I$ Reg D$ Reg

I n s t r.

O r d e r

Time (clock cycles)

ALU

I$ Reg D$ Reg sw

Save PC+4 into EPC

1st instruc,on of handler

Flush add, slt, lw

4/21/11 43 Spring 2011 -‐-‐ Lecture #25 4/21/11 Spring 2011 -‐-‐ Lecture #25

MulYple ExcepYons

•  Pipelining overlaps mulYple instrucYons –  Could have mulYple excepYons at once –  E.g., Page fault in LW same clock cycle as Overflow of following

instrucYon ADD

•  Simple approach: deal with excepYon from earliest instrucYon, e.g., LW excepYon serviced 1st –  Flush subsequent instrucYons

•  Called Precise excepYons •  In complex pipelines:

–  MulYple instrucYons issued per cycle –  Out-‐of-‐order compleYon –  Maintaining precise excepYons is difficult!

44

4/21/11 Spring 2011 -‐-‐ Lecture #25

Imprecise ExcepYons

•  Just stop pipeline and save state –  Including excepYon cause(s)

•  Let the soyware handler work out –  Which instrucYon(s) had excepYons –  Which to complete or flush

•  May require “manual” compleYon

•  Simplifies hardware, but more complex handler soyware •  Not feasible for complex mulYple-‐issue out-‐of-‐order

pipelines to always get exact instrucYon •  All computers today offer precise excepYons—affects

performance though

45

Agenda




•  Summary

4/21/11 46 Spring 2011 -‐-‐ Lecture #25

4/21/11 Spring 2011 -‐-‐ Lecture #25 47

Agenda




•  Summary

4/21/11 48 Spring 2011 -‐-‐ Lecture #25

4/21/11

9

4/21/11 Spring 2011 -‐-‐ Lecture #25

Beyond Virtual Memory

•  Even greater protecYon than virtual memory –  E.g., Amazon Web Services allows independent tasks run on same computer

•  Can a “small” operaYng system simulate the hardware of some machine, so that –  Another operaYng system can run in that simulated hardware?

– More than one instance of that operaYng system run on the same hardware at the same Yme?

– More than one different operaYng system can share the same hardware at the same Yme?

•  Answer: Yes

49 4/21/11 Spring 2011 -‐-‐ Lecture #25

SoluYon – Virtual Machine •  A virtual machine provides interface iden,cal to underlying bare hardware –  I.e., all devices, interrupts, memory, page tables, etc.

•  VirtualizaYon has some performance impact –  Feasible with modern high-‐performance computers

•  Examples –  IBM VM/370 (1970s technology!) –  VMWare –  Xen (used by AWS) –  Microsoy Virtual PC

50

Randy’s Personal Experience VM/370, circa 1973

•  Summer internship @ CoNY Dept Welfare Service

•  VM/370: allows programmer to write channel programs, basically machine instrucYons (CCW—channel control words) to directly control I/O devices

•  Let’s try to ring the computer’s console bell •  Terminal log prints out the following: !!!!RRRR....RING....GGGG!!!!

4/21/11 Spring 2011 -‐-‐ Lecture #25 51 4/21/11 Spring 2011 -‐-‐ Lecture #25

Virtual Machines

•  Host Opera,ng System: – OS actually running on the hardware –  Together with virtualiza,on layer, it simulates environment for …

•  Guest Opera,ng System: – OS running in the simulated environment

•  The resources of the physical computer are shared to create the virtual machines –  Processor scheduling by OS can create the appearance that each user has own processor

– Disk parYYoned to provide virtual disks

52

4/20/11 Spring 2011 -‐-‐ Lecture #25

Virtual Machine Monitor

•  Maps virtual resources to physical resources – Memory, I/O devices, CPUs

•  Guest code runs on naYve machine in user mode – Traps to VMM on privileged instrucYons and access to protected resources

•  Guest OS may be different from host OS •  VMM handles real I/O devices – Emulates generic virtual I/O devices for guest

53 4/20/11 Spring 2011 -‐-‐ Lecture #25

Example: Timer VirtualizaYon

•  In naYve machine, on Ymer interrupt – OS suspends current process, handles interrupt, selects and resumes next process

•  With Virtual Machine Monitor –  VMM suspends current VM, handles interrupt, selects and resumes next VM

•  If a VM requires Ymer interrupts –  VMM emulates a virtual Ymer –  Emulates interrupt for VM when physical Ymer interrupt occurs

54

4/21/11

10

Spring 2011 -‐-‐ Lecture #25

Virtual Machine InstrucYon Set Support

•  Similar to what need for Virtual Memory •  User and System modes •  Privileged instrucYons only available in system mode –  Trap to system if executed in user mode

•  All physical resources only accessible using privileged instrucYons –  Including page tables, interrupt controls, I/O registers

•  Renaissance of virtualizaYon support –  Current ISAs (e.g., x86) adapYng, following IBM’s path

4/20/11 55

Agenda




•  Summary

4/20/11 56 Spring 2011 -‐-‐ Lecture #25

And in Conclusion, …

•  Virtual Memory, Paging really used for ProtecYon, TranslaYon, Some OS opYmizaYons – Not really rouYnely paging to disk – Can think of as another level of memory hierarchy, but not really used like caches

•  Virtual Machines as even greater level of protecYon to allow greater level of sharing – Enables fine control, allocaYon, pricing of Cloud CompuYng

4/20/11 Spring 2011 -‐-‐ Lecture #25 57

Peer InstrucYon: Match the Phrase Match the memory hierarchy element on the ley with the closest phrase on the right:

1. L1 cache a. A cache for page table entries

2. L2 cache b. A cache for a main memory

3. Main memory c. A cache for disks

4. TLB d. A cache for a cache

4/20/11 Spring 2011 -‐-‐ Lecture #24 58

RED) 1 a, 2 b, 3 c, 4 d PINK) 1 b, 2 d, 3 c, 4 a

ORG) 1 a, 2 b, 3 d, 4 c BLU) 1 d, 2 b, 3 a, 4 c

GRN) 1 b, 2 d, 3 a, 4 c PUR) 1 d, 2 a, 3 b, 4 c

TEAL) 1 d, 2 c, 3 b, 4 a

Peer InstrucYon: Match the Phrase Match the memory hierarchy element on the ley with the closest phrase on the right:

1. L1 cache a. A cache for page table entries

2. L2 cache b. A cache for a main memory

3. Main memory c. A cache for disks

4. TLB d. A cache for a cache

4/20/11 Spring 2011 -‐-‐ Lecture #24 59

A) 1 a, 2 b, 3 c, 4 d E) 1 b, 2 d, 3 c, 4 a

B) 1 a, 2 b, 3 d, 4 c F) 1 d, 2 b, 3 a, 4 c

C) 1 b, 2 d, 3 a, 4 c G) 1 d, 2 a, 3 b, 4 c

H) 1 d, 2 c, 3 b, 4 a

Peer InstrucYon: True or False A program tries to load a word X that causes a TLB miss but not a page fault. Which are True or False: 1. A TLB miss means that the page table does not contain a valid mapping for virtual page corresponding to the address X

2. There is no need to look up in the page table because there is no page fault

3. The word that the program is trying to load is present in physical memory.

4/20/11 Spring 2011 -‐-‐ Lecture #24 60

RED) 1 F, 2 F, 3 F PNK) 1 T, 2 F, 3 F

ORG) 1 F, 2 F, 3 T BLU) 1 T, 2 F, 3 T

GRN) 1 F, 2 T, 3 F PUR) 1 T, 2 T, 3 F

TEL) 1 T, 2 T, 3 T

4/21/11

11

Peer InstrucYon: True or False A program tries to load a word X that causes a TLB miss but not a page fault or protecYon violaYons. Which are True or False: 1. A TLB miss means that the page table does not contain a valid mapping for virtual page corresponding to the address X

2. There is no need to look up the page table because there is no page fault

3. The word that the program is trying to load is present in physical memory.

4/20/11 Spring 2011 -‐-‐ Lecture #24 61

A) 1 F, 2 F, 3 F E) 1 T, 2 F, 3 F

B) 1 F, 2 F, 3 T F) 1 T, 2 F, 3 T

C) 1 F, 2 T, 3 F G) 1 T, 2 T, 3 F

H) 1 T, 2 T, 3 T

Peer InstrucYon: True or False TLBs entries have valid bits and dirty bits. Data caches have them also. A. The valid bit means the same in both: if valid = 0, it must miss in both TLBs and Caches. B. The valid bit has different meanings. For caches, it means this entry is valid if the address requested matches the tag. For TLBs, it determines whether there is a page fault (valid=0) or not (valid=1). C. The dirty bit means the same in both: the data in this block in the TLB or Cache has been changed. D. The dirty bit has different meanings. For caches, it means the data block has been changed. For TLBs, it means that the page corresponding to this TLB entry has been changed.

4/20/11 Spring 2011 -‐-‐ Lecture #24 62

Red) 1 F, 2 T, 3 F, 4 T

Org) 1 F, 2 T, 3 T, 4 F

Grn) 1 T, 2 F, 3 F, 4 T

Peer InstrucYon: True or False TLBs entries have valid bits and dirty bits. Data caches have them also. A. The valid bit means the same in both: if valid = 0, it must miss in both TLBs and Caches. B. The valid bit has different meanings. For caches, it means this entry is valid if the address requested matches the tag. For TLBs, it determines whether there is a page fault (valid=0) or not (valid=1). C. The dirty bit means the same in both: the data in this block in the TLB or Cache has been changed. D. The dirty bit has different meanings. For caches, it means the data block has been changed. For TLBs, it means that the page corresponding to this TLB entry has been changed.

4/20/11 Spring 2011 -‐-‐ Lecture #24 63

A) 1 F, 2 T, 3 F, 4 T

B) 1 F, 2 T, 3 T, 4 F

C) 1 T, 2 F, 3 F, 4 T

Documents

Agenda - University of California, Berkeley