Afe 4490

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LED2 Data

Amb (LED2) Data

LED1 Data

Amb (LED1) Data

AFESPI

(LED2tAmb) Data

(LED1tAmb) Data

+

Buffer ADC+

TIA

+Stage2

Gain

Photodiode

CPD

DigitalFilter

Rx

SPI Interface

Diagnostic

PDOpen orShort

CableOff

LEDOpen orShort

LEDDriver

LED CurrentControlDAC

TimingController

OSC

8 MHz

DiagnosticSignals

AFE

LED

5-V Supply

Tx Driver

Supply

2.2-V Supply

LED2

AMBLED2

LED1

AMBLED1

Filter

A F E 44 90

www.ti.com SBAS602B DECEMBER 2012 REVISED FEBRUARY 2013

I n teg ra ted A na log Fro nt -E nd fo r P u lse O x im e te rsCheck for Samples:AFE4490

1FEATURES23 Fully-Integrated Analog Front-End for

Pulse Oximeter Applications: Package: Compact QFN-40 (6 mm 6 mm)

Flexible Pulse Sequencing and Specified Temperature Range: 40C to +85CTiming Control

APPLICATIONS Transmit: Medical Pulse Oximeter Applications Integrated LED Driver

(H-Bridge or Push/Pull) Industrial Photometry Applications

110-dB Dynamic Range Across Full RangeDESCRIPTION(Enables Low Noise at Low LED Current)The AFE4490 is a fully-integrated analog front-end LED Current:(AFE) that is ideally suited for pulse-oximeter

Programmable Ranges of 50 mA, 75 mA,applications. The device consists of a low-noise

100 mA, 150 mA, and 200 mA, receiver channel with a 22-bit analog-to-digitalEach with 8-Bit Current Resolution converter (ADC), an LED transmit section, and Low Power: diagnostics for sensor and LED fault detection. The

AFE4490 is a very configurable timing controller. This 100 A + Average LED Currentflexibility enables the user to have complete control of

LED On-Time Programmability from the device timing characteristics. To ease clocking(50 s + Settle Time) to 4 ms requirements and provide a low-jitter clock to the

Independent LED2 and LED1 Current AFE4490, an oscillator is also integrated thatfunctions from an external crystal. The deviceReferencecommunicates to an external microcontroller or host Receive Channel with High Dynamic Range:processor using an SPI interface.

Input-Referred Noise:The AFE4490 is a complete AFE solution packaged13 pARMS (0.1-Hz to 5-Hz Bandwidth)in a single, compact QFN-40 package (6 mm

13.5 Noise-Free Bits (0.1 Hz to 5 Hz)

6 mm) and is specified over the operating Analog Ambient Cancellation Scheme with temperature range of 40C to +85C.Selectable 1-A to 10-A Ambient Current

Low Power: < 2.3 mA at 3.0-V Supply

Rx Sample Time: 50 s to 250 s

I-V Amplifier with Seven Separate LED2 andLED1 Programmable Feedback R and CSettings

Integrated Digital Ambient Estimation andSubtraction

Integrated Fault Diagnostics:

Photodiode and LED Open and

Short Detection Cable On/Off Detection

Supplies:

Rx = 2.0 V to 3.6 V

Tx = 3.0 V or 5.25 V

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SPI is a trademark of Motorola.3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright 20122013, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does not

necessarily include testing of all parameters.
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A F E 44 90

SBAS602B DECEMBER 2012REVISED FEBRUARY 2013 www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

FAMILY AND ORDERING INFORMATION

OPERATINGLED DRIVE LED DRIVE CURRENT POWER SUPPLY TEMPERATURE

PRODUCT PACKAGE-LEAD CONFIGURATION (mA, max) (V) RANGE

AFE4490 QFN-40 Bridge, push-pull 50, 75, 100, 150, and 200 3 to 5.25 40C to +85C

AFE4400 QFN-40 Bridge, push-pull 50 3 to 3.6 0C to +70C

ABSOLUTE MAXIMUM RATINGS (1)

Over operating free-air temperature range, unless otherwise noted.

VALUE UNIT

AVDD to AVSS 0.3 to +7 V

DVDD to DGND 0.3 to +7 V

AGND to DGND 0.3 to +0.3 V

Analog input to AVSS AVSS 0.3 to AVDD + 0.3 V

Digital input to DVDD DVSS 0.3 to DVDD + 0.3 V

Input current to any pin except supply pins (2) 7 mA

Momentary 50 mAInput current

Continuous 7 mA

Operating temperature range 40 to +85 C

Storage temperature range, Tstg 60 to +150 C

Maximum junction temperature, TJ +125 C

Human body model (HBM)1000 V

JEDEC standard 22, test method A114-C.01, all pinsElectrostatic discharge(ESD) ratings Charged device model (CDM)

500 VJEDEC standard 22, test method C101, all pins

(1) Stresses beyond those listed underAbsolute Maximum Ratingsmay cause permanent damage to the device. These are stress ratingsonly, and do not imply functional operation of the device at these or any other conditions beyond those indicated underRecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing beyond the supply rails must be current-limitedto 10 mA or less.

THERMAL INFORMATIONAFE4490

THERMAL METRIC(1) RHA (QFN) UNITS

40 PINS

JA Junction-to-ambient thermal resistance 35

JCtop Junction-to-case (top) thermal resistance 31

JB Junction-to-board thermal resistance 26

C/WJT Junction-to-top characterization parameter 0.1

JB Junction-to-board characterization parameter N/A

JCbot Junction-to-case (bottom) thermal resistance N/A

(1) For more information about traditional and new thermal metrics, see theIC Package Thermal Metricsapplication report,SPRA953.

2 Submit Documentation Feedback Copyright 20122013, Texas Instruments Incorporated

Product Folder Links: AFE4490
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A F E 44 90


RECOMMENDED OPERATING CONDITIONS

Over operating free-air temperature range, unless otherwise noted.

PARAMETER VALUE UNIT

SUPPLIES

RX_ANA_SUP AFE analog supply 2.0 to 3.6 V

RX_DIG_SUP AFE digital supply 2.0 to 3.6 V

TX_CTRL_SUP Transmit controller supply 3.0 to 5.25 V

[3.0 or (1.4 + VLED+ VCABLE)(1)(2),

H-bridge configuration Vwhichever is greater] to 5.25

LED_DRV_SUP Transmit LED driver supplyCommon anode [3.0 or (1.3 + VLED+ VCABLE)

(1)(2),V

configuration whichever is greater] to 5.25

Difference between LED_DRV_SUP and TX_CTRL_SUP 0.3 to +0.3 V

TEMPERATURE

Specified temperature range 40 to +85 C

Storage temperature range 60 to +150 C

(1) VLEDrefers to the voltage drop across the external LED connected between the TXP and TXM pins (in H-bridge mode) and from theTXP and TXM pins to LED_DRV_SUP (in the common anode configuration).

(2) VCABLErefers to voltage drop across any cable, connector, or any other component in series with the LED.

Copyright 20122013, Texas Instruments Incorporated Submit Documentation Feedback 3

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N = log 2FBIPD

6.6 I NOISE

A F E 44 90


ELECTRICAL CHARACTERISTICS

Minimum and maximum specifications are at TA= 40C to +85C. Typical specifications are at +25C.

All specifications are at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and f CLK= 8 MHz,

unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PERFORMANCE (Full-Signal Chain)

RF= 10 k 50 A

RF= 25 k 20 A

RF= 50 k 10 A

IIN_FS Full-scale input current RF= 100 k 5 A

RF= 250 k 2 A

RF= 500 k 1 A

RF= 1 M 0.5 A

PRF Pulse repetition frequency 61 5000 SPS

DCPRF PRF duty cycle 25%

RF= 10 k 50 AIIN_FS Full-scale input current

RF= 1 M 0.5 A

PSRRLED PSRR, transmit LED driver With respect to ripple on LED_DRV_SUP 75 dB

PSRRTx PSRR, transmit control With respect to ripple on TX_CTRL_SUP 60 dB

With respect to ripple on RX_ANA_SUP andPSRRRx PSRR, receiver 60 dBRX_DIG_SUP

Total integrated noise current, input-referred RF= 100 k, PRF = 625 Hz, duty cycle = 5% 36 pARMS(receiver with transmitter loop back,

RF= 500 k, PRF = 625 Hz, duty cycle = 5% 13 pARMS0.1-Hz to 5-Hz bandwidth)

RF= 100 k, PRF = 625 Hz, duty cycle = 5% 14.3 BitsNoise-free bits (receiver with transmitter loopNFB back, 0.1-Hz to 5-Hz bandwidth)(1) RF= 500 k, PRF = 625 Hz, duty cycle = 5% 13.5 Bits

RECEIVER FUNCTIONAL BLOCK LEVEL SPECIFICATION

RF= 500 k, ambient cancellation enabled,stage 2 gain = 4, PRF = 1300 Hz, 1.4 pARMSLED duty cycle = 25%Total integrated noise current, input-referred

(receiver alone) over 0.1-Hz to 5-Hz bandwidth RF= 500 k, ambient cancellation enabled,stage 2 gain = 4, PRF = 1300 Hz, 5 pARMSLED duty cycle = 5%

I-V TRANSIMPEDANCE AMPLIFIER

See the Receiver ChannelsectionG Gain RF= 10 kto RF = 1 M V/Afor details

Gain accuracy 7%

10k, 25k, 50k, 100k, 250k,Feedback resistance RF 500k, and 1M

Feedback resistor tolerance RF 7%

Feedback capacitance CF 5, 10, 25, 50, 100, and 250 pF

Feedback capacitor tolerance CF 20%

VOD(fs) Full-scale differential output voltage 1 V

Common-mode voltage on input pins Set internally 0.9 V

Includes equivalent capacitance ofExternal differential input capacitance 10 1000 pF

photodiode, cables, EMI filter, and so forth

With a 1-kseries resistor and a 10-nFVO(shield) Shield output voltage, VCM 0.9 V

decoupling capacitor to ground

(1) Noise-free bits (NFB) are defined as:

Where:IPDis the photodiode current, and INOISE is the input-referred RMS noise current.



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A F E 44 90


ELECTRICAL CHARACTERISTICS (continued)





AMBIENT CANCELLATION STAGE

G Gain 1, 1.5, 2, 3, and 4 V/V

Current DAC range 0 10 A

Current DAC step size 1 A

LOW-PASS FILTER

Low-pass corner frequency 3-dB attenuation 0.5 and 1 kHz

Duty cycle = 25% 0.004 dBPass-band attenuation, 2 Hz to 10 Hz

Duty cycle = 10% 0.041 dB

ANALOG-TO-DIGITAL CONVERTER

Resolution 22 Bits

See theADC Operation and AveragingSample rate 4 PRF SPS

Modulesection

ADC full-scale voltage 1.2 V

See theADC Operation and AveragingADC conversion time 50 PRF / 4 s

ModulesectionADC reset time 2 tCLK

TRANSMITTER

0, 50, 75, 100, 150, and 200Output current range (see theLEDCNTRL: LED Control mA

Registerfor details)

LED current DAC error 5%

Output current resolution 8 Bits

At 25-mA output current 110 dBTransmitter noise dynamic range,over 0.1-Hz to 5-Hz bandwidth At 100-mA output current 110 dB

Minimum sample time of LED1 and LED250 s

pulses

LED_ON = 0 1 ALED current DAC leakage current

LED_ON = 1 50 A

LED current DAC linearity Percent of full-scale current 0.5%

From zero current to 150 mA 7 sOutput current settling time(with resistive load) From 150 mA to zero current 7 s

DIAGNOSTICS

EN_SLOW_DIAG = 0Start of diagnostics after the DIAG_ENregister bit is set. 8 msEnd of diagnostic indicated by DIAG_ENDgoing high.

Duration of diagnostics state machineEN_SLOW_DIAG = 1Start of diagnostics after the DIAG_ENregister bit is set. 16 msEnd of diagnostic indicated by DIAG_ENDgoing high.

Open fault resistance > 100 k

Short fault resistance < 10 k



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A F E 44 90







INTERNAL OSCILLATOR

With an 8-MHz crystal connected to the XINfCLKOUT CLKOUT frequency 4 MHzand XOUT pins

DCCLKOUT CLKOUT duty cycle 50%

With an 8-MHz crystal connected to the XINCrystal oscillator start-up time 200 s

and XOUT pins

EXTERNAL CLOCK

Maximum allowable external clock jitter 50 ps

TIMING

Wake-up time from complete power-down 1000 ms

tRESET Active low RESET pulse duration 1 s

DIAG_END pulse duration at diagnostics CLKOUTtDIAGEND 4completion cycles

CLKOUTtADCRDY ADC_RDY pulse duration 1 cycles

DIGITAL SIGNAL CHARACTERISTICS

AFE_PDN, SPI CLK, SPI SIMO, SPI STE,VIH Logic high input voltage 0.75 RX_DIG_SUP VRESET

AFE_PDN, SPI CLK, SPI SIMO, SPI STE,VIL Logic low input voltage 0.25 RX_DIG_SUP VRESET

IIN Logic input current Digital inputs at VIH or VIL 0.1 A

DIAG_END, LED_ALM, PD_ALM, SPI SOMI,VOH Logic high output voltage RX_DIG_SUP 0.1 VADC_RDY, CLKOUT

DIAG_END, LED_ALM, PD_ALM, SPI SOMI,VOL Logic low output voltage 0.1 VADC_RDY, CLKOUT

SUPPLY CURRENT

RX_ANA_SUP = 3.0 V, with 8-MHz clock0.6 mA

running, Rx stage 2 disabledReceiver analog supply current

RX_ANA_SUP = 3.0 V, with 8-MHz clock0.7 mA

running, Rx stage 2 enabled

Receiver digital supply current RX_DIG_SUP = 3.0 V 0.27 mA

LED_DRVLED driver supply current With zero LED current setting 55 A

_SUP

TX_CTRLTransmitter control supply current 15 A

_SUP

Receiver current only5 A

(RX_ANA_SUP + RX_DIG_SUP)Complete power-down(using the AFE_PDN pin) Transmitter current only

2 A(LED_DRV_SUP + TX_CTRL_SUP)

Receiver current onlyPower-down Rx alone 220 A

(RX_ANA_SUP + RX_DIG_SUP)

Transmitter current onlyPower-down Tx alone 2 A

(LED_DRV_SUP + TX_CTRL_SUP)



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A F E 44 90







POWER DISSIPATION

Normal operation (excluding LEDs) 1.54 mWPD(q) Quiescent power dissipation

Power-down 0.1 W

LED_DRV_SUP current value.LED_DRV_SUP 1 A

Does not include LED current.

Power-down with the TX_CTRL_SUP 1 AAFE_PDN pin

RX_ANA_SUP 5 A

RX_DIG_SUP 0.1 A



Power-down with the TX_CTRL_SUP 1 APDNAFE register bit

RX_ANA_SUP 15 A

RX_DIG_SUP 20 A



TX_CTRL_SUP 15 APower-down Rx

RX_ANA_SUP 220 A

RX_DIG_SUP 220 A



TX_CTRL_SUP 2 APower-down Tx

RX_ANA_SUP 600 A

RX_DIG_SUP 230 A



After reset, with 8-MHz TX_CTRL_SUP 15 Aclock running

RX_ANA_SUP 600 A

RX_DIG_SUP 230 A

LED_DRV_SUP current value.LED_DRV_SUP 0.28 A

Does not include LED current.With stage 2 mode

TX_CTRL_SUP 0.1 Aenabled and 8-MHz clockrunning RX_ANA_SUP 700 A

RX_DIG_SUP 0.8 A



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A7 A6 A1 A0

SPISTE

SPISIMO

SCLK

'RQW FDUH, can be high or low.

D23 D22 D17 D16 D15 D14 D9 D8 D7 D6 D1 D0SPISOMI

~ ~ ~ ~ ~ ~CLK

tCLK

tDATA

tSCLK

tDECODE

tDOHD

A F E 44 90


PARAMETRIC MEASUREMENT INFORMATION

SERIAL INTERFACE TIMING

(1) The SPI_READ register bit must be enabled before attempting a serial readout from the AFE.

(2) Specify the register address whose contents must be read back on A[7:0].

(3) The AFE outputs the contents of the specified register on the SOMI pin.

Figure 1. Serial Interface Timing Diagram(1)(2)(3)

Table 1. Timing Requirements forFigure 1

2.0 V RX_DIG_SUP 3.6 VPARAMETER UNIT

MIN TYP MAX

fSPICLK SPI CLK frequency 8 MHz

tSPI_SU SPISIMO input data setup time with respect to SCLK rising edge 62.5 ns

tSPI_HO SPISIMO input data hold time with respect to SCLK rising edge 62.5 ns

tSOMI_VAL SPISOMI output data setup time tSPICLK/ 4 ns

tSOMI_HO SPISOMI output data hold time tSPICLK/ 2 ns

tRISE Rise time from 20% to 80% 5 ns

tFALL Fall time from 80% to 20% 5 ns



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INN

INP

RX_ANA_GND

VCM

DNC(1)

DNC

BG

VSS

TX_REF

DNC

CLKOUT

RESET

ADC_RDY

SPISTE

SPISIMO

SPISOMI

SCLK

PD_ALM/ADC Reset

LED_ALM

DIAD_END

1

2

3

4

5

6

7

8

9

10

30

29

28

27

26

25

24

23

22

21

TX

_CTRL

_SUP

11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31

RX

_ANA

_GN

LED

_D

RV

_GND

RX

_ANA

_SUP

LED

_D

RV

_GND

XIN

TXN

XOUT

TXP

RX

_ANA

_GN

LED

_D

RV

_GND

RXOUTP

LED

_D

RV

_SUP

RXOUTN

LED

_D

RV

_SUP

RX

_ANA

_SUP

RX

_DIG

_GND

RX

_DIG

_GND

AFE

_PDN

RX

_DIG

_GND

A F E 44 90


PIN CONFIGURATION

RHA PACKAGEQFN-40

(Top View)

(4) DNC = Do not connect.

PIN DESCRIPTIONSNAME NO. FUNCTION DESCRIPTION

Output signal that indicates ADC conversion completion.ADC_RDY 28 Digital

Can be connected to the interrupt input pin of an external microcontroller.

AFE-only power-down input; active low.AFE_PDN 20 Digital

Can be connected to the port pin of an external microcontroller.

Decoupling capacitor for internal band-gap voltage to ground.BG 7 Reference

(2.2-F decoupling capacitor to ground, expected voltage = 1.0 V.)

Buffered 4-MHz output clock output.CLKOUT 30 Digital

Can be connected to the clock input pin of an external microcontroller.

Output signal that indicates completion of diagnostics.DIAG_END 21 Digital


DNC (1) 5, 6 , 10 Do n ot c onn ec t the se p in s. L eav e a s o pen -c ircu it.

INN 1 Analog Receiver input pin. Connect to photodiode anode.

INP 2 Analog Receiver input pin. Connect to photodiode cathode.

LED_DRV_GND 12, 13, 16 Supply LED driver ground pin, H-bridge. Connect to common board ground.

LED driver supply pin, H-bridge. Connect to an external power supply capable of supplying theLED_DRV_SUP 17, 18 Supply

large LED current, which is drawn by this supply pin.

Output signal that indicates an LED cable fault.LED_ALM 22 Digital


(1) Leave pins as open circuit. Do not connect.



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A F E 44 90


PIN DESCRIPTIONS (continued)

NAME NO. FUNCTION DESCRIPTION

Output signal that indicates a PD sensor or cable fault.PD_AL M/ADC Rese t 23 Dig ital Can be co nne cted to the po rt p in o f a n ex terna l mic ro con trol le r.

In ADC bypass mode, the PD_ALM pin can be used to bring out the ADC reset signal.

AFE-only reset input, active low.RESET 29 Digital


RX_ ANA_GND 3, 3 6, 4 0 Su pp ly Rx a na log g ro und p in. Con ne ct to c ommon b oard grou nd.

RX_ANA_SUP 33, 39 Supply Rx analog supply pin (2.0 V to 3.6 V); 0.1-F decoupling capacitor to ground

RX_ DIG_ GND 1 9, 3 2 Su pp ly Rx d ig ital g ro und p in . Con ne ct to c ommon b oard grou nd.

RX_ DIG_ SUP 31 Su pp ly Rx d ig ital s upp ly p in (2.0 V to 3 .6 V); 0.1-F de co up li ng c ap aci to r to g ro un d

RXOUTN 34 Analog External ADC negative input when in ADC bypass mode

RXOUTP 35 Analog External ADC positive input when in ADC bypass mode

SCLK 24 SPI SPI clock pin

SPISIMO 26 SPI SPI serial in master out

SPISOMI 25 SPI SPI serial out master in

SPISTE 27 SPI SPI serial interface enable

TX _CTRL_ SUP 11 Su pp ly Tran smit co ntro l s up ply pi n, 5 V (0.1- F de co up li ng ca pac itor to g rou nd)

TX_REF 9 Reference Tx reference voltage

TXN 14 Analog LED driver out B, H-bridge output. Connect to LED.TXP 15 Analog LED driver out B, H-bridge output. Connect to LED.

Input common-mode voltage output.Connect a series resistor (1 k) and a decoupling capacitor (10 nF) to ground.

VCM 4 ReferenceThe voltage across the capacitor can be used to shield (guard) the INP, INM traces.Expected voltage = 0.9 V.

VSS 8 Supply Substrate ground. Connect to common board ground.

Crystal oscillator pins.X OUT 37 Dig ital Conn ect a n e xterna l 8 -MHz c ry stal b etwee n the se p in s with the c orre ct lo ad ca pac itor

(as specified by vendor) to ground.

Crystal oscillator pins.XIN 38 Digital Connect an ext ernal 8-MHz crystal bet ween t hese pins with t he correct load capacitor

(as specified by vendor) to ground.



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0

100

200

300

400

500

600

700

0 10 20 30 40 50

InputReferredNoiseCurrent

pArmsin5HzBandwidth

Pleth Current (A)

Duty Cycle = 1%

Duty Cycle = 5%

Duty Cycle = 10%

Duty Cycle = 15%

Duty Cycle = 20%

Duty Cycle = 25%

C005

For each setting RF adjusted for Full-Scale Output.

Amb Cancellation & stage 2 Gain = 4 used for Low

Pleth currents (0.125uA, 0.25uA & 0.5uA).

Noise is calculated in 5Hz B/W. 0

100

200

300

400

500

600

700

0 10 20 30 40 50

InputReferredNoiseCurrent

pArmsin5HzBandwidth

Pleth Current (A)

Duty Cycle = 1%

Duty Cycle = 5%

Duty Cycle = 10%

Duty Cycle = 15%

Duty Cycle = 20%

Duty Cycle = 25%

C006



Pleth currents (0.125uA, 0.25uA & 0.5uA.)

Noise is calculated in 5Hz band.

46.0

46.2

46.4

46.6

46.8

47.0

47.2

47.4

47.6

47.8

48.0

3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

LED_

DRV_

SUP

Current(A)

LED_DRV_SUP Voltage (V) C003

With LED Current = 0mA0

100

200

300

400

500

600

0 10 20 30 40 50

InputReferredNoiseCurrent,

pArmsin5HzBandwidth

Pleth Current (A)

Duty Cycle = 1%Duty Cycle = 5%

Duty Cycle = 10%

Duty Cycle = 15%

Duty Cycle = 20%

Duty Cycle = 25%

C004




Noise is calculated in 5Hz B/W.

400

500

600

700

800

900

2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6

RX

AnalogCurrent(A)

RX Supply Voltage (V)

Stage 2 & Amb Cancel Disabled

Stage 2 & Amb Cancel Enabled

C001

PRF = 600HzStage 2 Gain = 4

RX_ANA_SUP = Rx_DIG_SUP

14.65

14.70

14.75

14.80

14.85

14.90

14.95

15.00

3.0 3.5 4.0 4.5 5.0

TX_

CTRL_

SUP

Current(A)

TX_CTRL_SUP Voltage (V) C002

PRF = 600Hz

A F E 44 90


TYPICAL CHARACTERISTICSAt TA= +25C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and fCLK= 8 MHz, unless

otherwise noted.

Figure 2. TOTAL Rx CURRENT vs VOLTAGE Figure 3. TX_CTRL_SUP CURRENT vs VOLTAGE

Figure 4. LED_DRV_SUP CURRENT vs VOLTAGE Figure 5. INPUT-REFERRED NOISE CURRENT vsPLETH CURRENT (PRF = 100 Hz) (1)

Figure 6. INPUT-REFERRED NOISE CURRENT vs Figure 7. INPUT-REFERRED NOISE CURRENT vsPLETH CURRENT (PRF = 300 Hz) PLETH CURRENT (PRF = 600 Hz)

(1) Data at PRF = 625 Hz, 5% duty cycle.



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10

11

12

13

14

15

16

0 10 20 30 40 50

Noise-FreeBitsin5HzBandwidth

Pleth Current (A)

Duty Cycle = 1%

Duty Cycle = 5%

Duty Cycle = 10%

Duty Cycle =15%

Duty Cycle = 20%

Duty Cycle = 25%

C011


Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA).

RMS noise is calculated in 5Hz B/W & NFB is calculated using 6.6 uRMS noise.

10

11

12

13

14

15

16

0 10 20 30 40 50


Pleth Current (A)

Duty Cycle = 1%

Duty Cycle = 5%

Duty Cycle = 10%

Duty Cycle =15%

Duty Cycle = 20%

Duty Cycle = 25%

C012


Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA).


10

11

12

13

14

15

16

0 10 20 30 40 50


Pleth Current (A)

Duty Cycle = 1%

Duty Cycle = 5%

Duty Cycle = 10%

Duty Cycle =15%

Duty Cycle = 20%

Duty Cycle = 25%

C009

For each setting RF adjusted for Full-Scale Output.Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA).


10

11

12

13

14

15

16

0 10 20 30 40 50


Pleth Current (A)

Duty Cycle = 1%

Duty Cycle = 5%

Duty Cycle = 10%

Duty Cycle =15%

Duty Cycle = 20%

Duty Cycle = 25%

C010

For each setting RF adjusted for Full-Scale Output.Amb Cancellation & stage 2 Gain = 4 used for Low pleth currents (0.125uA, 0.25uA & 0.5uA.)


0

100

200

300

400

500

600

700

800

0 10 20 30 40 50

InputReferredNoiseCu

rrent,

pArmsin5HzBandwidth

Pleth Current ( A)

Duty Cycle = 1%

Duty Cycle = 5%

Duty Cycle = 10%


Duty Cycle = 25%

C007

For each RF adjusted for Full-Scale Output.




0

200

400

600

800

1000

1200

1400

0 10 20 30 40 50

InputReferredNoiseCu

rrent,

pArmsin5HzBandwidth

Pleth Current ( A)

Duty Cycle = 1%

Duty Cycle = 5%

Duty Cycle = 10%


Duty Cycle = 25%

C008


Amb Cancellation & stage 2 Gain = 4 used for

Low Pleth currents (0.125uA, 0.25uA & 0.5uA).


A F E 44 90


TYPICAL CHARACTERISTICS (continued)At TA= +25C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and fCLK= 8 MHz, unless

otherwise noted.

Figure 8. INPUT-REFERRED NOISE CURRENT vs Figure 9. INPUT-REFERRED NOISE CURRENT vsPLETH CURRENT (PRF = 1200 Hz) PLETH CURRENT (PRF = 2500 Hz)

Figure 10. NOISE-FREE BITS vs Figure 11. NOISE-FREE BITS vsPLETH CURRENT (PRF = 100 Hz) PLETH CURRENT (PRF = 300 Hz)

Figure 12. NOISE-FREE BITS vs Figure 13. NOISE-FREE BITS vsPLETH CURRENT (PRF = 1200 Hz)PLETH CURRENT (PRF = 600 Hz) (2)

(2) Data at PRF = 625 Hz, 5% duty cycle.


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500

400

300

200

100

0

100

200

300

400

500

0 50 100 150 200 250

DACS

tepError(uA)

TX LED DAC Setting C017

TX_REF = 0.5V 0

20

40

60

80

100

0 50 100 150 200 250

TXCurrent(mA)

TX LED DAC Setting

Expected + 1%

Expected 1%

Actual DAC Current

C018

TX Reference Voltage = 0.5V

500

400

300

200

100

0

100

200

300

400500

0 50 100 150 200 250

DACS

tepError(uA)


TX_REF = 0.5V500

400

300

200

100

0

100

200

300

400500

0 50 100 150 200 250

DACS

tepError(uA)


TX_REF = 0.5V

10

11

12

13

14

15

0 10 20 30 40 50


Pleth Current (A)

Duty Cycle = 1%Duty Cycle = 5%Duty Cycle = 10%Duty Cycle = 15%Duty Cycle = 20%Duty Cycle = 25%

C013

For each setting RF adjusted for Full-

Scale Output.

Amb Cancellation & stage 2 Gain = 4

used for Low Pleth currents (0.125uA,

0.25uA & 0.5uA).

RMS noise is calculated in 5Hz B/W &

NFB is calculated using 6.6 uRMS noise.

50

60

70

80

90

100

110

120

0 20 40 60 80 100

TXDynamicRange(d

B)

% of Full-Scale LED Current

100mA Range

150mA Range

200mA Range

C014

A F E 44 90



otherwise noted.

Figure 14. NOISE-FREE BITS vs Figure 15. Tx DYNAMIC RANGEPLETH CURRENT (PRF = 2500 Hz)

Figure 16. DAC CURRENT STEP vs Figure 17. DAC CURRENT STEP vsTx LED SETTING (Tx Range = 200 mA) Tx LED SETTING (Tx Range = 150 mA)

Figure 18. DAC CURRENT STEP vs Figure 19. Tx CURRENT LINEARITY (100-mA Range)Tx LED SETTING (Tx Range = 100 mA)



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0

200

400

600

800

1000

1200

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

NumberofOccurences

LED Current (mA)

C023

TX_RANGE = 150mA,Data from 7737 devices

0

200

400

600

800

1000

1200

135

137

139

141

143

145

147

149

151

153

155

157

159

161

163

165

NumberofOccurences

LED Current (mA)C024


0

200

400

600

800

88.4

8.8

9.2

9.6 1

0

10.4

10.8

11.2

11.6 1

2

NumberofOccurences

LED Current (mA)C021


0

200

400

600

800

1000

1200

1400

1600

1800

2000

2200

30

31

32

33

34

35

36

37

38

39

40

NumberofOccurences

LED Current (mA)

C022


0

20

40

60

80

100

120

140

160

0 50 100 150 200 250

TXCurrent(mA)

TX LED DAC Setting

Expected + 1%

Expected 1%

Actual DAC Current

C019

TX Reference Voltage = 0.75V0

20

40

60

80

100

120

140

160

180

200

0 50 100 150 200 250

TXCurrent(mA)

TX LED DAC Setting

Expected + 1%

Expected 1%

Actual DAC Current

C020

TX Reference Voltage = 1.0V

A F E 44 90



otherwise noted.

Figure 20. Tx CURRENT LINEARITY (150-mA Range) Figure 21. Tx CURRENT LINEARITY (200-mA Range)

Figure 22. LED CURRENT WITH Figure 23. LED CURRENT WITHTx DAC SETTING = 17 (10 mA) Tx DAC SETTING = 60 (35 mA)

Figure 24. LED CURRENT WITH Figure 25. LED CURRENT WITHTx DAC SETTING = 120 (70 mA) Tx DAC SETTING = 255 (150 mA)



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Device

Digital

Filter

SPI

+

Buffer 4GADC+

TIA

+Stage 2

Gain

Photodiode

CPDFilter

SPIInterface

Diagnostics

Timing

Controller

OSC

8 MHz

Diagnostic

Signals

INN

INP

RX_

ANA_

GND

VCM

DNC(1)

DNC(1)

BG

VSS

TX_

REF

TX_

CTRL_

SUP

LED_

DRV_

GND

LED_

DRV_

GND

TXN

TXP

LED_

DRV_

GND

LED_

DRV_

SUP

LED_

DRV_

SUP

RX_

DIG_

GND

AFE_PDN

DIAG_END

LED_ALM

PD_ALM/ADC Reset

SPICLK

SPISOMI

SPISIMO

SPISTE

ADC_RDY

RESET

CLKOUT

RX_

DIG_

SUP

RX_

DIG_

GND

RX_

ANA_

SUP

RXOUTN

RXOUTP

RX_

ANA_

GND

XOUT

XIN

RX_

ANA_

SUP

RX_

ANA_

GND

DNC(1)

Control

ReferenceCF

CF

RF

RF

LED

Driver

LED Current

Control DAC

LED

CF

A F E 44 90


OVERVIEW

The AFE4490 is a complete analog front-end (AFE) solution targeted for pulse-oximeter applications. The deviceconsists of a low-noise receiver channel, an LED transmit section, and diagnostics for sensor and LED faultdetection. To ease clocking requirements and provide the low-jitter clock to the AFE, an oscillator is alsointegrated that functions from an external crystal. The device communicates to an external microcontroller or hostprocessor using an SPI interface. Figure 26 shows a detailed block diagram for the AFE4490. The blocks aredescribed in more detail in the following sections.

Figure 26. Detailed Block Diagram


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R CF FRx Sample Time

10

LED2

SLED2 CONVLED2

Amb

Amb

SLED1_amb

SLED1

SLED2_amb

CONVLED1

CONVLED2_amb

CONVLED1_amb

LED1

Rx

Ambient-cancellation current can be set digitally using SPI interface.

CF

CF

RF

RF

CPD

+TIA

+Stage 2

Gain

RF

RF

+Buffer ADC

ADC

ADC Clock

ADC Convert

ADC Output Rate

PRF Sa/sec

I-V Amplifier Amb cancellation DAC BufferFilter ADC

Ambient

DAC

A F E 44 90


RECEIVER CHANNEL

This section describes the receiver channel functionality.

Receiver Front-End

The receiver consists of a differential current-to-voltage (I-V) transimpedance amplifier that converts the inputphotodiode current into an appropriate voltage, as shown inFigure 27. The feedback resistor of the amplifier (R

F)

is programmable to support a wide range of photodiode currents. Available R F values include: 1 M, 500 k,250 k, 100 k, 50 k, 25 k, and 10 k.

Figure 27. Receiver Front-End

The RF amplifier and the feedback capacitor (CF) form a low-pass filter for the input signal current. Always ensurethat the low-pass filter has sufficiently high bandwidth (as shown by Equation 1) because the input currentconsists of pulses. For this reason, the feedback capacitor is also programmable. Available C F values include:5 pF, 10 pF, 25 pF, 50 pF, 100 pF, and 250 pF. Any combination of these capacitors can also be used.

(1)

The output voltage of the I-V amplifier includes the pleth component (the desired signal) and a componentresulting from the ambient light leakage. The I-V amplifier is followed by the second stage, which consists of acurrent digital-to-analog converter (DAC) that sources the cancellation current and an amplifier that gains up thepleth component alone. The amplifier has five programmable gain settings: 1, 1.5, 2, 3, and 4. The gained-uppleth signal is then low-pass filtered (500-Hz bandwidth) and buffered before driving a 22-bit ADC. The currentDAC has a cancellation current range of 10 A with 10 steps (1 A each). The DAC value can be digitally

specified with the SPI interface.

The output of the ambient cancellation amplifier is separated into LED2 and LED1 channels. When LED2 is on,the amplifier output is filtered and sampled on capacitor CR. Similarly, the LED1 signal is sampled on the CLED1capacitor when LED1 is ON. In between the LED2 and LED1 pulses, the idle amplifier output is sampled toestimate the ambient signal on capacitors CLED2_amband CLED1_amb.

The sampling duration is termed the Rx sample time and is programmable for each signal, independently.Sampling can start after the I-V amplifier output is stable (to account for LED and cable settling times). The Rxsample time is used for all dynamic range calculations; the minimum time supported is 50 s.


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Device

Digital Control for Ambient-Cancellation DAC

RxDigital

LED2 Data

ADC Output RatePRF Samples per Second

Ambient (LED2)Data

LED1 Data

Ambient (LED1)Data

SPIBlock

SPIInterface

Host Processor

Ambient Estimation Block

Ambient information is available in the host

processor.

The processor can:

* Read ambient data

* Estimate ambient value tobe cancelled

* Set the value to be used by the ambientcancellation DAC using the SPI of AFE

Front End

(LED2 Ambient)Data

(LED1Ambient)Data

ADC

A F E 44 90


A single, 22-bit ADC converts the sampled LED2, LED1, and ambient signals sequentially. Each conversiontakes a maximum of 25% of the pulse repetition period (PRP) and provides a single digital code at the ADCoutput. As discussed in theReceiver Timingsection, the conversions are staggered so that the LED2 conversionstarts after the end of the LED2 sample phase, and so on. This configuration also means that the Rx sampletime for each signal is no greater than 25% of the pulse repetition period.

Note that four data streams are available at the ADC output (LED2, LED1, ambient LED2, and ambient LED1) at

the same rate as the pulse repetition frequency. The ADC is followed by a digital ambient subtraction block thatadditionally outputs the (LED2 ambient LED2) and (LED1 ambient LED1) data values.

Ambient Cancellation Scheme

The receiver provides digital samples corresponding to ambient duration. The host processor (external to theAFE) can use these ambient values to estimate the amount of ambient light leakage. The processor must thenset the value of the ambient cancellation DAC using the SPI, as shown inFigure 28.

Figure 28. Ambient Cancellation Loop (Closed by the Host Processor)



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V = 2DIFF

IPLETH

RF

RI

+ IAMB

RF

RI

ICANCEL

RG

Rf

Cf

Rf

Cf

x

VDIFF

Ri

Ri

Rg

Rg

IPLETH+ IAMB

ICANCEL

Value of ICANCELset using

the SPI interface.

ICANCEL

A F E 44 90


Using the set value, the ambient cancellation stage subtracts the ambient component and gains up only the plethcomponent of the received signal, as shown inFigure 29.

The amplifier gain is programmable to 1, 1.5, 2, 3, and 4.

Figure 29. Front-End (I-V Amplifier and Cancellation Stage)

The differential output of the second stage is VDIFF, as given byEquation 2:

Where:

RI= 100 k,

IPLETH= photodiode current pleth component,

IAMB= photodiode current ambient component, and

ICANCEL= the cancellation current DAC value (as estimated by the host processor). (2)



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A F E 44 90


Receiver Control Signals

LED2 sample phase (SLED2): When this signal is high, the amplifier output corresponds to the LED2 on-time.The amplifier output is filtered and sampled into capacitor CLED2. To avoid settling effects resulting from the LEDor cable, program SLED2to start after the LED turns on. This settling delay is programmable.

Ambient sample phase (SLED2_amb):When this signal is high, the amplifier output corresponds to the LED2 off-time and can be used to estimate the ambient signal (for the LED2 phase). The amplifier output is filtered andsampled into capacitor CLED2_amb.

LED1 sample phase (SLED1): When this signal is high, the amplifier output corresponds to the LED1 on-time.The amplifier output is filtered and sampled into capacitor CLED1. To avoid settling effects resulting from the LEDor cable, program SLED1to start after the LED turns on. This settling delay is programmable.

Ambient sample phase (SLED1_amb):When this signal is high, the amplifier output corresponds to the LED1 off-time and can be used to estimate the ambient signal (for the LED1 phase). The amplifier output is filtered andsampled into capacitor CLED1_amb.

LED2 convert phase (CONVLED2): When this signal is high, the voltage sampled on CLED2 is buffered andapplied to the ADC for conversion. The conversion time duration is always 25% of the pulse repetition period. Atthe end of the conversion, the ADC provides a single digital code corresponding to the LED2 sample.

Ambient convert phases (CONVLED2_amb, CONVLED1_amb): When this signal is high, the voltage sampled on

CLED2_amb (or CLED1_amb) is buffered and applied to the ADC for conversion. The conversion time duration isalways 25% of the pulse repetition period. At the end of the conversion, the ADC provides a single digital codecorresponding to the ambient sample.

LED1 convert phase (CONVLED1): When this signal is high, the voltage sampled on CLED1 is buffered andapplied to the ADC for conversion. The conversion time duration is always 25% of the pulse repetition period. Atthe end of the conversion, the ADC provides a single digital code corresponding to the LED1 sample.

Receiver Timing

SeeFigure 30for a timing diagram detailing the control signals related to the LED on-time, Rx sample time, andthe ADC conversion times for each channel.



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Photodiode Current

Or

I-V Output

Ambient Level

(Dark Level)

SR,Sample RED

SR_amb,

Sample Ambient(RED Phase)

CONVR,RED ADC Converts

(REDAmbient)

SIR,Sample IR

SIR_amb,Sample Ambient

(IR Phase)

CONVIR,IR ADC Converts

(IR Ambient)

Plethysmograph Signal

ADCLKR,Red ADC

Sample Clock

ADCLKIR,IR ADC

Sample Clock

RED

N

RED

N+1

RED ADCOutput Data

IR

N-1

IR

N

N

N+2

N+1

N

N+1

IR ADCOutput Data

A F E 44 90


NOTE: Relationship to the AFE4490EVM is: LED1 = IR and LED2 = RED.

Figure 30. Rx Timing Diagram


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8-MHz Crystal

Timer

Module

Diagnostics

Module

ADC

Oscillator

Divide-

by-2

CLKOUT

4 MHz

XIN XOUT

A F E 44 90


CLOCKING AND TIMING SIGNAL GENERATION

The crystal oscillator generates a master clock signal using an external 8-MHz crystal. A divide-by-2 blockconverts the 8-MHz clock to 4 MHz, which is used by the AFE to operate the timer modules, ADC, anddiagnostics. The 4-MHz clock is buffered and output from the AFE in order to clock an external microcontroller.The clocking functionality is shown inFigure 31.

Figure 31. AFE Clocking

TIMER MODULE

See Figure 32 for a timing diagram detailing the various timing edges that are programmable using the timer

module. The rising and falling edge positions of 11 signals can be controlled. The module uses a single 16-bitcounter (running off of the 4-MHz clock) to set the time-base.

All timing signals are set with reference to the pulse repetition period (PRP). Therefore, a dedicated compareregister compares the 16-bit counter value with the reference value specified in the PRF register. Every time thatthe 16-bit counter value is equal to the reference value in the PRF register, the counter is reset to '0'.



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LED1 (IR LED)

On Signal

LED2 (RED LED)On Signal

tLED LED on-time

d0.25 T.

Rx sample time = tLEDsettle time.

0

T

0.2

5

T

0.5

0

T

0.7

5

T

1.0

T

ADC Conversion

Pulse Repetition PeriodT = 1 / PRF

ADC Reset

ADC_RDY Pin

CONVLED1_amb,Convert Ambient Sample

[LED1 (IR) Phase]

CONVLED1,

Convert LED1 (IR) Sample


[LED2 (RED) Phase]

CONVLED2,Convert LED2 (RED) Sample

SLED2,Sample LED2 (RED)

SLED2_amb,Sample Ambient

[LED2 (RED) Phase]

SLED1,Sample LED1 (IR)


[LED1 (IR) Phase]

A F E 44 90


NOTE: Programmable edges are shown in blue and red.

Figure 32. AFE Control Signals


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Timer Compare16-Bit Register 11

16-Bit Counter


Start

Stop


StartStop


Start

Stop


Start

Stop


Start

Stop

Timer Compare

16-Bit Register 6

Start

Stop

Timer Compare16-Bit PRF Register

PRFPulse


StartStop


Start

Stop


Start

Stop


Start

Stop

START-A

STOP-A

START-B

STOP-B

START-C

STOP-D

START-D

STOP-D

RED LEDS

R

IR LED SR

SRSample RED

S

R

S

R

S

R

S

R

SR

S

R

S

R

S

R

ResetCounter

Reset

SIRSample IR

SR_amb,Sample Ambient

(red phase)

SIR_amb,

Sample Ambient(IR phase)

CONVR,Convert RED Sample

CONVIR,Convert IR Sample

CONVIR_amb,Convert Ambient Sample(IR Phase)

CONVR_amb,Convert Ambient Sample(RED Phase)

ADCConversion

Timer Module

Enable

En

En

En

En

En

En

En

En

En

En

En

En

CLKIN

Reset

Enable

START

STOP

Set

ResetEnable

Timer Compare Register

Start Reference Register

Stop Reference Register

CounterInput

utputSignal

A F E 44 90


For the 11 signals in Figure 30, the start and stop edge positions are programmable with respect to the PRFperiod. Each signal uses a separate timer compare module that compares the counter value withpreprogrammed reference values for the start and stop edges. All reference values can be set using the SPIinterface.

When the counter value equals the start reference value, the output signal is set. When the counter value equalsthe stop reference value, the output signal is reset. Figure 33 shows a diagram of the timer compare register.

With a 4-MHz clock, the edge placement resolution is 0.25 s. The ADC conversion signal requires four pulses ineach PRF clock period. The 11th timer compare register uses four sets of start and stop registers to control theADC conversion signal.

Figure 33. Compare Register

The ADC conversion signal requires four pulses in each PRF clock period. Timer compare register 11 uses foursets of start and stop registers to control the ADC conversion signal, as shown in Figure 34.

Figure 34. Timer Module


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A F E 44 90


Using the Timer Module

The timer module registers can be used to program the start and end instants in units of 4-MHz clock cycles.These timing instants and the corresponding registers are listed inTable 2.

Note that the device does not restrict the values in these registers; thus, the start and end edges can bepositioned anywhere within the pulse repetition period. Care must be taken by the user to program suitablevalues in these registers to avoid overlapping the signals and to make sure none of the edges exceed the valueprogrammed in the PRP register. Writing the same value in the start and end registers results in a pulse durationof one clock cycle. The following steps describe the timer sequencing configuration:

1. With respect to the start of the PRP period (indicated by timing instant t0 in Figure 35), the sequence ofconversions must be followed in order: convert LED2 LED2 ambient LED1 LED1 ambient.

2. Also, starting from t0, the sequence of sampling instants must be staggered with respect to the respectiveconversions as follows: sample LED2 ambient LED1 LED1 ambient LED2.

3. Finally, align the edges for the two LED pulses with the respective sampling instants.

Table 2. Clock Edge Mapping to SPI Registers

TIME INSTANT(SeeFigure 35and EXAMPLE

Figure 36) DESCRIPTION CORRESPONDING REGISTER ADDRESS AND REGISTER BITS (Decimal)

t0 Start of pulse repetition period No register control

t1 Start of sample LED2 pulse Sample LED2 start count (bits 15-0 of register 01h) 4800

t2 End of sample LED2 pulse Sample LED2 end count (bits 15-0 of register 02h) 6399

t3 Start of LED2 pulse LED2 start count (bits 15-0 of register 03h) 4800

t4 End of LED2 pulse LED2 end count (bits 15-0 of register 04h) 6399

t5 Start o f s ampl e LE D2 a mb ie nt p uls e S ampl e a mb ien t LE D2 s ta rt c oun t (bits 15 -0 o f regi ster 0 5h) 0

t6 En d o f s ample LE D2 a mbi ent p ul se S ampl e a mb ien t LE D2 e nd c ou nt (bi ts 1 5-0 o f reg ister 0 6h ) 1 599

t7 Start of sample LED1 pulse Sample LED1 start count (bits 15-0 of register 07h) 1600

t8 End of sample LED1 pulse Sample LED1 end count (bits 15-0 of register 08h) 3199

t9 Start of LED1 pulse LED1 start count (bits 15-0 of register 09h) 1600

t10 End of LED1 pulse LED1 end count (bits 15-0 of register 0Ah) 3199

t11 Start of sample LED1 ambient pulse Sample ambient LED1 start count (bits 15-0 of register 0Bh) 3200

t12 End of sample LED1 ambient pulse Sample ambient LED1 end count (bits 15-0 of register 0Ch) 4700

t13 Start of convert LED2 pulse LED2 convert start count (bits 15-0 of register 0Dh) 0t14 End of convert LED2 pulse LED2 convert end count (bits 15-0 of register 0Eh) 1599

t15 Start of convert LED2 ambient pulse LED2 ambient convert start count (bits 15-0 of register 0Fh) 1600

t16 End of convert LED2 ambient pulse LED2 ambient convert end count (bits 15-0 of register 10h) 3199

t17 Start of convert LED1 pulse LED1 convert start count (bits 15-0 of register 11h) 3200

t18 End of convert LED1 pulse LED1 convert end count (bits 15-0 of register 12h) 4799

t19 Start of convert LED1 ambient pulse LED1 ambient convert start count (bits 15-0 of register 13h) 4800

t20 End of convert LED1 ambient pulse LED1 ambient convert end count (bits 15-0 of register 14h) 6399

t21 St art of first ADC conversion reset pulse ADC reset 0 start count (bits 15-0 of regist er 15h) 0

t22 End of first ADC conver sion reset pulse ADC reset 0 end count ( bits 15-0 of r egist er 16h) 0

t23 Start o f s ec on d ADC c onv ersio n res et p uls e A DC res et 1 s ta rt c ou nt (bi ts 1 5-0 o f regi ster 1 7h) 1 600

t24 En d o f s ec ond ADC c on ve rs io n res et p ul se A DC res et 0 e nd co un t (bi ts 1 5-0 o f reg is ter 1 8h ) 1 600

t25 Start o f third ADC c onv ersio n res et p uls e A DC res et 2 s ta rt c ou nt (bi ts 1 5-0 o f regi ster 1 9h) 3 200

t26 End of third ADC conversion reset pulse ADC reset 0 end count ( bits 15-0 of r egist er 1Ah) 3200

t27 Start o f fou rth A DC c on versi on rese t p ul se A DC res et 3 s ta rt c ou nt (bi ts 1 5-0 o f regi ster 1 Bh ) 4 800

t28 En d o f fou rth A DC co nv ersi on res et pu ls e A DC res et 0 e nd co un t (bi ts 1 5-0 o f reg is ter 1 Ch ) 4 800

t29 End of pulse repetition period Pulse repet ition period count (bit s 15- 0 of register 1D h) 6399



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LED1 (IR LED)On Signal

LED2 (RED LED)On Signal

t0

ADC Conversion

Pulse Repetition Period,One Cycle

ADC Reset


[LED1 (IR) Phase]

CONVLED1,Convert LED1 (IR) Sample

CONVLED2_amb,

Convert Ambient Sample[LED2 (RED) Phase]




[LED2 (RED) Phase]



[LED1 (IR) Phase]

t29

t3 t4

t10t9

t5 t6

t7 t8

t11 t12

t2t1

t13 t14

t15 t16

t17 t18

t19 t20

t21

t22

t23

t24

t25

t26

t27

t28

A F E 44 90


(1) RED = LED2, IR = LED1.

Figure 35. Programmable Clock Edges



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t0 t29

ADC Conversion


t14

t15t16

t13

t17t18

t19 t20

t21

t22

t23

t24

t25

t26

t27

t28ADC Reset


[LED1 (IR) Phase]

CONVLED1,Convert LED1 (IR) Sample


[LED2 (RED) Phase]


One 4-MHzClock Cycle

A F E 44 90


(1) RED = LED2, IR = LED1.

Figure 36. Relationship Between the ADC Reset and ADC Conversion Signals


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ADC Clock

ADC Convert

LED2 DataADC Output Rate

PRF Samples per Second

ADC

ADC

Ambient(LED2) Data

LED1 Data

Ambient

(LED1) Data

x igital

Averager

Register30

Number of Averages

22-Bits Register42

LED2 Data

Register43

LED2_Ambient Data

Register44

LED1 Data

Register

45 LED1_Ambient Data

ADC Reset

ADC Reset

A F E 44 90


ADC OPERATION AND AVERAGING MODULE

The ADC reset signal must be positioned at 25% intervals of the pulse repetition period (that is, 0%, 25%, 50%,and 75%). After the falling edge of the ADC reset signal, the ADC conversion phase starts. Each ADCconversion takes 50 s.

There are two modes of operation: without averaging and with averaging. The averaging mode can averagemultiple ADC samples and reduce noise to improve dynamic range because the ADC conversion time is usuallyshorter than 25% of the pulse repetition period. Figure 37shows a diagram of the averaging module.

Figure 37. Averaging Module

Operation Without Averaging

In this mode, the ADC outputs a digital sample one time for every 50 s. At the next rising edge of the ADC resetsignal, the first 22-bit conversion value is written into the result registers sequentially as follows (see Figure 38):

At the 25% reset signal, the first 22-bit ADC sample is written to register 2Ah.

At the 50% reset signal, the first 22-bit ADC sample is written to register 2Bh.

At the 75% reset signal, the first 22-bit ADC sample is written to register 2Ch. At the next 0% reset signal, the first 22-bit ADC sample is written to register 2Dh. The contents of registers2Ah and 2Bh are written to register 2Eh and the contents of registers 2Ch and 2Dh are written to register2Fh.

At the rising edge of the ADC_RDY signal, the contents of all six result registers can be read out.

Operation With Averaging

In this mode, all ADC digital samples are accumulated and averaged after every 50 s. At the next rising edge ofthe ADC reset signal, the average value (22-bit) is written into the output registers sequentially as follows (seeFigure 39):

At the 25% reset signal, the averaged 22-bit word is written to register 2Ah.

At the 50% reset signal, the averaged 22-bit word is written to register 2Bh.

At the 75% reset signal, the averaged 22-bit word is written to register 2Ch. At the next 0% reset signal, the averaged 22-bit word is written to register 2Dh. The contents of registers 2Ahand 2Bh are written to register 2Eh and the contents of registers 2Ch and 2Dh are written to register 2Fh.

At the rising edge of the ADC_RDY signal, the contents of all six result registers can be read out.


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ADC Conversion

Pulse Repetition PeriodT = 1 / PRF

ADC Reset

ADC RDY Pin

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

0% 25% 50% 75%

ADC Data

ADC data 1 arewritten into

register 42.


register 43.


register 44.

ADC data 13 are written intoregister 45.

Register 42 and register 43are written into register 46.


0%

17 18 19 20

0 T 1.0 T

NUMAV[7:0] + 1 =0.25 Pulse Repetition Period

50 s

A F E 44 90


The number of samples to be used per conversion phase is specified in the CONTROL1 register (NUMAV[7:0]).The user must specify the correct value for the number of averages, as described in Equation 3:

(3)

When the number of averages is '0', the averaging is disabled and only one ADC sample is written to the result

registers.Note that he number of average conversions is limited by 25% of the PRF. For example, eight samples can beaveraged with PRF = 625 Hz, and four samples can be averaged with PRF = 1250 Hz.

Figure 38. ADC Data Without Averaging (When Number of Averages = 0)



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ADC Conversion

Pulse repetition periodT = 1/PRF

ADC Reset

ADC_RDY Pin

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

0% 25% 50% 75%

ADC Data

Average ofADC data 1 to 3 are

written intoregister 42.

Average ofADC data 5 to 7are written into

register 43.

Average ofADC data 9 to 11 are

written intoregister 44.

Average ofADC data 13 to 15 are written

into register 45.



0%

17 18 19 20

0 T 1.0 T

A F E 44 90


NOTE: Example is with three averages. The value of the NUMAVG[7:0] register bits = 2.

Figure 39. ADC Data with Averaging Enabled



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Clocking

InternalADC

+

TIA

RXOUTP

+

Stage 2Gain

RXOUTN

INP

INN

Device

External

ADC

PD_ALM ADC_RDY

Use the ADC_Resetsignal on the PD_ALM pin

to clock the external ADC.

Use ADC_RDY tosync the external

ADC with the AFE.

ADC+

TIA

RXOUTP

+

Stage 2Gain

RXOUTN

INP

INN

Device

A F E 44 90


AFE ANALOG OUTPUT MODE (ADC Bypass Mode)

The ADC bypass mode brings out the analog output voltage of the receiver front-end on two pins (RXOUTP,RXOUTN), around a common-mode voltage of approximately 0.9 V. In this mode, the internal ADC of theAFE4490 is disabled.Figure 40shows a block diagram of this mode.

Figure 40. AFE4490 Set to ADC Bypass Mode

In ADC bypass mode, one of the internal clocks (ADC_Reset) can be brought out on the PD_ALM pin, as shownin Figure 41. This signal can be used to convert each of the four phases (within every pulse repetition period).Additionally, the ADC_RDY signal can be used to synchronize the external ADC with the AFE. See Figure 42forthe timing of this mode.

Figure 41. AFE4490 in ADC Bypass Mode with ADC_Reset to PD_ALM Pin



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LED1 (IR LED)On Signal

LED2 (Red LED)On Signal

t0

ADC_RDY(Pin 28)


ADC Reset(Pin 23)



[LED2 (RED) Phase]



[LED1 (IR) Phase]

t29

t3 t4

t10t9

t5 t6

t7 t8

t11 t12

t2t1

t21

t22

t23

t24

t25

t26

t27

t28

A F E 44 90


NOTE: RED = LED2, IR = LED1.

Figure 42. AFE4490 Analog Output Mode (ADC Bypass) Timing Diagram

In ADC bypass mode, the ADC reset signal can be used to start conversions with the external ADC. Useregisters 15h through 1Ch to position the ADC reset signal edges appropriately. Also, use the EN_RSTCLK onthe PD_ALM pin register bit to bring out the ADC reset signal to the PD_ALM pin. ADC_RDY can be used toindicate the start of the pulse repetition period to the external ADC.



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RX_ANA_SUP(2.0 V to 3.6 V)

I/OPins

Device

1.8 V

1.8 V

RX_DIG_SUP(2.0 V to 3.6 V)

RX_ANA_SUP to1.8-V Regulator

Rx Analog Modules

RX_DIG_SUP to1.8-V Regulator

Rx DigitalRx I/OBlock

A F E 44 90


RECEIVER SUBSYSTEM POWER PATH

The block diagram inFigure 43shows the AFE4490 Rx subsystem power routing.

Figure 43. Receive Subsystem Power Routing



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LED

CurrentControl

8-Bit Resolution

LED2 CurrentReference


H-BridgeDriver

H-Bridge

LED2_ON

LED1_ON

LED2_ONOrLED1_ON

Register LED2 Current Reference

Register LED1 Current Reference

5-V Supply

Tx

ILED

CBULK

H-Bridge SupplyExternalSupply

A F E 44 90


TRANSMIT SECTION

The transmit section integrates the LED driver and the LED current control section with 8-bit resolution. Thisintegration is designed to meet the specified dynamic range (based on a 1-sigma LED current noise).

The LED2 and LED1 reference currents can be independently set. The current source (I LED) locally regulates andensures that the actual LED current tracks the specified reference.

Two LED driver schemes are supported: An H-bridge drive for a two-terminal back-to-back LED package, as shown in Figure 44. The minimum H-

bridge supply voltage must be 2.5 V + (maximum voltage drop across the LED).

A push-pull drive for a three-terminal LED package; seeFigure 45. The minimum external supply voltage =2.0 V + (maximum voltage drop across the LED). This value is the nominal value and depends on the registryLED current settings (refer to the LED_RANGE[1:0] bits in theLEDCNTRLregister).

Figure 44. Transmit: H-Bridge Drive



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LEDCurrentControl

8-Bit Resolution



H-BridgeDriver

LED2_ON

LED1_ON

LED2_ONOrLED1_ON

Register RED Current Reference

Register IR Current Reference

Tx

ILED

CBULK

ExternalSupply

5-V SupplyH-Bridge Supply

A F E 44 90


Figure 45. Transmit: Push-Pull LED Drive for Common Anode LED Configuration



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50uA0 mA to 200 mA(See the LEDRANGE bits

in the LEDCNTRL register.)

LED_ON

1 PA

TX_CTRL_SUP_5V

LED_DRV_SUP_5V

Device

Tx LEDBridge

LEDCurrentControl

DAC

Tx Referenceand Control

A F E 44 90


Transmitter Power Path

The block diagram inFigure 46shows the AFE4490 Tx subsystem power routing.

Figure 46. Transmit Subsystem Power Routing

LED Power Reduction During Periods of Inactivity

The diagram in Figure 47 shows how LED bias current passes 50 A whenever LED_ON occurs. In order tominimize power consumption in periods of inactivity, the LED_ON control must be turned off.

Figure 47. LED Bias Current



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To Rx Front-End

INM

INP

Cable

n ernaLED_DRV_SUP

n er

Documents

Afe 4490