Advancements in the process of SMT assembly

Advancements in the process of SMT assembly

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An overview of the industry

Introduction:

Until the early 1990s, the automotive sector in India was highly protected. This was in the

form of steep import tariffs and measures that restricted the participation of foreign companies.

Hindustan Motors (HM) and Premier Automobile (PAL) that were set up in 1940's dominated the

vehicle market and industry. In the 1950s, the arrival of Tata Motors, Bajaj Auto, and Mahindra &

Mahindra led to steadily increasing vehicle production in India, while the 1960s witnessed the

establishment of the two- and three-wheeler industry in India. However, the automotive industry

witnessed tremendous growth after the entry of Maruti Udyog in the 1980s. In 1983, the

government permitted Suzuki - for some time, the only FDI player - to enter the market in a joint

venture with Maruti - a state operated enterprise at the time. Ten years later, as part of a broader

move to liberalize its economy, India de-licensed passenger car manufacturing and opened it up

further to foreign participation. That brought a wave of FDI to India's vehicle industry. Import

barriers have been progressively relaxed. Today, almost all of the major global players are present

in India. The automotive industry is today a key sector of the Indian economy and a major foreign

exchange earner for the country.

India is amongst the fastest growing economies, with stable macroeconomic indicators.

India clocked a GDP growth rate of 8.5% during the FY 2003-04. The government is targeting a

GDP growth rate of 8% over the next 5 years. The most significant aspect about the GDP is the

decreasing contribution of the agricultural sector to the GDP facilitated by a simultaneous

increase in the contribution of services & industrial sectors. This provides stability to the GDP

growth, as agricultural sector is largely dependent on the monsoons, which are unpredictable.

The country's foreign exchanges reserves are at an all-time high of around USD 130 bn.

Exports from India have been rising. The Balance of Trade (Exports - Imports), although, still

negative, has remained stable over the last few years. All these factors coupled with pro-reform

measures of the government have helped India absorb external shocks without any major impact

on the economic growth.

The interest rates have been falling consistently over the years while the government has

managed to keep the inflation rates at 4-5% levels. Thus, the real rate of interest has come down.


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Lower rate of interest along with easy availability of finance has spurred consumption demand

among households. Other demographic factors such as growing working population, favorable

urbanization trends, increase in two-income households, etc. have also contributed to the increase

in consumption demand.

Government Policies & Automotive Sector:

The auto sector is one of the main drivers of the economy. Every commercial vehicle

manufactured, creates 13.31 jobs, while every passenger car creates 5.31 jobs and every two-

wheeler creates 0.49 jobs in the country. Besides, the automobile industry has an output multiplier

of 2.24, i.e. for every additional rupee of output in the auto industry, the overall output of the

Indian economy increases by Rs. 2.24. Realizing this, successive governments have taken various

measures to provide the much-required push to the auto sector.

The road infrastructure, in particular, had been given special importance by the previous

government of NDA with the 'Golden Quadrilateral' project and the 'North-South" and "East-

West" corridor projects. This momentum has been maintained by the present Congress-led United

Progressive Alliance (UPA) government with its continued support to road infrastructure

development. The excise and customs duties on cars and auto-components have been

continuously declining over the past five years. All these factors have contributed in providing the

impetus to the auto sector.

The government has chalked out a plan regarding Bharat Stage IV (equivalent to Euro IV)

norms by 2010. The government is also planning to form auto clusters to improve international

competitiveness of domestic industries. First such cluster will be set up in the Pimpri-Chinchwad

area of Maharashtra at a cost of Rs. 67 crores.

In the 2004 Budget the government announced new incentives to facilitate Research &

Development activity in India, which has been continued in the 2005 budget.

All these efforts are directed towards increasing the competitiveness of Indian auto industries and

providing better, technologically advanced and environmental friendly products to the end user.


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Introduction to WOORY Automotive industry:

PRODUCT OVERVIEW:

HVAC ACTUATOR

Fig1 HVAC actuators

Actuators are a device for moving HVAC door flap to control temperature fan speed, and air

circulation inside of vehicle.

Controlling temperature inside of vehicle

Inlet Mode Temp

In-Take the exterior

fresh air and circulating

interior air

Controlling the blow in/outlet direction

of each mode, vent, vent/floor,

def./floor and def.

Actuator, Using for

inside

temperature adjustment

(AIRCON/HEATER)

Table No 1: Controlling modes inside of vehicle


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Basic Specifications

Inlet Rated Voltage (VDC) 11 ~ 14

Technical Data

No Load speed (RPM)

Rated Speed (RPM)

Rated Current (mA)

Stall Current (mA)

Stall Torque (NCm)

Noise Level (dBA)

Operating Temp (°C)

2.0 ~ 7.0

0.7 ~ 6.0

50 ~ 150

<200 ~ 500

100 ~ 250NCm

35 ~ 40

-40 ~ 85

Table 2: Basic specifications of actuators

CONTROL HEAD:

Fig 2: control heads

Control Head which driver fit heater and air conditioner for the most suitable atmosphere.

Improving dependability, easy and gentle control and high durability.


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MCU Compiler

Name Application Notes

Metro Works C-

HC08 68HC08 Family C, C++ IDE

COSMIC C

68HC12 Family

68HC08 Family

ST7 Family

ODS Version

CSC-PCM C PIC 15XX, PIC 16XX

PIC 17XX, PIC 18XX -

HITEC-C PIC 15XX, PIC 16XX

PIC 17XX, PIC 18XX -

METROWORKS

FOR ST7 MCU ST7 Family -

INTELCOMPILER Intel 80C196 -

TMS370Series

Compiler TMS370C756 8bit 16K-OTP

DALLAS 80

Series Compiler DS80C320 8bit

Table 3: MCU compiler data


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Chapter: 1

1.0Introduction:

The assembling process of PCBs can be by using technologies. They are THT and SMT.

Traditional through-hole Dual In-Line Package assemblies reached their limits in terms of

improvements in cost, weight, volume, and reliability at approximately 68L. SMT allows

production of more reliable assemblies with higher I/O, increased board density, and reduced

weight, volume, and cost. The weight of printed board assemblies (PBAs) using SMT is reduced

because surface mount components (SMCs) can weigh up to 10 times less than their conventional

counterparts and occupy about one-half to one-third the space on the printed board (PB) surface.

SMT also provides improved shock and vibration resistance due to the lower mass of components.

The smaller lead lengths of surface mount components reduce parasitic losses and provide more

effective decoupling. Surface mounting was originally called "planar mounting". Surface-mount

technology was developed in the 1960s and became widely used in the late 1980s. Much of the

pioneering work in this technology was by IBM. The design approach first demonstrated by IBM

in 1960 in a small-scale computer was later applied in the Launch Vehicle Digital Computer used

in the Instrument Unit. Components were mechanically redesigned to have small metal tabs or

end caps that could be directly soldered to the surface of the PCB. Components became much

smaller and component placement on both sides of a board became far more common with surface

mounting than through-hole mounting, allowing much higher circuit densities


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CHAPTER: 2

2.0 About SMT:

Surface Mount Technology is the latest technology used in the assembling of PCBs.In this

method both leaded and non-leaded electrical components attached to the surface of a conductive

pattern that does not utilize leads in feed through holes. In SMT both components and conductive

tracer (i.e. connections) are installed on the same side of substrate or surface. Substrate can be

ceramic, paper plastic, rigid and flexible PCB’s. Printed circuit board designing especially those

requiring high on board density. Fewer holes need to be drilled on abrasive boards. The errors in

the component placement also corrected easily. And components can be placed on the both sides of

the board. The components used in SMT are called Surface Mount Components and the devices

used in assembling them are called Surface Mount Devices.

2.1 Types of SMT:

SMT replaces DIPs with surface mount components. The assembly is soldered by reflow

and/or wave soldering processes depending on the mix of surface mount and through-hole mount

components. When attached to PBs, both active and passive SMCs form three major types of SMT

assemblies, commonly referred to as Type 1, Type II, and Type III (see Figure 1).

Type 1:

Type I is a full SMT board with parts on one or both sides of the board. In type1 both active

and passive components mounted on the primary and secondary side of the printed board.

Type 2:

Type 2 is the most common type SMT board. It has a combination of through-hole

components and SMT components. Often, surface mount chip components are located on the

secondary side of the Printed Board (PB). Active SMCs and DIPs are then found on the primary

side. Multiple soldering processes are required.


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Fig 2.1 Type1 SMT

Fig 2.2 Type 2 SMT

Fig 2.3 Type 3 SMT


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Type 3:

Type III assemblies are similar to Type II. They also use passive chip SMCs on

the secondary side, but on the primary side only DIPs are used.

2.2 Surface Mount Components:

Many but not all through whole components have a surface mountable counterpart. Due to

some physical limitations so conventional components cannot be manufactured as SMC (Surface

Mount Components). For example high capacity capacitor and power transformers, still most

circuit can be assembled, using SMT, even though some conventional through hole components

are required. It is important for SMT surface designer and service technician to know the general

physical configuration and operating parameters of various SMC’s. All SMC’s in familiar are

available separately SMC’s used for automatic assemblies are supplied in rills of paper or in

magazine.

DETAILS ABOUT SOME (SMC’S)

1. Chip resister:

These are most widely produced of all SMC’s. They are originally developed for used in

hybrid micro circuit. The chip registers are leadless registers. Constructionally deice is similar to

thick film resister.

2. Chip Capacitor:

There are originally developed from use in hybrid micro circuits. There are basically three

types of surface mountable chip capacitor.

a) Multi-layer Ceramic

b) Electrolytic

c) Tantalum


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Ceramic multi-layer chip capacitors are commonly used. They are stable and highly reliable.

The capacitance values available are from 1 PF to 1 F. Package style is identical to chip resister.

The size of chip capacitor depends on the value of capacitor.

For high capacity electrolytic and tantalum capacitor are used. Tantalum capacitors are

available for the values of 0.1 F to 100 F. Aluminum electrolytic capacitors are larger than that

of tantalum. Tantalum capacitors are available in the values of 1.5 F to 47 F.

3. Potentiometer:

Both single and multitier trimming potentiometers are available in surface mountable

configuration. They are made from ceramic or high temperature plastic so as to protect than from

emersion soldering. The dimension of smallest single term trimmer is 4 x 4 mm. Multi terms

trimmers are not designed for repeated adjustments. They can be adjusted mostly 10 times. The

trimmers are designed to be adjusted by means of miniature screw driver or special tools.

4. Inductors:

Much kind of surface mountable lead and leadless inductors and even transformers are

available. Inductance’s value ranges from few 10’s of Nano henry to 1 milli Henry ( 10’s of nano

to mh )

5. Descript Semiconductors :

Many diodes, transistors and descript semiconductors are available in miniature surface

mountable packages. The S O D ( Small outline Diode ) package is leadless cylinder used for

diodes. The SOT ( Small outline transistor ) packages are used for transistors, diodes various up

opto electronic components.


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6. Integrated Circuits (IC’s) :

Surface mountable IC’s are developed by Texel Instruments. The most popular surface

mountable IC packages is small – outlet (SO) configuration developed by Philips. It resembles, a

miniature (Dual In Line Package ) DIP. An 50 i.e. small outlet device occupies 1/4th

board space

of an equipment (Dual In Line Package) DIP.

7. Other Surface Mountable Components:

There are many other surface mountable devices available like photo transistor, infrared red

LED,PLCC, ceramic filter, switches. PLCC is used to mount nonleaded component


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CHAPTER: 3

3.0Process of assembling:

There are mainly five stages in the assembling of PCB

1) Solder paste printing and dispensing

2) Component placement

3) Soldering

4) Inspection

5) Rework

Fig 3.1 Type 1 assembling process

The process sequence for type1 is shown inn fig 3.1.For single sided type1 solder paste is

printed on the board and the components are placed later soldering and cleaning is done.For

double sided one the board is turned over and process is repeated.


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Fig 3.2 Type2&3 assembling process

In the type2 SMT is same as the type1 but in this due to the mix up of active and passive

components the board undergo two types of soldering. Passive components and low pin count gull

wing are exposed to wave soldering.

3.1 Surface Mount Design:

The manufacturing is gaining more recognition as it becomes clear that cost reduction of printed

wiring assemblies cannot be controlled by manufacturing engineers alone. Design for manufacturability-

which includes considerations of land pattern, placement, soldering, cleaning, repair, and test-is

essentially a yield issue. Thus, companies planning surface mount products face a challenge in creating

manufacturability designs.

Of all the issues in design for manufacturability, land pattern design and interpackage spacing are

the most important. Interpackage spacing controls cost-effectiveness of placement, soldering, testing,

inspection, and repair. A minimum interpackage spacing is required to satisfy all these manufacturing

requirements, and the more spacing that is provided, the better.

Land pattern

Function

Packing moisture sensitivity

Solder joints reliability

Test nodes placement


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Land Pattern Design:

The surface mount land patterns, also called footprints or pads, define the sites where components

are to be soldered to the PC board. The design of land patterns is very critical, because it determines

solder joint strength and thus the reliability of solder joints, and also impacts solder defects, lean ability,

testability, and repair or rework. In other words, the very producibility or success of SMT is dependent

upon the land pattern design.

Design for Testability:

In SMT boards, designing for testability requires that test nodes be accessible to automated test

equipment (ATE). This requirement naturally has an impact on board real estate. In addition, the

requirement impacts cost, which is dependent upon defects.

3.2 Types of soldering:

1) Hand soldering

2) Wave soldering

3) Infrared/convective reflow soldering

Hand soldering:

Hand soldering the soldering paste is applied to the board and the SMCs are placed on it by hand,

so it is called as hand soldering. In general the components that cannot withstand high temperature levels

in wave soldering or reflow soldering and the components which are not possible to solder inside the

machine are hand soldered.

Wave soldering:

It is done using a wave soldering machine which uses the ultraviolet energy. It is important to

avoid the possibility of thermal shock during soldering and carefully controlled preheat is therefore

required. The rate of preheat should not exceed 4°C/second and a target figure 2°C/second is

recommended. Although an 80°C to 120°C temperature differential is preferred, recent developments

allow a temperature differential between the component surface and the soldering temperature of 150°C

(Maximum) for capacitors of 1210 size and below with a maximum thickness of 1.25mm. The user is

cautioned that the risk of thermal shock increases as chip size or temperature differential increases.

Mildly activated rosin fluxes are preferred. The minimum amount of solder to give a good joint should


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be used. Excessive solder can lead to damage from the stresses caused by the difference in coefficients

of expansion between solder, chip and substrate.

Fig 3.3 wave soldering machine

Infrared/Convective Reflow Soldering:

There are basically two types of infrared reflow processes: focused (radiant) and non-focused

(convective). Focused IR, also known as Lamp IR, uses quartz lamps that produce radiant energy

to heat the product. In non- focused or diffused IR, the heat energy is transferred from heaters by

convection. A gradual heating of the assembly is necessary to drive off volatiles from the solder

paste. This is accomplished by various top and bottom heating zones that are independently


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controlled. After an appropriate time in preheat, the assembly is raised to the reflow temperature

for soldering and then cooled. The most widely accepted reflow is now "forced convection" reflow.

It is considered more suitable for SMT packages and has become the industry standard. The

advantage of forced convection reflow is better heat transfer from hot air that is constantly being

replenished in large volume thus supplying more consistent heating.. For wave soldering

components, must be spaced sufficiently far apart avoid ridriging or shadowing(inability of solder

to penetrate properly in to small spaces).This is less important for reflow soldering but sufficient

space must be allowed to enable rework should it be required.

Fig 3.4 Reflow soldering machine


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3.3Component placement:

Automatic placement equipment can select the position on circuit board from 1000 to 5 lakhs

components per hour .A pick and place machine is used to place the components.

Fig 3.5 Pick and place machine

Fig 3.6 Component loader


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Pick and place machine is the heart of surface mount .This machine pick and places the electronic

components onto the PCB prior to the soldering. This machine uses vacuum pick up to hold the

components. Few other had vision assisted alignment. In general pick and place machine offers

better speed and accuracy than through hole insertion machines. The components are loaded in the

rack shown in fig 3.6.

3.4 Inspection:

Due to small size of components SMT board requires very careful inspection particularly for

solder ball, improperly soldered joints and missed solder connections, etc.Some components are

specially difficult to inspect like quad PLCC’s (Plastic Loaded Chip Carrier) i.e. IC having J –

profile pins along each four sides and it has more than 28 pins. Complete SMT board can be tested

by hand or automatic testing equipment. Whether testing is done by hand or automatically the test

probes should be touch to SMC’s solder pad or their conductive traces. The test probes should not

be touch to terminals of SMC’s properly designed SMT boards have test point location.

AOI (automatic inspection machine):

This machine is visual inspection machine to detect the bad position of the components

mounted on the PCB.AOI machine detects bad component placement using the high resolution

camera and image processing technology. By this it can detect soldering status and mounting. It

display results on monitor and mark on defected components using ink (NG Marking) or others. It

has strong (OCR) optical character reorganization. Just with one camera it can provide examination

speed upto 2 fov (field of view)Teaching time can be reduced by ATT (auto teaching tool).It

supports laser lighting by which the high and loose mounting can be detected.


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Fig 3.7 AOI machine

System configuration:

1)PC Section:

It manages system operation and stores data.

-vision board it acquires digital video data from camera.

- Motion board it controls motors of X and Y axis.and signal processing of various kinds of

sensors and switches.

-Integrated motion: using the closed loop servo mechanism , it adjusts X and Y axes nad width of

the conveyor automatically and controls laser rotation etc.

2)Control section:


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-i/o board : it relays driving signal of the motion board and various kinds of I/O signals.

-light control: it supplies power to the light control and controls the 265 levels of brightness.

-it controls the interface b/w motion board and step driver /servo amp,and the inputs and output

ports are necessary for system operation.

3) MOTOR section:

Step motor: it moves or controls the motion section of X and Y axes.

Servo motor: it actuates the robots of X and Y axes.

Step motor : it actuates conveyor system and laser rotation.

4)Moniter :

It displays information necessary for system opration inspection.

5)Vision section:

Camera: it converts image inspection area into digital signals and send them to vision board.

Lighting device: light is controlled by the arrangement of white led of high brightness in 3

levels(coaxial,vertical and horizontal)

Lighting controller: it is connected to pc to control the power and brightness of vericsl ,coaxial and

horizontal lights.

6)laser:

It inspects and detects the soldering ,reverse insertion, by checking loose components and their

hight.

7)NG marker:

After insertion ,the locations of defects on the relavent PCB are markedby NG marker (Optional).

8)conveyor system:


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It supplies the pcb in the previous process to the location of inspection and fixes pcb for

inspection,then discharge pcb to the following process.

Fig 3.8 AOI configuration

3.5ADVANTAGES OF SMT:

There are various advantages of SMT.

1. Reduce Circuit Board Size : The compact size of SMC’s considerably reduces area of circuit

board.

2. Light in weight : SMC’s are lighter than their through hole counter port. e.g. 8 – pin DIP,

LM 308 M opamp weighs 600 mg. The so package vargen of same IC Weighs 60 gm.

3. The low weight of SMC’s and smaller circuit board together gives 5 to 1 weight advantages

over conventional board. Also SMT boards are thin therefore they gives 8:1 volume advantage

over conventional boards.


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4. Double – Sided Circuit Board : SMT can also used double sided board with an advantage that

components can be placed on the both sides.

5. Subminiature Circuits : SMT circuits are nearly as tiny as hybrid integrated circuits.

6. Automated assembly : SMCs are much more compacted with automatic assembly equipment.

The time consuming in drilling holes in circuit board is climinated. SMC’s have no wire leads

to cut, bend and insert. Therefore SMT boards can be automatically assemble quickly than

conventional boards.

7. Lower Cost : The SMC’s cost is generally more, till SMT can reduce over all board cost for

variety of reasons. e.g. saving of 40% cost results from elimination of drilling hole equipment.

8. Other Advantages : Some advantages of SMT are less obvious than above.

i) Compact size of SMT so it is used in mobile.


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CHAPTER-4

4.0 I CT:

Mechanical and chemical process challenges initially limited the acceptance of SMT. As

those challenges have been overcome the another electronic test access obstacle has been come

apparent. Testing is the crucial part of SMT process. The physical test access is allowed in THT.

But where as in SMT the packing density is increased so physical test access in denied. So some

new technologies are introduced to test SMT manufactured PCBs.

4.1In circuit test fixture basics:

In order to carry out the test it is necessary to gain access to each node on the board. The

most common way of achieving this is to generate a "bed of nails" fixture. The term bed of nails is

a rather graphic description of what many fixtures look like, having a large number of test points or

probes proud of a board that holds them in place. Although the concept of the in-circuit test fixture

or bed of nails is broadly the same whatever manufacturer is used, there are a number of variations

on the basic theme.

Fig4.0: Bed of nails ICT fixture


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Fig 4.1: Probe able test pad

The In-circuit test fixture is required to interface the main tester with the particular board

under test. It will have a main connector that interfaces to the tester and wires that are taken from

the connector to individual pins / probes / or "nails" that make contact with the required nodes on

the board under test. The probes are held in place by what may be termed a base-board. This is

precision drilled to ensure that the probes are held in exactly the right place for the fixture to make

contact with the required nodes on the board. The board is held in place accurately by the fixture

and pulled onto spring loaded pins that make contact with connections on the board. The board

may either be pulled down under the action of a vacuum or it may be achieved mechanically. At

one time when board component densities were much lower it was often possible to place special

ATE pads onto the board to enable good connection to be made. Nowadays with very much more

compact boards this is not possible. Instead connections are made onto the component pads. This is

obviously more difficult because of the solder and the component connection itself, but can still be

achieved to a high degree of reliability. Typically each spring exerts a force of between 100 and

200g to ensure that good contact is made. This obviously means that the total force required for all

the pins on a board can be very significant. Sometimes supports for the board are required to

ensure that it does not flex too much as this may result in cracking some delicate surface mount

components. Typically pins are placed on a 0.1 inch matrix. Many new surface mount IC packages

require a much finer pitch, and to achieve this adapter is often used.


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There are about three main methods for pulling the board onto the probes:

Vacuum: This form of fixture uses a vacuum to pull the board down onto the pins. It has

the advantage that as the vacuum exists over the whole area of the board, the board is

evenly pulled down onto the pins, but it does require any holes in the board to be sealed

before the in-circuit test stage of the production process.

Pneumatic: This form of fixture uses a compressed air source, present in most

manufacturing areas to be used.

Mechanical: This uses a simple lever or other mechanical arrangement to pull the board

down onto the pins.

Fig 4.2: ICT machine

4.2 Wireless In-circuit test fixtures:

Another form of ICT fixture is known as a wireless fixture. This does not mean that it uses

wireless / radio communications, but instead the fixture does not use traditional wires but it uses a

printed circuit board. This provides a number of advantages:


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Reduces complexity of fixture: Most ICT fixtures require many wires to run between the

individual probes and the fixture connector that interfaces to the main ICT system

connector. There can often be several hundred wires, making the fixture very complicated

and difficult to work upon.

Reduces spurious resistance: The wires within an ICT fixture need to be long enough to

allow the fixture to be opened to enable proper access. The length of the wires can

introduce a significant amount of resistance that can reduce the overall measurement

accuracy of the system. Using a wireless ICT fixture enables the track lengths to be

shortened and resistance level decreased.

Improves reliability: the large number of wires in an ICT fixture introduces a means of

failure. Wires can easily break and become disconnected. The use of a wireless fixture,

using PCB technology significantly improves the level of reliability.

Reduces fixture cost: Using modern software, it is possible to reduce the cost of the

fixture production by using a PCB. Using automatic routing of the tracks in the PCB layout

software means that PCB design is automated to a large degree. This means that the

complex wiring is removed from the fixture production process.

Test pins / probes for in-circuit test fixtures

There is a great variety of different types of pin or test probe that can be used for in-circuit

test fixtures.

The in -circuit test probes or test pins or probes are spring loaded and comprise a barrel

with its internal spring, and the plunger. The test probes fit into a socket that enables them

to be replaced when they become worn of damaged.

4.3Basic In-Circuit Test Probe or Contact:

The major design changes are within the head or tip that contacts the board under test. Each

type of head has a particular application for which it is best suited.

Concave tips: These in-circuit test probes are often used for connecting on to terminal

posts.

Spherical radius convex tips: These may be used when mating with an edge connection on

a printed circuit board.


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Cone tips: This format for an in circuit test probe is often used for mating with a PCB via

hole, or directly onto a PCB track..

Single pointed tips: These are often used for mating with solder joints as the tip is able to

penetrate the oxide film on the solder to make good contact.

Multi-pointed tips : These may be used when a connection is required through a larger

area of solder - the multiple serrations mean that several points of contact can be made

through the oxide layer on the solder. They may also be used to mate with the connection to

a conventional component, i.e. not surface mount. The probe serrations will connect to the

solder and wire that protrudes through the board.

The wiring in the fixtures is generally not neatly loomed together. Whilst this may not be as

aesthetically pleasing, it reduces the levels of cross-talk and spurious capacitance. It also reduces

the wire lengths within the fixture as the shortest route between two points can be taken within

reason.

4.4 New trends in ICT:

In circuit testing is still a valuable tool in today's electronics manufacturing environment.

While many thought ICT would be phased out many years ago because the smaller components

and more compact circuit boards have been proved wrong. However to be able to used ICT

satisfactorily, it is necessary design for in-circuit test right from the earliest concept of the board. In

this way sufficient access can be gained to provide a high test coverage for the printed circuit board

or assembly.

By adopting design for in-circuit test guidelines, it is often possible to provide a sufficiently

high level of access to test most of the components on the board.

Design guidelines for In Circuit Testing, ICT

In order to maximize the coverage and capability of an In Circuit Test, ICT system, it is

necessary to ensure that the board is sufficiently testable for the ICT system to provide a useful

test. Guidelines can be adopted to help ensure that the circuit can be tested satisfactorily.

The ideas mentioned below are some ideas that can be implemented to improve the ICT

performance:


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1. Provide accessible location holes: In order that the connections can be made to the

board, it is necessary to have accurate position or location holes that can be used to

accurately locate the PCB onto the test fixture. In this way the PCB can make accurate

location onto any probes or connections required. Requirements for the tooling holes may

include:

o Three preferred but a minimum of two, on opposite diagonal corners

o Tooling or location holes should not be plated to ensure their accuracy

o Tooling or location holes should not be obscured and they should be free from

components etc in the vicinity of the hole to enable any locating spigots on the test

fixture to mate with the hole.

o Location accuracy of the tooling or location holes should typically be within 0.05

mm, i.e. 0.002 inches, although with techniques changing all the time, check the

requirements for the actual tester..

2. Connect resets and other key lines via a resistor: One key design for ICT parameter is

to ensure that any key reset or other lines that might be taken to ground or the supply rail,

are taken there via a resistor. In this way if the In Circuit Tester needs to control these

points on the chip to undertake a performance check, then it is able to have control.

3. Provide a probe-able pad for each circuit node: When using in-circuit testing, it is

necessary to get access to each node in the circuit to enable sufficient test coverage to be

achieved. Probe-able test pads are ideally dedicated test pads, but with circuits becoming

much smaller this is not always possible. Often ICT manufacturers claim fixtures can probe

solder joints. Check this out as this technique can lead to lower reliability testing.

4. Probe-able test pads should all be on one side of the board: When possible test pads

for the test probes should all be on the same side (underside) of the PCB. This means that

single sided fixtures can be employed. These are cheaper, simpler and faster to use than

double sided fixtures.


Page | 29

5. Test pad finish: Any test pads should have a good conductive finish. This will include

solder, but often the gold plating if used elsewhere in the board can be used, although it

adds cost.

6. Test pad size should be sufficient for the fixtures: The test pad size will need to balance

available space on the PCB with the size required for the test probes. They should be

sufficient to allow the probe to make contact, and should have space around them to take up

any tolerances in the fixture, PCB, etc, so that the probes do not cause shorts.

7. Test pad density must be considered: The density of the test pads should not be so great

that it becomes impossible to manufacture the fixture. It is necessary to check this with the

fixture manufacturer as figures vary according to the type of fixture that will be used.

8. Fill plated through holes: If there is a likelihood that vacuum fixtures will be used, it is

necessary to fill the plated through holes as part of the manufacturing process. Methods for

filling other holes will also be required.

4.5 MDA:

The Manufacturing Defect Analyzer, MDA is a basic form of In-Circuit Tester. As the name

implies, the MDA is aimed at only providing a straightforward test of the board to reveal

manufacturing defects. As the majority of manufacturing defects are simple connectivity issues, the

MDA is restricted to making measurements of continuity. This significantly reduces its cost

making it more viable in many areas of test. MDA basics The concept for the MDA is based

around the concept that the design of a board has been previously proven, and parts are reliable and

very few defective components will be delivered. Therefore it should only be manufacturing

defects that will impact the performance of a board or assembly. As most of the defects consist if

solder splashes and poor or open joints, then the majority of failures will be detected by testing for

a relatively simple spectrum of failure types.

While Manufacturing Defect Analyzers are primarily focused on the detection of the very basic

faults, even the most basic testers these days will also detect missing components, although the

exact functionality for any given MDA will only be revealed in the datasheet / specification. Often

the tester will be able to detect the presence of resistors, capacitors and transistors. The detection of

integrated circuits can also be achieved using the protection diodes to indicate whether the

component is correctly placed.


Page | 30

The tester makes connection to the board under test using a bed of nails fixture, and this

means that a different fixture is generally required for each board. It needs to make contact with

specific points on the board, where often there may be a test point or land area for the probe.

Like other forms of In-Circuit Tester, an MDA will use the printed circuit board CAD data

for the generation of the fixture design and the test programme. This often allows up to around

80% of the test programme to be generated automatically.

4.6 MDA Advantages / Disadvantages:

Like any other technology the manufacturing defect analyzer has its advantages and

disadvantages. This need to be considered when choosing which type of tester and test technology

should be used.

SUMMARY OF ADVANTAGES AND DISADVANTAGES OF A

MANUFACTURING DEFECT ANALYZER, MDA

ADVANTAGES DISADVANTAGES

Machine is much less costly than

a full ICT

Can detect open and short

circuits which form the major

number of defects

Can detect some values

dependent upon the MDA

capability

Limited component diagnostics

Still requires bed of nails fixture

and its associated costs

Component access can be an

issue with current board density

levels

Table 4: Advantages and Disadvantages of MDA

An MDA machine is very much simpler than a full ICT. This makes it an attractive

proposition for many situations, particularly within smaller companies where the capital

expenditure investment of a full ICT machine may not be viable. In many other situations a

Manufacturing Defect Analyzer may be a viable option is where the fault spectrum does not

warrant a full In-Circuit test. This decision can only be made in the light of an analysis of existing

fault spectra for a given manufacturing line.


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CHAPTER-5

5.0 IEEE boundary scan test access:

As the bed of nails test fixture is not suitable for testing of high density boards as well it is

required to repair after testing few PCBs so it adds cost to the board development cost and MDA is

failed to ensure the continuity of component the SMT needs an accurate, speedy and reliable tester

Boundary-scan essential for dramatically reducing development and production costs, speeding test

development through automation, and improving product quality because of increased fault

coverage.

5.1What is Boundary-Scan?

Boundary-scan, as defined by the IEEE Std.-1149.1 standard, is an integrated method for

testing interconnects on printed circuit boards (PCBs) that are implemented at the integrated circuit

(IC) level. The inability to test highly complex and dense printed circuit boards using traditional in-

circuit testers and bed of nail fixtures was already evident in the mid-eighties. Due to physical

space constraints and loss of physical access to fine pitch components and BGA devices, fixturing

cost increased dramatically while fixture reliability decreased at the same time.

5.2A Brief History of Boundary-Scan:

In the 1980s, the Joint Test Action Group (JTAG) developed a specification for boundary-

scan testing that was standardized in 1990 as the IEEE Std. 1149.1-1990. In 1993 a new revision to

the IEEE Std. 1149.1 standard was introduced (titled 1149.1a) and it contained many clarifications,

corrections, and enhancements. In 1994, a supplement containing a description of the Boundary-

Scan Description Language (BSDL) was added to the standard. Since that time, this standard has

been adopted by major electronics companies all over the world. Applications are found in high

volume, high-end consumer products, telecommunication products, defense systems, computers,

peripherals, and avionics. In fact, due to its economic advantages, some smaller companies that

cannot afford expensive in-circuit testers are using boundary-scan.

The boundary-scan test architecture provides a means to test interconnects between

integrated circuits on a board without using physical test probes. It adds a boundary-scan cell that

includes a multiplexer and latches to each pin on the device.

http://www.corelis.com/support/BSDL.htm



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Fig 5.1 - Typical Boundary-Scan Cell

Boundary-scan cells in a device can capture data from pin or core logic signals, or force data

onto pins. Captured data is serially shifted out and externally compared to the expected results.

Forced test data is serially shifted into the boundary-scan cells. All of this is controlled from a

serial data path called the scan path or scan chain. Figure 1 depicts the main elements of a

boundary-scan cell. By allowing direct access to nets, boundary-scan eliminates the need for a

large number of test vectors, which are normally needed to properly initialize sequential logic.

Tens or hundreds of vectors may do the job that had previously required thousands of vectors.

Potential benefits realized from the use of boundary-scan are shorter test times, higher test

coverage, increased diagnostic capability and lower capital equipment cost.

The principles of interconnect test using boundary-scan are illustrated in Figure 5.2. Figure

5.2 depicts two boundary-scan compliant devices, U1 and U2, which are connected with four nets.

U1includes four outputs that are driving the four inputs of U2 with various values. In this case, we

assume that the circuit includes two faults: a short between Nets 2 and 3, and an open on Net 4.

We will also assume that a short between two nets behaves as a wired-AND and an open is sensed


Page | 33

as logic 1. To detect and isolate the above defects, the tester is shifting into the U1 boundary-scan

register the patterns shown in Figure 5.2 and applying these patterns to the inputs of U2. The inputs

values of U2 boundary-scan register are shifted out and compared to the expected results. In this

case, the results (marked in red) on Nets 2, 3, and 4 do not match the expected values and,

therefore, the tester detects the faults on Nets 2, 3, and 4.Boundary-scan tool vendors provide

various types of stimulus and sophisticated algorithms, not only to detect the failing nets, but also

to isolate the faults to specific nets, devices, and pins.

Fig 5.2 - Interconnect Test Example

The IEEE-1149.1 standard defines test logic in an integrated circuit which provides applications to

perform:

Chain integrity testing

Interconnection testing between devices

Core logic testing (BIST)

In-system programming


Page | 34

In-Circuit Emulation

Functional testing

Fig 5.3 Main building blocks of a JTAG


Page | 35

Fig 5.4 Boundary-Scan Chain with Multiple Chips

Fig 5.5 Boundary-Scan Test Vectors


Page | 36

5.3 JTAG TAP Interface Signals:

Abbreviation Signal Description

TCK Test Clock Synchronizes the internal state machine operations

TMS Test Mode State Sampled at the rising edge of TCK to determine the

next state

TDI Test Data In

Represents the data shifted into the device's test or

programming logic. It is sampled at the rising edge of

TCK when the internal state machine is in the correct

state.

TDO Test Data Out

Represents the data shifted out of the device's test or

programming logic and is valid on the falling edge of

TCK when the internal state machine is in the correct

state

TRST Test Reset An optional pin which, when available, can reset the

TAP controller's state machine

Required Test Instructions

Working in conjunction with the TAP controller is an IR (Instruction Register) providing

which type of test to perform. The 1149.1 Standard requires that all compliant devices must

perform the following three instructions:

EXTEST Instruction

The EXTEST instruction performs a PCB interconnect test, places an IEEE 1149.1

compliant device into an external boundary test mode, and selects the boundary scan

register to be connected between TDI and TDO. During EXTEST instruction, the boundary

scan cells associated with outputs are preloaded with test patterns to test downstream

devices. The input boundary cells are set up to capture the input data for later analysis.

SAMPLE/PRELOAD Instruction

The SAMPLE/PRELOAD instruction allows an IEEE 1149.1 compliant device to remain in


Page | 37

its functional mode and selects the boundary scan register to be connected between the TDI

and TDO pins. During SAMPLE/PRELOAD instruction, the boundary scan register can be

accessed through a data scan operation, to take a sample of the functional data input/output

of the device. Test data can also be preloaded into the boundary-scan register prior to

loading an EXTEST instruction.

BYPASS Instruction

Using the BYPASS instruction, a device's boundary scan chain can be skipped, allowing

the data to pass through the bypass register. This allows efficient testing of a selected

device without incurring the overhead of traversing through other devices. The BYPASS

instruction allows an IEEE 1149.1 compliant device to remain in a functional mode and

selects the bypass register to be connected between the TDI and TDO pins. Serial data is

allowed to be transferred through a device from the TDI pin to the TDO pin without

affecting the operation of the device.


Page | 38

CHAPTER-6

6.1 Boundary-Scan Applications:

While it is obvious that boundary-scan based testing can be used in the production phase of a

product, new developments and applications of the IEEE-1149.1 standard have enabled the use of

boundary-scan in many other product life cycle phases. Specifically, boundary-scan technology is

now applied to product design, prototype debugging and field service as depicted in Figure 6.1.

This means the cost of the boundary-scan tools can be amortized over the entire product life cycle,

not just the production phase.

To facilitate this product life cycle concept, boundary-scan tool vendors such as Corelli’s

offer an integrated family of software and hardware solutions for all phases of a product's life-

cycle. All of these products are compatible with each other, thus protecting the user's investment.

Fig 6.1 - Product Life Cycle Support


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6.2 Applying Boundary-Scan for Product Development:

The on-going marketing drive for reduced product size, such as portable phones and digital

cameras, higher functional integration, faster clock rates, and shorter product life-cycle with

dramatically faster time-to- market has created new technology trends. These trends include

increased device complexity, fine pitch components, such as surface-mount technology (SMT),

systems-in-package (SIPs), multi-chip modules (MCMs), ball-grid arrays (BGAs), increased IC

pin-count, and smaller PCB traces. These technology advances, in turn, create problems in PCB

development:

Many boards include components that are assembled on both sides of the board. Most of

the through-holes and traces are buried and inaccessible.

Loss of physical access to fine pitch components, such as SMTs and BGAs, makes it

difficult to probe the pins and distinguish between manufacturing and design problems.

Often a prototype board is hurriedly built by a small assembly shop with lower quality

control as compared to a production house. A prototype generally will include more

assembly defects than a production unit.

When the prototype arrives, a test fixture for the ICT is not available and, therefore,

manufacturing defects cannot be easily detected and isolated.

Small-size products do not have test points, making it difficult or impossible to probe

suspected nodes.

Many Complex Programmable Logic Devices (CPLDs) and flash memory devices (in BGA

packages) are not socketed and are soldered directly to the board.

Every time a new processor or a different flash device is selected, the engineer has to learn

from scratch how to program the flash memory.

When a design includes CPLDs from different vendors, the engineer must use different in-

circuit programmers to program the CPLDs.

Boundary-scan technology is the only cost-effective solution that can deal with the above

problems. In recent years, the number of devices that include boundary-scan has grown


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dramatically. Almost every new microprocessor that is being introduced includes boundary-scan

circuitry for testing and in-circuit emulation. Most of the CPLD and field programmable array

(FPGA) manufacturers, such as Altera, Lattice and Xilinx, to mention a few, have incorporated

boundary-scan logic into their components, including additional circuitry that uses the boundary-

scan four-wire interface to program their devices in-system.

As the acceptance of boundary-scan as the main technology for interconnect testing and in-

system programming (ISP) has increased, the various boundary-scan test and ISP tools have

matured as well. The increased number of boundary-scan components and mature boundary-scan

tools, as well as other factors that will be described later, provide engineers with the following

benefits:

Easy to implement Design-For- Testability (DFT) rules. A list of basic DFT rules is

provided later in this article.

Design analysis prior to PCB layout to improve testability.

Packaging problems are found prior to PCB layout.

Little need for test points.

No need for test fixtures.

More control over the test process.

Quick diagnosis (with high resolution) of interconnection problems without writing any

functional test code.

Program code in flash devices.

Design configuration data placement into CPLDs.

JTAG emulation and source-level debugging.

6.3 What Boundary-Scan Tools are needed?

In the previous section, we listed many of the benefits that a designer enjoys when

incorporating boundary-scan in his product development. In this section we describe the tools and

design data needed to develop boundary-scan test procedures and patterns for ISP, followed by a


Page | 41

description of how to test and program a board. We use a typical board as an illustration for the

various boundary-scan test functions needed. A block diagram of such a board is depicted in Figure

6.2.

Fig 6.2 - Typical Board with Boundary-Scan Components

A typical digital board with boundary-scan devices includes the following main components:

Various boundary-scan components such as CPLDs, FPGAs, Processors, etc., chained

together via the boundary-scan path.

Non-boundary-scan components (clusters).

Various types of memory devices.

Flash Memory components.

Transparent components such as series resistors or buffers.

Most of the boundary-scan test systems are comprised of two basic elements: Test Program

Generation and Test Execution. Generally, a Test Program Generator (TPG) requires the netlist of

the Unit Under Test (UUT) and the BSDL files of the boundary-scan components. The TPG


Page | 42

automatically generates test patterns that allow fault detection and isolation for all boundary-scan

testable nets of the PCB. A good TPG can be used to create a thorough test pattern for a wide range

of designs. For example, Scan Express TPG typically achieves net coverage of more than 60%,

even though the majority of the PCB designs are not optimized for boundary-scan testing. The

TPG also creates test vectors to detect faults on the pins of non-scan able components, such as

clusters and memories that are surrounded by scan able devices.

Some TPGs also generate a test coverage report that allows the user to focus on the non-

testable nets and determine what additional means are needed to increase the test coverage.

Test programs are generated in seconds. For example, when Corelis ScanExpress TPG™

was used, it took a 3.0 GHz Pentium 4 PC 23 seconds to generate an interconnect test for a UUT

with 5,638 nets (with 19,910 pins). This generation time includes netlist and all other input files

processing as well as test pattern file generation.

Test execution tools from various vendors provide means for executing boundary-scan tests

and performing in-system programming in a pre-planned specific order, called a test plan. Test

vectors files, which have been generated using the TPG, are automatically applied to the UUT and

the results are compared to the expected values. In case of a detected fault, the system diagnoses

the fault and lists the failures as depicted in Figure 6.3. Figure 6.3 shows the main window of the

Corelis test execution tool, scan Express Runner™. scan Express Runner gives the user an

overview of all test steps and the results of executed tests. These results are displayed both for

individual tests as well as for the total test runs executed. scan Express Runner provides the ability

to add or delete various test steps from a test plan, or re-arrange the order of the test steps in a plan.

Tests can also be enabled or disabled and the test execution can be stopped upon the failure of any

particular test.

Different test plans may be constructed for different UUTs. Tests within a test plan may be

re-ordered, enabled or disabled, and unlimited different tests can be combined into a test plan. scan

Express Runner can be used to develop a test sequence or test plan from various independent sub-

tests. These sub-tests can then be executed sequentially as many times as specified or continuously


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if desired. A sub-test can also program CPLDs and flash memories. For ISP, other formats, such as

SVF, JAM, and STAPL, are also supported. To test the board depicted in Figure 6.2, the user must

execute a test plan that consists of various test steps as shown in Figure 6.3.

Fig 6.3 - Scan Express Runner Main Window

The first and most important test is the scan chain infrastructure integrity test. The scan chain

must work correctly prior to proceeding to other tests and ISP. Following a successful test of the

scan chain, the user can proceed to testing all the interconnections between the boundary-scan

components. If the interconnect test fails, scan Express Runner displays a diagnostic screen that

identifies the type of failure (such as stuck-at, Bridge, Open) and lists the failing nets and pins as

shown in Figure 6.4. Once the interconnect test passes, including the testing of transparent


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components, it makes sense to continue testing the clusters and the memory devices. At this stage,

the system is ready for in-system programming, which typically takes more time as compared to

testing.

Fig 6.4 - Scan Express Runner Diagnostics Display

During the design phase of a product, some boundary-scan vendors will provide design

assistance in selecting boundary-scan-compliant components, work with the developers to ensure

that the proper BSDL files are used, and provide advice in designing the product for testability.

6.4 Applying Boundary-Scan for Production Test:

Production testing, utilizing traditional In-Circuit Testers that do not have boundary-scan

features installed, experiences similar problems that the product developer had and more:


Page | 45

Loss of physical access to fine pitch components, such as SMTs and BGAs, reduces bed-of-

nails ICT fault isolation.

Development of test fixtures for ICTs becomes longer and more expensive.

Development of test procedures for ICTs becomes longer and more expensive due to more

complex ICs.

Designers are forced to bring out a large number of test points, which is in direct conflict

with the goal to miniaturize the design.

In-system programming is inherently slow, inefficient, and expensive if done with an ICT.

Assembling boards with BGAs is difficult and subject to numerous defects, such as solder

smearing.


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CHAPTER-7

7.0 JTAG Embedded Functional Test:

Recently, a test methodology has been developed which combines the ease-of-use and low

cost of boundary-scan with the coverage and security of traditional functional testing. This new

technique, called JTAG Emulation Test (JET), lets engineers automatically develop PCB

functional test that can be run at full speed., If the PCB has an on-board processor with a JTAG

port (common, even if the processor doesn't support boundary-scan), JET and boundary-scan tests

can be executed as part of the same test plan to provide extended fault coverage to further

complement or replace ICT testing. Corelli’s Scan Express JET™ provides JTAG embedded test

for a wide range of processors.

7.1 Production Test Flow:

Figure 7.1 shows different production flow configurations. The diagram shows two typical

ways that boundary-scan is deployed:

As a stand-alone application at a separate test station or test bench to test all the

interconnects and perform ISP of on-board flash and other memories. JTAG embedded

functional test (JET) may be integrated with boundary-scan.

Fig 7.1 - Typical Production Flow Configurations


Page | 47

Integrated into the ICT system, where the JTAG control hardware is embedded in the ICT

system and the boundary-scan (and possibly JET) software is a module called from the ICT

software system.

In the first two cases, the test flow is sometimes augmented with a separate ICT stage after

the JTAG-based testing is completed, although it is becoming more common for ICT to be skipped

altogether or at least to be limited to analog or special purpose functional testing.

The following are major benefits in using boundary-scan test and in-system programming in

production:

No need for test fixtures.

Integrates product development, production test, and device programming in one

tool/system.

Engineering test and programming data is reused in Production.

Fast test procedure development.

Preproduction testing can start the next day when prototype is released to production.

Dramatically reduces inventory management – no pre-programmed parts eliminates device

handling and ESD damage.

Eliminates or reduces ICT usage time – programming and screening.

Production test is an obvious area in which the use of boundary-scan yields tremendous

returns. Automatic test program generation and fault diagnostics using boundary-scan software

products and the lack of expensive fixturing requirements can make the entire test process very

economical. For products that contain edge connectors and digital interfaces that are not visible

from the boundary-scan chain, boundary-scan vendors offer a family of boundary-scan controllable

I/Os that provide a low cost alternative to expensive digital pin electronics.


Page | 48

7.2 Field Service and Installation:

The role of boundary-scan does not end when a product ships. Periodic software and

hardware updates can be performed remotely using the boundary-scan chain as a non-intrusive

access mechanism. This allows flash updates and reprogramming of programmable logic, for

example. Service centers that normally would not want to invest in special equipment to support a

product now have an option of using a standard PC or laptop for boundary-scan testing. A simple

PC-based boundary-scan controller can be used for all of the above tasks and also double as a fault

diagnostic system, using the same test vectors that were developed during the design and

production phase. This concept can be taken one step further by allowing an embedded processor

access to the boundary-scan chain. This allows diagnostics and fault isolation to be performed by

the embedded processor. The same diagnostic routines can be run as part of a power-on self-test

procedure.

7.3 Boundary-Scan Design-for-Test Basic Considerations:

As mentioned earlier in this article, the design for boundary-scan test guidelines are simple to

understand and follow compared to other traditional test requirements. It is important to remember

that boundary-scan testing is most successful when the design and test engineering teams work

together to ensure that testability is "designed in" from the start. The boundary-scan chain is the

most critical part of boundary-scan implementations. When that is properly implemented,

improved testability inevitably follows.

Below is a list of basic guidelines to observe when designing a boundary-scan-testable board:

If there are programmable components in a chain, such as FPGAs, CPLDs, etc., group them

together in the chain order and place the group at either end of the chain. It is recommended

that you provide access to Test Data In (TDI) and Test Data Out (TDO) signals where the

programmable group connects to the non-programmable devices.

All parts in the boundary-scan chain should have 1149.1-compliant test access ports

(TAPs).


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Use simple buffering for the Test Clock (TCK) and Test Mode Select (TMS) signals to

simplify test considerations for the boundary-scan TAP. The TAP signals should be

buffered to prevent clocking and drive problems.

Group similar device families and have a single level converter interface between them,

TCK, TMS, TDI, TDO, and system pins.

TCK should be properly routed to prevent skew and noise problems.

Use the standard JTAG connector on your board as depicted in Corelis documentation.

Ensure that BSDL files are available for each boundary-scan component that is used on

your board and that the files are validated.

Design for interconnect testing requires board-level system understanding to ensure higher test

coverage and elimination of signal level conflicts.

Determine which boundary-scan components are on the board. Change as many non-

boundary-scan components to IEEE 1149.1-compliant devices as possible in order to

maximize test coverage.

Check non-boundary-scan devices on the board and design disabling methods for the

outputs of those devices in order to prevent signal level conflicts. Connect the enable pins

of the conflicting devices to boundary-scan controllable outputs. Corelis tools will keep the

enable/disable outputs at a fixed disabling value during the entire test.

Ensure that your memory devices are surrounded by boundary-scan components. This will

allow you to use a test program generator, such as ScanExpress TPG, to test the

interconnects of the memory devices.

Check the access to the non-boundary-scan clusters. Make sure that the clusters are

surrounded by boundary-scan components. By surrounding the non-boundary-scan clusters

with boundary-scan devices, the clusters can then be tested using a boundary-scan test tool.

If your design includes transparent components, such as series resistors or non-inverting

buffers, your test coverage can be increased by testing through these components using

scan Express TPG.



Page | 50

Connect all I/Os to boundary-scan controllable devices. This will enable the use of

boundary-scan, digital I/O module, such as the ScanIO-300LV, to test all your I/O pins,

thus increasing test coverage.


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Limitations

1. SMT target is to develop high density boards so we have to compromise in the rating of

boards.

2. Some components could not withstand very high temperatures in soldering oven, so we need

to solder them separately in THT process.

3. SMC Standardization: The same SMC from two different manufacturers may have different

dimensions, which may create a problem. Hence standardization is necessary. Till today no

standardization is made.

4. SMC Availability: Some 15,000 components are available as SMC but not all of them may

be available when needed i.e. wanted.

5. High startup expenses: The startup cost of SMT for both manufacturers and individual

experimenters can be high. For manufacturers automated production equipment is most

expensive investment. For experimenters requires new assembly tools and stock of surface

mountable resisters, capacitors, Diodes, transistors, ICs, etc.

6. Thus the overall cost is very high.

7. In MDA the continuity is the problem in testing of some components for different frequencies.

And in this we need to develop perfect patterns on probe able test pads.

8. In boundary scan test the perfect data isolation is the problem because of forced data out for

some occasions.


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Conclusion:

SMT is more advantages than the conventional circuit board. Because it reduces the size of

circuit board, cost, weight etc. And the new automated machines easier our work and make it more

accurate. Due to above advantages SMT circuit can be mount on the coin or on the postal stamp.

Also the circuit can be mounted on both sides of the circuit board. So now a day it is used in

mobile, calculator or the circuit where small space circuit is required. But it needed to overcome

the problems in soldering and testing of the PCBs. By using MDA in addition to the bed of nails

test fixture the faults can be easily detected. By using CAD software in designing of probe able test

pads the accuracy of the tester increases. But this physical test access does not give accurate results

for latest and some double sided PCBs so we need to adopt latest technology like boundary scan

test access which can detect line faults, short faults and open faults etc. The AOI machine can work

in integration with boundary scan test access which is very helpful in detecting faults in initial

stages itself. While it is obvious that boundary-scan based testing can be used in the production

phase of a product, new developments and applications of the IEEE-1149.1 standard have enabled

the use of boundary-scan in many other product life cycle phases. Specifically, boundary-scan

technology is now applied to product design, prototype debugging and field service .This means

the cost of the boundary-scan tools can be amortized over the entire product life cycle, not just the

production phase.


Page | 53

Bibliography:

1) E-BOOK ON SURFACE MOUNT TECHNOLOGYCOMPILED BY DR. KANTESH

DOSS ELCOTEQ, INC.

2) MIRTEC automatic machines user manual.

3) www.logextechno.com

4) Non-Contact Test Access for Surface Mount Technology IEEE 1149.1-1990

5) www.radioelectronics.com

6) Surface Mount Technology: Principles and Practice by Ray P. Prasad

7) The Electronic Packaging Handbook edited by Glenn R. Blackwell

http://www.google.co.in/search?tbo=p&tbm=bks&q=inauthor:%22Ray+P.+Prasad%22

Documents

Advancements in the process of SMT assembly