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Advanced SW/HW Optimization Techniques for Application Specific MCSoC m5151117 Yumiko Kimezawa Supervised by Prof. Ben Abderazek Graduate School of Computer Science and Engineering Adaptive Systems Laboratory September 8, 2011 Research Plan Seminar 1

Advanced SW/HW Optimization Techniques for Application Specific MCSoC m5151117 Yumiko Kimezawa Supervised by Prof. Ben Abderazek Graduate School of Computer

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Advanced SW/HW Optimization Techniques for Application

Specific MCSoC

m5151117

Yumiko Kimezawa

Supervised by Prof. Ben Abderazek

Graduate School of Computer Science and Engineering

Adaptive Systems Laboratory

September 8, 2011 Research Plan Seminar 1

Outline

1. Background2. Problems3. Research Goal4. Research Approach5. Research Schedule

September 8, 2011 Research Plan Seminar 2

Background

• Electrocardiography (ECG)- Electrical activity of the heart- Used for diagnosis of heart disease

• Processing ECG signals involves heavy computation

• Previous proposed ECG processing system- Parallel processing using additional cores for

analyzing ECG signals

September 8, 2011 Research Plan Seminar 3

BackgroundPeriod-Peaks Detection (PPD) Algorithm (1)

Figure: A typical ECG graph

September 8, 2011 4Research Plan Seminar

Period detection

Peaks processing

Data reading

Derivation

Autocorrelation

Finding interval

Extraction

Store of results

Discrimination

September 8, 2011 5Research Plan Seminar

BackgroundPeriod-Peaks Detection (PPD) Algorithm (2)

A. Ben Abdallah, Y. Haga, K. Kuroda, An Efficient Algorithm and Embedded Multicore Implementation for ECG Analysis in Multi-lead Electrocardiogram Records , IEEE Proc. of the 39th he International Conference on Parallel Processing , San Diego, pp.99-103, Sept. 13-16, 2010.

The system consists of mainly 2 modules• Master module

- Signal reading, filtering and display part• PPD module

- Analyzing ECG signal using Period-Peaks Detection (PPD) algorithm

August 22, 2011 6Master's Thesis Research PlanSeptember 8, 2011 6Research Plan Seminar

BackgroundSystem Base Architecture (1)

• 3-lead system is implemented

ADC 1

ADC 12

FIR 1

FIR12

Buffer

ECGSignal

Analysis

1:Signal reading 2:Filtering 3:Analysis 4:Display

12 leads

External Memory

Patient: AP = # mV Q = # mVR = # mV S = # mVT = # mV U = # mV

Interval = # ms

Not implemented Our ideal system architecture

September 8, 2011 7Research Plan Seminar

BackgroundSystem Base Architecture* (2)

* A. Ben Abdallah, Y. Haga, K. Kuroda, An Efficient Algorithm and Embedded Multicore Implementation for ECG Analysis in Multi-lead Electrocardiogram Records , IEEE Proc. of the 39th he International Conference on Parallel Processing , San Diego, pp.99-103, Sept. 13-16, 2010.

Single lead 3-lead

Logic utilization 15% 38%

Processing time 11.209 s 16.975 s

Problems

• BANSMOM runs sample data only- Can not read actual data- Difficultly in estimation of real processing time - Cannot estimate real system complexity and power

• Low hardware usability - The more leads, the more larger logic utilization

• Current driver software is not well parallelized

September 8, 2011 8Research Plan Seminar

Research Goal

• Research about software and hardware optimization techniques for Embedded Multicore SoC (BANSMOM)- Capturing and analyzing of real ECG signals- Research about HW optimization- Parallelizing PPD algorithm (driver software)

September 8, 2011 9Research Plan Seminar

Research Approach (1)

• Hardware/Software optimization- Hardware

• Adding A/D converters• Fast data transfer between each memory

DMA controller- Software

• Parallelizing Period-Peaks Detection (PPD) algorithm by refining the code and looking for parallel tasks

September 8, 2011 Research Plan Seminar 10

Research Approach (2) : Data flow

: Control signal

Graphic LCD Controller

Master CPUMemory

MasterCPU

Timer

GraphicLCDLED

JTAGUART

PPD Module Master Module

LEDController

Avalon Bus

FIR FilterTimer

Slave CPU Memory

SlaveCPU

ExternalMemory

SharedMemory

FPGA

Analog ECG data from the sensor

Line-in

Data conversion HSMC

A/D converter

DMAcontroller

September 8, 2011 11Research Plan Seminar

Evaluation Methodology• Environment

- Language: Verilog HDL- Tools: Quartus II, SOPC Builder, and NIOS II IDE- Target device: Stratix III DSP Board (EP3SL150F1152C2)- Sensor: Pulse wave/PCG sensor TK-701T- Target data: actual ECG signals

• Parameters- Hardware complexity- Processing time

September 8, 2011 12Research Plan Seminar

Stratix III

Sensor

2011 2012 2013

9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3

September 8, 2011 13Research Plan Seminar

• Investigating suitable resolution and sampling rate for A/D conversion• Selecting appropriate an A/D converter

• Adding the A/D converter into the system• Getting actual data using the sensor

•Adding DMA controller into the system

• Optimization of software

•Verification of the system

• Writing master’s thesis

Research Schedule

Thank you for listening

September 8, 2011 14Research Plan Seminar

September 8, 2011 Research Plan Seminar 15

16

Period detection

Peaks detection

Reading data

Derivation

Autocorrelation

Find interval

Extraction of max point

Store results

Discrimination

Research Plan Seminar

• Based on autocorrelation approach

Research Approach (2)

Parallelizing this phase

September 8, 2011

2011 2012 2013

9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3

September 8, 2011 17Research Plan Seminar

• Investigating suitable resolution and sampling rate for A/D conversion• Selecting appropriate an A/D converter

• Adding the A/D converter into the system• Getting actual data using the sensor

•Adding DMA controller into the system

• Optimization of software

•Verification of the system

• Writing master’s thesis

Research Schedule