Advanced Metallization

Conference 2006

(AMC 2006)

These proceedings represent the work of presenters at the Conferences held

October 17-19, 2006, in San Diego, California, U.S.A. and September 26-27, 2006, at

the University of Tokyo, Tokyo, Japan. This combined Conference is MRS affiliated

and sponsored by the Continuing Education in Engineering, University Extension,

University of California at Berkeley, California, U.S.A.

EDITORS:

Stephen W. Russell

Micron Technology

Boise, Idaho, U.S.A.

Michael E. Mills

Dow Chemical -- Advanced Electronic Materials

Midland, Michigan, U.S.A.

Akihiko Osaki

Rcnesas Technology Corporation

Myogo, Japan

Takashi YodaToshiba CorporationYokohama, Japan

IMIRISI

Materials Research Society

CONTENTS

Preface xix

Acknowledgments xxi

Materials Research Society Conference Proceedings xxiii

KEYNOTE PRESENTATION

**Nanostructured Materials for Interconnects 3

Gael F. Close and H.-S. Philip Wong

DESIGNANDINTERCONNECTMODELING

* Modeling and Extraction of Nanometer Scale

Interconnects: Challenges and Opportunities 17

Roberto Suaya, Rafael Escovar, Salvador Ortiz,Kauslav Banerjee, andNavin Srivastava

On-Chip Differential-Transmission-Line (DTL)Interconnect for 22nm Technology 29

Kenichi Okada, Hiroyuki Ito, and Kazuya Masu

MVLTILE VEL PROCESSINTEGRATION

* Reliable and Manufacturable 45nm BEOL Structure

Using Hybrid Porous PAr/Porous SOG Stack 37

Hideshi Miyajima, Kei Watanabc, Miyoko Shimada,Toshinobu Sakanaka, Naofumi Nakamura,Tsutomu Shimayama, Yoshiyuki Enomoto,

Hiroyuki Yano, and Takashi Yoda

A Reliable Interconnect Integration Scheme CombiningAir Gaps and Electro-less Deposition 45

R. Daamen, A. Kolics, J. Michelon, J. Noiray,P.H.L. Bancken, V.H. Nguyen, G.J.A.M. Verheijden,and R.G.R. Weemaes

** Keynote

Invited Paper

v

Damascene Copper Integration Issues in SiCOH Dielectric 53

Anthony K. Stamper, Gasner Barthold, Christine Bunke,Anil Chinthakindi, Edward Cooney III, Eduardo Garcia,

Zhong-Xiang He, Frank Jackson, Steffen Kaldor,

Ryan Kelly, Debra Leach, Peter Lindgren,Thomas McDevitt, Timothy Milmore, Matthew Moon,Brian Pfeifer, Christopher Pluchino, Bruce Porth,

Michael Premsagar, Mai Randall, Colleen Snavely,Aurelia Suwarno-Handayana, Matthew Tiersch,

Arthur Winslow, and Robert Zwonik

Low-k/Cu Interconnect Integration With Low-DamageAsh Using Atomic Hydrogen *>1

Kazuhiro Tomioka, Seiichi Kondo, Naofumi Ohhashi,

Takamasa Suzuki, Eiichi Soda, and Nobuyoshi Kobayashi

COPPER

* Challenges and Opportunities for Electrochemical

Deposition in Interconnects *»9

Tom Ritzdorf

Surface Scattering Revisited: Dimensional and Low

Temperature Trends 77

Sywert Hidde Brongersma and Wenqi Zhang

Cu Resistivity in Narrow Lines: Impact of ElectroplatingChemistry on Grain Boundaries Contribution 83

Sylvain Maitrejean, Thieny Mourier, Pascal Chausse,Valerie Safraoui, Philippe Holliger, Maryline Cordeau,and Joaquin Tones

Cu Thin Film Deposition From Supercritical CarbonDioxide Fluids Using a Flow-Type Deposition Processor ...91

Eiichi Kondoh, Michiru Hirose, and Junpei Fukuda

High Sputter Bias Super Secondary Grain Growth

Initiation (In Structures) 9*7

Kris Vanstreels, Sywert H. Brongersma, Jan D'Haen,Steven Demuynck, Ward De Ceuninck, Rudi Caluwaerts,and Marc D'Olieslaeger

*Invited Paper

VI

Integration and Characterization of a Hybrid Cu Line

Coating Using CoWP Self Aligned Barrier Capped With

a Low-k Etch Stop Liner 105

Julie Guillan, Laurent G. Gosset, Sonarith Chhun,Michel Gallitre, Alexis Farcy, Emmanuel Oilier,

Philippe Brim, Valerie Girault, Emmanuel Petitprez,Marc Juhcl, Raphael Gras, Arulkumar Shanmugasundram,Chad Peterson, Sothachett Van, and Joaquin Torres

Reaction Mechanism of Low-Temperature DamagelessCleaning of Cu20 by HCOOH Ill

Masakazu Sugiyama, Isao Gunji, Kenji Ishikawa,Masafumi Nakaishi, Kouichi Yamashita, and

Takayuki Ohba

Controlling the Resistivity of Fine Line Cu Interconnects 117

Khyoupin Khoo, Jin Onuki, Takahiro Nagano,Yasunori Chonan, Haruo Akahoshi, Toshimi Tobita,

Masahiro Chiba, Talsuyuki Saito, and Kensuke Ishikawa

Influence of Barrier Crystallization on CV Characteristics

of MIS Structures 123

Ramona Ecke, Michael Rennau, Sven Zimmermann,Stefan E. Schulz, and Thomas Gessner

Electrografting of Ultra-Thin (sub-lOnm) Seed Layers for

Advanced Copper Metallization 129

Frederic Raynal, Emmanuel Guidotti, Jose Gonzalez,Sebastien Roy, and Stephane Getin

Controlling Impurity Levels of Copper ElectrodepositedFilms in the Damascene Process 137

Anthony Meunier, Celine Bondoux, Laurent Omnes,

Francois Jomard, and Arnaud Etcheberry

Cu Diffusion Barrier Property Improvement of Ru byAl Stuffing for Future Highly Reliable Interconnect 145

Atsushi Seki, Hoon Kim, and Yukihiro Simogaki

vn

METALLIZATION, MATERIAL SCIENCE

ANDINTERFACES

* Metallization Materials and Processes Beyond 45nm Node:

Challenges and New Solutions for Barrier Deposition, Copper

Seeding and Capping 155

Paul-Henri Haumesser, Anne Roule, Segolene Olivier,

Tifenn Decorps, Thierry Mourier, Wim Besling,Laurent Gosset, Julie Guillan, Raphael Gras,

Sonarith Chhun, Gerard Passemard, and Joaquin Torres

* Three-Dimensional Imaging of Nano-Voids in CopperInterconnects Using Incoherent Bright Field (IBF)

Tomography 163

Peter Ercius, David A. Muller, Matthew Weyland, and

Lynne M. Gignac

Electroless CoWP Capping for Cu/Low-k Integration 171

Takashi Ishigami, Tomoatsu Ishibashi, Xinming Wang,Haruko Ono, Akira Owatari, Seiichi Kondo, and

Nobuyoshi Kobayashi

Impacts of Cu Metallization on High Density Damascene

Cu/TiN/Ta2Os/TiN/Cu Metal-insulator-Metal Capacitors 177

Maryline Thomas, Alexis Farcy, Cedric Perrot,Mickael Gros-Jean, Patrick Joubin, Igor Matko,

Maryline Cordeau, Pierre Caubet, Rym Benaboud,

Alexandre Bonnard, Simon Guillaumet,

Thierry Jagueneau, Claire Richard, Emilie Deloffre,Sebastien Cremer, Bernard Chenevier, and

Joaquin Torres

Novel PVD Process of Barrier Metal for Cu Interconnects

Extendable to 45nm Node and Beyond 185

H. Sakai, N. Shimizu, N. Ohtsuka, T. Tabira, T. Kouno,M. Nakaishi, and M. Miyajima

W-CVD Using Bisisopropylcyclopentadienyltungstendihydride 191

S. Imai, T. Kagawa, H. Kurozaki, A. Ogura, M. Ishikawa,

I. Muramoto, H. Machida, and Y. Ohshita

* Invited Paper

vin

Ultra Thin lnm-Thick Continuous PEALD-Ru Formation

for Masking Bottom Barrier Metal From Etching Solvent

in Wet Phase and Oxidation in Gas Phase 197

Daekyun Jeong, Ozawa Souki, Inoue Hiroaki,Akira Shimizu, and Hiroshi Shinriki

Effect of IrOx Crystal Orientation on Adhesion Propertiesof Pt/IrO, Bottom Electrode in FeRAM Capacitors 203

Daisuke Inomata, Yasushi Igarashi, Kazuhide Abe,and Takashi Taguchi

Self-Aligned Barriers on Cu Interconnections for CMOS

Image Sensor Technology 209

Laurin Dumas, Cecile Jenny, Giuseppe Anastasi,

Marc Juhel, Chantal Trouiller, Thierry Jagueneau,and Claire Richard

PVD TaN/Ta Barrier Studies on Impact to RC Performance

and Resistivity Behavior for 45nm Node 215

Michael Beck, Lawrence A. Clevengcr, Armin Fischer,Naftali E. Lustig, Bum Ki Moon, and Theodorus E. Standaert

Electroless Deposition of Co-Based Barriers: Selectivity,Corrosion and Growth Properties ....221

Tifenn Decorps, Paul-Henri Haumesser, Segolene Olivier,Anne Roule, Xavier Avale, Mickael Joulaud, Olivier Pollet,Eric Chainet, and Gerard Passemard

Thin Film Characterization of PEALD Ru Layers on an

ALD WNC Substrate 227

Henny Volders, Zsolt Tokei, Fabrice Sinapi, Hugo Bender,Alessandro Benedetti, Bert Brijs, Thierry Conard,Alexis Franquet, Johnny Steenbergen, YoussefTravaly,Hessel Sprey, Wei-Min Li, Akira Shimizu, and

Hyung Sang Park

Conformal Deposition of Metal Oxide Films in SupercriticalCarbon Dioxide 233

Adam O'Neil and James J. Watkins

Chemical Vapor Deposition Growth and Characterization

of Amorphous Ruthenium Phosphorous Alloy Films 239John G. Ekerdt, Jinhong Shin, Lucas B. Henderson,Wyatt A. Winkenwerder, Abdul Waheed, and

Richard A. Jones

IX

Properties of Ge/HfN, Bilayer as a Diffusion Barrier for

Cu Metallization 245Seemant Rawal, KeeChan Kim, David P. Norton,

Tim Anderson, and Lisa McElwee-White

ADVANCEDSEMICONDUCTOR DEVICE

ARCHITECTURE (< 32nm)

* Integration of Carbon Nanotubes Into Via Structures 2f?»3

Yuji Awano

High Performance Ultra Low-k (k=2.0/keff=2.4) HybridDielectrics/Cu Dual-Damascene Interconnects With

Selective Barrier Layer for 32nm-node 2<*3Yumi Hayashi, Kazumichi Tsumura, Miyoko Shimada,Kei Watanabe, Hideshi Miyajima, Takamasa Usui, and

Hideki Shibata

PEALD of Ru Layer on ALD-WNC Barrier for Cu/Porous

Low-k Integration 2<>9K. Namba, T. Ishigami, M. Enomoto, S. Kondo,H. Shinriki, D. Jeong, A. Shimizu, N. Saitoh,W-M. Li, S. Yamamoto, T. Kawasaki, T. Nakada,

and N. Kobayashi

Mechanical Models of Polycrystalline 3D-IC Interwafer Vias Z75

Daniel N. Bentz, Max O. Bloomfield, Jian-Qiang Lu,

Ronald J. Gutmann, and Timothy S. Cale

Physical Properties of PECVD Amorphous Carbon Depositedat High Temperature for Use as an Etch Hard Mask 2.81

Steven R. Smith, Roshan J. George, Doug H. Lee,

Donghui Lu, and Oleh P. Karpenko

LOW-kINTERLAYER DIELECTRICS

* Non-Poisoning Dual Damascene Patterning Scheme for

Low-k and Ultra Low-k BEOL 2t81W. Cote, D. Edelstein, C. Bunke, P. Biolsi, W. Wille,H. Baks, R. Conti, T. Dalton, T. Houghton, W-K. Li,Y-H. Lin, S. Moskowitz, D. Restaino, T. Van Kleeck,S. Vogt, and T. Ivers

*Invited Paper

x

Photo-Stimulated Desorption From Porous Low-k Films

by UV Cure Treatments With Various Wavelength 295Fuminori Ito, Tsuneo Takeuchi, and Yoshihiro Hayashi

Silylation Gas Restoration Subsequent to All-in-One

RIE Process Without Air Exposure for Porous Low-k

SiOC/Copper Dual-Damascene Interconnects 301

A. Kojima, N. Nakamura, N. Matsunaga, H. Hayashi,K. Kubota, R. Asako, K. Maekawa, H. Shibata, T. Yoda,and T. Ohiwa

Material Design of Porous Low-k Materials for 45nm Node

Interconnects 307K. Watanabc, H. Miyajima, M. Shimada, N. Nakamura,T. Shimayama, Y. Enomoto, FI. Yano, and T. Yoda

Effect of Surface Modification of Nano-Porous Low-k Film

on Cu Barrier Layers 313Bum Ki Moon, A. Simon, M. Shall Pallachalil, T. Bolom,H. Wendt, M. Chae, P. Dehaven, C. Dziobkowski, A. Madan,

P. Flailz, S.M. Choi, S.L. Liew, J, Working, S. Grunow,S.O. Kim, E. Kallalioglu, M. Beck, and L. Clevenger

Computational Approach to Structures, Properties, andUltraviolet-Cure Mechanism of a Porous-SiOC Material 321

Jiro Ushio, Tomoyuki Hamada, Takahisa Ohno,

Shin-Ichi Nakao, Katsumi Yoneda, Manabu Kato,and Nobuyoshi Kobayashi

Effect of UV Cure on Adhesive and Cohesive Failure of

Low-k Films: Implications for Integration ...327

David M. Gage, Jonathan F. Stebbins, and

Rcinhold I-I. Dauskardt

* Influence of Precursor Chemistry and Process Conditions on the

Structure and Properties of Porous Low-k Organosilicate Glasses 331

Raymond N. Vrlis, Dinjun Wu, Stephen A. Motika,Mark L. O'Neill, Mary K. Haas, Brian K. Peterson,

Scott J. Weigel, Mark D, Bilner, Patrick T. Hurley,and Eugene J. Karwacki

*Invited Paper

xi

Si-C2H4-Si Network Formation for Improvement of PECVD

SiOCH Film Properties 339

Manabu Shinriki, Nobuo Tajima, Tomoyuki Hamada,

Takahisa Ohno, Katsumi Yoneda, Seiichi Kondo,

Shinichi Ogawa, Kazuhiro Miyazawa, Yoshiaki Inaishi,

Kaoru Sakoda, Satoshi Hasaka, and Minora Inoue

Post Integration Porogen Removal Approach Using a

PECVD Ultra Low-k Material 345

L. Favennec, V. Jousseaume, A. Zenasni, M. Assous,

T. David, and G. Passemard

A Porous SiCOH Dielectric With k=2.4 for High Performance

BEOL Interconnects 3 $ I

S.M. Gates, A. Grill, C. Dimitrakopoulos, D. Restaino,

M. Lane, V. Patel, S. Cohen, E. Simonyi, E. Liniger,Y. Ostrovski, R. Augur, M. Sherwood, N. Klymko,S. Molis, W. Landers, D. Edelstein, S. Sankaran,R. Wisnieff, T. Ivers, K. Yim, V. Nguyen, T. Nowak,

J.C. Rocha, S. Reiter, and A. Demos

Barrier-Free Interconnect With Organic Spin-On Dielectric 35»9

Nobuhide Maeda, Yoshio Takimoto, Kenzo Maejima,Michio Nakajima, and Keisuke Funatsu

Porogen Precursors for ULK (k<2.2) PECVD Dielectrics 3>*t

Steven Bilodeau, Phil Chen, William Giannetto,

Chongying Xu, William Hunks, Thomas H. Baum,

and Jeffrey F. Roeder

Process Response of UV Curable CVD Porous Ultra-Low-k

Dielectric 375

Sharath Hosali, Gregory Smith, Larry Smith, Sanjit Das,

and Sitaram Arkalgud

Stress Analysis of Low-k Material Interface During CMP 3 K3

Yoshihiro Mochizuki, Hideki Shibata, Manabu Tsujimura,and Hirokuni Hiyama

Non-Uniform UV Curing Effects on Mechanical and

Fracture Properties ofOrganosilicate Low-k Thin Films 3H9

Taek-Soo Kim, Naoto Tsuji, Nathan Kemeling,Kiyohiro Matsushita, and Reinhold H. Dauskardt

xu

Diffusion of Aqueous Solutions in Nanoporous Ultra Low-k

Films 395

Carole Couturier, Patrick Leduc, Thierry Farjot, and

Gerard Passemard

Dependence of Ultra Low-k Film (1.8<k-value<2.5)Properties and Stack Characteristics on UV-CuringTreatment Efficiency 401

Julicn Viliello, Laurent-Luc Chapelon, Daniel Barbier,

and Joaquin Torres

Ultra Low-k Dielectrics Prepared by PECVD Using a

Single-Precursor and Treated by UV Assisted Thermal

Processing 407

Qingguo (Gordon) Wu, Easwar Srinivasan, Dan Vitkavage,

Roey Shaviv, Hui-Jung Wu, Harald TeNijenhuis,Tom Mountsier, Bart van Schravendijk, Jim Lee,Simon Kuo, Feng-Yu Hsu, J-.I. Huang, Climbing Huang,and S.J. Sung

Mechanically Strong Ultralow-k Nanoporous Silica

Made of SiOx Nanoparticlcs 413

Shinji Nozaki, Hiroshi Ono, and Kazuo Uchida

Optimizing the Ultra-Violet Cure Process for Porous

Organosilicate Films Produced by Plasma Enhanced

Chemical Vapor Deposition 419

Mary K. Haas, Carlo Waldfried, Palani Sakthivel,

Mark L. O'Neill, Darren Moore, Orlando Escorcia,Scott J, Weigel, Patrick T. I lurley, andKathleen E. Theodorou

Effect of Low-k Surface Roughness on Subsequent Metal

Layers 425

Casey E. Smith, D.W. Mueller, P.D. Maiz, and R.F. Reidy

RELIABILITYAND PERFORMANCE

* In Situ Studies and Monte Carlo Simulation of Electromigration-Induced Void Evolution in Dual In-Laid Cu Interconnect

Structures for Several Geometries 435

A.V, Vairagar, M.A. Meyer, K. Zscheeh, W. Shao,

S.G. Mhaisalkar, A.M. Ciusak. and K.N. Tu

*Invited Paper

xin

Impact of Dielectric Material and Metal Arrangement on

Thermal Behavior of Interconnect Systems 445

Knut Schulze, Stefan E. Schulz, and Thomas Gessner

Microstructural Evolution of Cu Interconnect Under AC,

Pulsed DC and DC Current Stress 453

Leen Biesemans, Kris Vanstreels, Sywert H. Brongersma,Jan D'Haen, Ward De Ceuninck, and Marc D'Olieslaeger

Infusion Processing for Reliable Copper Interconnects 45"

S. Kondo, T. Ishigami, M. Enomoto, S. Sherman,

M. Tabat, and J. Hautala

Reliability Improvement and Its Mechanism for Cu

Interconnects With Cu-Al Alloy Seeds 467

Kenichi Mori, Kazuyoshi Maekawa, Noriaki Amou,Daisuke Kodama, Hiroshi Miyazaki, Naohito Suzumura,Kazuhito Honda, Yukinori Hirose, Koyu Asai, and

Masahiro Yoneda

Nanometer-Scale Stress Field Evaluation of Cu/ILD

Pattern; Comparison Between Cathodoluminescence

Spectroscopy and Thermal Stress Analyses by Finite

Element Method 475

Masako Kodera, Sachiyo Ito, Masahiko Hasunuma,

and Shigeru Kakinuma

Cu/Low-kTDDB Degradation Using Ultra Low-k (ULK)Dielectrics 481

Noriko Miura, Kinya Goto, Shinobu Hashii,

Naohito Suzumura, Hiroshi Miyazaki,Masahiro Matsumoto, Masazumi Matsuura,and Koyu Asai

Low-k Materials Face Damages Induced by Mismatch of

Thermal Expansion Around the Global Bus Lines When

Operation Frequency is High 489

H. Kato, T. Yoshida, T. Tatsuta, and E. Kondoh

The Stress Control of Capping Insulators as a Key to

Preventing Electromigration and Stress-Induced VoidingFailures -495

Daisuke Kodama, Shoich Fukui, Noriko Miura,

Kinya Goto, Naohito Suzumura, Masazumi Matsuura,

Takeshi Furusawa, and Hiroshi Miyazaki

xrv

The Effect of SiN Preclean Conditions on ElectromigrationLifetime and Resistance of Cu Interconnects 501

JeffGambino, Thomas L. McDevitt, Felix P. Anderson,Jason Gill, Stephen A. Mongeon, and Jay Burnham

Characterization and Integration of a PECVD Advanced

Barrier (k=4.0) for 45nm CMOS Technology and Below 509

Laurent-Luc Chapelon, Philippe Brun, Julien Vitiello,

Daniel Barbier, and Joaquin Torres

Influence of Porosity and Film Thickness on Adhesion of

Nanoporous Organic Dielectrics 517

Andrew V. Kearney, Heitor Chang, Michael E. Mills,

and Reinhold H. Dauskardt

Integration and Reliability of Advanced Dielectric Barriers

in Copper Damascene Applications 521

Huiwen Xu, Mehul Naik, Li-Qun Xia, Vladimir Zubkov,

Ritwik Bhatia, Chad Peterson, and Hichem M'Saad

Interface Chemistry and Adhesion Strength Between Porous

SiOCH Extra-Low-k Film and SiCN Layers Under Different

Plasma Treatments 527

Shou-Yi Chang, Jien-Yi Chang, and Su-Jien Lin

CMP

*

Changing Density Requirements for Semiconductor

Manufacturing 535

Howard S. Landis and Jeanne-tania Sucharilavcs

Evaluation of MBT Anticorrosive Layer on Cu Surface

for Chemical-Mechanical Polishing Application 543

H. Nishizawa, 0. Sugiura, Y. Matsumura, and

M, Kinoshita

Impact of Direct CMP on Surface and Bulk Propertiesof High Porosity Low-k Dielectrics 549

Nancy 1 leylen, Fabrice Sinapi, YoussefTravaly,Guy Vereeeke, Mikhail Bakianov, Laureen Carbonell,Jan Van Hoeymissen, David Ilellin, J.L. Hernandez,

Gerald Beyer, and Paul Fischer

* Invited Paper

xv

Charging Induced Missing Pattern on Metal Layers in^

65nm Technology Node 5-

Y.C. Ee, C. Perera, J.B. Tan, B.C. Zhang, Y.K. Siew,

B.M. Seah, R. Joy, C.H. Low, H. Liu, S.T. Chua,

Freda C.H. Lim, Thomas Fu, and L.C. Hsia

Surface Roughness Evaluation of Electrochemical

Mechanical Polishing (ECMP)Yasushi Toma, Akira Kodera, Tsukuru Suzuki,

Takayuki Saitoh, Flirokuni Hiyama, Itsuki Kobata,

Yutaka Wada, Akira Fukunaga, and Manabu Tsujimura

Study on Groove Pattern Layout for Slurry Flow Control

in CMP Process

Keiichi Kimura, Katsuya Nagayama, Hirofumi Morishita,

Yosuke Inatsu, and Panart Khajornrungruang

^tf5

*7l

Characterization of Organic Dielectric for Sealing

Air-Gaps With STP Technology 5?7

Norio Sato, Katsuyuki Machida, Hiromu Ishii,

Yoji Ishimura, Hidenori Saito, Sumitoshi Asakuma,

Masafumi Kawagoe, and Hideki Adachi

Characteristics of Thick Multilevel Interconnection

Based on Gold Electroplating and STP Technique f>83

N. Shimoyama, K. Ono, N. Sato, H. Ishii, T. Kamei,

K. Kudou, and K. Machida

Effect of Slurry Chemistry and Pattern Density on Sheet

Resistance in Tungsten Chemical Mechanical Polishing 581

Jae-Hong Kim, Sang Jun Park, Pil Keun Song,Hyun Joo Kim, Seon Byoung Kwon, Sun Young Cho,

Yong Taek Song, Choon Kun Ryu, and Sung Ki Park

CONTACTLEVEL SILICIDE

* Material and Integration Scaling in the Contact Module

Beyond the 65nm Node 591

Eric Gerritsen

*Invited Paper

xvi

New Barrier Metal and ALD-W Process for Low Stable

Resistance in Contact Metallization Beyond 45nm CMOS 605

Kazuhito Ichinose, Akie Yutani, Kazuyoshi Maekawa,

Koyu Asai, and Masahiro Yoneda

Native Oxide Removal Application Using NF3/NH3 Remote

Plasma for Ni Silicidc Process 611

Takashi Kuratomi, Keiichi Tanaka, Daniel I. Diehl,

See-Eng Phan, Xinliang Lu, David Or, Jianxin Lei,

Gigi Lai, Kishore Lavu, Chong Jiang, Kevin Moraes,Chien-Teh Kao, Takuya Futase, and Kazuyoshi Maekawa

Evaluation ofVery Low Resistivity TiNx Film Using Cat

(Catalytic) Radical Reaction With TiCL, 617

M. Harada, IC. Kamada, S. Toyoda, N. Katou, and

H. Ushikwa

The Application of HARP for PMD Gap-Fill for 65nm

Technology Node and Below 623

H. Liu, W. Lu, Z.G. Sun, L. Goh, B. Zuo, V. Ho,M.S. Zhou, L.C. Hsia, T. Chu, C. Ching, H.S. Tang,K.S. Too, and G. Zou

Anomalous Whisker Generation in Ni-Silicided Source

and Drain for Three-Dimensional Beam-Channel MOS

Transistor on SOI Substrate 631

Shunpei Matsumura, Atsushi Sugimura, Kiyoshi Okuyama,and Hideo Sunami

Low-Resistance Ti-Silicide Contact Formation to p+Layer for Use in Analog Devices... 637

Hiroyuki Kuehiji and Masaaki Sato

Properties of Chemical Reaction During Ni and

Ni-Silicide Deposition Using Ni(PF3)4 and Si.^Hs 643

M. Ishikawa, I. Muramoto, I-I. Machida, S. Imai,A. Ogura, and Y. Ohshita

Mitigation of Size Effect on the Resistivity of Chemical

Vapor Deposited W Thin Film and Applications to Bit

Line Materials for Advanced Memory Devices 649

Soo-Hyun Kim, Jeong Tae Kim, Tae Kyung Kim,

Eun-Soo Kim, Nohjung Kwak, and Jinwoong Kim

xvi t

A Self Assembly Monolayer Activated Electroless

Deposition Process for Interconnect and Contact

Applications 65"

Y. Shacham-Diamand, M. Yoshino, A. Duhin,

Y. Sverdlov, and T. Osaka

PACKAGING/EMERGING TECHNOLOGY

Low-Cost Through-Hole Electrode Interconnection for

3D-SiP Using Room-Temperature Bonding 66?

Naotaka Tanaka, Yasuhiro Yoshimura, Takahiro Naito,and Takashi Akazawa

A Crackless and Highly Reliable Cu Etrim Fuse Using the Pinch

Effect for 65nm 671

K. Kono, T. Yonezu, S. Obayashi, M. Arakawa, Y. Asano,T. Uchida, and T. Iwamoto

Mass Production of Wafer-Level-Packaging Technology UsingSilicon-Via-Contacts for Optical and Other Sensor Applications .677

Juergen Leib, Florian Bieck, Nathapong Suthiwongsunthor,and Hidefumi Yamamoto

Author Index .,683

Subject Index 691

xviii