SAdvanced Grid SynchronizAdvanced Grid SynchronizAdvanced Grid SynchronizyYif i W ( ifYifei Wang (yifeg (y

Department of EDepartment of E

I IntroductionI. IntroductionDistributed generation (DG) has gained great public interest as an effective approach toDistributed generation (DG) has gained great public interest as an effective approach to

t l t i f bl ( i d t bi l l ) dgenerate electric power from renewable energy sources (e.g. wind turbines, solar panels) andother micro-sources (e.g. fuel cells, micro-turbines).other micro sources (e.g. fuel cells, micro turbines).DG units can operate in stand alone and grid connected modes The interfacing powerDG units can operate in stand-alone and grid-connected modes. The interfacing powerelectronics of DG units can be controlled through voltage regulation and current regulation.g g g gFor current controlled grid connected DG systems phase locked loop (PLL) is popular for theFor current controlled grid-connected DG systems, phase-locked loop (PLL) is popular for thedetection of grid phase angle, which is a vital piece of information for grid synchronization.

Input:pThree-phase gridThree phase grid voltage signalsvoltage signals

Output:Instantaneous grid phase angle

Requirements:Requirements:Fast transient responseFast transient responseI it t ltImmunity to voltage

b l & h iunbalance & harmonicsF d t bilitFrequency adaptability

II Ad d G id S h i ti PLLII. Advanced Grid Synchronization PLLII. Advanced Grid Synchronization PLLBasic PLL based on the synchronous reference frame has to compromise between differentBasic PLL based on the synchronous reference frame has to compromise between differentrequirements − a higher control bandwidth results in faster transient response and moreq g psensitivity to harmonic disturbances while a lower bandwidth has the contrary effectssensitivity to harmonic disturbances, while a lower bandwidth has the contrary effects.The proposed advanced grid synchronization PLL cascades multiple generalized delayed signalcancellation (DSC) operators to eliminate harmonic signals and makes it possible for gridcancellation (DSC) operators to eliminate harmonic signals, and makes it possible for grid

h i ti PLL t j b th f t d i d i it t h isynchronization PLL to enjoy both fast dynamic response and immunity to harmonics.The proposed PLL scheme can have its cascaded delayed signal cancellation (CDSC) operatorThe proposed PLL scheme can have its cascaded delayed signal cancellation (CDSC) operatordesigned in the synchronous or the stationary reference frame i e the dq or the αβ frame fordesigned in the synchronous or the stationary reference frame, i.e. the dq- or the αβ-frame, fordifferent benefits. The whole PLL system is therefore named as dq- or αβ-frame CDSC-PLL.y q βTheir delay factors (n m etc) can be flexibly specified for different harmonic scenarios TwoTheir delay factors (n, m, etc) can be flexibly specified for different harmonic scenarios. Twotypical ones are 1) CDSC-PLL1 with delay factors 4, 6, 24 to address symmetrical harmonics,and 2) CDSC-PLL2 with 2 4 8 16 to address both symmetrical and asymmetrical harmonicsand 2) CDSC PLL2 with 2, 4, 8, 16 to address both symmetrical and asymmetrical harmonics.

fdq-framedq frameC SCCDSC-PLLCDSC PLL

αβ frameαβ-frameCDSC PLLCDSC-PLL

zation Phase Locked Loopzation Phase-Locked Loopzation Phase-Locked Looppi @ lb t ) d Y i Li ( i li@ lb t )ei.wang@ualberta.ca) and Yunwei Li (yunwei.li@ece.ualberta.ca)g@ ) (y @ )

Electrical and Computer Engineering University of Alberta CanadaElectrical and Computer Engineering, University of Alberta, Canada

III Frequency AdaptationIII. Frequency Adaptationq y pWhen grid frequency variations occur CDSC-PLL can use the shown frequency feedback loopWhen grid frequency variations occur, CDSC PLL can use the shown frequency feedback loop( i d t ith d β f CDSC PLL) t d t ll d l ti i it CDSC t(equipped to either dq- or αβ-frame CDSC-PLL) to update all delay times in its CDSC operators,so as to maintain accurate harmonic elimination and achieve frequency adaptability.so as to maintain accurate harmonic elimination and achieve frequency adaptability.

IV Reduction of Discretization ErrorIV. Reduction of Discretization ErrorWhen the CDSC-PLL system is implemented with practical discrete controllers (e g DSP)When the CDSC-PLL system is implemented with practical discrete controllers (e.g. DSP),di ti ti i d t id l li f d/ i d id fdiscretization error can arise due to non-ideal sampling frequency and/or varied grid frequency.Such error can be greatly reduced by an interpolation method specially developed for CDSC-Such error can be greatly reduced by an interpolation method specially developed for CDSCPLL The method can also be adapted for many other delay based PLL schemesPLL. The method can also be adapted for many other delay-based PLL schemes.

Relative error vs.sampling frequencysampling frequency

before and afterbefore and afterth i t l tithe interpolation method is used

V E i t l R ltV. Experimental ResultsV. Experimental ResultsE i t d ith dSPACE® DS1103 l tfExperiments are done with a dSPACE® DS1103 platformfor various test cases, some of which are presented here.for various test cases, some of which are presented here.The follo ing plots sho detected grid phase angleThe following plots show detected grid phase anglevs. input grid voltage with 1) voltage unbalance & sag,p g g ) g g,2) harmonics and 3) frequency variations Experimental2) harmonics, and 3) frequency variations. p

platform

CDSC PLL1platform

CDSC-PLL1CDSC PLL1

CDSC-PLL2CDSC PLL2

Voltage Unbalance & Sag Harmonics Frequency VariationsVoltage Unbalance & Sag Harmonics Frequency Variations

VI C l iVI. ConclusionVI. ConclusionTh d d d id h i ti PLL d d d l d i l ll ti tThe proposed advanced grid synchronization PLL uses cascaded delayed signal cancellation toeliminate harmonic components in grid voltage signals, so the PLL system can achieve fasteliminate harmonic components in grid voltage signals, so the PLL system can achieve fastresponse with high bandwidth without suffering from the detection error caused by harmonicsresponse with high bandwidth without suffering from the detection error caused by harmonics.Frequency variations are considered and can be handled with the developed frequencyq y p q yfeedback loopfeedback loop.

ffDiscretization error in practical implementation is also considered and can be effectively reducedwith the developed interpolation methodwith the developed interpolation method.E i t l lt f t i l t t t d t if th PLL fExperimental results of some typical test cases are presented to verify the PLL performance.