Advanced DVB-S/S2 Demodulator M88DS3103 - cabbala.net

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Advanced DVB-S/S2 Demodulator

M88DS3103

Data Sheet Revision Number: 0.0

Revision Date: November 26, 2010

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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH MONTAGE PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN MONTAGE'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, MONTAGE ASSUMES NO LIABILITY WHATSOEVER, AND MONTAGE DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF MONTAGE PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Montage may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Montage reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

*Other names and brands may be claimed as the property of others.

Do not disclose or distribute to any third party without written permission of Montage.

Copyright © Montage Technology 2010.

Advanced DVB-S/S2 DemodulatorM88DS3103

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PrefaceThis data sheet is the primary reference for the M88DS3103 (Advanced DVB-S/S2 Demodulator). It includes complete pin information, functional description, register description, electrical specification and mechanical package data for engineers who may evaluate or use the M88DS3103.

Terms and Abbreviations

ConventionsThe following conventions are used in this data sheet for easy and effective explanation.

• Cross-references are highlighted as hyperlinks in blue for attention. Click them to go to the corresponding page for details.

• Number representation− A hexadecimal number is represented by XXH. For example, 10H.− A binary number with two or more bits is represented by XXXXB – for example, 1100B; A binary number

with only one bit is represented by 0 or 1.− All other numbers should be considered as decimal numbers. Commonly they are considered as unsigned

integers unless otherwise stated, such as floating-point number, signed integer, etc.• Signal levels are represented by an uppercase HIGH or LOW. Example: This is an active LOW reset signal.

Term Definition Term Definition

ADC Analog-to-Digital Converter IF Intermediate Frequency

AFC Automatic Frequency Correction ISI Intersymbol Interference

AGC Automatic Gain Control LDPC Low Density Parity Check

APSK Amplitude and Phase Shift Keying LNB Low Noise Block

BCH Bose-Chaudhari-Hocquenghem LPF Lowpass Filter

BER Bit/Byte Error Rate LQFP Low Profile Quad Flat Pack

CCI Co-Channel Interference LSB Least Significant Bit

CNR Carrier Noise Ratio MSB Most Significant Bit

CRC Cyclic Redundancy Check Msps Mega symbol per second

CRL Carrier Recovery Loop PID Packet IDentifer

DDS Direct Digital Synthesizer PLL Phase Lock Loop

DiSEqC™ Digital Satellite Equipment Control PSK Phase Shift Keying

DVB-S Digital Video Broadcast over Satellite PWM Pulse Width Modulation

DVB-S2 Digital Video Broadcast over Satellite (Second Generation)

QPSK Quadrature Phase Shift Keying

FEC Forward Error Correction RF Radio Frequency

FFT Fast Fourier Transform RS Reed-Solomon

FIR Finite Impulse Response SNR Signal Noise Ratio

fmclk Frequency of the Master Clock TRL Timing Recovery Loop

FSK Frequency Shift Keying UPL User Package Length

GPIO General Purpose Input/Output UWP Unique Word Processor

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Revision History

Revision Number Revision DateChanges

Page Number Description

0.0 11/26/2010 - Initial release

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Table of ContentsPreface ..................................................................................................................................................................... iTerms and Abbreviations....................................................................................................................................... iConventions ............................................................................................................................................................ iRevision History..................................................................................................................................................... iiFeatures .................................................................................................................................................................. 1Applications ........................................................................................................................................................... 1General Description............................................................................................................................................... 1Block Diagram........................................................................................................................................................ 2

1 Pin Information............................................................................................................................................... 3

1.1 Pin Assignment ...................................................................................................................................... 3

1.2 Pin Description ....................................................................................................................................... 4

2 Function Description ..................................................................................................................................... 7

2.1 ADC ........................................................................................................................................................ 7

2.2 Analog AGC............................................................................................................................................ 7

2.3 AFC......................................................................................................................................................... 7

2.4 Baseband I/Q Impairments Canceller ..................................................................................................... 7

2.5 DDS, Filter Bank and Digital AGC .......................................................................................................... 7

2.6 CCI Canceller.......................................................................................................................................... 7

2.7 TRL ......................................................................................................................................................... 7

2.8 Adaptive Equalizer .................................................................................................................................. 8

2.9 Match Filter ............................................................................................................................................. 8

2.10 UWP........................................................................................................................................................ 8

2.11 CRL......................................................................................................................................................... 8

2.12 Transmitter I/Q Impairments Canceller ................................................................................................... 8

2.13 FEC......................................................................................................................................................... 82.13.1 DVB-S Mode and DVB-S2 Mode ............................................................................................ 82.13.2 DVB-S FEC ............................................................................................................................. 9

2.13.2.1 Digital AGC......................................................................................................... 92.13.2.2 Viterbi ................................................................................................................. 92.13.2.3 Sync Detector ..................................................................................................... 92.13.2.4 De-interleaver ..................................................................................................... 92.13.2.5 RS Decoder ........................................................................................................ 92.13.2.6 Descrambler ..................................................................................................... 10

2.13.3 DVB-S2 FEC ......................................................................................................................... 102.13.3.1 SNR Estimation ................................................................................................ 102.13.3.2 Demapper and De-interleaver .......................................................................... 102.13.3.3 LDPC Decoder ................................................................................................. 102.13.3.4 BCH Decoder ................................................................................................... 10

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2.14 PID Filter ............................................................................................................................................... 11

2.15 MPEG Formatter................................................................................................................................... 112.15.1 DVB Common Interface ........................................................................................................ 122.15.2 Parallel Interface ................................................................................................................... 122.15.3 Serial Interface ...................................................................................................................... 14

2.16 DiSEqC™ 2.X Interface ........................................................................................................................ 142.16.1 LNB Voltage Control.............................................................................................................. 152.16.2 LNB Signaling Control ........................................................................................................... 152.16.3 DiSEqC™ Configuration Flow ............................................................................................... 17

2.17 2-Wire Bus Interface ............................................................................................................................. 182.17.1 2-Wire Bus Repeater............................................................................................................. 18

2.18 FSK Interface........................................................................................................................................ 19

2.19 Clock Generation and Auxiliary Clock Output....................................................................................... 19

2.20 System Control ..................................................................................................................................... 202.20.1 Blind Scan Mode ................................................................................................................... 202.20.2 Sleep Mode ........................................................................................................................... 202.20.3 Lock Indication ...................................................................................................................... 202.20.4 Reset ..................................................................................................................................... 20

3 Register Information .................................................................................................................................... 21

3.1 Register Map......................................................................................................................................... 21

3.2 Register Description.............................................................................................................................. 263.2.1 Common Registers for Both DVB-S and DVB-S2 Modes (Unless Otherwise Indicated) ...... 263.2.2 Registers For DVB-S2 Mode Only ........................................................................................ 543.2.3 Registers For DVB-S Mode Only .......................................................................................... 58

4 Electrical Characteristics ............................................................................................................................ 64

4.1 Absolute Maximum Ratings .................................................................................................................. 64

4.2 Recommended Operating Conditions................................................................................................... 64

4.3 DC Electrical Characteristics ................................................................................................................ 64

4.4 AC Electrical Characteristics................................................................................................................. 65

5 Mechanical Package Data............................................................................................................................ 66

5.1 48-Pin Package..................................................................................................................................... 66

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List of FiguresFigure 1. QFN 48-Pin Pinout.................................................................................................................................. 3

Figure 2. DVB Common Interface Format............................................................................................................ 12

Figure 3. Parallel Interface Format....................................................................................................................... 13

Figure 4. Parallel Interface Timing ....................................................................................................................... 13

Figure 5. Serial Interface Format ......................................................................................................................... 14

Figure 6. Timing Diagram of Tone Burst Control Signal ...................................................................................... 15

Figure 7. DiSEqC™ Message Formats................................................................................................................ 16

Figure 8. Bit Transmission on DiSEqC™ Interface .............................................................................................. 16

Figure 9. Bit Transmission on DiSEqC™ Interface Under Envelop Mode ........................................................... 16

Figure 10. 2-Wire Bus Read Operation.................................................................................................................. 18

Figure 11. 2-Wire Bus Write Operation .................................................................................................................. 18

Figure 12. 2-Wire Bus Repeater ............................................................................................................................ 19

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Montage Technology Confidential and Proprietary vi

List of TablesTable 1. Pin Description of 48-Pin Package ......................................................................................................... 4

Table 2. MPEG-TS Interface Selection............................................................................................................... 11

Table 3. LNB Signaling Mode Selection ............................................................................................................. 15

Table 4. 2-Wire Bus Chip Address Selection...................................................................................................... 18

Table 5. Register Map (Common Registers for DVB-S & DVB-S2 Mode Unless Otherwise Indicated) ............. 21

Table 6. Register Map for DVB-S2 Mode Only ................................................................................................... 24

Table 7. Register Map for DVB-S Mode Only ..................................................................................................... 25

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Features• Multi-standard demodulation

− Compliant with DVB-S/S2 specification− QPSK, 8PSK, 16APSK and 32APSK

demodulation schemes− Maximum channel bit rate: 168 Mbps − Maximum symbol rates: 45 Msps for QPSK,

8PSK and 16APSK; 37 Msps for 32APSK

• DSP features− Symbol rate sweeping− I/Q impairment cancellation− Automatic spectrum inversion− Adaptive equalizer for RF reflection removal− Roll-off factor automatic identification− Blind scan for programming search− High performance on-chip micro-controller− Multi-error monitor− Accurate SNR estimation− Multi-lock indicators− Clipping rate reporter− DC removal− Automatic frequency correction (AFC)− Fast timing loop acquisition− Robust frame synchronization scheme− Excellent phase noise performance− Fast system recovery from fading or other

abnormal conditions− Co-channel interference cancellation− Constellation monitor− DiSEqC envelop mode supported

• Interface− DVB-S/S2 common, parallel and serial MPEG

output interface compliant− Exchangeable Data0 with Data7 output of serial

MPEG TS mode− MPEG TS PID filter − The clock of serial mode can be configured as

192/144/115.2/96/72 MHz− 2-wire serial bus to configure the device− 2-wire bus repeater for tuner configuration− DiSEqC™ 2.X compliant interface− DiSEqC™ envelop mode− FSK interface− General purpose input/output (GPIO) − Dedicated reference clock generation

• System− On-chip 8-bit ADC

− On-chip PLL for master clock from a 4/8/10/16/27 MHz external clock or quartz crystal

− Sleep mode supported

• Technology− Power supplies: 1.2 V and 3.3 V− Low power consumption− Package: 48-pin QFN with exposed pad− RoHS compliant

Applications• Digital satellite set-top boxes• Digital satellite receivers

General DescriptionThe M88DS3103 is an advanced single-chip demodulatorfor digital satellite television broadcasting. It is fullycompliant with the DVB-S/S2 standard and can supportQPSK, 8PSK, 16APSK and 32APSK demodulationschemes. The chip provides a fast, easy-to-apply andcost-effective front-end solution for digital satellitereceiver.

The M88DS3103 accepts baseband differential or single-ended I and Q signals from a tuner, then digitizes,demodulates and decodes the signals, and finally outputsan MPEG transport stream.

The M88DS3103 supports symbol rate from 1 Msps up to45 Msps, and code rate from 1/4 to 9/10. Its featurescover blind scan, fade detection, timing and carrierrecovery, performance monitoring, co-channelinterference cancellation, command interface, andDiSEqC™ 2.X interface, etc. The device is controlled viaa 2-wire serial bus.

The M88DS3103 works properly with 1.2 V and 3.3 Vvoltage supplies, and consumes less power. The chip isavailable in a 48-pin QFN package and is RoHScompliant.

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Revision Number: 0.0Revision Date: November 26, 2010Document Number: SW-0186-S Preliminary 1


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Block Diagram

AGC& Pre-adjust

Timing Recovery,Multiple Roll-off Nyquist &

Interpolation Filters

Carrier Recovery,SNR Estimation & Soft-decision

Micro-controller

DVB-S Mode FEC

DVB-S2 Mode FEC

Error Monitor & Output Formatter

M_D

ATA

[7:0

]

M_E

RR

M_V

AL

M_S

YN

C

M_C

KO

UT

DISEQCDISEQC_IN

XTAL_OUTXTAL_IN

QNQP

IPIN

AAGC

SDASCL

SDATSCLT

DiSEqC Interface

MPEG Interface

Clock

LOCKLock

Indication

____

__R

ESET

Reset

ADDR_SEL

CKXTAL

8

OLFLNB_EN

VSELPower & Supply

8-bit ADC

FSKTX_OUT

FSKRX_IN FSK Interface

2-wire Bus M88DS3103

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1 Pin Information

1.1 Pin Assignment Figure 1. QFN 48-Pin Pinout

Ground – An exposed pad at the bottom of the package.

XTAL_IN

GNDA

IP

FSKTX_OUT

GNDA

XTAL_OUT

VDDA

IN

QP

VCC

QN

NC

SC

LT

AAG

C

SC

L

SD

A

AD

DR

_SE

L

SD

AT

VC

C

VD

DD

CK

XTAL

VC

C

____

__R

ESE

T

VC

C

VCC

M_SYNC

M_DATA6

M_DATA7

M_DATA5

M_VAL

M_DATA3

M_DATA0

M_DATA2

M_DATA1

M_DATA4O

LF

GN

DD

VSE

L

LNB

_EN

LOC

K

VD

DD

FSK

RX

_IN

M88DS3103QFN 48-Pin

VCC

1

2

3

4

5

6

7

8

9

10

11

12

48 47 46 45 44 43 42 41 40 39 38 37

36

35

34

33

32

31

30

29

28

27

26

25

13 14 15 16 17 18 19 20 21 22 23 24

VC

C

DIS

EQ

C

DIS

EQ

C_I

N

M_E

RR

M_C

KO

UT

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1.2 Pin Description Table 1. Pin Description of 48-Pin Package (Sheet 1 of 3)

Name No. Type DescriptionOutput Drive (mA)

Specificities

A/D Converter

IP 6 I Positive In-phase Baseband Input - -

IN 7 I Negative In-phase Baseband Input - -

QN 9 I Negative Quadrature-phase Baseband Input - -

QP 10 I Positive Quadrature-phase Baseband Input - -

Analog AGC

AAGC 13 O(Open-drain)

Analog AGC Control Output to Tuner 4 5 V tolerance

MPEG Interface1

M_DATA[7:0] 33, 32, 31, 30, 28, 27, 26, 25

O Output MPEG-TS Data. When Serial interface is enabled, only M_DATA0 is used, and M_DATA[7:1] are unused and will output ‘0’.

4 -

M_CKOUT 37 O Output Byte/Bit Clock A clock synchronous to MPEG-TS outputs.

4 -

M_VAL 34 O Data Valid Flag An active level indicates that the corresponding output MPEG-TS data is the valid bytes/bits of MPEG-TS packet.

4 -

M_SYNC 36 O Output Frame Start PulseAn active level for an M_CKOUT cycle indicates the start of an output frame.

4 -

M_ERR 38 O MPEG Data Error Indication An active level indicates that there is uncorrected error in the current MPEG-TS packet or frame.

4 -

DiSEqC™ Interface

DISEQC_IN 43 I DiSEqC™ Input This is an input pin with Schmitt Trigger. It can be used as input of the DiSEqC™ interface when pin DISEQC behaves as DiSEqC™ output only. If pin DISEQC is bi-directional, pin DISEQC_IN should be no connection.

This pin can also be used as FSK transmitter input.

- -

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DISEQC 44 I/O DiSEqC™ Input/Output This is a bi-directional pin with Schmitt Trigger. It can be used as both input and output, or just as an output when pin DISEQC_IN is used as the input of the DiSEqC™ interface.

This pin can be used as FSK receiver detection flag.

4 -

LNB_EN 41 O LNB Enable Control Output

This is an output pin that can be used to control the On/Off of the LNB supply.

This pin can also be used as FSK receiver output.

4 -

OLF 40 I LNB Overflow Flag InputThis is an input pin that can be used to input the LNB overflow flag.

This pin can also be used to enable FSK transmitter.

- -

VSEL 45 O LNB Voltage SelectionThis is an output pin that can be used to select the LNB voltage.

4 -

FSK Interface

FSKRX_IN 48 I FSK Modem Input - -

FSKTX_OUT 1 O FSK Modem Output - -

2-wire Interface

ADDR_SEL 20 I 2-wire Bus Slave Address Selection This pin selects 2-wire bus slave address.

- -

SDA 17 I/O(Open-drain)

Serial Data of 2-wire BusThis is a bi-directional pin with Schmitt Trigger. It can be used as both input and output.

4 5 V tolerance

SCL 18 I Serial Clock of 2-wire Bus with Schmitt Trigger

- 5 V tolerance

SDAT 15 I/O(Open-drain)

Serial Data of 2-wire Bus RepeaterThis is a bi-directional pin with Schmitt Trigger. It can be used as the 2-wire bus data repeater for tuner configuration.

4 5 V tolerance

SCLT 14 O(Open-drain)

Serial Clock of 2-wire Bus RepeaterIt can be used as the 2-wire bus clock repeater for tuner configuration.

4 5 V tolerance

Table 1. Pin Description of 48-Pin Package (Sheet 2 of 3)


Specificities

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Clock, Reset and Test

CKXTAL 23 O Auxiliary Clock Output This pin outputs a reference clock.

4 -

XTAL_OUT 4 O Crystal Oscillator Output 4 -

XTAL_IN 3 I Crystal Oscillator Input / External Clock InputThe master clock need to be derived from a 4/8/10/16/27 MHz quartz crystal or clock.

- -

LOCK 42 O Lock IndicationThis is an output to indicate the lock status of the selected module.

4 -

RESET 24 I Global Hardware Reset (Active LOW)This is an active LOW reset signal that, when asserted, resets all function blocks and registers. RESET pin is an input pin with Schmitt Trigger.

- -

Power Supply and Ground

VDDA 5 Power 3.3 V Analog Supply - -

VDDD 19, 46 Power 3.3 V Digital I/O Pad Supply - -

VCC 12, 16, 21, 22,

29, 35, 47

Power 1.2 V Digital Core Supply - -

GNDA 2, 8 Ground Analog Ground - -

GNDD 39 Ground Digital Ground - -

Others

NC 11 - No Connection - -

Note:1. The MPEG interface can be disabled. When disabled, the MPEG interface (including M_DATA[7:0], M_CKOUT, M_VAL, M_SYNC and M_ERR pins) will be in High Impedance state.

Table 1. Pin Description of 48-Pin Package (Sheet 3 of 3)


Specificities

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2 Function Description

2.1 ADCThe M88DS3103 provides a high-performance 8-bit ADC (Analog-to-Digital Converter) to sample the analog I/Q signals. The ADC receives baseband differential I/Q signals through two differential pairs, IP/IN pins and QP/QN pins. It also accepts single-ended I/Q signal through IP/QP pins. The sampling frequency of the ADC is 96 MHz.

2.2 Analog AGCThe analog AGC (Automatic Gain Control) block outputs a PWM (Pulse Width Modulation) signal to control the gain stage of an external tuner, which in turn is used to keep the input signal power of the ADC in a reasonable range.

The PWM signal is converted from the difference between the AGC reference value and the sampled signal from the ADC. The AGC reference value of the AGC loop is programmable via bits I_REF_ADC[7:0] (32H). The PWM signal will be output on the AAGC pin.

2.3 AFC The AFC (Automatic Frequency Correction) module estimates the coarse frequency offset of the current channel independent of the timing information. This module can be bypassed by setting bit AFC_BYP (0CH).

2.4 Baseband I/Q Impairments CancellerThe baseband I/Q impairments canceller compensates the I/Q impairments in sample domain. It removes the DC component in the I channel and Q channel respectively, and corrects amplitude or phase imbalance between the I/Q channels.

The DC offset cancellation loop works automatically. This module can be bypassed by setting bit IQ_IMPAIR_BB_BYP (0CH).

2.5 DDS, Filter Bank and Digital AGCThe DDS (Direct Digital Synthesizer) shifts the center frequency of the input signal according to the frequency offset value, and then outputs a frequency-shifted signal to the filter bank. The filter bank filters and decimates the signal to match up different symbol rates. Usually, the decimation filter and corresponding LPF filter are selected automatically and the selections can be read out from register C9H. However, they can also be selected manually by setting register C9H. Following each decimation stage, there is a digital AGC loop that is used to normalize the signal power.

2.6 CCI CancellerThe CCI (Co-Channel Interference) canceller is employed to detect and eliminate the additive co-channel interference introduced in the data path.

The CCI canceller is flexible and is able to cancel strong co-channel interference. The CCI canceller can be bypassed by setting bit CCI_BYP (56H).

2.7 TRLThe TRL (Timing Recovery Loop) determines the boundary of successive symbols and recovers the symbol values at optimum sampling instants.

The user can set a coarse normalized symbol rate in registers 61H and 62H.

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2.8 Adaptive EqualizerThe adaptive equalizer is used to cancel the ISI (Intersymbol Interference) introduced either by channel reflection or by imperfect properties of the prior blocks.

The equalizer can be bypassed by setting bit EQU_BYP (76H).

2.9 Match FilterIn this module, the recovered symbols pass through a square-root Nyquist filter to match the shape of the transmitted signal.

The roll-off factor of the filter can be 0.35, 0.25 or 0.2, as selected by bits ROLL_OFF_FTR[1:0] (76H). In DVB-S mode, 0.35 should be selected. In DVB-S2 mode, if the roll-factor is known, the user can select it in the same register field; if the roll-off factor is unknown, the device will identify it automatically, and the correct factor will be indicated in the same register field after the DVB-S2 FEC module locks.

2.10 UWPThe UMP (Unique Word Processor) is employed for DVB-S2 mode only. This module decodes the PLSCODE of the physical layer frame to determine the boundary of the frame and maintain the frame synchronization. At the same time, it corrects the frequency offset and phase rotation by utilizing any possible physical layer header or pilot. This module also performs physical layer descrambling.

Co-working with the micro-controller, this module determines the modulation format, code rate and pilot structure. It also detects whether the spectrum is inverted. After the DVB-S2 FEC module locks, the spectrum inversion status can be read from bit S2_SPEC_INV (89H).

2.11 CRLThe CRL (Carrier Recovery Loop) compensates the residual carrier frequency offset and phase offset.

In DVB-S mode, a traditional 2nd order phase lock loop is used for frequency tracking, but in DVB-S2 mode, the fine frequency offset is estimated using the header or pilot.

In DVB-S mode, the CRL lock detection value can be read from register 7DH. In DVB-S2 mode, the CRL can compensate the phase noise detected by a phase noise detector.

2.12 Transmitter I/Q Impairments CancellerThe transmitter I/Q impairments canceller cancels the I/Q impairments in symbol domain. It removes the DC component in the I channel and Q channel respectively, and corrects amplitude and phase imbalance between I and Q channels.

This module can be bypassed by setting bit IQ_IMPAIR_TR_BYP (0CH).

2.13 FEC

2.13.1 DVB-S Mode and DVB-S2 ModeThe M88DS3103 provides a high-performance solution for both DVB-S legacy and advanced DVB-S2 digital satellite television reception. The device supports QPSK demodulation for DVB-S legacy transmission, and uses the system information contained in transmission to ensure efficient demodulation of the DVB-S2 signal. The DVB-S signal is then processed by a legacy (Viterbi/Reed-Solomon) FEC, and the DVB-S2 signal is processed by an advanced (LDPC/BCH) FEC.

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The device can automatically identify the signal type (DVB-S or DVB-S2) and then pass the signal through the corresponding path for processing. If the signal type is known, the user can also specify the signal type in bit DVB_MD (08H) manually.

Registers S2_LDPC_1 to S2_CRC8_2 (D1H ~ F9H) are for DVB-S2 mode only, while the registers S_CTRL_0 to S_DAGC_5 (D0H ~ FFH) are for DVB-S mode only. Refer to Section 3, “Register Information” for details.

2.13.2 DVB-S FEC

2.13.2.1 Digital AGCThe digital AGC normalizes the power of the signal input to the DVB-S FEC (Forward Error Correction) module. It also indicates the SNR (Signal Noise Ratio) in bits S_SNR[7:0] (FFH) for device performance monitoring. This module can be soft reset via programming bit S_DAGC_SOFT_RST (D0H).

2.13.2.2 Viterbi As an inner decoder, the Viterbi decodes convolutional codes. It receives soft decision data from the digital AGC and outputs decoded bit stream to the sync detector. The Viterbi module can automatically determine code rate, puncture mode and phase when these information are not given. It can also automatically detect and correct the spectrum inversion.

If the code rate is not provided, the Viterbi will automatically search for the code rate and display it in bits S_VTB_CODE[2:0] (E6H). This module can be soft reset via programming bit S_VTB_SOFT_RST (D0H).

2.13.2.3 Sync DetectorThe sync detector searches the sync word in the decoded byte stream for frame synchronization. A frame consists of 204 bytes starting with a sync word. Once the sync detector is locked, it will output data to the de-interleaver.

2.13.2.4 De-interleaverThe Deinterleaver is an opposite process to the interleaver in the transmitter. It de-interleaves the input data and restores the initial order of the data flow. The interleaving depth is 12 and the cell depth is 17 (204 bytes in total) for DVB-S applications. The de-interleaver can be bypassed by setting bit S_DEINT_BYP (D0H).

2.13.2.5 RS DecoderThis module decodes the Reed-Solomon codes with Berlekamp-Massey algorithm. The decoder can detect 16 errorous bytes and correct up to 8 errorous bytes out of 204 bytes for each frame.

When no more than 8 errorous bytes are detected in a frame, the errors are correctable and the frame is a corrected one; otherwise, the errors are uncorrectable and the frame is an uncorrected one. However, the RS decoder can be configured not to correct any error by bit S_RS_UNCORR_ERR (F8H), though it still detects errors.

The numbers of the corrected frames and the uncorrected frames can be read out from registers S_RS_0 to S_RS_5 (F0H ~ F5H). The values in these registers can be held or cleared, as controlled by bits S_PK_CNT_HLD & S_PK_CNT_CLR (F8H). The RS decoder can be bypassed by setting bit S_RS_BYP (D0H).

In addition, the RS decoder is able to estimate the BER (Bit/Byte Error Rate) by counting the number of error bits or error bytes before they are corrected. The counted number can be read out from registers for BER calculation.

The BER (Bit / Byte Error Rate) can be calculated by:

Byte Error Rate = ‘S_BER_CNT[15:0]’ / [2(2 x ‘S_NUM_BYT[2:0]’ + 12)]

Bit Error Rate = ‘S_BER_CNT[15:0]’ / [8 x 2(2 x ‘S_NUM_BYT[2:0]’ + 12)]

Where,

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S_NUM_BYT[2:0] defines the total number of data bytes are checked and is set by register F9H;

S_BER_CNT[15:0] counts the bit/byte error number and can be read out from registers F6H and F7H.

2.13.2.6 DescramblerThis module descrambles the incoming data stream, and it also provides an additional frame synchronization function. The output of the descrambler is then fed to the MPEG formatter.

The lock status of the descrambler is indicated in bit S_DESC_LCK (D1H). If required, the descrambler can be bypassed by setting bit S_DESC_BYP (D0H).

2.13.3 DVB-S2 FEC

2.13.3.1 SNR EstimationThe function of this block is to estimate the SNR (Signal-to-Noise Ratio) of the signal input to the DVB-S2 FEC module. The SNR can be calculated using this formula:

SNR = 10 ∗ log(2∗ |Signal_Power_Indicator|2 / Noise_Power)

Where, Signal_Power_Indicator and Noise_Power can be read out from bits S2_POWER_IND[7:0] (8EH) and bits S2_N_POWER[13:0] (8CH & 8DH).

2.13.3.2 Demapper and De-interleaverThe incoming symbols are demapped into soft decisions by the demapper. The demapper supports constellations of QPSK, 8PSK, 16APSK and 32APSK.

The de-interleaver maps the symbols within one signal frame back to their original positions in the frame. The de-interleaved data is then sent to the LDPC decoder for further processing.

2.13.3.3 LDPC DecoderThe LDPC (Low Density Parity Check) decoder is used as the inner decoder to decode the soft decision information. It supports coding rates of 1/4, 1/3, 2/5, 3/5, 1/2, 2/3, 3/4, 4/5, 5/6, 8/9 and 9/10.

The decoder records the number of LDPC frames in bits S2_LDPC_FM_CNT[23:0] (D5H ~ D7H), and the number of failure frames in register bits S2_LDPC_FAIL_CNT[23:0] (D8H ~ DAH) to allow monitoring of errors.

2.13.3.4 BCH DecoderThe BCH (Bose-Chaudhari-Hocquenghem) decoder is used as the outer decoder to decode the bit stream based on the BCH frames.

The BCH decoder also provides an error monitoring function. It can count the number of uncorrectable BCH frames in bits S2_BCH_ERR_CNT[15:0] (E1H~E2H), and the number of bits have been recovered by BCH decoder in bits S2_BCH_RECOVER_CNT[15:0] (E3H~E4H) for error estimation.

The output of the BCH decoder is processed by a deframing block and a CRC checker. After that, the data is fed to the MPEG formatter. Con

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2.14 PID FilterThe PID filter module is used to select or reject certain TS packages with assigned PID. User can set the maximum of 15 PIDs through bits PID_FILTER_TABLE[12:0] (EDH & EEH), and bits PID_FIL_TABLE_INDEX[3:0] (EFH) (index from 1 to 15). Please notice that the PID table of index 0 is reserved as PID0x000~PID0x00F. After setting the PID table and index, user should enable this setting through the corresponding bit of PID_FILTER_EN[15:0] (EBH & ECH). For example, PID_FILTER_EN[15] is used to enable the PID table of index 15. Also, user can choose a PID filter work mode from either allowing the TS packages with the PID in the PID filter table to be transferred, or allowing the rest of the packages to be transferred. The work mode is programmable via bit PID_FILTER_MD (FEH).

For example, the PID filter can be used to cancel the null packages to lower the total bit rate on MPEG TS output interface. In order to filter out the null packages properly, the corresponding registers should be set in following sequence.

1. Set OUTFORMAT_3 (EDH) to FFH;2. Set OUTFORMAT_4 (EEH) to 3FH;3. Set OUTFORMAT_5 (EFH) to 51H;4. Set OUTFORMAT_2 (ECH) to 02H;

Please notice that PID filter and frame speed automatic function (bit FRAME_SPEED_AT (FEH)) should not be enabled at the same time.

2.15 MPEG FormatterThe formatter outputs standard MPEG-TS (Transport Stream) through the MPEG interface. It supports three MPEG-TS interface formats: DVB common interface, parallel interface and serial interface format.

When bit DVB_MD (08H) = 1, the interface format is selected by two bits as shown in Table 2.

For both DVB-S and DVB-S2 mode, the MPEG output pins are M_SYNC, M_VAL, M_DATA[7:0], M_ERR and M_CKOUT. The functions of these pins are described below:

• M_SYNC: this signal indicates the first valid byte (or bit in serial interface mode) of an MPEG-TS packet.

• M_VAL: strobe signal that indicates whether the byte supplied on M_DATA[7:0] pins (or bit supplied on M_DATA0 in serial mode) is one of the valid bytes/bits of the MPEG-TS packet.

• M_DATA[7:0]: MPEG-TS data. In serial interface mode, only M_DATA0 pin is used to output the MPEG-TS data, and M_DATA[7:1] pins are unused and will output ‘0’. The output TEI (Transport Error Indicator) bit in an MPEG packet can be forced to ‘1’ in case that uncorrectable errors occur in the MPEG packet. The TEI bit is programmable via bit EI_ENA (FDH). The output sync bytes B8H on M_DATA[7:0] can be inverted via setting bit INV_B8 (EEH).

• M_ERR: this signal indicates whether there is uncorrected error in the current MPEG-TS packet or frame.

• M_CKOUT: data clock to update all the outputs. It can be either continuous or punctured according to the selected output interface format. The M_CKOUT high/low level times can be set via bit CI_DIV_H[5:0] and CI_DIV_L[5:0] (FEH &EAH). Also, the active edge of M_CKOUT are programmable via bit CKOUT_POL

Table 2. MPEG-TS Interface Selection

Bit CI_EN (FDH) Bit NP_SEL (FDH) Interface

00 Parallel interface

1 Serial interface

1 (Don’t care) Common interface

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(FDH).

The MPEG-TS outputs are valid when all the previous stages are locked. The polarity of M_SYNC, M_VAL and M_ERR is programmable via register FDH. In DVB-S2 mode, MPEG interface can be forced to output ‘0’ before FEC is locked by setting S2_MPEG_OUT_MUX (FDH).

For more details, please see registers OUTFORMAT_0 to OUTFORMAT_7 (FDH~FFH, EAH~EFH).

2.15.1 DVB Common InterfaceWhen common interface format is selected, the MPEG outputs are M_CKOUT, M_VAL, M_SYNC and M_DATA[7:0]. Though it is not required by the DVB-CI specification, the M_ERR signal is still supplied to indicate whether there are uncorrected errors in the current MPEG-TS packet.

In common interface mode, the M_CKOUT signal is continuous and its frequency and active edge are programmable. An appropriate division ratio should be set to ensure that the clock frequency is always greater than the data rate.


Figure 2 shows the timing of the DVB common interface.

Figure 2. DVB Common Interface Format

2.15.2 Parallel InterfaceWhen the parallel interface is selected, the MPEG output pins are M_CKOUT, M_VAL, M_SYNC, M_DATA[7:0] and M_ERR.

Each data frame outputs at M_DATA[7:0] and has 188 bytes of valid MPEG-TS data. M_CKOUT in this mode is a punctured data clock. Its frequency and active edge are programmable. Note that the frequency of M_CKOUT should be always greater than the data rate for proper operation.


Figure 3 and Figure 4 show the parallel interface format and timing.

M_CKOUT

M_VAL

M_SYNC

M_DATA[7:0] 47H

Note: Suppose M_CKOUT is active at the falling edge.

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Figure 3. Parallel Interface Format

Figure 4. Parallel Interface Timing

M_CKOUT

M_VAL

M_SYNC

M_DATA[7:0]

The M_CKOUT is active at rising edge.

The M_CKOUT is active at falling edge.

No Error

M_ERR

Uncorrected Frame No Error

188 MPEG-TS bytes

The pin M_ERR is active HIGH.

The pin M_VAL is active HIGH.

The pin M_SYNC is active HIGH.

Note: 1. The active edge of pin M_CKOUT is programable.2. The polarity of pin M_VAL, pin M_SYNC and pin M_ERR are programable.

M_VAL

M_SYNC

M_DATA[7:0]

M_ERR

M_CKOUT

first byte of an MPEG-TS packet

Master Clock

T

M_CKOUT is active at rising edge

M_CKOUT is active at falling edge

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2.15.3 Serial InterfaceWhen serial interface is selected, the outputs are M_CKOUT, M_VAL, M_SYNC, M_DATA0, and M_ERR.

In this mode, the MPEG data is supplied as a serial bit steam on M_DATA0 and M_CKOUT is a bit clock. The device can clock out 1504 bits of valid MPEG-TS data per each frame, and M_CKOUT determines the maximum achievable throughput. The frequency of M_CKOUT is programmable via bits CLKXM_DIV[1:0] (22H) and CLKXM_SEL[1:0] (24H).


Figure 5 shows the timing of the serial interface.

Figure 5. Serial Interface Format

2.16 DiSEqC™ 2.X InterfaceThe M88DS3103 provides a DiSEqC™ 2.X interface that enables bi-directional communication between the microprocessor and an external device such as LNB (Low Noise Block). The DiSEqC™ module and the corresponding registers can be reset via configuring bit DISEQC_GLOBAL_RST (07H). The chip also supports DiSEqC™ envelop mode by setting bit DSEC_ENVELOP_EN (b5, A2H).

The DiSEqC input / output pins are DISEQC_IN, DISEQC, LNB_EN, OLF and VSEL. The functions of these pins are described below:

• DISEQC_IN: This is an input pin of the DiSEqC™ interface when DISEQC pin behaves as DiSEqC™ output only (bit DSEC_IN_SEL (A2H) = 0).

• DISEQC: This is a bi-directional pin of the DiSEqC™ interface. When bit DSEC_IN_SEL (A2H) = 1, this pin can

M_CKOUT

M_VAL

M_SYNC

M_DATA0

No Error

M_ERR

Uncorrected Frame No Error

188 x 8 = 1504 MPEG-TS bits

Duration = 1 bit

The pin M_CKOUT is active at rising edge.

The pin M_CKOUT is active at falling edge.

The pin M_ERR is active HIGH.

The pin M_VAL is active HIGH.

The pin M_SYNC is active HIGH.

Note: 1. The active edge of pin M_CKOUT is programable.2. The polarity of pin M_VAL, pin M_SYNC and pin M_ERR are programable.

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be used as both input and output of the DiSEqC™ interface; When bit DSEC_IN_SEL (A2H) = 0, this pin is just an output pin of the DiSEqC™ interface and DISEQC_IN pin is used as the input. The output on this pin can be programmed via bits DSEC_OUT_MD[1:0] (A2H).

• LNB_EN: This is an output pin that can be used to control the On/Off of the LNB supply via configuring bit DSEC_LNB_EN (A2H).

• OLF: This is an input pin that can be used to input the LNB overflow flag. The result can be read out from bit DSEC_OLF (A2H).

• VSEL: This is an output pin that can be used to select the LNB voltage via setting bit DSEC_VOLT_SEL (A2H).

2.16.1 LNB Voltage ControlThe M88DS3103 can output a HIGH or LOW level signal at LNB_EN and VSEL pins. This feature can be used for On/Off control of the LNB supply or used for voltage selection. This function is controlled by bits DSEC_LNB_EN & DSEC_VOLT_SEL (A2H).

2.16.2 LNB Signaling Control

Normally, signaling is transmitted with a 22 kHz carrier frequency through the DiSEqC™ interface. The M88DS3103 supports three signaling modes: continuous mode, tone burst mode and DiSEqC™ mode via setting bits DSEC_LNB_CTRL_SEL[1:0] (A1H). The tone burst mode includes unmodulated tone bust mode and modulated tone bust mode.

Refer to Table 3 for more details.

Figure 6. Timing Diagram of Tone Burst Control Signal

In DiSEqC™ mode, the DiSEqC™ messages are transmitted in a format as shown in Figure 7. An odd parity bit ‘P’ is added after each byte automatically.

Table 3. LNB Signaling Mode Selection

Bits DSEC_LNB_

CTRL_SEL[1:0]LNB Signaling Mode Output

00 Continuous mode A continuous 22 kHz tone signal.

01 Modulated tone burst mode The output signal lasts for 12.5 ms. It is 9 bursts (with 22 kHz carrierfrequency) of 0.5 ms each and separated by 8 intervals of 1 ms each. SeeFigure 6.

10 Unmodulated tone burst mode The signal is a continuous burst (with 22 kHz carrier frequency) of 12.5 ms.See Figure 6.

11 DiSEqC™ mode Transmit / Receive DiSEqC™ messages.

Unmodulated Tone Burst Mode

Modulated Tone Burst Mode

12.5 ms

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Figure 7. DiSEqC™ Message Formats

Figure 8 shows the bit transmission representations used on the DiSEqC™ interface.

Figure 8. Bit Transmission on DiSEqC™ Interface

When DiSEqC™ envelop mode is enabled via bit DSEC_ENVELOP_EN (A2H), the bit transmission representations used on the DiSEqC™ interface is as shown in Figure 9.

Figure 9. Bit Transmission on DiSEqC™ Interface Under Envelop Mode

Receiving Message

FRAMING P ADDRESS P COMMAND P DATA P

FRAMING P DATA P DATA P

Transmitting Message

11 Pulses 11 Pulses 11 Pulses Nextbitidle

Transmission of binary 1

Transmission of binary 0 (DSEC_SWITCH (A1H) = 1)


11 Pulses 11 Pulses 11 Pulses Nextbitidle

Transmission of binary 1



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2.16.3 DiSEqC™ Configuration Flow

N

Y

Y

N

N

Y

N

Y

Is DiSEqC interface ready? Bit DSEC_RDY (A1H) = 0?

Set tone frequency. Bits DSEC_TONE_FREQ (A0H) = 45HSet bit transmission format. 1. Bit DSEC_SWITCH (A1H) = 0, the transmission of binary 0 is active during 22 pulses, then 11 inactive pulses.2. Bit DSEC_SWITCH (A1H) = 1, the transmission of binary 0 is active during 33 pulses.Config DiSEqC output modeBit DSEC_OUT_MD[1:0] (A2H) = 00H

Choose DiSEqC signalling mode.Bits DSEC_LNB_CTRL_SEL[1:0] (A1H)

Start transmitting. Bit DSEC_RDY (A1H) = 0

Software reset/or force bits

DSEC_OUT_MD[1:0] (A2H) to 10/11

End


End

Write message (up to 8 bytes). Registers DISEQC_3 to DISEQC_10 (A3H ~ AAH)Set transmitting message length. Bits DSEC_TRAN_LENGTH[2:0] (A1H)Enable receiving (if needed).Bit DSEC_RCV_EN (A1H) = 1


End

Stop receiving.Bit DSEC_RCV_EN (A1H) = 0,Read received data from registers A3H-AAH.

Tone bust modeDSEC_LNB_CTRL_SEL[1:0] = 01 / 10

Continuous modeDSEC_LNB_CTRL_SEL[1:0] = 00

Want to stop?

Transmitting completed?Bit DSEC_RDY back to 0?

N

Y

Transmitting completed?Bit DSEC_RDY back to 0?

Require LNB to reply?

DiSEqC modeDSEC_LNB_CTRL_SEL[1:0] = 11

Delay 300 ms.Read the length of the receiving data from Bits DSEC_TRAN_LENGTH[2:0] (A1H).

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2.17 2-Wire Bus InterfaceThe device is controlled through a 2-wire bus. It is a pure 2-wire bus slave. It supports up to two chip addresses as selected by Pin ADDR_SEL. Please see Table 4 for details.

The frequency of the 2-wire bus can be up to 400 kHz. Refer to Figure 10 and Figure 11 for the details of read and write operation.

Figure 10. 2-Wire Bus Read Operation

Figure 11. 2-Wire Bus Write Operation

2.17.1 2-Wire Bus RepeaterTo avoid unwanted noise disturbing the tuner performance, the M88DS3103 offers a 2-wire bus repeater dedicated for tuner control. The tuner is connected to the M88DS3103 through the SCLT and SDAT pins. See Figure 12.

Table 4. 2-Wire Bus Chip Address Selection

ADDR_SEL PinChip’s Operation Address

Write Read

0B D0H D1H

1B D2H D3H

D 7 D 0D1D 2D 3D4D 5D6 D7 D 0D 1D2D3D4D5D 6

A7 A0A1A2A3A4A5A6

SCL

SDA

start R /WACK by device base address

ACK by device stop

data byte 1ACK by

m icro data byte n stop

SCL

SDA

start A DDR _SE L R/WACK by device

ACK by m icro

ADDR_S EL

2-w ire slave address

2-w ire slave address

D7 D0D1D2D3D4D5D6 D7 D0D1D2D3D4D5D6 D7 D0D1D2D3D4D5D6

A7 A0A1A2A3A4A5A6 D7 D0D1D2D3D4D5D6

SCL

SDA

start ADDR_SEL R/W

ACK by device base address

ACK by device

ACK by devicedata byte 1

data byte 2ACK by device data byte 3

ACK by device data byte n

ACK by device stop

SCL

SDA

2-wire slave address

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Every time the 2-wire bus master wants to access the tuner registers, it must enable the repeater first by configuring bit 2_WIRE_REP_EN (03H). When the repeater is enabled, the SDAT and SCLT pins are active. The messages on the SDA and SCL pins is repeated on the SDAT and SCLT pins. The repeater will be automatically disabled once the access times to the tuner reaches the configured value set in bits 2_WIRE_REP_TM[2:0] (03H). When disabled, the SCLT and SDAT pins are completely isolated from the 2-wire bus and become inactive (HIGH).

Please note that the 2-wire bus master can not access the demodulator registers while the repeater is enabled.

Figure 12. 2-Wire Bus Repeater

2.18 FSK InterfaceThe FSK (Frequency Shift Keying) module is composed of an FSK transmitter block and an FSK receiver block. They are physical layer FSK transceiver block contained by M88DS3103. With the FSK module, M88DS3103 can exchange messages with another FSK transceiver that uses the same upper layer protocol. The FSK module is designed to have the maximum flexibility to support various of applications. The physical layer parameters of the FSK module is fully configurable by registers 49H and 75H.

The relative pins are FSKRX_IN, FSKTX_OUT. Also, pins DISEQC, DISEQC_IN, LNB_EN and OLF can be configured as FSK relative pins by setting bit FSK_EN (29H). The functions of these pins are described below:

• FSKRX_IN: FSK Modem Input.

• FSKTX_OUT: FSK Modem Output.

• DISEQC_IN: this pin can be configured as FSK transmitter input.

• OLF: this pin can be used to enable FSK transmitter.

• LNB_EN: this pin can be configured as FSK receiver output.

• DISEQC: this pin can be used as FSK receiver detection flag.

2.19 Clock Generation and Auxiliary Clock OutputThe M88DS3103 adopts a 4/8/10/16/27 MHz external quartz crystal, or alternatively, a 4/8/10/16/27 MHz external clock to generate the master clock. The device integrates a on-chip PLL to generate clocks for different internal modules.

The device provides a clock output on the CKXTAL pin for external use. The frequency of the output clock is determined by register 29H.

Demodulator Registers

Repeater Enable/Disable

SC

L

SD

A

SDAT

SCLT

Tuner

Tuner Registers

2-Wire Bus Master

M88DS3103

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2.20 System Control

2.20.1 Blind Scan ModeThis function provides faster searching for available channels. When the M88DS3103 has no prior information about the available channels, blind scan can be used to estimate the channel information, such as DVB-S mode or DVB-S2 mode, carrier frequency, symbol rate, modulation, code rate and the number of the available channels. The blind scan mode can be enabled by setting bit BLIND_SCAN_EN (08H).

2.20.2 Sleep ModeThe M88DS3103 supports sleep mode to save power consumption. When the sleep mode is enabled by setting bit SLEEP_MD (04H), only the 2-wire bus and the global control registers (00H ~29H) are active; all other blocks and registers are put to inactive state. Exiting the sleep mode by clearing bit SLEEP_MD (04H), the device resumes normal operations.

2.20.3 Lock Indication The LOCK pin can be used to indicate the lock status of the analog AGC or the FEC module as selected by bits LCK_SRC_SEL[1:0] (03H). The pin stays inactive when the selected module is unlocked. When the selected module is locked, the LOCK pin goes to an active level, and it will remain active until the selected module becomes unlocked. The active level of LOCK pin is programmable via bit LCK_POL (03H).

2.20.4 ResetThe M88DS3103 supports 4 types of reset: power on reset, hardware reset, global reset and software reset.

The power on reset is automatically performed upon system power-on.

The hardware reset can be performed by holding RESET pin LOW for 1 μs or above. The hardware reset clears internal status of each function block and resets the registers to their default values.

The global reset has almost the same effect as the hardware reset, except that it does not affect control registers (00H ~29H), the 2-wire bus slave, the DiSEqC™ module and its relative registers. The global reset can be enabled by setting bit GLOBAL_RST (07H) to ‘0’.

The software reset is active HIGH. It only clears the internal status of each function block and flip-flop, and does not affect any registers and 2-wire bus slave. The device can be software reset by setting bit SW_RST (00H) to ‘1’. In addition, some function blocks such as analog AGC, TRL, CRL, digital AGC, Viterbi and FEC, can be individually reset by setting their respective reset bits. This kind of resets only clears internal status of the corresponding block with the registers unaffected.

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3 Register Information

3.1 Register MapTable 5. Register Map (Common Registers for DVB-S & DVB-S2 Mode Unless Otherwise Indicated) (Sheet 1 of 3)

Register Name Addr

Bit NamePage

7 6 5 4 3 2 1 0

CTRL_0 00H CHIP_ID[6:0] SW_RST P26

CTRL_1 01H CHIP_VER[7:0] P26

CTRL_2 02H CHIP_VER[15:8] P26

CTRL_3 03H LCK_SRC_SEL[1:0] LCK_POL 2_WIRE_REP_EN

Reserved 2_WIRE_REP_TM[2:0] P27

CTRL_4 04H Reserved 1X_CLK_ INV

SLEEP_ MD

P27

CTRL_7 07H GLOBAL_ RST

DISEQC_ GLOBAL_

RST

Reserved P28

CTRL_8 08H BLIND_ SCAN_EN

Reserved DVB_MD Reserved 2_WIRE_ SLAVE_EN

P28

CTRL_12 0CH Reserved AFC_BYP IQ_IMPAIR_TR_BYP

IQ_IMPAIR_BB_BYP

P29

CTRL_13 0DH S2_FEC_LCK

Reserved S2_HEADER_LCK

CRL_LCK TRL_LCK AAGC_LCK

P29

ANA_2 22H CLKXM_DIV[1:0] Reserved P31

ANA_4 24H CLKXM_SEL[1:0] Reserved P31

CTRL_14 27H Reserved MPEG_HIMP

P30

CTRL_15 29H CKXTAL_ENB

FSK_EN D0/D7_EXCHA

NGE

HALF_CLK_SEL

Reserved P30

AAGC_0 30H Reserved CLIP_EN Reserved P31

AAGC_2 32H I_REF_ADC[7:0] P31

AAGC_5 35H LCK_RIPL_RNG[7:0] P32

AAGC_9 39H CLIP_WINDOW[7:0] P32

AAGC_17 41H CLIP_CNT[11:4] P32

AAGC_18 42H Reserved CLIP_CNT[3:0] P32

FSK_0 49H Reserved FSK_ADDR[3:0] P33

DCRM_3 4DH Reserved IQ_SWITCH_BF_PPF

P37

CCI_2 56H Reserved CCI_BYP P37

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TRL_1 61H SYMB_RATE[7:0] P38

TRL_2 62H SYMB_RATE[15:8] P38

FSK_1 75H FSK_REG_DATA[7:0] P34

EQU_0 76H EQU_BYP Reserved ROLL_OFF_FTR[1:0] P38

CRL_1 7DH CRL_LCK_DET[7:0] P38

CRL_2 7EH CONST_MD[1:0] S2_PILOT_MD

Reserved CODE_RATE[3:0] P39

CRL_12 88H PHASE_NOISE[7:0] P39

CRL_13 89H S2_SPEC_INV

Reserved PHASE_NOISE[11:8] P40

SNR_1 8CH Reserved S2_N_POWER[5:0] P40

SNR_2 8DH S2_N_POWER[13:6] P40

SNR_3 8EH S2_POWER_IND[7:0] P41

FFT_1 91H Reserved FFT_LENGTH[1:0] FFT_OVL[4:0] P41

FFT_5 95H FFT_TUNER_OFFSET [9:8]

Reserved P41

FFT_6 96H FFT_TUNER_OFFSET[7:0] P41

FFT_7 97H Reserved FFT_SNR_THR[3:0] P42

FFT_9 99H Reserved FFT_FLAT_FTR[5:0] P42

DISEQC_0 A0H DSEC_TONE_FREQ[7:0] P42

DISEQC_1 A1H DSEC_RCV_EN

DSEC_RDY

DSEC_TRAN_LENGTH[2:0] DSEC_SWITCH

DSEC_LNB_CTRL_SEL[1:0]

P43

DISEQC_2 A2H DSEC_OUT_MD[1:0] DSEC_ENVELOP_EN

DSEC_IN_SEL

DSEC_RCV_ERR

DSEC_OLF DSEC_LNB_EN

DSEC_VOLT_SEL

P44

DISEQC_3 A3H DSEC_MSG0[7:0] P45







DISEQC_10 AAH DSEC_MSG7[7:0] P46

Table 5. Register Map (Common Registers for DVB-S & DVB-S2 Mode Unless Otherwise Indicated) (Sheet 2 of 3)

Register Name Addr

Bit NamePage

7 6 5 4 3 2 1 0

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DISEQC_11 ABH DSEC_PAR_ERR7

DSEC_PAR_ERR6

DSEC_PAR_ERR5

DSEC_PAR_ERR4

DSEC_PAR_ERR3

DSEC_PAR_ERR2

DSEC_PAR_ERR1

DSEC_PAR_ERR0

P47

MCUC_0 B0H PROG_DATA[7:0] P47

MCUC_1 B1H Reserved PROG_DATA[13:8] P48

MCUC_2 B2H Reserved MCU_START

P48

SYS_9 C9H AT_DECI_SEL

DECI_SEL[2:0] Reserved LPF_SEL[2:0] P49

OUTFORMAT_0

EAH CI_DIV_H[1:0] CI_DIV_L[5:0] P50

OUTFORMAT_1

EBH PID_FILTER_EN[15:8] P50

OUTFORMAT_2

ECH PID_FILTER_EN[7:0] P50

OUTFORMAT_3

EDH PID_FILTER_TABLE[7:0] P50

OUTFORMAT_4

EEH Reserved INV_B8 PID_FILTER_TABLE[12:8] P51

OUTFORMAT_5

EFH Reserved PID_FIL_TABLE_INDEX[3:0] P51

OUTFORMAT_6

FDH S2_MPEG_OUT_MUX

CKOUT_POL

SYNC_POL

VAL_POL ERR_POL NP_SEL EI_ENA CI_EN P50

OUTFORMAT_7

FEH QPSK_R_EN

FRAME_SPEED_AT

PID_FILTER_MD

R_CNT_OUT

CI_DIV_H[5:2] P50

Table 5. Register Map (Common Registers for DVB-S & DVB-S2 Mode Unless Otherwise Indicated) (Sheet 3 of 3)

Register Name Addr

Bit NamePage

7 6 5 4 3 2 1 0

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Table 6. Register Map for DVB-S2 Mode Only

Register Name Addr

Bit NamePage

7 6 5 4 3 2 1 0

S2_LDPC_1 D1H Reserved SOFT_DEC_SEL

S2_LDPC_CNT_CLR

P54

S2_LDPC_5 D5H S2_LDPC_FM_CNT[7:0] P54



S2_LDPC_8 D8H S2_LDPC_FAIL_CNT[7:0] P55

S2_LDPC_9 D9H S2_LDPC_FAIL_CNT[15:8] P55

S2_LDPC_10

DAH S2_LDPC_FAIL_CNT[23:16] P55

S2_BCH_1 E1H S2_BCH_ERR_CNT[7:0] P55

S2_BCH_2 E2H S2_BCH_ERR_CNT[15:8] P55

S2_BCH_3 E3H S2_BCH_RECOVER_CNT[7:0] P56

S2_BCH_4 E4H S2_BCH_RECOVER_CNT[15:8] P56

S2_DEFRAMING_2

F3H S2_BBHEAD_ERR_CNT[7:0] P56

S2_DEFRAMING_3

F4H S2_BBHEAD_ERR_CNT[15:8] P56

S2_DEFRAMING_5

F6H S2_BBHEAD_CNT_CL

R

Reserved P57

S2_CRC8_0 F7H S2_UPL_ERR_CNT[7:0] P57

S2_CRC8_1 F8H S2_UPL_ERR_CNT[15:8] P57

S2_CRC8_2 F9H Reserved S2_UPL_ERR_CNT_

CLR

P57

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Table 7. Register Map for DVB-S Mode Only

Register Name Addr

Bit NamePage

7 6 5 4 3 2 1 0

S_CTRL_0 D0H Reserved S_DESC_BYP

S_RS_BYP S_DEINT_BYP

S_VTB_SOFT_RST

S_FEC_SOFT_RST

S_DAGC_SOFT_RST

P58

S_CTRL_1 D1H S_VTB_FAIL

Reserved S_DAGC_LCK

S_VTB_LCK

S_SYNC_LCK

S_DESC_LCK

P58

S_VTB_0 E0H S_RATE_SEL[4:0] S_SPEC_INV

S_ROT_90D

S_ROT_180D

P59

S_VTB_6 E6H S_VTB_CODE[2:0] Reserved P59

S_RS_0 F0H S_PK_CNT[7:0] P60

S_RS_1 F1H S_PK_CNT[15:8] P60

S_RS_2 F2H S_CORR_PK_CNT[7:0] P60

S_RS_3 F3H S_CORR_PK_CNT[15:8] P60

S_RS_4 F4H S_UNCORR_PK_CNT[7:0] P60

S_RS_5 F5H S_UNCORR_PK_CNT[15:8] P61

S_RS_6 F6H S_BER_CNT[7:0] P61

S_RS_7 F7H S_BER_CNT[15:8] P61

S_RS_8 F8H S_RS_UNCORR_

ERR

S_PK_CNT_HLD

S_PK_CNT_CLR

S_BER_ON

S_ERR_SRC_SEL

Reserved P62

S_RS_9 F9H Reserved S_NUM_BYT[2:0] P62

S_SYNC_0 FAH Reserved S_MISMATCH[1:0] S_ACQ_MD[1:0] S_TRK_MD[1:0] P63

S_DES_0 FCH Reserved S_DESC_MD_SEL[1:0] P63

S_DAGC_5 FFH S_SNR[7:0] P63

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3.2 Register Description

3.2.1 Common Registers for Both DVB-S and DVB-S2 Modes (Unless Otherwise Indicated)

CTRL_0

CTRL_1

CTRL_2

Address: 00HDefault: E0H

Name Bit Type Description

CHIP_ID[6:0] 7:1 R M88DS3103’s Chip ID.

SW_RST 0 RW Software Reset.0: Normal operation;1: Reset the internal status of all functional blocks without affecting the registers. Please note that this bit is NOT self-clearing and it should be clear to ‘0’ after reset. In order to avoid any impact on the status of functional blocks caused by configuring registers at initialization, follow the steps below:1. Configure all the registers;2. Set this bit to ‘1’ to reset the internal status of all functional blocks;3. Clear this bit to ‘0’ to start normal operations.

Address: 01HDefault: D0H


CHIP_VER[7:0] 7:0 R Chip Version (8 LSB).This register indicates the lower byte of the chip version. The higher byte is indicated in register 02H.

Address: 02HDefault: 00H


CHIP_VER[15:8] 7:0 R Chip Version (8 MSB).This register indicates the higher byte of the chip version. The lower byte is indicated in register 01H.

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CTRL_3

CTRL_4



LCK_SRC_SEL[1:0] 7:6 RW Pin LOCK Output Source Selection.This field selects a lock flag to be indicated on the LOCK pin. This pin goes to the active level when the selected event occurs.00: FEC is locked.01: Analog AGC is locked.10~11: Reserved.Note: The active level of LOCK pin is programmable via bit LCK_POL (b5, 03H).

LCK_POL 5 RW Polarity of Pin LOCK.0: Pin LOCK is active HIGH;1: Pin LOCK is active LOW.

2_WIRE_REP_EN 4 RW 2-wire Bus Repeater Enable.This bit controls whether the 2-wire bus repeater is enabled.0: Disabled.1: Enabled.

- 3 - Reserved.

2_WIRE_REP_TM[2:0] 2:0 RW 2-wire Bus Repeater Access Times.This field defines the number of times for which the tuner registers are accessed via 2-wire bus repeater. This value is effective only when the 2-wire bus repeater is enabled (bit 2_WIRE_REP_EN (03H)=1).A read operation costs 2 access times and a write operation costs 1 access times.The total access times can be set from 0 (000b) to 7 (111b).When the total access times exceed the value specified in this field, the 2-wire bus repeater will be automatically disabled.



- 7:2 - Reserved.

1X_CLK_INV 1 RW 1X Master clock Inversion.This bit controls whether the 1X master clock inversion is enabled.0: Disabled.1: Enabled.

SLEEP_MD 0 RW Sleep Mode Enable.When this bit is ‘1’, the master clock is gated and the chip is in low power mode. However, the control registers (00H ~29H) are still accessible. Exit from the sleep mode by clearing this bit.

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CTRL_7d

CTRL_8



GLOBAL_RST 7 RW Global Reset.0: Normal operation;1: Reset all modules and registers, except the control registers (00H~29H), the 2-wire bus slave, the DiSEqC module and its corresponding register.Please note that this bit is NOT self-cleaning and it should be clear to ‘0’ after reset.

DISEQC_GLOBAL_RST 6 RW DiSEqC Global Reset.0: Normal operation;1: Reset DiSEqC module and the corresponding registers.Please note that this bit is NOT self-cleaning and it should be clear to ‘0’ after reset.

- 5:0 - Reserved.



BLIND_SCAN_EN 7 RW Blind Scan Enable.This bit controls whether the blind scan is enabled.0: Disabled;1: Enabled.

- 6:3 - Reserved.

DVB_MD 2 RW DVB Mode SelectionThe M88DS3103 supports both DVB-S/S2 demodulation. Set this bit to match the proper mode.0: Select DVB-S mode;1: Select DVB-S2 mode.

- 1 - Reserved.

2_WIRE_SLAVE_EN 0 RW Registers Access Enable.0: Only the system control registers (00H ~29H) can be accessed;1: The entire registers can be accessed. (Default)

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CTRL_12

CTRL_13

Address: 0CHDefault: 00H


- 7:3 - Reserved.

AFC_BYP 2 RW AFC Bypass Enable.0: Normal operation;1: The AFC module is bypassed.

IQ_IMPAIR_TR_BYP 1 RW Transmitter I/Q Impairment Canceller Bypass Enable.0: Normal operation;1: Transmitter I/Q impairment Canceller is bypassed.

IQ_IMPAIR_BB_BYP 0 RW Baseband I/Q Impairment Canceller Bypass Enable.0: Normal operation;1: Baseband I/Q impairment Canceller is bypassed.

Address: 0DHDefault: 00H


S2_FEC_LCK 7 R FEC Module Lock Flag (For DVB-S2 Mode Only).In DVB-S2 mode, a ‘1’ in this bit indicates FEC module is locked; otherwise it is unlocked. This bit is valid only when DVB-S2 mode is enabled (bit DVB_MD (b2, 08H) =1).

- 6:4 - Reserved.

S2_HEADER_LCK 3 R Header Lock Flag (For DVB-S2 Mode only).In DVB-S2 mode, a ‘1’ in this bit indicates the header of physical layer frame is locked; otherwise it is unlocked. This bit is valid only when DVB-S2 mode is enabled (bit DVB_MD (b2, 08H) =1).

CRL_LCK 2 R CRL Lock Flag.A ‘1’ in this bit indicates CRL is locked; otherwise it is unlocked.

TRL_LCK 1 R TRL Lock Flag.A ‘1’ in this bit indicates TRL is locked; otherwise it is unlocked.

AAGC_LCK 0 R Analog AGC Lock Flag.A ‘1’ in this bit indicates analog AGC is locked; otherwise it is unlocked.

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CTRL_14

CTRL_15



- 7:1 - Reserved.

MPEG_HIMP 0 RW MPEG Output High Impedance.0: MPEG pins outputs high impendance;1: MPEG pins are in normal operation.



CKXTAL_ENB 7 RW CKXTAL Pin Output Enable.This bit controls whether to enable the output of a clock on CKXTAL pin.0: Enabled;1: Disabled.

FSK_EN 6 RW FSK Interface Enable.This bit controls whether to enable the FSK interface.0: Enabled. Pins DISEQC, DISEQC_IN, LNB_EN and OLF are configured as FSK relative pins;1: Disabled.

D0/D7_EXCHANGE 5 RW M_DATA0 and M_DATA7 Switch Enable.In serial mode, this bit controls the data is output through either M_DATA0 orM_DATA7.0: Output through M_DATA0;1: Output through M_DATA7.

HALF_CLK_SEL 4 RW Half Crystal Clock Output Selection.This bit selects to output a crystal clock, or half of the crystal clock. The crystal clock is determined by external crystal oscillator or clock input at Pin XTAL_IN.0: Output a crystal clock;1: Output half of the crystal clock.

- 3:0 - Reserved.

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ANA_2

ANA_4

AAGC_0

AAGC_2

Address: 22HDefault: ACH


CLKXM_DIV[1:0] 7:6 RW CLKXM_DIV {CLKXM_SEL[1:0], CLKXM_DIV[1:0]}, which is a 4-bit register used to selection a reference clock.0011: selects a 192 MHz reference clock;0100: selects a 144 MHz reference clock;0101: selects a 115.2 MHz reference clock;0110: selects a 96 MHz reference clock;1100: selects a 72 MHz reference clock.Bits CLKXM_SEL[1:0] can be found at register (b7-6, 24H).

- 5:0 - Reserved.

Address: 24HDefault: 5CH


CLKXM_SEL[1:0] 7:6 RW Please refer to bits CLKXM_DIV[1:0] (b7-6, 22H) for more detail.

- 5:0 - Reserved.



- 7:3 - Reserved.

CLIP_EN 2 RW Clipping Adjust Function EnableThis bit controls whether to enable the clipping adjust function.0: Disabled;1: Enabled.

- 1:0 - Reserved.



I_REF_ADC[7:0] 7:0 RW Analog AGC Reference Value.This field defines the reference value of the analog AGC. The AGC loop will try to adjust the average magnitude of the signal sampled by the ADC towards this reference value.

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AAGC_5

AAGC_9

AAGC_17

AAGC_18



LCK_RIPL_RNG[7:0] 7:0 RW Lock Ripple Range (U8.0).This lock ripple range is used to determine if the AGC loop is locked. If the difference between the average ADC sampled signal and the AGC reference signal is within this lock ripple range, the AGC loop is considered as locked.This is a 8-bit unsigned floating point number, the lower 4 bits representing the integer part and the higher 4 bits representing the decimal part.



CLIP_WINDOW[7:0] 7:0 RW Clipping Window.This register defines the time window for clipping rate calculation.

Clipping rate = 100% *CLIP_CNT[11:0] / (212 + CLIP_WINDOW[7:0]).Where,Bits CLIP_CNT[11:0] represent the clipping counter and are stored in registers 41H & 42H.



CLIP_CNT[11:4] 7:0 R Clipping Counter (S12.12).CLIP_CNT[11:0] is a 12-bit clipping counter used for clipping rate calculation. This counter counts the number of clipping during the time window. Refer to the description of CLIP_WINDOW[7:0] (39H) for more details. The lower 4 bits are stored in register 42H.



- 7:4 - Reserved.

CLIP_CNT[3:0] 3:0 R Refer to 8 MSB in register 41H for more details.Confid

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FSK_0



- 7:4 - Reserved.

FSK_ADDR[3:0] 3:0 RW FSK Address.Please refer to register 75H for more detail.

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FSK_1

Address: 75HDefault: see the description below for details


FSK_REG_DATA[7:0] 7:0 RW If FSK_ADDR[3:0] = 00H, this register is configured as FSKT_CAR[7:0];

Transmitter carrier frequency = FSKT_CAR[17:0]/220 * FmclkFSKT_CAR[15:8] can be configured when FSK_ADDR[3:0] = 01H, FSKT_CAR[17:16] can be configured when FSK_ADDR[3:0] = 02H.The default value of this register is 22H.

If FSK_ADDR[3:0] = 01H, this register is configured as FSKT_CAR[15:8]. Please refer to ‘If FSK_ADDR[3:0] = 00H’ for details.The default value of this register is 62H.

If FSK_ADDR[3:0] = 02H, this register is configured as [7:6]: FSKT_CAR[17:16], Please refer to ‘If FSK_ADDR[3:0] = 00H’ for details.[5:4]: FSKR_CAR_SMR[1:0], smooth ratio of carrier before bit slicer.[3:0]: FSKT_DELTAF[11:8], Please refer to ‘If FSK_ADDR[3:0] = 03H’ for details.The default value of this register is 01H.

If FSK_ADDR[3:0] = 03H, this register is configured as FSKT_DELTAF[7:0];

Transmitter delta frequency = FSKT_DELTAF[11:0]/220 * Fmclk.FSKT_DELTAF[11:8] can be configured when FSK_ADDR[3:0] = 02H.The default value of this register is B5H.

If FSK_ADDR[3:0] = 04H, this register is configured as FSKR_CAR[7:0];

Receiver carrier frequency = FSKR_CAR[17:0]/220 * FmclkFSKR_CAR[15:8] can be configured when FSK_ADDR[3:0] = 05H,FSKR_CAR[17:16] can be configured when FSK_ADDR[3:0] = 06HThe default value of this register is 22H.

If FSK_ADDR[3:0] = 05H, this register is configured as FSKR_CAR[15:8];Please refer to ‘If FSK_ADDR[3:0] = 04H’ for details.The default value of this register is 52H.

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FSK_REG_DATA[7:0] 7:0 RW If FSK_ADDR[3:0] = 06H, this register is configured as: [7:6]: FSKR_CAR[17:16], Please refer to ‘If FSK_ADDR[3:0] = 04H’ for details.[5:4]: Reserved;[3:0]: FSKR_DELTAF[11:8], Please refer to ‘If FSK_ADDR[3:0] = 07H’ for details. The default value of this register is 01H.

If FSK_ADDR[3:0] = 07H, this register is configured as FSKR_DELTAF[7:0].

Receiver delta frequency = FSKR_DELTAF[11:0]/220 * FmclkThe default value of this register is B5H.

If FSK_ADDR[3:0] = 08H, this register is configured as:

[7:4]: ALPHA_E[3:0]:[3:0]: ALPHA_M[3:0]: Bits ALPHA_E[3:0] and ALPHA_M[3:0] are used to configure the PLL parameter, alpha.

Alpha = (1+ALPHA_M[3:0]/16)*2-ALPHA_E[3:0]

The default value of this register is 84H.

If FSK_ADDR[3:0] = 09H, this register is configured as: [7:4]: BETA_E[3:0]; [3:0]: BETA_M[3:0];Bits BETA_E[3:0] and BETA_M[3:0] are used to configure the PLL parameter, beta.

Beta = (1+BETA_M[3:0]/16)*2-BETA_E[3:0]+6


If FSK_ADDR[3:0] = 0AH, this register is configured as: [7:4]: FSKR_CARDET_THR[3:0], carrier lock detector threshold;[3:0]: DECI_K[3:0], decimation ratio from 1 to 16;The default value of this register is F3H.

If FSK_ADDR[3:0] = 0BH, this register is configured as: [7]: PGA gain control switch: ‘0’ is max 7, ‘1’ is max 9; [6]: PGA_GAIN_INI[3], Please refer to ‘If FSK_ADDR[3:0] = 0DH’ for details. [5]: SLICER_THR, set the factor of bit slicer '0'/'1' threshold

0: Threshold = 1/2*DECI_K[3:0]*FSKR_DELTAF[11:0]/Fmclk;1: Threshold = 3/4*DECI_K[3:0]*FSKR_DELTAF[11:0]/Fmclk.

[4:0]: FSKR_AGC_REF, reference level of AGC.The default value of this register is B8H.

FSK_1



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FSK_REG_DATA[7:0] 7:0 RW If FSK_ADDR[3:0] = 0CH, this register is configured as: [7]: FSKR_MOD, FSK receiver polarity

0: Normal; Fc+Fdelta name as '1'; 1: Polarity is inverted.

[6]: FSKT_MOD_POL, FSK transmitter polarity0: Normal; Fc+Fdelta name as '1'; 1: Polarity is inverted.

[5:3]: FSKT_MOD, FSK transmitter mode 000: Force Tx_out = 0; 001: Force Tx_out = 1; 010: Reserved; 011: Force Tx_out = Fc; 100: Force Tx_out = Fc - Fdelta; 101: Force Tx_out = Fc + Fdelta; 110: Reserved; 111: Modulator on.[2]: TX_EN polarity, polarity of FSK transmitter enable signal 0: Normal; 1: Polarity is inverted.[1:0]: PWM_MOD, PWM mode 00: Set 2nd-PWM on; 01: Set 1st-PWM on; 10: Reserved; 11: Set 1-bit out.The default value of this register is 38H.

If FSK_ADDR[3:0] = 0DH, this register is configured as: [7]: DAGC mode selection

0: Set DAGC on; 1: Force DAGC output 256.

[6]: FSK_AGC_RST, FSK AGC reset 0: Normal; 1: Reset; [5:3]: G_BOOST, adjust PGA gain step before fix it[2:0]: PGA_GAIN_INIT[2:0], PGA gain initial value

LSB of PGA_GAIN_INIT[3:0], the MSB of PGA_GAIN_INIT[3] can be config-ured when FSK_ADDR[3:0] = 0BH.


FSK_1



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DCRM_3

CCI_2

FSK_REG_DATA[7:0] [7:0] RW If FSK_ADDR[3:0] = 0EH, this register is configured as [7:6]: AGC_LOCK_DURATION 00: 8192 cycles; 01: 2048 cycles; 10: 512 cycles; 11: 256 cycles.[5:3]: FSK receiver detection flag signal level represention on Pin DISEQC.000: Reserved;001: ‘LOW’, no signal; ‘HIGH’, there is a signal, but can not be identified;010: ‘LOW’, only detects Fc, no Fdelta; ‘HIGH’, detects both Fc and Fdelta;011: ‘LOW’, no signal; ‘HIGH’, detects Fdelta;100: ‘LOW’, PLL is unlocked; ‘HIGH’, PLL is locked;101: ‘LOW’, no signal; ‘HIGH’, PLL is locked;110: ‘LOW’, either PLL is unlocked, or no Fdelta;

‘HIGH’, PLL is locked, and detects Fdelta;111: ‘LOW’, no signal, or PLL is unlocked, or no Fdelta;

‘HIGH’, PLL is locked, and detects Fdelta;[2:0]: FSKR_LOCKCNT_THR FSK receiver lock counter threshold = 2(11+FSKR_LOCKCNT_THR[2:0])


If FSK_ADDR[3:0] = 0FH, this register sets FSK receiver AGC Accumulator in write operation, and indicates AGC gain in read operation.



- 7:1 - Reserved.

IQ_SWITCH_BF_PPF 0 RW I/Q Switch Before Ping-pong Filer.If I and Q data are sampled at different time before Ping-pong filer, set ‘1’ in this bit to switch the I and Q data.



- 7:1 - Reserved.

CCI_BYP 0 RW Co-Channel Interference Cancellation Bypass Enable.0: Normal operation;1: Co-channel interference cancellation is bypassed.

FSK_1



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TRL_1

TRL_2

EQU_0

CRL_1



SYMB_RATE[7:0] 7:0 RW Symbol Rate (Lower Byte).Refer to register 62H for more details.



SYMB_RATE[15:8] 7:0 RW Symbol Rate (Higher Byte).SYMB_RATE[15:0] is used to set a coarse normalized symbol rate for the TRL. The SYMB_RATE[15:0] is calculated by

SYMB_RATE[15:0] = (Real symbol rate / Sample rate) * 216.Where,‘Real symbol rate’ is the symbol rate of the channel;‘Sample rate’ is 96 MHz sampling clock.



EQU_BYP 7 RW The Adaptive Equalizer Bypass Enable.0: Normal operation;1: The adaptive equalizer is bypassed.

- 6:2 - Reserved.

ROLL_OFF_FTR[1:0] 1:0 RW Roll-off Factor.These bits define or indicate the roll-off factor of the match filter.00: Roll-off factor is 0.35;01: Roll-off factor is 0.25;10: Roll-off factor is 0.20.11: Reserved.



CRL_LCK_DET[7:0] 7:0 R CRL Lock Detected Value (For DVB-S Only).This register indicates the lock detected value of CRL in the DVB-S mode.This bit is valid only when DVB-S mode is enabled (bit DVB_MD (b2, 08H)=0).

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CRL_2

CRL_12

Address: 7EHDefault: 00H


CONST_MD[1:0] 7:6 R Constellation Mode.This register indicates the constellation pattern of the signal.00: QPSK 01: 8PSK10: 16APSK 11: 32APSK

S2_PILOT_MD 5 R Pilot Mode Indication (For DVB-S2 Mode Only).In CRL module, this bit indicates if pilot is on, and it’s only valid in DVB-S2 mode.0: Pilot off;1: Pilot on.This bit is valid only when DVB-S2 mode is enabled (bit DVB_MD (b2, 08H)=1).

- 4 - Reserved.

CODE_RATE[3:0] 3:0 R Code Rate.These bits indicate the code rate of the channel.0000: 1/4 0001: 1/30010: 2/5 0011: 1/20100: 3/5 0101: 2/30110: 3/4 0111: 4/51000: 5/6 1001: 8/91010: 9/10 1011~1111: Reserved.



PHASE_NOISE[7:0] 7:0 R Phase Noise (S12.16) (8 LSB)Refer to register 89H for more details.

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CRL_13

SNR_1

SNR_2



S2_SPEC_INV 7 RW Spectrum Inversion (For DVB-S2 Mode Only)0: Spectrum is not inverted;1: Spectrum is inverted.This bit can also be written by MCU automatically. In DVB-S2 mode, user can read this bit for spectrum inversion information after FEC is locked. This bit is valid only when DVB-S2 mode is enabled (bit DVB_MD (b2, 08H)=1).

- 6:4 - Reserved.

PHASE_NOISE[11:8] 3:0 R Phase Noise (S12.16) (4 MSB)PHASE_NOISE[11:0] is a 12-bit register that indicates the phase noise. The lower 8 bits are stored in register 88H.

Address: 8CHDefault: 00H


- 7:6 - Reserved.

S2_N_POWER[5:0] 5:0 R Noise Power (6 LSB) (For DVB-S2 Mode Only).Refer to register 8DH for full details.



S2_N_POWER[13:6] 7:0 R Noise Power (8 MSB) (For DVB-S2 Mode Only).In DVB-S2 mode, S2_N_POWER[13:0] is a 14-bit noise power that is used to calculate SNR. Refer to Section 2.13.3.1, " SNR Estimation" on page 10 for more details.This register indicates the higher 8 bits of S2_N_POWER[13:0] and lower 6 bits are in register 8CH.This bit is valid only when DVB-S2 mode is enabled (bit DVB_MD (b2, 08H)=1).

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SNR_3

FFT_1

FFT_5

FFT_6

Address: 8EHDefault: 00H


S2_POWER_IND[7:0] 7:0 R Signal Power Indicator (U8.1) (For DVB-S2 Mode Only).In DVB-S2 mode, S2_POWER_IND[7:0] is a 8-bit signal power indicator that is used to calculate SNR. Refer to Section 2.13.3.1, " SNR Estimation" on page 10 for more details.This bit is valid only when DVB-S2 mode is enabled (bit DVB_MD (b2, 08H)=1).



- 7 - Reserved.

FFT_LENGTH[1:0] 6:5 RW FFT Length.These 2 bits define the number of points for FFT analysis. The result of FFT analysis becomes more accurate when takes more numbers of points, but the blind scan will spend more time.

FFT_OVL[4:0] 4:0 RW FFT Overlap.These 5 bits define the overlap range of blind scan. The blind scan takes more time when the FFT overlap gets larger.

Address: 95HDefault: 9CH


FFT_TUNER_OFFSET[9:8] 7:6 R FFT Tuner Offset (2 MSB).This register represents the higher two bits of a 10-bit tuner offset. In the blind scan mode, FFT_TUNER_OFFSET[9:0] indicates the tuner offset of next blind scan window.FFT_TUNER_OFFSET[7:0] is indicated in register 96H.

- 5:0 - Reserved.



FFT_TUNER_OFFSET [7:0]

7:0 R FFT Tuner Offset (8 LSB).Refer to the description of bits FFT_TUNER_OFFSET[9:8] (95H) for full details.

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FFT_7

FFT_9

DISEQC_0



- 7:4 - Reserved.

FFT_SNR_THR[3:0] 3:0 RW SNR Threshold.This register defines the SNR threshold of the channel in blind scan mode. The SNR threshold should be properly set, because, the larger the SNR threshold, the more possible it might lose some channels; the smaller the SNR threshold, the more possible it might get false channels.



- 7:6 - Reserved.

FFT_FLAT_FTR[5:0] 5:0 RW FFT Flatten Factor The 6-bit FFT flatten factor is used to determine whether there are channels in the current window. The FFT flatten factor should be properly set, because, the larger the FFT flatten factor, the more possible it might lose some channels; the smaller the FFT flatten factor, the more possible it might get false channels.The default setting is 10H.

Address: A0HDefault: 00H


DSEC_TONE_FREQ [7:0]

7:0 RW Tone Frequency.This register is used to set the DiSEqC™ tone frequency (ftone).

The ftone is calculated by:

ftone = fmclk / (DSEC_TONE_FREQ[7:0] * 64)

Where,fmclk is the frequency of the master clock (96 MHz).

For example, if DiSEqC™ tone frequency is 22 kHz, this register should be 96M/(22k*64) = 45H.

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DISEQC_1

Address: A1HDefault: 00H


DSEC_RCV_EN 7 RW DiSEqC™ Interface Receiver Enable.This bit controls whether the DiSEqC™ Interface is enabled to receive messages from an external device (such as LNB).0: Disabled;1: Enabled.

DSEC_RDY 6 RW DiSEqC™ Interface Transmission Ready / Data Transmitting StartWrite a ‘0’ in this bit to start transmitting messages to the external device. After transmitting starts, the interface status can be read from this bit as follows: 0: The transmission is completed, and the interface is ready for a new message transmission. 1: The transmission is on going;

DSEC_TRAN_LENGTH[2:0]

5:3 RW DiSEqC™ Message LengthThis is the length (in byte) of messages transmitted to or received from an external device. The length of transmitted message should include framing, address, command and data, but exclude the parity bits.

DSEC_SWITCH 2 RW Representation Mode SwitchingThis bit is used to switch the representation of binary 0 during transmission.0: Modulation is active during 33 pulses.1: Modulation is active during 22 pulses, then inactive during the following 11 pulses.Refer to Figure 8 on page 16 for more details.

DSEC_LNB_CTRL_SEL [1:0]

1:0 RW Signaling Mode Selection.00: Continuous mode. 01: Modulated tone burst mode. 10: Unmodulated tone burst mode. 11: DiSEqC™ mode. Refer to Section 2.16.2, "LNB Signaling Control" on page 15 for more details.This bit is valid only when bit DSEC_OUT_MD[1:0] (b7~6, A2H) = 0X).

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DISEQC_2

Address: A2HDefault: Not available


DSEC_OUT_MD[1:0] 7:6 RW Pin DISEQC Output Selection.0X: Pin DISEQC transmits the LNB signal (select by bit DSEC_LNB_CTRL_SEL [1:0] (A1H));10: Force pin DISEQC output ‘0’;11: Force pin DISEQC output ‘1’;

DSEC_ENVELOP_EN 5 RW DiSEqC Envelop Mode Enable.0: Normal operation;1: DiSEqC envelop mode is enabled.

DSEC_IN_SEL 4 RW Pin DISEQC and Pin DISEQC_IN Functional Selection.This bit defines the functions of pin DiSEqC and pin DISEQC_IN.0: Pin DISEQC is used to output DiSEqC™ message only and pin DISEQC_IN is

used to input DiSEqC™ message.1: Pin DISEQC is bi-directional. Both input and output DiSEqC™ message is

transmitted through this pin.

DSEC_RCV_ERR 3 R Receive Data Error Flag.A ‘1’ in this bit indicates error occurred while receiving data from LNB. This bit will be cleared automatically after read.

DSEC_OLF 2 R Pin OLF Status Indication.This bit indicates the status of pin OLF.0: Pin OLF is logic LOW;1: Pin OLF is logic HIGH.Pin OLF is an input pin that can be used to indicate the available functions and conditions of a DiSEqC slave. For example, it can be used to indicate the overflow flag of an LNB.

DSEC_LNB_EN 1 RW Pin LNB_EN Output Control.This control bit controls the output level on pin LNB_EN.0: Pin LNB_EN outputs LOW;1: Pin LNB_EN outputs HIGH.Pin LNB_EN is an output pin that can be used to select the available functions and conditions of a DiSEqC slave. For example, it can be used to control the On/Off of the LNB supply.

DSEC_VOLT_SEL 0 RW Pin VSEL Output Control.This control bit controls the output level on pin VSEL.0: Pin VSEL outputs LOW;1: Pin VSEL outputs HIGH.Pin VSEL is an output pin that can be used to select the available functions and conditions of a DiSEqC slave. For example, it can be used to select the LNB voltage.

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DISEQC_3

DISEQC_4

DISEQC_5

DISEQC_6



DSEC_MSG0[7:0] 7:0 RW DiSEqC™ Message Contents (Byte 0). This register contains the first byte of the message to be sent to or received from an external device. In serial transmission, MSB of each byte is sent first.This bit is valid only when bit DSEC_LNB_CTRL_SEL[1:0] (b1~0, A1H) = 11).



DSEC_MSG1[7:0] 7:0 RW DiSEqC™ Message Contents (Byte 1). This register contains the second byte of the message to be sent to or received from an external device. In serial transmission, MSB of each byte is sent first.This bit is valid only when bit DSEC_LNB_CTRL_SEL[1:0] (b1~0, A1H) = 11).



DSEC_MSG2[7:0] 7:0 RW DiSEqC™ Message Contents (Byte 2). This register contains the third byte of the message to be sent to or received from an external device. In serial transmission, MSB of each byte is sent first.This bit is valid only when bit DSEC_LNB_CTRL_SEL[1:0] (b1~0, A1H) = 11).



DSEC_MSG3[7:0] 7:0 RW DiSEqC™ Message Contents (Byte 3). This register contains the fourth byte of the message to be sent to or received from an external device. In serial transmission, MSB of each byte is sent first.This bit is valid only when bit DSEC_LNB_CTRL_SEL[1:0] (b1~0, A1H) = 11).

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DISEQC_7

DISEQC_8

DISEQC_9

DISEQC_10



DSEC_MSG4[7:0] 7:0 RW DiSEqC™ Message Contents (Byte 4). This register contains the fifth byte of the message to be sent to or received from an external device. In serial transmission, MSB of each byte is sent first.This bit is valid only when bit DSEC_LNB_CTRL_SEL[1:0] (b1~0, A1H) = 11).



DSEC_MSG5[7:0] 7:0 RW DiSEqC™ Message Contents (Byte 5). This register contains the sixth byte of the message to be sent to or received from an external device. In serial transmission, MSB of each byte is sent first.This bit is valid only when bit DSEC_LNB_CTRL_SEL[1:0] (b1~0, A1H) = 11).



DSEC_MSG6[7:0] 7:0 RW DiSEqC™ Message Contents (Byte 6). This register contains the seventh byte of the message to be sent to or received from an external device. In serial transmission, MSB of each byte is sent first.This bit is valid only when bit DSEC_LNB_CTRL_SEL[1:0] (b1~0, A1H) = 11).

Address: AAHDefault: Not available


DSEC_MSG7[7:0] 7:0 RW DiSEqC™ Message Contents (Byte 7). This register contains the eighth byte of the message to be sent to or received from an external device. In serial transmission, MSB of each byte is sent first.This bit is valid only when bit DSEC_LNB_CTRL_SEL[1:0] (b1~0, A1H) = 11).

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DISEQC_11

MCUC_0

Address: ABHDefault: Not available


DSEC_PAR_ERR7 7 R Parity Error Flag of DiSEqC™ message (Byte 7)‘1’ indicates that parity error occurred in the eighth byte of the received DiSEqC™ message. The byte is stored in register AAH.

DSEC_PAR_ERR6 6 R Parity Error Flag of DiSEqC™ message (Byte 6)‘1’ indicates that parity error occurred in the seventh byte of the received DiSEqC™ message. The byte is stored in register A9H.

DSEC_PAR_ERR5 5 R Parity Error Flag of DiSEqC™ message (Byte 5)‘1’ indicates that parity error occurred in the sixth byte of the received DiSEqC™ message. The byte is stored in register A8H.

DSEC_PAR_ERR4 4 R Parity Error Flag of DiSEqC™ message (Byte 4)‘1’ indicates that parity error occurred in the fifth byte of the received DiSEqC™ message. The byte is stored in register A7H.

DSEC_PAR_ERR3 3 R Parity Error Flag of DiSEqC™ message (Byte 3)‘1’ indicates that parity error occurred in the fourth byte of the received DiSEqC™ message. The byte is stored in register A6H.

DSEC_PAR_ERR2 2 R Parity Error Flag of DiSEqC™ message (Byte 2)‘1’ indicates that parity error occurred in third byte of the received DiSEqC™ message. The byte is stored in register A5H.

DSEC_PAR_ERR1 1 R Parity Error Flag of DiSEqC™ message (Byte 1)‘1’ indicates that parity error occurred in second byte of the received DiSEqC™ message. The byte is stored in register A4H.

DSEC_PAR_ERR0 0 R Parity Error Flag of DiSEqC™ message (Byte 0)‘1’ indicates that parity error occurred in the first byte of the received DiSEqC™ message. The byte is stored in register A3H.

Address: B0HDefault: 00H


PROG_DATA[7:0] 7:0 W Program Data (8 LSB).This register sets the lower 8 bits of PROG_DATA[13:0].Refer to bits PROG_DATA[13:8] (B1H) for more details.

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MCUC_1

MCUC_2



- 7:6 - Reserved.

PROG_DATA[13:8] 5:0 W Program Data (6 MSB).PROG_DATA[13:0] is a 14-bit register used to upload the program data into the MCU memory. The lower 8 bits are store in register B0H.Please note that the program data must be written into PROG_DATA[7:0] first and then into PROG_DATA[13:8]. Only when (and each time) bits PROG_DATA[13:8] have been filled, the total 14 bits of program data in PROG_DATA[13:0] will be loaded into the MCU memory and the current memory address will be automatically increased by 1. MCU totally reserves (4K * 14) bits for program data.



- 7:1 - Reserved.

MCU_START 0 RW MCU Start.Write a ‘1’ to this bit first to reset the MCU, then write a ‘0’ to this bit to start the MCU.0: Start MCU (Clear upload address pointer).1: Reset MCU.

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SYS_9

Address: C9HDefault: 00H


AT_DECI_SEL 7 RW Automatic Decimation Factor and LPF Coefficient Selection.0: Decimation factor and LPF coefficient are specified by the user through bits

DECI_SEL[2:0] and LPF_SEL[2:0] in register C9H;1: Decimation factor and LPF coefficient is automatically selected by micro-

controller. The results can be read out from bits DECI_SEL[2:0] and LPF_SEL[2:0] in register C9H.

DECI_SEL[2:0] 6:4 RW Decimation Factor Selection.These bits select or indicate the decimation factor for the different range of symbol rate. 000: The decimation factor for the symbol rate larger or equal to 20 MHz;001: The decimation factor for the symbol rate in range of [10 MHz, 20 MHz);010: The decimation factor for the symbol rate in range of [5 MHz, 10 MHz);011: The decimation factor for the symbol rate in range of [2.5 MHz, 5 MHz);100: The decimation factor for the symbol rate in range of [1.25 MHz, 2.5 MHz);101: The decimation factor for the symbol rate less or equal to 1.25 MHz;110 ~ 111: Reserved.

- 3 - Reserved.

LPF_SEL[2:0] 2:0 RW LPF Coefficient Selection.Through the FIR-downconverter, the symbol rate range is extended to [1~45) Msps. This register selects or indicates the coefficients of Low Pass Filters for different symbol rates.000: LPF coefficient for symbol rate in range of (40 Msps ~45 Msps)/

2DECI_SEL[2:0];001: LPF coefficient for symbol rate in range of (34.3 Msps ~40 Msps)/

2DECI_SEL[2:0];010: LPF coefficient for symbol rate in range of (30 Msps ~34.3 Msps)/

2DECI_SEL[2:0];011: LPF coefficient for symbol rate in range of (24.6 Msps ~30 Msps)/

2DECI_SEL[2:0];100: LPF coefficient for symbol rate in range of (21.3 Msps ~24.6 Msps)/

2DECI_SEL[2:0];101: LPF coefficient for symbol rate in range of (1 Msps ~21.3 Msps)/

2DECI_SEL[2:0];110~111: Reserved.

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OUTFORMAT_0

OUTFORMAT_1

OUTFORMAT_2

OUTFORMAT_3

Address: EAHDefault: C3H


CI_DIV_H[1:0] 7:6 RW These are lower 2-bit of CI_DIV_H[5:0].Please refer to bit CI_DIV_H[5:2] (b3-0, FEH) for more details.

CI_DIV_L[5:0] 5:0 RW CI_DIV_L[5:0] is a 6-bit register, which is used to calculate the length of low level of the MPEG clock.The MPEG low level time = (CI_DIV_L[5:0]+1)/Fmclk.The time’s range is from 1~63.

Address: EBHDefault: 00H


PID_FILTER_EN[15:8] 7:0 RW This is the higher byte of PID_FILTER_EN[15:0].PID_FILTER_EN[15:0] is a 16-bit register. Each bit of PID_FILTER_EN[15:0] correspond to a PID filter in the PID filter table (0~15). In this table, the PID filter 1~15 is programmable. However, the PID filter 0 is only for the PID 000~00F, and is not configurable.The lower byte is in register ECH.

Address: ECHDefault: 00H


PID_FILTER_EN[7:0] 7:0 RW This is the lower byte of PID_FILTER_EN[15:0].Please refer to bits PID_FILTER_EN[15:8] in the register EBH for more details.

Address: EDHDefault: 00H


PID_FILTER_TABLE[7:0] 7:0 RW This is the lower byte of PID_FILTER_TABLE[12:0].Please refer to bits PID_FILTER_TABLE[12:8] in the register EEH for more details.Con

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OUTFORMAT_4

OUTFORMAT_5

Address: EEHDefault: 00H


- 7:6 - Reserved.

INV_B8 5 RW B8H InversionThis bit determines whether the output sync bytes B8H are inverted to 47H.0: Non-inverted.1: Inverted (recommended).

PID_FILTER_TABLE[12:8] 4:0 RW This is the higher 5-bit of PID_FILTER_TABLE[12:0].PID_FILTER_TABLE[12:0] is a 13-bit PID to be written into the PID filter table (0 ~15). In this table, the PID filter 1~15 is programmable. However, the PID filter 0 is only for the PID 000~00F, and is not configurable.The lower byte is in register EDH.

Address: EFHDefault: 00H


- 7:4 - Reserved.

PID_FIL_TABLE_INDEX[3:0]

3:0 W The index of the PID filter table (0~15) is present by PID_FIL_TABLE_INDEX[3:0].When this register is written, the PID in PID_FILTER_TABLE[12:0] is sent to the corresponding location of the PID filter table.

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OUTFORMAT_6

Address: FDHDefault: 42H


S2_MPEG_OUT_MUX 7 RW DVB-S2 MPEG Output MUX.0: Normal operation;1: MPEG interface will output ‘0’ until FEC is locked.Note: This bit only for DVB-S2, it should be set ‘0’ for DVB-S mode.

CKOUT_POL 6 RW Active Edge of Pin M_CKOUT.This bit selects the active edge of pin M_CKOUT to update the MPEG-TS outputs.0: Active at rising edge;1: Active at falling edge.

SYNC_POL 5 RW Pin M_SYNC Output Polarity.This bit defines the output polarity of pin M_SYNC.0: Pin M_SYNC is active HIGH;1: Pin M_SYNC is active LOW.

VAL_POL 4 RW Pin M_VAL Output Polarity.This bit defines the output polarity of pin M_VAL.0: Pin M_VAL is active HIGH;1: Pin M_VAL is active LOW.

ERR_POL 3 RW Pin M_ERR Output Polarity.This bit defines the output polarity of pin M_ERR.0: Pin M_ERR is active HIGH;1: Pin M_ERR is active LOW.

NP_SEL 2 RW Serial / Parallel Interface Selection.This bit is valid when bit S2_CI_EN (FDH) is 0.0: Parallel interface;1: Serial interface.

EI_ENA 1 RW Determines whether the output TEI bit in MPEG packet is changed in DVB-S2 mode.0: Unchanged;1: Force to ‘1’ in case that uncorrectable packet error occurs in MPEG packet; otherwise, unchanged.

CI_EN 0 RW Common Interface Selection.0: Parallel or serial interface, as selected by bit S2_NP_SEL (FDH));1: Common interface.

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OUTFORMAT_7

Address: FEHDefault: 20H


QPSK_R_EN 7 RW QPSK-R Enable.0: QPSK-R is disabled;1: QPSK-R is enabled.

FRAME_SPEED_AT 6 RW Frame Speed Automatic.0: Normal operation;1: Adjust distance between 2 frames automatically.

PID_FILTER_MD 5 RW PID Filter Work Mode.0: Allow the TS packages with the PID in PID filter table transfered;1: Reject the TS packages with the PID in PID filter table transfered.

R_CNT_OUT 4 RW Read Counter Out.1: read the counter information from register FDH, FEH, EAH and EBH;0: read the original write information from register FDH, FEH, EAH and EBH.

CI_DIV_H[5:2] 3:0 RW These are higher 4-bit of CI_DIV_H[5:0].CI_DIV_H[5:0] is a 6-bit register, which is used to calculate the length of high level of the MPEG clock.The MPEG high level time = (CI_DIV_H[5:0]+1)/Fmclk.The time’s range is from 1~63.

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3.2.2 Registers For DVB-S2 Mode Only

S2_LDPC_1 (For DVB-S2 mode only)




Address: D1HDefault: 00H


- 7:2 - Reserved.

SOFT_DEC_SEL 1 RW Soft Decision Selection.0: New;1: Old.

S2_LDPC_CNT_CLR 0 RW LDPC Frame Counter Clear.Write ‘1’ in this bit to clear the LDPC frame counter and the LDPC failure frame counter in registers D5H~DAH.



S2_LDPC_FM_CNT[7:0] 7:0 R LDPC Frame Counter (Lower Byte).Refer to bits S2_LDPC_FM_CNT[23:16] in register D7H for more details.



S2_LDPC_FM_CNT[15:8] 7:0 R LDPC Frame Counter (Middle Byte).Refer to bits S2_LDPC_FM_CNT[23:16] in register D7H for more details.



S2_LDPC_FM_CNT[23:16] 7:0 R LDPC Frame Counter (Higher Byte).This is the higher 8 bits of the LDPC frame counter (S2_LDPC_FM_CNT[23:0]). The counter will add ‘1’ each time a frame is input.Bits S2_LDPC_FM_CNT[15:0] are in registers D5H and D6H.Con

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S2_BCH_1 (For DVB-S2 mode only)




S2_LDPC_FAIL_CNT[7:0] 7:0 R LDPC Failure Frame Counter (Lower Byte).Refer to bits S2_LDPC_FAIL_CNT[23:16] in register DAH for more details.



S2_LDPC_FAIL_CNT [15:8]

7:0 R LDPC Failure Frame Counter (Middle Byte).Refer to bits S2_LDPC_FAIL_CNT[23:16] in register DAH for more details.

Address: DAHDefault: 00H


S2_LDPC_FAIL_CNT [23:16]

7:0 R LDPC Failure Frame Counter (Higher Byte).This is the higher 8 bits of the LDPC failure frame counter (S2_LDPC_FAIL_CNT[23:0]). The counter will add ‘1’ if the iteration process of a frame is failed.Bits S2_LDPC_FAIL_CNT[15:0] are in registers D8H and D9H.

Address: E1HDefault: 00H


S2_BCH_ERR_CNT[7:0] 7:0 R BCH Error Frame Counter (Lower Byte).Refer to bits S2_BCH_ERR_CNT[15:8] in register E2H.



S2_BCH_ERR_CNT[15:8] 7:0 R BCH Error Frame Counter (Higher Byte).This is the higher 8 bits of the BCH decoder error frame counter (S2_BCH_ERR_CNT[15:0]). The counter indicates the number of uncorrectable frames after BCH decoding. The counter will overflow if it is full.Bits S2_BCH_ERR_CNT[7:0] are in register E1H.

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S2_DEFRAMING_2 (For DVB-S2 mode only)




S2_BCH_RECOVER_CNT [7:0]

7:0 R BCH Recovered Bit Counter (Lower Byte).Refer to bits S2_BCH_RECOVER_CNT[15:8] in register E4H.



S2_BCH_RECOVER_CNT [15:8]

7:0 R BCH Recovered Bit Counter (Higher Byte).This is the higher 8 bits of the BCH decoder recovered bit counter (S2_BCH_RECOVER_CNT [15:0]). The counter indicates the number of bits have been recovered during BCH decoding. The counter will overflow if it is full.Bits S2_BCH_RECOVER_CNT [7:0] are in register E3H.

Address: F3HDefault: 03H


S2_BBHEAD_ERR_CNT [7:0]

7:0 R Baseband Header Error Counter (Lower byte).Refer to bits S2_BBHEAD_ERR_CNT[15:8] in register F4H for more details.



S2_BBHEAD_ERR_CNT [15:8]

7:0 R Baseband Header Error Counter (Higher byte).This is the higher byte of the baseband header CRC error counter (S2_BBHEAD_ERR_CNT[15:0]).The S2_BBHEAD_ERR_CNT[15:0] indicates the number of erroneous baseband header in cyclic redundancy check (CRC).Bits S2_BBHEAD_ERR_CNT[7:0] are in register F3H.

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S2_CRC8_0 (For DVB-S2 mode only)





S2_BBHEAD_CNT_CLR 7 RW Baseband Header Error Counter Clear Enable.Write ‘1’ in this bit to clear the baseband header error counter in registers F3H & F4H.

- 6:0 - Reserved.



S2_UPL_ERR_CNT[7:0] 7:0 R UPL CRC Error Counter (Lower byte).Refer to bits S2_UPL_ERR_CNT[15:8] in register F8H for more details.



S2_UPL_ERR_CNT[15:8] 7:0 R UPL CRC Error Counter (Higher byte).This is the higher byte of the UPL (User Package Length) CRC error counter (S2_UPL_ERR_CNT[15:0]). The counter indicates the number of erroneous user package in CRC.Bits S2_UPL_ERR_CNT[7:0] are in register F7H.



- 7:1 - Reserved.

S2_UPL_ERR_CNT_CLR 0 RW UPL CRC Error Counter Clear Enable.A ‘1’ in this bit clears the UPL CRC error counter in registers F7H & F8H.

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3.2.3 Registers For DVB-S Mode Only

S_CTRL_0 (For DVB-S mode only)

S_CTRL_1 (For DVB-S mode only)



- 7:6 - Reserved.

S_DESC_BYP 5 RW DVB-S Descrambler Bypass Enable.0: Normal operation;1: Descrambler is bypassed.

S_RS_BYP 4 RW RS Decoder Bypass Enable.0: Normal operation;1: RS decoder is bypassed.

S_DEINT_BYP 3 RW DVB-S De-interleaver for Bypass Enable.0: Normal operation;1: The de-interleaver for DVB-S mode is bypassed.

S_VTB_SOFT_RST 2 RW DVB-S Viterbi Soft Reset.0: Normal operation;1: Soft reset the Viterbi module without affecting the corresponding registers.

S_FEC_SOFT_RST 1 RW DVB-S FEC Soft Reset.0: Normal operation;1: Soft reset FEC module for DVB-S without affecting the corresponding registers.

S_DAGC_SOFT_RST 0 RW DVB-S Digital AGC Soft Reset.0: Normal operation;1: Soft reset digital AGC for DVB-S module without affecting the corresponding registers.



S_VTB_FAIL 7 - DVB-S Viterbi Fail Flag.A ‘1’ in this bit indicates DVB-S Viterbi is failed; otherwise it works properly.

- 6:4 - Reserved.

S_DAGC_LCK 3 R DVB-S Digital AGC Lock Flag.A ‘1’ in this bit indicates digital AGC is locked; otherwise it is unlocked.

S_VTB_LCK 2 R DVB-S Viterbi Decoder Lock Flag.A ‘1’ in this bit indicates Viterbi decoder is locked; otherwise it is unlocked.

S_SYNC_LCK 1 R DVB-S Sync Detector Lock Flag.A ‘1’ in this bit indicates Sync Detector is locked; otherwise it is unlocked.

S_DESC_LCK 0 R DVB-S Descrambler Lock Flag.A ‘1’ in this bit indicates Descrambler is locked; otherwise it is unlocked.

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S_VTB_0 (For DVB-S mode only)

S_VTB_6 (For DVB-S mode only)

Address: E0HDefault: F8H


S_RATE_SEL[4:0] 7:3 RW Viterbi Decoder Code Rate Selection.Each bit of S_RATE_SEL[4:0] selects the corresponding code rate to be tried in Viterbi decoder.S_RATE_SEL[4] =1: try code rate 7/8;S_RATE_SEL[3] =1: try code rate 5/6;S_RATE_SEL[2] =1: try code rate 3/4;S_RATE_SEL[1] =1: try code rate 2/3;S_RATE_SEL[0] =1: try code rate 1/2.In order to quickly get right one, user are recommended to try all kinds of code rate by setting bits S_RATE_SEL[4:0] to 1 1111.

S_SPEC_INV 2 RW Spectrum Inversion.0: Spectrum is not inverted;1: Spectrum is inverted.

S_ROT_90D 1 RW 90 Degree Rotation of Constellation0: Normal operation;1: Constellation rotates 90 degree.

S_ROT_180D 0 RW 180 Degree Rotation of Constellation0: Normal operation;1: Constellation rotates 180 degree.

Address: E6HDefault: 0BH


S_VTB_CODE[2:0] 7:5 R Viterbi Code Rate Indicator.This field indicates an appropriate code rate to be applied on income signal.000: 7/8;001: 5/6;010: 3/4;011: 2/3;100: 1/2.101~111: Reserved.

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S_RS_0 (For DVB-S mode only)







S_PK_CNT[7:0] 7:0 R Packet Counter (Lower byte)Refer to the description of register F1H for full details.



S_PK_CNT[15:8] 7:0 R Packet Counter (Higher byte).This is the higher byte of a 16-bit measured value that counts the MPEG-TS packets elapsed since the packet counters were enabled. The lower byte is in register F0H.



S_CORR_PK_CNT[7:0] 7:0 R Corrected Packet Counter (Lower byte)Refer to the description of register F3H for full details.



S_CORR_PK_CNT[15:8] 7:0 R Corrected Packet Counter (Higher byte)This is the higher byte of a 16-bit measured value that counts MPEG-TS packets that were corrected by the RS Decoder since the packet counters were enabled. The lower byte is in register F2H.



S_UNCORR_PK_CNT[7:0] 7:0 R Uncorrected Packet Counter (Lower byte)Refer to the description of register F3H for full details.

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S_UNCORR_PK_CNT[15:8] 7:0 R Uncorrected Packet Counter (Higher byte)This is the higher byte of a 16-bit measured value that counts MPEG-TS packets detected as erroneous by the RS Decoder but not correctable, since the packet counters were enabled. The lower byte is in register F4H.



S_BER_CNT[7:0] 7:0 R Internal Byte/Bit Error Counter (Lower byte)Refer to the description of register F7H for full details.



S_BER_CNT[15:8] 7:0 R Internal Error Bits/Bytes Counter (Higher byte)This is the higher byte of a 16-bit measured value that counts the internal error bits/bytes. Note that these are the raw error bits/bytes which include any error falling within the R/S redundancy bytes. The lower byte is in register F6H.

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S_RS_UNCORR_ERR 7 RW RS Uncorrected Error.0: Normal operation;1: The Reed-Solomon decoder will not correct errors though it still detects errors.

S_PK_CNT_HLD 6 RW Hold Packet Counter.This bit determines whether the counters (registers F0H to F5H) can be updated. 0: Can be updated;1: Hold, can not be updated.

S_PK_CNT_CLR 5 RW Clear Packet Counter.A ‘0’ in this bit clears the packet counters (registers F0H to F5H).

S_BER_ON 4 RW Start Counting Bit/Byte Errors.A ‘1’ in this bit starts counting bit/byte errors before RS correction. This bit will be automatically reset to 0 when a certain number of data bytes defined in register F9H have elapsed.

S_ERR_SRC_SEL 3 RW Error Source Selection.This bit determines either bit errors or byte errors are counted by RS.0: Bit errors;1: Byte errors.

- 2:0 - Reserved.



- 7:3 - Reserved.

S_NUM_BYT[2:0] 2:0 RW Number of Data Bytes.This field defines the total number of data bytes checked during BER estimation.

The number of bytes = 2(2*S_NUM_BYT[2:0] + 12).Note that this setting is valid only when bit S_BER_ON (b4,F8H) = 0.

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S_SYNC_0 (For DVB-S mode only)

S_DES_0 (For DVB-S mode only)

S_DAGC_5 (For DVB-S mode only)

Address: FAHDefault: 06H


- 7:6 - Reserved.

S_MISMATCH[1:0] 5:4 RW Represent an integer that defines the number of mismatched bits allowed in a sync byte during track mode.

S_ACQ_MD[1:0] 3:2 RW Represent an integer that defines the number of the continuous sync bytes in Pre-Track mode.The number of the continuous sync bytes = S_ACQ_MD[1:0] + 3.In Pre-Track mode, if there are ‘S_ACQ_MD[1:0] + 3’ continuous sync bytes including B8H found on the expected position, the sync detector enters to Track mode; if there are ‘S_ACQ_MD[1:0] + 3’ continuous sync bytes including 47H found on the expected position, the sync detector enters to Locate mode.

S_TRK_MD[1:0] 1:0 RW Represent an integer that defines the number of the continuous frames in Track mode.The number of the continuous frames = S_TRK_MD[1:0] + 1.In Track mode, if the sync byte is not detected on the expected position within ‘S_TRK_MD[1:0] + 1’ continuous frames, the sync detector enters to hunt mode.

Address: FCHDefault: 00H


- 7:2 - Reserved.

S_DESC_MD_SEL[1:0] 1:0 RW Descrambler Tracking Mode Selection.Determine when the Descrambler is in tracking mode (locked) or in acquisition mode (unlocked).00: The Descrambler goes to tracking mode when it detects an inverted sync byte B8H at the expected position; otherwise, it goes to acquisition mode.10: The Descrambler goes to tracking mode when it detects an inverted sync byte B8H and seven sync bytes 47H on the expected positions; it goes to acquisition mode if any sync byte is wrong.X1: The Descrambler is locked when detects a sync byte B8H on the expected position. It freezes in tracking mode once it is locked.

Address: FFHDefault: Not available


S_SNR[7:0] 7:0 R SNR Indicator.This register indicates a coefficient for calculating the real SNR of the channel.Real SNR = 10 * In(S_SNR[7:0] / 8) In(10)

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4 Electrical Characteristics

4.1 Absolute Maximum Ratings

4.2 Recommended Operating Conditions

4.3 DC Electrical Characteristics

Symbol Parameter Min Max Unit

VDDA, VDDD 3.3 V Power Supply for the Analog Part and the I/O Pad

-0.3 3.8 V

VCC 1.2 V Power Supply for the Digital Core -0.2 1.44 V

V5VT Voltage on 5V Tolerant Pins -0.5 +5.5 V

VIN Voltage on Input Pins -0.3 VDDD+0.3 V

TSTG Storage Temperature -40 +150 °C

Note: Stresses above the Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended period may affect device reliability.

Symbol Parameter Min Typ Max Unit

VDDA, VDDD 3.3 V Power Supply for the Analog Part and the I/O Pad

2.97 3.3 3.63 V

VCC 1.2 V Power Supply for the Digital Core 1.08 1.2 1.32 V

TA Operating Ambient Temperature 0 - 70 °C

Note: Device functionality is not guaranteed at any conditions beyond the recommended operating conditions.


VIL Low Level Input Voltage 0.8 V

VIH High Level Input Voltage 2.0 V

VOL Low Level Output Voltage 0.3 V

VOH High Level Output Voltage 2.5 V

ICC Supply Current for VCC 2361 mA

IDDA Supply Current for VDDA 33 mA

IDDD Supply Current for VDDD 12 mA

Note: 1. Test condition: 8PSK, symbol rate = 27.5 Msps, 3/4 code rate, C/N = 9.0 dB, RF level = -45 dBm, frequency = 1450 MHz.

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4.4 AC Electrical Characteristics

@ TOP = 25 °C, VDDA = 3.3 V, VDDD = 3.3 V, VCC = 1.2 V, unless otherwise specified.


F Master clock Frequency 96 MHz

TRST Hardware Reset Duration 9/F ns

FSCL1 2-wire Bus Data Rate 400 kHz

TPULSE1 SCL and SDA High and Low Level State Duration 1250 ns

Tprop2 Digital Outputs Propagation Time with regard to

CKEXT rising edge1/(2F) ns

Ptotal Total Power Consumption 4303 mW

Note:1. 2-wire bus data rate is limited to 400 kHz/s for 2-wire bus messages intended to be repeated to the tuner on the private 2-wire bus.2. Cload is 80 pF.3. Test condition: 8PSK, symbol rate = 27.5 Msps, 3/4 code rate, C/N = 9.0 dB, RF level = -45 dBm, frequency = 1450 MHz.

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5 Mechanical Package Data5.1 48-Pin Package

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Contact Information

Montage Technology, Inc.

Address: 2025 Gateway Place, Suite 262, San Jose, CA 95110, USA

Tel: 408-982-2788

Fax: 408-982-2789

Website: www.montage-tech.com

Email: [email protected]

Montage Technology (Shanghai) Co., Ltd.

Address: Rm# A1601, Technology Bldg., 900 Yi Shan Rd., Shanghai 200233, China

Tel: +86 21 51696833

Fax: +86 21 54263132

Website: www.montage-tech.com

E-mail: [email protected]

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Documents

Advanced DVB-S/S2 Demodulator M88DS3103 - cabbala.net