ADSP-214xx SHARC Processor Hardware Reference · 2017-10-20 · a ADSP-214xx SHARC® Processor Hardware Reference Includes ADSP-2146x, ADSP-2147x, ADSP-2148x Product Families Revision

a

ADSP-214xx SHARC® ProcessorHardware Reference

Includes ADSP-2146x, ADSP-2147x, ADSP-2148x Product Families

Revision 0.3, July 27, 2010

Part Number82-000469-01

Analog Devices, Inc.One Technology WayNorwood, Mass. 02062-9106

Copyright Information© 2010 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express writ-ten consent from Analog Devices, Inc.

Printed in the USA.

DisclaimerAnalog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by impli-cation or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark NoticeThe Analog Devices logo, Blackfin, EZ-KIT Lite, SHARC, the SHARC logo, TigerSHARC, and VisualDSP++ are registered trademarks of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of their respective owners.

CONTENTS

CONTENTS

PREFACE

Purpose of This Manual ................................................................ lxi

Intended Audience ........................................................................ lxi

Manual Contents ......................................................................... lxii

What’s New in This Manual ........................................................ lxv

Technical or Customer Support ................................................... lxvi

Registration for MyAnalog.com ............................................. lxvi

EngineerZone ....................................................................... lxvii

Social Networking Web Sites ................................................ lxvii

Supported Processors .................................................................. lxvii

Product Information ................................................................. lxviii

Analog Devices Web Site ..................................................... lxviii

VisualDSP++ Online Documentation ................................. lxviii

Technical Library CD ............................................................ lxix

Notation Conventions .................................................................. lxx

INTRODUCTION

Design Advantages ........................................................................ 1-1

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Contents

SHARC Family Product Offerings ........................................... 1-2

Processor Architectural Overview .................................................. 1-2

Processor Core ........................................................................ 1-2

I/O Peripherals ....................................................................... 1-3

I/O Processor ..................................................................... 1-3

Digital Audio Interface (DAI) ............................................. 1-3

Interrupt Controller ........................................................... 1-4

Signal Routing Unit ............................................................ 1-4

Digital Peripheral Interface (DPI) ....................................... 1-4

Interrupt Controller ........................................................... 1-4

Signal Routing Unit 2 ......................................................... 1-5

Development Tools ....................................................................... 1-5

Differences from Previous Processors ............................................. 1-5

I/O Architecture Enhancements .............................................. 1-6

I/O PROCESSOR

Features ........................................................................................ 2-2

Register Overview ......................................................................... 2-3

DMA Channel Registers ............................................................... 2-3

DMA Channel Allocation ....................................................... 2-3

Standard DMA Parameter Registers ......................................... 2-4

Extended DMA Parameter Registers ........................................ 2-8

Data Buffers ......................................................................... 2-10

Chain Pointer Registers ......................................................... 2-11

TCB Storage ............................................................................... 2-13

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Serial Port TCB ..................................................................... 2-14

SPI TCB ............................................................................... 2-14

UART TCB .......................................................................... 2-15

Link Port TCB ...................................................................... 2-15

FIR Accelerator TCB ............................................................. 2-16

IIR Accelerator TCB .............................................................. 2-17

FFT Accelerator TCB ............................................................ 2-18

External Port TCB ................................................................. 2-19

Clocking ..................................................................................... 2-22

Functional Description ............................................................... 2-22

Automated Data Transfer ....................................................... 2-22

DMA Transfer Types ............................................................. 2-23

DMA Direction ..................................................................... 2-24

Internal to External Memory ............................................. 2-24

Peripheral to Internal Memory .......................................... 2-24

Peripheral to External Memory (SPORTs) .......................... 2-25

Internal Memory to Internal Memory ................................ 2-25

DMA Controller Addressing .................................................. 2-25

Internal Index Register Addressing ..................................... 2-27

External Index Register Addressing .................................... 2-28

DMA Channel Status ............................................................ 2-28

DMA Start and Stop Conditions ............................................ 2-29

Operating Modes ........................................................................ 2-30

DMA Chaining ..................................................................... 2-32

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Contents

TCB Memory Storage ....................................................... 2-32

Chain Assignment ............................................................ 2-33

Starting Chain Loading .................................................... 2-34

TCB Chain Loading Priority ............................................. 2-35

Chain Insert Mode (SPORTs Only) .................................. 2-36

Fixed DMA Channel Arbitration ........................................... 2-36

Peripheral DMA Bus ......................................................... 2-42

External Port DMA Bus .................................................... 2-43

SPORT/External Port DMA Bus ....................................... 2-43

Rotating DMA Channel Arbitration ...................................... 2-44

Rotating Priority by Group ............................................... 2-44

Interrupts ................................................................................... 2-45

Sources ................................................................................. 2-45

Unchained DMA Interrupts .............................................. 2-45

Chained DMA Interrupts ................................................. 2-46

Transfer Completion Types .................................................... 2-46

Internal Transfer Completion ............................................ 2-47

Access Completion ........................................................... 2-47

Core Single Word Transfer Interrupts .................................... 2-47

Interrupt Versus Channel Priorities ........................................ 2-48

Debug Features ........................................................................... 2-49

Emulation Considerations ..................................................... 2-49

Effect Latency ............................................................................ 2-49

Write Effect Latency ............................................................. 2-49

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IOP Effect Latency ................................................................ 2-49

IOP Throughput ................................................................... 2-50

Programming Model ................................................................... 2-50

General Procedure for Configuring DMA .............................. 2-51

EXTERNAL PORT

Features ....................................................................................... 3-2

Pin Descriptions ........................................................................... 3-3

Pin Multiplexing ..................................................................... 3-3


Clocking AMI/SDRAM ................................................................ 3-5

Clocking AMI/DDR2 ................................................................... 3-6

External Port Arbitration ............................................................... 3-7

Functional Description ................................................................. 3-7

Operating Mode .................................................................... 3-10

Arbitration Freezing .......................................................... 3-10

Asynchronous Memory Interface ................................................. 3-10

Features ................................................................................. 3-11

Functional Description .......................................................... 3-11

Asynchronous Reads ......................................................... 3-12

Asynchronous Writes ......................................................... 3-12

Parameter Timing ............................................................. 3-14

Idle Cycles ........................................................................ 3-14

Address Mapping .............................................................. 3-14

Operating Modes ................................................................... 3-15

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Contents

Data Packing .................................................................... 3-15

External Access Extension ................................................ 3-15

Predictive Reads ............................................................... 3-16

SDRAM Controller(ADSP-2147x/ADSP-2148x) ................................................... 3-17

Features ................................................................................ 3-17

Functional Description ......................................................... 3-18

SDRAM Commands ........................................................ 3-20

Load Mode Register ...................................................... 3-20

Bank Activation ............................................................ 3-21

Single Precharge ........................................................... 3-21

Precharge All ................................................................ 3-22

Read/Write ................................................................... 3-22

Auto-Refresh ................................................................ 3-24

No Operation/Command Inhibit .................................. 3-24

Command Truth Table ................................................. 3-24

Address Mapping .............................................................. 3-25

Address Translation Options ......................................... 3-26

Address Width Settings ................................................. 3-27

16-Bit Address Mapping ................................................... 3-28

Refresh Rate Control ........................................................ 3-32

Internal SDRAM Bank Access ........................................... 3-34

Single Bank Access ........................................................ 3-34

Multibank Access .......................................................... 3-35

Multi Bank Operation with Data Packing ..................... 3-36

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Timing Parameters ............................................................ 3-37

Fixed Timing Parameters ............................................... 3-37

Data Mask ........................................................................ 3-38

Resetting the Controller .................................................... 3-38

Operating Modes ................................................................... 3-38

Parallel Connection of SDRAMs ....................................... 3-38

Buffering Controller for Multiple SDRAMs ................... 3-39

SDRAM Read Optimization ............................................. 3-40

Core Accesses ................................................................ 3-41

DMA Access ................................................................. 3-43

Notes on Read Optimization ......................................... 3-43

Self-Refresh Mode ............................................................. 3-44

Forcing SDRAM Commands ............................................. 3-45

Force Precharge All ....................................................... 3-45

Force Load Mode Register ............................................. 3-46

Force Auto-Refresh ........................................................ 3-46

DDR2 DRAM Controller (ADSP-2146x) .................................... 3-46

Features ................................................................................. 3-46

Pin Descriptions .................................................................... 3-48


DDR2 Commands ............................................................ 3-51

Load Mode Register ...................................................... 3-51

Load Extended Mode Register ...................................... 3-52

Load Extended Mode Register 2 ................................... 3-53

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Contents

Load Extended Mode Register 3 ................................... 3-53

Bank Activation ............................................................ 3-53

Precharge ...................................................................... 3-54

Precharge All ................................................................ 3-54

Burst Read .................................................................... 3-54

Burst Write ................................................................... 3-55

Auto-Refresh ................................................................ 3-56

Self-Refresh Entry ......................................................... 3-57

Self-Refresh Exit ........................................................... 3-57

Precharge Power-Down Entry ....................................... 3-58

Precharge Power-down Exit ........................................... 3-59

No Operation/Command Inhibit .................................. 3-60

Address Mapping .............................................................. 3-60

Address Translation Options ......................................... 3-60

Page Interleaving Map .................................................. 3-60

Bank Interleaving Map .................................................. 3-61

Address Width Settings ................................................. 3-61

16-Bit Address Mapping ............................................... 3-62

Address Map Tables ...................................................... 3-63

Refresh Rate ..................................................................... 3-66

Data Mask ........................................................................ 3-68

Resetting the Controller .................................................... 3-68

Disabling the Controller ................................................... 3-69

Initialization Sequence .......................................................... 3-69

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Initialization Time ............................................................ 3-70

Internal DDR2 Bank Access .............................................. 3-71

Single Bank Access ........................................................ 3-71

Multibank Access .......................................................... 3-71

Force Activation Window .............................................. 3-72

Multi Bank Operation with Data Packing ..................... 3-73

Fixed Timing Parameters ............................................... 3-74

Operating Modes ................................................................... 3-75

Parallel Connection of DDR2s .......................................... 3-75

Buffering Controller for Multiple DDR2s ...................... 3-76

Read Optimization ............................................................ 3-76

DDR2 Read Optimization ............................................ 3-77

Self-Refresh Mode ......................................................... 3-79

Single-Ended Data Strobe .............................................. 3-81

On Die Termination (ODT) ......................................... 3-81

Additive Latency ........................................................... 3-82

Forcing DDR2 Commands ........................................... 3-82

Data Transfer .............................................................................. 3-84

Data Buffers .......................................................................... 3-84

AMI Receive Buffer ........................................................... 3-84

AMI Transmit Buffer ........................................................ 3-84

DMA Buffer ..................................................................... 3-85

Core Access ........................................................................... 3-85

External Port Dual Data Fetch ........................................... 3-85

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Contents

Conditional Instructions ................................................... 3-86

SIMD Access ........................................................................ 3-86

SDRAM ........................................................................... 3-86

DDR2 .............................................................................. 3-87

External Instruction Fetch ................................................ 3-88

Interrupt Vector Table (IVT) ........................................ 3-88

Fetching ISA Instructions From External Memory ......... 3-89

Instruction Packing ....................................................... 3-90

16-Bit Instruction Storage and Packing ......................... 3-90

8-Bit Instruction Storage and Packing ........................... 3-92

Mixing Instructions and Data in External Bank 0 .......... 3-93

Addressing for Various Memory Sizes ............................ 3-93

Writing Instructions to External Memory ...................... 3-94

Instruction Cache ......................................................... 3-95

Fetching VISA Instructions From External Memory .......... 3-98

External Port DMA .................................................................. 3-100

External Port DMA Parameter Registers .............................. 3-100

Operating Modes ................................................................ 3-102

Internal DMA Addressing ............................................... 3-102

Standard DMA ............................................................... 3-103

Circular Buffered DMA .................................................. 3-103

Chained DMA Mode .......................................................... 3-104

Changing DMA Direction on the Fly .............................. 3-104

Scatter/Gather DMA ........................................................... 3-106

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External Address Calculation ........................................... 3-106

Delay Line DMA ................................................................. 3-111

External Address Calculation for Reads ............................ 3-112

Interrupts ................................................................................ 3-114

Access Completion .......................................................... 3-115

Internal Transfer Completion .......................................... 3-115

Interrupt Dependency on DMA Mode ............................ 3-115

External Port Throughput ......................................................... 3-116

AMI Data Throughput ........................................................ 3-117

SDRAM Throughput .......................................................... 3-117

Throughput Conditional Instructions .............................. 3-117

DDR2 Throughput ............................................................. 3-118

DMA Throughput .......................................................... 3-118

Core Throughput ............................................................ 3-118

External Instruction Fetch Throughput ................................ 3-119

Effect Latency ........................................................................... 3-120

Write Effect Latency ............................................................ 3-121

Programming Models ................................................................ 3-121

External Port ....................................................................... 3-121

DMA .................................................................................. 3-121

Standard DMA .............................................................. 3-121

Chained DMA ................................................................ 3-122

Delay Line DMA ............................................................ 3-123

Disabling and Re-enabling DMA ..................................... 3-124

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Contents

Additional Information ................................................... 3-124

AMI Initialization .......................................................... 3-125

SDRAM Controller ............................................................. 3-126

Power-Up Sequence ........................................................ 3-126

Output Clock Generator Programming Model ................ 3-127

Self-Refresh Mode .......................................................... 3-127

Changing the VCO Clock During Runtime ................... 3-128

DDR2 Controller ............................................................... 3-129

Power-Up Sequence ........................................................ 3-129

Frequency Change in Precharge Power-Down Mode ........ 3-130

External Instruction Fetch ................................................... 3-131

AMI Configuration ........................................................ 3-132

SDRAM Configuration .................................................. 3-132

External Memory Access Restrictions ................................... 3-132

LINK PORTS—ADSP-2146X

Features ........................................................................................ 4-2



Clocking ...................................................................................... 4-4


Architecture ............................................................................ 4-5

Protocol .................................................................................. 4-5

Intercommunication ............................................................... 4-7

Self-Synchronization ............................................................. 4-10

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Contents

Multi-Master Conflicts .......................................................... 4-10

Example Token Passing .......................................................... 4-11

Data Transfer .............................................................................. 4-13

Link Buffers .......................................................................... 4-13

Transmit Buffer ................................................................. 4-14

Receive Buffer ................................................................... 4-14

Buffer Status ..................................................................... 4-15

Core Transfers ....................................................................... 4-15

DMA Transfers ...................................................................... 4-16

Interrupts ................................................................................... 4-16

Interrupt Sources ................................................................... 4-17

Interrupt Service ................................................................... 4-17

Access Completion ............................................................ 4-18

Internal Transfer Completion ............................................ 4-18

DMA Access .......................................................................... 4-19

Chained DMA .................................................................. 4-19

Core Access ........................................................................... 4-19

Service Request Interrupts ..................................................... 4-20

Debug Features ........................................................................... 4-21

Shadow Register .................................................................... 4-21

Buffer Hang Disable (BHD) .................................................. 4-22

Effect Latency ............................................................................. 4-22

Write Effect Latency .............................................................. 4-22

Link Port Effect Latency ........................................................ 4-22

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Contents


Changing the Link Port Clock ............................................... 4-23

Receive DMA ....................................................................... 4-24

Transmit DMA ..................................................................... 4-24

MEMORY-TO-MEMORY PORT DMA

Features ........................................................................................ 5-2


Clocking ...................................................................................... 5-2


Data Transfer Types ...................................................................... 5-3

Data Buffer ............................................................................. 5-3

DMA Transfer ........................................................................ 5-4

Interrupts ..................................................................................... 5-4

MTM Throughput ....................................................................... 5-5

Effect Latency .............................................................................. 5-5

Write Effect Latency ............................................................... 5-5

MTM Effect Latency .............................................................. 5-5

Programming Model ..................................................................... 5-5

FFT/FIR/IIR HARDWARE MODULES

FFT Accelerator ............................................................................ 6-3

Features .................................................................................. 6-4

Register Descriptions .............................................................. 6-4

Clocking ................................................................................. 6-5

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Functional Description ............................................................ 6-5

Compute Block ................................................................... 6-5

Data Memory ..................................................................... 6-6

Coefficient Memory ............................................................ 6-6

Accelerator States ................................................................ 6-6

Reset State ...................................................................... 6-6

Idle State ........................................................................ 6-7

Read State ....................................................................... 6-7

Processing State ............................................................... 6-7

Write State ...................................................................... 6-7

Internal Memory Storage ..................................................... 6-8

Small FFT N=256 ........................................................ 6-9

Operating Modes ................................................................... 6-11

Small FFT Computation (= 512 Points) .......................... 6-11

Example for FFT Size N=512 ............................................ 6-12

Vertical FFT ................................................................. 6-12

Special Product—Number of Iterations is N/128 = 4 ..... 6-12

Horizontal FFT ............................................................. 6-13

No Repeat Mode ............................................................... 6-14

Repeat Mode .................................................................... 6-14

Unpacked Data Mode ...................................................... 6-14

Inverse FFT ...................................................................... 6-15

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Contents

Data Transfer ........................................................................ 6-15

FFT Buffers ...................................................................... 6-15

DMA Transfers ................................................................. 6-15

DMA Channels and TCB Structure .............................. 6-16

Chained DMA .............................................................. 6-16

Interrupts ............................................................................. 6-17

Interrupt Sources ............................................................. 6-18

Servicing DMA Interrupts ................................................ 6-18

Servicing MAC Status Interrupts ....................................... 6-18

FFT Performance .................................................................. 6-19

Small FFT (N is = 256) ...................................................... 6-19

Vertical FFT cycles .......................................................... 6-20

Special Prod cycles ............................................................ 6-20

Horizontal FFT cycles ...................................................... 6-20

Debug Features ..................................................................... 6-20

Local Memory Access ....................................................... 6-20

Shadow Register ............................................................... 6-20

Effect Latency ....................................................................... 6-21

Write Effect Latency ......................................................... 6-21

FFT Accelerator Effect Latency ......................................... 6-21

Programming Model ............................................................. 6-21

N

Contents

N >= 512, No Repeat ........................................................ 6-24

Configure the FFT Control Register .............................. 6-24

Vertical FFT Configuration ........................................... 6-25

Special Buffer Configuration ......................................... 6-25

Horizontal FFT Configuration ...................................... 6-26

N >= 512, Repeat ............................................................. 6-26

Debug Mode ..................................................................... 6-27

Write to Local Memory ................................................. 6-27

Read from Local Memory .............................................. 6-28

FIR Accelerator ........................................................................... 6-28

Features ................................................................................. 6-28

Register Overview ................................................................. 6-29

Clocking ............................................................................... 6-29


Compute Block ................................................................. 6-31

Partial Sum Register .......................................................... 6-32

Delay Line Memory .......................................................... 6-33

Coefficient Memory .......................................................... 6-33

Prefetch Data Buffer ......................................................... 6-33

Processing Output ............................................................. 6-34

Internal Memory Storage ................................................... 6-35

Coefficients and Input Buffer Storage ............................ 6-35

Operating Modes ................................................................... 6-37

Single Rate Processing ....................................................... 6-37

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Contents

Single Iteration ............................................................. 6-37

Multi-Iteration ............................................................. 6-37

Window Processing ......................................................... 6-38

Multi Rate Processing ...................................................... 6-38

Decimation ...................................................................... 6-38

Interpolation .................................................................... 6-39

Channel Processing ........................................................... 6-40

Floating-Point Data Format .............................................. 6-42

Fixed-Point Data Format .................................................. 6-42

Data Transfer ........................................................................ 6-42

DMA Access ..................................................................... 6-42

Chain Pointer DMA ..................................................... 6-43

Interrupts ............................................................................. 6-44

Interrupt Sources .............................................................. 6-45

Debug Features ..................................................................... 6-45


Single Step Mode .............................................................. 6-46

Emulation Considerations ................................................ 6-46

Effect Latency ....................................................................... 6-46


FIR Accelerator Effect Latency .......................................... 6-46

FIR Throughput ................................................................... 6-47

Additional Information ..................................................... 6-48


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Single Channel Processing ................................................. 6-48

Multichannel Processing .................................................... 6-49

Debug Mode ..................................................................... 6-52

Write to Local Memory ................................................. 6-52

Read from Local Memory .............................................. 6-52

Single Step Mode .............................................................. 6-53

FIR Programming Example ............................................... 6-53

IIR Accelerator ............................................................................ 6-55

Features ................................................................................. 6-55

Register Overview ................................................................. 6-55

Clocking ............................................................................... 6-56


Multiply and Accumulate (MAC) Unit .............................. 6-59

Data Memory ................................................................... 6-60

Coefficient Memory .......................................................... 6-60

Internal Memory Storage ................................................... 6-60

Coefficient Memory Storage .......................................... 6-60

Operating Modes ................................................................... 6-61

Window Processing ........................................................... 6-61

40-Bit Floating-Point Mode .............................................. 6-61

Data Transfers ....................................................................... 6-62

DMA Access ..................................................................... 6-62

Chain Pointer DMA ...................................................... 6-62

Interrupts .............................................................................. 6-64

ADSP-214xx SHARC Processor Hardware Reference xxi

Contents

Interrupt Sources .............................................................. 6-64

Debug Features ..................................................................... 6-65


Single Step Mode .............................................................. 6-66

Emulation Considerations ................................................ 6-66

Effect Latency ....................................................................... 6-66


IIR Accelerator Effect Latency ........................................... 6-67

IIR Throughput .................................................................... 6-67


Writing to Local Memory ................................................. 6-69

Reading from Local Memory ............................................ 6-70

Single Step Mode .............................................................. 6-71

Programming Example ...................................................... 6-71

PULSE WIDTH MODULATION

Features ........................................................................................ 7-2


Multiplexing Scheme .............................................................. 7-4

SRU Programming ....................................................................... 7-5


Clocking ...................................................................................... 7-6


Two-Phase PWM Generator .................................................... 7-6

Switching Frequencies ......................................................... 7-6

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Contents

Duty Cycles ........................................................................ 7-7

Dead Time ....................................................................... 7-12

Output Control Unit ............................................................. 7-13

Output Enable .................................................................. 7-13

Output Polarity ................................................................. 7-13

Complementary Outputs .................................................. 7-14

Crossover .......................................................................... 7-14

Emergency Dead Time for Over Modulation .......................... 7-15

Output Control Feature Precedence ................................... 7-17

Operation Modes ........................................................................ 7-18

Waveform Modes .................................................................. 7-18

Edge-Aligned Mode .......................................................... 7-18

Center-Aligned Mode ........................................................ 7-19

PWM Timer Edge Aligned Update ........................................ 7-21

Single Update Mode .......................................................... 7-22

Double Update Mode ....................................................... 7-22

Effective Accuracy ................................................................. 7-23

Synchronization of PWM Groups ......................................... 7-24

Interrupts ................................................................................... 7-25

Debug Features ........................................................................... 7-27

Status Debug Register ............................................................ 7-27


Effect Latency ............................................................................. 7-27


ADSP-214xx SHARC Processor Hardware Reference xxiii

Contents

PWM Effect Latency ............................................................. 7-27

MEDIA LOCAL BUS

Features ........................................................................................ 8-3



Device Configuration and Status Registers ............................... 8-4

Channel Configuration Registers ............................................. 8-4

Clocking ...................................................................................... 8-5


Operating Modes .......................................................................... 8-7

Streaming Channel Frame Synchronization .............................. 8-7

Big-Endian and Little-Endian Mode ....................................... 8-8

Data Transfer ............................................................................... 8-8

Core Driven Data Transfer ...................................................... 8-8

I/O Local Channel Buffering .............................................. 8-8

DMA .................................................................................... 8-10

Ping-Pong DMA ............................................................... 8-11

Circular Buffer DMA ....................................................... 8-13

Interrupts ................................................................................... 8-14

Interrupt Source .................................................................... 8-15

Servicing Interrupts ............................................................... 8-15

Debug Features ........................................................................... 8-15

Loop-Back Test Mode ........................................................... 8-16


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Contents

I/O Interrupt Mode ............................................................... 8-16

DMA Modes ......................................................................... 8-17

DIGITAL APPLICATION/DIGITAL PERIPHERAL INTERFACES

Features ........................................................................................ 9-2


Clocking ....................................................................................... 9-4


DAI/DPI Signal Naming Conventions .................................... 9-7

I/O Pin Buffers ....................................................................... 9-7

Pin Buffers as Signal Output ............................................... 9-8

Pin Buffers as Signal Input ................................................ 9-10

Pin Buffers as Open Drain ................................................ 9-11

DAI/DPI Pin Buffer Status ................................................ 9-11

Unused DAI/DPI Pins ...................................................... 9-12

Miscellaneous Buffers ............................................................ 9-12

DAI/DPI Peripherals ............................................................. 9-14

Output Signals With Pin Buffer Enable Control ................ 9-14

Output Signals Without Pin Buffer Enable Control ........... 9-16

Signal Routing Units (SRUs) ................................................. 9-16

Signal Routing Matrix by Groups ...................................... 9-16

DAI/DPI Group Routing .................................................. 9-18

Rules for SRU Connections ............................................... 9-20

Making SRU Connections ................................................. 9-20

ADSP-214xx SHARC Processor Hardware Reference xxv

Contents

DAI Routing Capabilities ................................................ 9-24

DPI Routing Capabilities .................................................. 9-25

Pin Buffer Input ........................................................... 9-26

Pin Buffer Enable ......................................................... 9-26

Miscellaneous Signals .................................................... 9-27

DAI Default Routing .................................................................. 9-28

DPI Default Routing .................................................................. 9-31

Interrupts ................................................................................... 9-32

System Versus Exception Interrupts ....................................... 9-32


DAI Interrupt Channels ........................................................ 9-33

DAI Interrupt Priorities ........................................................ 9-34

DPI Interrupt Channels ........................................................ 9-34

DPI Interrupt Priorities ......................................................... 9-34

DAI Miscellaneous Interrupts ............................................... 9-35

DPI Miscellaneous Interrupts ............................................... 9-35

DAI/DPI Interrupt Mask Events ........................................... 9-36

DAI Interrupt Acknowledge .................................................. 9-38

DPI Interrupt Acknowledge .................................................. 9-39

Core versus DAI/DPI Interrupts ............................................ 9-39

Debug Features ........................................................................... 9-40

DAI Shadow Registers ........................................................... 9-40

DPI Shadow Registers ........................................................... 9-40

Loop Back Routing ............................................................... 9-40

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Contents

Effect Latency ............................................................................. 9-42


Signal Routing Unit Effect Latency ........................................ 9-42


DAI Example System ............................................................. 9-43

SERIAL PORTS

Features ...................................................................................... 10-2

Pin Descriptions ......................................................................... 10-4

SRU Programming ...................................................................... 10-5

SRU SPORT Receive Master ................................................. 10-6

SRU SPORT Signal Integrity ................................................. 10-6

Register Overview ....................................................................... 10-7

Clocking ..................................................................................... 10-8

Master Clock ......................................................................... 10-8

Master Frame Sync ................................................................ 10-9

Slave Mode .......................................................................... 10-10

Functional Description ............................................................. 10-10

Architecture ........................................................................ 10-11

Data Types and Companding ............................................... 10-12

Companding the Data Stream ......................................... 10-13

Transmit Path ................................................................. 10-14

Receive Path ................................................................... 10-15

Frame Sync ......................................................................... 10-16

Sampling Edge ................................................................ 10-16

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Frame Sync and Data Sampling ....................................... 10-16

Serial Word Length ......................................................... 10-18

Internal Versus External Frame Syncs ............................. 10-18

External Frame Sync Sampling .................................... 10-19

Logic Level Frame Syncs ............................................. 10-20

Data-Independent Frame Sync ................................... 10-20

Operation Modes ..................................................................... 10-21

Mode Selection ................................................................... 10-23

Channel Order First ....................................................... 10-24

Standard Serial Mode .......................................................... 10-25

Timing Control Bits ....................................................... 10-25

Clocking Options .......................................................... 10-26

Frame Sync Options ....................................................... 10-26

Framed Versus Unframed Frame Syncs ............................ 10-26

Early Versus Late Frame Syncs ........................................ 10-27

Left-Justified Mode ............................................................. 10-28

Master Serial Clock and Frame Sync Rates ...................... 10-29


I2S Mode ............................................................................ 10-30

Master Serial Clock and Frame Sync Rates ...................... 10-30


Multichannel Mode ............................................................ 10-31

Clocking Options ........................................................... 10-32

Frame Sync Options ....................................................... 10-32

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Frame Sync Delay (MFD) ............................................... 10-33

Transmit Data Valid Signal .............................................. 10-33

Transmit Data Valid Output ........................................ 10-34

Timing Control Bits ........................................................ 10-35

Number of Channels (NCH) ........................................... 10-35

Active Channel Selection Registers .................................. 10-36

Companding Selection .................................................... 10-36

Companding Limitations (ADSP-2146x) ......................... 10-37

Packed Mode ....................................................................... 10-37

Clocking Options ........................................................... 10-38

Frame Sync Options ........................................................ 10-38

Timing Control Bits ........................................................ 10-39

Data Transfers ........................................................................... 10-39

Data Buffers ........................................................................ 10-40

Transmit Buffers (TXSPxA/B) ......................................... 10-40

Receive Buffers (RXSPxA/B) ........................................... 10-41

Buffer Status .................................................................. 10-41

Data Buffer Packing ............................................................ 10-42

Core Transfers ..................................................................... 10-43

Single Word Transfers ..................................................... 10-43

Frame Sync Generation ................................................... 10-44

Internal Memory DMA Transfers ......................................... 10-44

External Memory DMA Transfers ........................................ 10-45

Standard DMA .................................................................... 10-46

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DMA Chaining ................................................................... 10-47

DMA Chain Insertion Mode ............................................... 10-48

Frame Sync Generation ................................................... 10-48

Interrupts ................................................................................. 10-49

Internal Transfer Completion .............................................. 10-50

Shared Channels ................................................................. 10-50

Error Detection ................................................................... 10-51

Error Status ........................................................................ 10-53

Debug Features ......................................................................... 10-53

SPORT Loopback ............................................................... 10-54

LoopBack Routing .......................................................... 10-54

Buffer Hang Disable (BHD) ................................................ 10-54

Effect Latency .......................................................................... 10-54

Write Effect Latency ........................................................... 10-55

SPORT Effect Latency ........................................................ 10-55

Programming Model ................................................................. 10-55

Setting Up and Starting DMA Master Mode ........................ 10-55

Setting Up and Starting Chained DMA ............................... 10-56

Enter DMA Chain Insertion Mode ...................................... 10-56

Setting Up and Starting Multichannel Mode ........................ 10-57

Multichannel Mode Backward Compatibility .................. 10-58

Programming Packed Mode ................................................. 10-59

Additional Information for External Frame Sync Operation ...................................................... 10-59

Companding As a Function ................................................. 10-60

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INPUT DATA PORT

Features ...................................................................................... 11-2


SRU Programming ...................................................................... 11-5


Clocking ..................................................................................... 11-6


Operating Modes ........................................................................ 11-8

PDAP Port Selection ............................................................. 11-9

Data Hold ............................................................................. 11-9

PDAP Data Masking ........................................................... 11-10

PDAP Data Packing ............................................................ 11-10

No Packing ..................................................................... 11-10

Packing by 2 ................................................................... 11-11

Packing by 3 ................................................................... 11-12

Packing by 4 ................................................................... 11-13

Data Transfer ............................................................................ 11-14

Data Buffer ......................................................................... 11-14

Core Transfers .................................................................... 11-15

SIP Data Buffer Format ................................................... 11-16

PDAP Data Buffer Format .............................................. 11-18

DMA Transfers .................................................................... 11-19

Data Buffer Format for DMA .......................................... 11-19

DMA Channel Priority ................................................... 11-20

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Standard DMA ............................................................... 11-20

Ping-Pong DMA ............................................................. 11-21

Multichannel DMA Operation ....................................... 11-21

Multichannel FIFO Status .............................................. 11-22

Interrupts ................................................................................. 11-23

Interrupt Acknowledge ........................................................ 11-23

Threshold Interrupts ........................................................... 11-23

DMA Interrupts .................................................................. 11-24

FIFO Overflow Interrupts ................................................... 11-24

Debug Features ......................................................................... 11-25

Status register Debug .......................................................... 11-25

Buffer Hang Disable ........................................................... 11-25

Shadow Registers ................................................................ 11-25

Core FIFO Write ................................................................ 11-26

Effect Latency .......................................................................... 11-26


IDP Effect Latency .............................................................. 11-26


Setting Miscellaneous Bits ................................................... 11-27

Starting Core Interrupt-Driven Transfer .............................. 11-27

Additional Notes ............................................................ 11-28

Starting A Standard DMA Transfer ...................................... 11-29

Starting a Ping-Pong DMA Transfer .................................... 11-30

Servicing Interrupts for DMA ............................................. 11-31

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ASYNCHRONOUS SAMPLE RATE CONVERTER

Features ...................................................................................... 12-2


SRU Programming ...................................................................... 12-3


Clocking ..................................................................................... 12-5


Serial Data Ports .................................................................... 12-9

Operating Modes ........................................................................ 12-9

TDM Daisy Chain Mode .................................................... 12-10

TDM Input Daisy Chain ................................................ 12-11

TDM Output Daisy Chain ............................................. 12-11

Bypass Mode ....................................................................... 12-12

Matched-Phase Mode (ADSP-21488) .................................. 12-12

Data Format Matched-Phase Mode .................................. 12-14

Group Delay ................................................................... 12-14

Decimation Rate ................................................................. 12-15

Muting Modes ..................................................................... 12-15

Soft Mute ....................................................................... 12-15

Hard Mute ...................................................................... 12-16

Auto Mute ...................................................................... 12-16

Interrupts ................................................................................. 12-16

Debug Features ......................................................................... 12-17

Effect Latency ........................................................................... 12-17

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SRC Effect Latency ............................................................. 12-18

SONY/PHILIPS DIGITAL INTERFACE

Features ...................................................................................... 13-2


SRU Programming ..................................................................... 13-4


Clocking .................................................................................... 13-7

S/PDIF Transmitter .................................................................... 13-7


Input Data Format ........................................................... 13-9

Operating Modes ................................................................ 13-11

Full Serial Mode ............................................................. 13-11

Standalone Mode ............................................................ 13-11

Data Output Mode ......................................................... 13-12

S/PDIF Receiver ....................................................................... 13-13

Functional Description ....................................................... 13-13

Clock Recovery .............................................................. 13-15

Output Data Format ...................................................... 13-15

Channel Status ............................................................... 13-16

Operating Modes ................................................................ 13-16

Compressed or Non-linear Audio Data ............................ 13-16

Emphasized Audio Data .............................................. 13-17

Single-Channel Double-Frequency Mode .................... 13-18

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Clock Recovery Modes .................................................... 13-18

Digital On-Chip PLL .................................................. 13-18

External Analog PLL ................................................... 13-19

Interrupts ................................................................................. 13-19

Transmitter Interrupt ........................................................... 13-19

Receiver Interrupts .............................................................. 13-20

Receiver Error Interrupts ..................................................... 13-20

Debug Features ......................................................................... 13-21

Loop Back Routing .............................................................. 13-21

Effect Latency ........................................................................... 13-21



Programming the Transmitter .............................................. 13-21

Programming the Receiver ................................................... 13-22

Interrupted Data Streams on the Receiver ............................ 13-23

PRECISION CLOCK GENERATOR

Features ...................................................................................... 14-2


SRU Programming ...................................................................... 14-4


Clocking ..................................................................................... 14-5


Serial Clock ........................................................................... 14-6

Frame Sync ........................................................................... 14-7

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Frame Sync Output .......................................................... 14-7

Divider Mode Selection .................................................... 14-8

Phase Shift ....................................................................... 14-8

Pulse Width ..................................................................... 14-9

Default Pulse Width ....................................................... 14-10

Timing Example for I2S Mode ........................................ 14-11

Operating Modes ...................................................................... 14-11

Normal Mode ..................................................................... 14-12

Bypass Mode ....................................................................... 14-13

One-Shot Mode .................................................................. 14-13

External Event Trigger ......................................................... 14-14

External Event Trigger Delay .......................................... 14-15

Audio System Example ........................................................ 14-16

Clock Configuration Examples ............................................ 14-18

Effect Latency .......................................................................... 14-19


PCG Effect Latency ............................................................ 14-19


Frame Sync Phase Setting .................................................... 14-20

External Event Trigger ......................................................... 14-20

Debug Features ......................................................................... 14-21

SERIAL PERIPHERAL INTERFACE PORTS

Features ...................................................................................... 15-2


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SRU Programming ...................................................................... 15-4


Clocking ..................................................................................... 15-6

Choosing the Pin Enable for the SPI Clock ........................... 15-7


SPI Transaction ..................................................................... 15-9

Single Master Systems .......................................................... 15-10

Multi Master Systems .......................................................... 15-11

Operating Modes ...................................................................... 15-12

Transfer Initiate Mode ......................................................... 15-13

SPI Modes ........................................................................... 15-14

Slave Select Outputs ............................................................ 15-15

Variable Frame Delay for Slave ............................................. 15-17

Data Transfers ........................................................................... 15-18

Buffers ................................................................................ 15-18

Core Buffer Status ........................................................... 15-19

DMA Buffer Status ......................................................... 15-20

Core Transfers ..................................................................... 15-20

Backward Compatibility .................................................. 15-21

DMA Transfers ...................................... 15-21

DMA Chaining ............................................................... 15-23

DMA Transfer Count ...................................................... 15-23

Full Duplex Operation .................................................... 15-24

Interrupts ................................................................................. 15-24

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Interrupt Sources ................................................................ 15-24

Multi Master Error .............................................................. 15-26

Debug Features ......................................................................... 15-27

Shadow Receive Buffers ....................................................... 15-27

Internal Loopback Mode ..................................................... 15-28

Loop Back Routing ......................................................... 15-28

Effect Latency .......................................................................... 15-28


SPI Effect Latency ............................................................... 15-29


Changing SPI Configuration ............................................... 15-29

Master Mode Transfers ........................................................ 15-30

Core Master Transfers ..................................................... 15-31

DMA Master Transfers ................................................... 15-31

Slave Mode Transfers ........................................................... 15-32

Core Slave Transfers ........................................................ 15-32

DMA Slave Transfers ...................................................... 15-33

Chained DMA Transfers ..................................................... 15-33

Stopping SPI Transfers ........................................................ 15-33

Switching From Transmit to a New DMA ............................ 15-34

Switching From Receive to a New DMA .............................. 15-35

DMA Error Interrupts ......................................................... 15-37

Multi-Master Transfers ................................................... 15-38

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PERIPHERAL TIMERS

Features ...................................................................................... 16-2


SRU Programming ...................................................................... 16-3


Read-Modify-Write ............................................................... 16-5

Clocking ..................................................................................... 16-5


Operating Modes ........................................................................ 16-7

Pulse Width Modulation Mode (PWM_OUT) ....................... 16-8

PWM Waveform Generation ........................................... 16-10

Single-Pulse Generation .................................................. 16-11

Pulse Mode ..................................................................... 16-12

Pulse Width Count and Capture Mode (WDTH_CAP) ....... 16-12

External Event Watchdog Mode (EXT_CLK) ....................... 16-15

Interrupts ................................................................................. 16-17

Sources ................................................................................ 16-17

Watchdog Functionality ....................................................... 16-19

Debug Features ......................................................................... 16-19

Loopback Routing ............................................................... 16-19

Loopback Routing ............................................................... 16-19

Effect Latency ........................................................................... 16-19


Peripheral Timers Effect Latency .......................................... 16-20

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PWM Out Mode ................................................................ 16-21

WDTH_CAP Mode ........................................................... 16-22

EXT_CLK Mode ................................................................ 16-23

SHIFT REGISTER – ADSP-2147X

Features ...................................................................................... 17-2


SRU Programming ..................................................................... 17-3


Clocking .................................................................................... 17-4


Operating Modes ........................................................................ 17-6

Serial Data Output ................................................................ 17-6

Parallel Data Output ............................................................. 17-7

Effect Latency ............................................................................ 17-8

Write Effect Latency ............................................................. 17-8

Shift Register Effect Latency .................................................. 17-8


REAL-TIME CLOCK—ADSP-2147X

Features ................................................................................ 18-2


Clocking .................................................................................... 18-3


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Interrupts ................................................................................. 18-10

WATCHDOG TIMER – ADSP-2147X

Features ...................................................................................... 19-2



Clocking ..................................................................................... 19-4


Operating Mode ......................................................................... 19-6

Trip Count ............................................................................ 19-6

Debug Features ........................................................................... 19-7


Effect Latency ............................................................................. 19-7


Watchdog Timers Effect Latency ............................................ 19-7


UART PORT CONTROLLER

Features ...................................................................................... 20-2

SRU Programming ...................................................................... 20-3


Clocking ..................................................................................... 20-4


Serial Communication ........................................................... 20-7

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Contents

Operating Modes ........................................................................ 20-8

Data Packing ........................................................................ 20-8

9-Bit Transmission Mode ...................................................... 20-8

Packed Mode .................................................................... 20-9

Data Transfer Types .................................................................. 20-10

Data Buffers ....................................................................... 20-10

Transmit Holding Registers (UARTTHR) ....................... 20-10

Receive Buffer Registers (UARTRBR) ............................. 20-11

Core Transfers ..................................................................... 20-12

DMA Transfers ................................................................... 20-13

DMA Chaining .............................................................. 20-14

Interrupts ................................................................................. 20-14

Interrupt Routing ............................................................... 20-15

DPI ................................................................................ 20-15

UART ............................................................................ 20-16

DMA Interrupts .................................................................. 20-16

Core Interrupts .................................

Documents

ADSP-214xx SHARC Processor Hardware Reference · 2017-10-20 · a ADSP-214xx SHARC® Processor Hardware Reference Includes ADSP-2146x, ADSP-2147x, ADSP-2148x Product Families Revision