Adc 12034

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A D C 12 03 0 , A D C 12 03 2 , A D C 1 20 34A D C 12 03 8 , A D C 12 H 0 3 0 , A D C 12 H 03 2

A D C 12 H 03 4 , A D C 12H 03 8www.ti.com SNAS080J MAY 2004REVISED SEPTEMBER 2008

A D C 1 2 H 0 3 0 / A D C 1 2 H 0 3 2 / A D C 1 2 H 0 3 4 / A D C 1 2 H 0 3 8 ,AD C12 030 /AD C12 032 /AD C12 034 /AD C1 2038 Se l f -Ca l ib r a t i ng 12 -B i t P l us S i gn Se r i a l I /O A /D

Co nv er te rs w i th M U X an d Sa m p le /H o ldCheck for Samples: ADC12030, ADC12032, ADC12034, ADC12038, ADC12H030, ADC12H032, ADC12H034, ADC12H038

1FEATURES Fully tested and guaranteed with a 4.096Vreference

234 Serial I/O (MICROWIRE Compatible) 0V to 5V analog input range with single 5V 2, 4, or 8 chan differential or single-ended

power supplymultiplexer No Missing Codes over temperature Analog input sample/hold function

Power down mode APPLICATIONS Variable resolution and conversion rate

Medical instruments Programmable acquisition time

Process control systems Variable digital output word length and format

Test equipment

No zero or full scale adjustment required

DESCRIPTIONNOTE: Some of these devices may be obsolete and are described and shown here for reference only.See our web site for product availability.

The ADC12030, and ADC12H030 families are 12-bit plus sign successive approximation Analog-to-DigitalConverters with serial I/O and configurable input multiplexers. The ADC12034/ADC12H034 andADC12038/ADC12H038 have 4 and 8 channel multiplexers, respectively. The differential multiplexer outputs andADC inputs are available on the MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2 pins. The ADC12030/ADC12H030has a two channel multiplexer with the multiplexer outputs and ADC inputs internally connected. The ADC12030family is tested with a 5 MHz clock, while the ADC12H030 family is tested with an 8 MHz clock. On request,these ADCs go through a self calibration process that adjusts linearity, zero and full-scale errors to less than 1LSB each.

The analog inputs can be configured to operate in various combinations of single-ended, differential, or pseudo-differential modes. A fully differential unipolar analog input range (0V to +5V) can be accommodated with a single+5V supply. In the differential modes, valid outputs are obtained even when the negative inputs are greater thanthe positive because of the 12-bit plus sign output data format.

The serial I/O is configured to comply with NSC MICROWIRE. For voltage references see the LM4040, LM4050or LM4041.

Table 1. Key Specifications

VALUE UNIT

12-bit plus sign Resolution 12-bit plus sign

conversion time

ADC12H30 family 5.5 s (max)

12-bit plus sign ADC12030 family 8.8 s (max)throughput time

ADC12H30 family 8.6 s (max)

ADC12030 family 14 s (max)

Integral Linearity Error 1 LSB (max)

Single Supply 5V 10%1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2TRI-STATE is a registered trademark of Texas Instruments.3TRI-STATE is a registered trademark of National Semiconductor Corporation.4All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright 20042008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does not

necessarily include testing of all parameters.
http://www.ti.com/product/adc12030?qgpn=adc12030http://www.ti.com/product/adc12032?qgpn=adc12032http://www.ti.com/product/adc12034?qgpn=adc12034http://www.ti.com/product/adc12038?qgpn=adc12038http://www.ti.com/product/adc12h030?qgpn=adc12h030http://www.ti.com/product/adc12h032?qgpn=adc12h032http://www.ti.com/product/adc12h034?qgpn=adc12h034http://www.ti.com/product/adc12h038?qgpn=adc12h038http://www.ti.com/http://www.ti.com/product/adc12030#sampleshttp://www.ti.com/product/adc12032#sampleshttp://www.ti.com/product/adc12034#sampleshttp://www.ti.com/product/adc12038#sampleshttp://www.ti.com/product/adc12h030#sampleshttp://www.ti.com/product/adc12h032#sampleshttp://www.ti.com/product/adc12h034#sampleshttp://www.ti.com/product/adc12h038#sampleshttp://www.ti.com/product/adc12h038#sampleshttp://www.ti.com/product/adc12h034#sampleshttp://www.ti.com/product/adc12h032#sampleshttp://www.ti.com/product/adc12h030#sampleshttp://www.ti.com/product/adc12038#sampleshttp://www.ti.com/product/adc12034#sampleshttp://www.ti.com/product/adc12032#sampleshttp://www.ti.com/product/adc12030#sampleshttp://www.ti.com/http://www.ti.com/product/adc12h038?qgpn=adc12h038http://www.ti.com/product/adc12h034?qgpn=adc12h034http://www.ti.com/product/adc12h032?qgpn=adc12h032http://www.ti.com/product/adc12h030?qgpn=adc12h030http://www.ti.com/product/adc12038?qgpn=adc12038http://www.ti.com/product/adc12034?qgpn=adc12034http://www.ti.com/product/adc12032?qgpn=adc12032http://www.ti.com/product/adc12030?qgpn=adc12030

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A D C 12 03 0 , A D C 12 03 2 , A D C 12 03 4A D C 12 03 8 , A D C 12H 03 0 , A D C 1 2 H 03 2A D C 12H 03 4 , A D C 12H 03 8SNAS080J MAY 2004REVISED SEPTEMBER 2008 www.ti.com

Table 1. Key Specifications (continued)

VALUE UNIT

Power consumption 33 mW (max)

Power down 100 W (typ)

ADC12038 Simplified Block Diagram

Connection Diagram

Figure 1. 16-Pin Wide BodySO Packages

Top View

2 Submit Documentation Feedback Copyright 20042008, Texas Instruments Incorporated

Product Folder Links: ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034ADC12H038
http://www.ti.com/product/adc12030?qgpn=adc12030http://www.ti.com/product/adc12032?qgpn=adc12032http://www.ti.com/product/adc12034?qgpn=adc12034http://www.ti.com/product/adc12038?qgpn=adc12038http://www.ti.com/product/adc12h030?qgpn=adc12h030http://www.ti.com/product/adc12h032?qgpn=adc12h032http://www.ti.com/product/adc12h034?qgpn=adc12h034http://www.ti.com/product/adc12h038?qgpn=adc12h038http://www.ti.com/http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SNAS080J&partnum=ADC12030http://www.ti.com/product/adc12030?qgpn=adc12030http://www.ti.com/product/adc12032?qgpn=adc12032http://www.ti.com/product/adc12034?qgpn=adc12034http://www.ti.com/product/adc12038?qgpn=adc12038http://www.ti.com/product/adc12h030?qgpn=adc12h030http://www.ti.com/product/adc12h032?qgpn=adc12h032http://www.ti.com/product/adc12h034?qgpn=adc12h034http://www.ti.com/product/adc12h038?qgpn=adc12h038http://www.ti.com/product/adc12h038?qgpn=adc12h038http://www.ti.com/product/adc12h034?qgpn=adc12h034http://www.ti.com/product/adc12h032?qgpn=adc12h032http://www.ti.com/product/adc12h030?qgpn=adc12h030http://www.ti.com/product/adc12038?qgpn=adc12038http://www.ti.com/product/adc12034?qgpn=adc12034http://www.ti.com/product/adc12032?qgpn=adc12032http://www.ti.com/product/adc12030?qgpn=adc12030http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SNAS080J&partnum=ADC12030http://www.ti.com/http://www.ti.com/product/adc12h038?qgpn=adc12h038http://www.ti.com/product/adc12h034?qgpn=adc12h034http://www.ti.com/product/adc12h032?qgpn=adc12h032http://www.ti.com/product/adc12h030?qgpn=adc12h030http://www.ti.com/product/adc12038?qgpn=adc12038http://www.ti.com/product/adc12034?qgpn=adc12034http://www.ti.com/product/adc12032?qgpn=adc12032http://www.ti.com/product/adc12030?qgpn=adc12030

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Top View

Figure 3. 24-Pin Wide BodySO, DIP, SSOP-EIAJ Packages

Top View


Top View

Copyright 20042008, Texas Instruments Incorporated Submit Documentation Feedback 3


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Pin Functions

Pin Descriptions

Pin Name Pin Description

Analog Inputs to the MUX (multiplexer). A channel input is selected by the address information at the DI pin, whichis loaded on the rising edge of SCLK into the address register (See Table 3 Table 4 Table 5). The voltage applied

CH0 thru CH7to these inputs should not exceed VA+ or go below VA- or below GND. Exceeding this range on an unselectedchannel may corrupt the reading of a selected channel.

COM Analog input pin that is used as a pseudo ground when the analog multiplexer is single-ended.

MUXOUT1 Multiplexer Output pins. If the multiplexer is used, these pins should be connected to the A/DIN pins, directly orMUXOUT2 through an amplifier and/of filter.

Converter Input pins. MUXOUT1 is usually tied to A/DIN1. MUXOUT2 is usually tied to A/DIN2. If external circuitryA/DIN1

is placed between MUXOUT1 and A/DIN1, or MUXOUT2 and A/DIN2, it may be necessary to protect these pinsA/DIN2

against voltage overload.. The voltage at these pins should not exceed V A+ or go below AGND (see Figure 29).

Data Output pin. This pin is an active push/pull output when CS is low. When CS is high, this output is TRI-STATE. The conversion result (D0D12) and converter status data are clocked out by the falling edge of SCLK on

DOthis pin. The word length and format of this result can vary (see Table 2). The word length and format are controlledby the data shifted into the multiplexer address and mode select register (see Table 6).

Serial Data input pin. The data applied to this pin is shifted by the rising edge of SCLK into the multiplexer addressDI and mode select register. Table 3 through Table 6 show the assignment of the multiplexer address and the mode

select data.

This pin is an active push/pull output which indicates the status of the ADC12030/2/4/8. A logic low on this pinEOC indicates that the ADC is busy with a conversion, Auto Calibration, Auto Zero or power down cycle. The rising edge

of EOC signals the end of one of these cycles.

A logic low is required at this pin to program any mode or to change the ADC's configuration as listed in ModeProgramming Table 6. When this pin is high, the ADC is placed in the read data only mode. While in the read dataonly mode, bringing CS low and pulsing SCLK will only clock out the data stored in the ADCs output shift register.

CONVThe data on DI will be neglected. A new conversion will not be started and the ADC will remain in the mode and/orconfiguration previously programmed. Read data only cannot be performed while a conversion, Auto Cal or AutoZero are in progress.

Chip Select input pin. When a logic low is applied to this pin, the rising edge of SCLK shifts the data on DI into theaddress register. This low also brings DO out of TRI-STATE. With CS low the falling edge of SCLK shifts the dataresulting from the previous ADC conversion out at the DO output, with the exception of the first bit of data. WhenCS is low continuously, the first bit of the data is clocked out on the rising edge of EOC (end of conversion). WhenCS is toggled the falling edge of CS always clocks out the first bit of data. CS should be brought low while SCLK islow. The falling edge of CS interrupts a conversion in progress and starts the sequence for a new conversion.

CS When CS is brought back low during a conversion, that conversion is prematurely terminated. The data in the

output latches may be corrupted. Therefore, when CS is brought low during a conversion in progress, the dataoutput at that time should be ignored. CS may also be left continuously low. In this case it is imperative that thecorrect number of SCLK pulses be applied to the ADC in order to remain synchronous. After the ADC supply poweris applied the device expects to see 13 clock pulses for each I/O sequence. The number of clock pulses the ADCexpects is the same as the digital output word length. This word length can be modified by the data shifted in on theDO pin. Table 6 details the data required.

Data Output Ready pin. This pin is an active push/pull output which is low when the conversion result is beingDOR

shifted out and goes high to signal that all the data has been shifted out.

Serial Data Clock input. The clock applied to this input controls the rate at which the serial data exchange occurs.The rising edge loads the information on the DI pin into the multiplexer address and mode select shift register. Thisaddress controls which channel of the analog input multiplexer (MUX) is selected and the mode of operation for theADC. With CS low the falling edge of SCLK shifts the data resulting from the previous ADC conversion out on DO,

SCLKwith the exception of the first bit of data. When CS is low continuously, the first bit of the data is clocked out on therising edge of EOC (end of conversion). When CS is toggled the falling edge of CS always clocks out the first bit ofdata. CS should be brought low when SCLK is low. The rise and fall times of the clock edges should not exceed1 s.

Conversion Clock input. The clock applied to this input controls the successive approximation conversion timeCCLK

interval and the acquisition time. The rise and fall times of the clock edges should not exceed 1 s.

Positive analog voltage reference input. In order to maintain accuracy, the voltage range of VREF (VREF = VREF+ VREF+ VREF) is 1 VDC to 5.0 VDC and the voltage at VREF+ cannot exceed VA+. See Figure 28 for recommended

bypassing.

The negative analog voltage reference input. In order to maintain accuracy, the voltage at this pin must not goVREF- below GND or exceed VA+. (See Figure 28).

Power Down pin. When PD is high the ADC is powered down; when PD is low the ADC is powered up, or active.PD

The ADC takes a maximum of 250 s to power up after the command is given.



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Pin Descriptions (continued)

Pin Name Pin Description

These are the analog and digital power supply pins. V A+ and VD

+ are not connected together on the chip. TheseVA

+

pins should be tied to the same supply voltage and bypassed separately (see Figure 28). The operating voltageVD

+

range of VA+ and VD+ is 4.5 VDC to 5.5 VDC.

DGND The digital ground pin (see Figure 28).

AGND The analog ground pin (see Figure 28).

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings (1) (2)

Positive Supply Voltage (V+ = VA+ = VD+) 6.5V

Voltage at Inputs andexcept CH0CH7 and COM 0.3V to (V+ +0.3V)

Outputs

Voltage at AnalogCH0CH7 and COM GND 5V to (V+ +5V)

Inputs

|VA+ VD+| 300 mV

Input Current at Any Pin (3) 30 mA

Package Input Current (3) 120 mA

Package DissipationTA = 25C

(4) 500 mWat

ESD Susceptibility (5) Human Body Model 1500V

N Packages (10 seconds) 260C

Vapor Phase (60 seconds) 215CSoldering Information

SO Package (6): Infrared (15 seconds) 220C

Storage Temperature 65C to +150C

(1) All voltages are measured with respect to GND, unless otherwise specified.(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, seethe Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristicsmay degrade when the device is not operated under the listed test conditions.

(3) When the input voltage (VIN) at any pin exceeds the power supplies (V IN < GND or VIN > VA+ or VD+), the current at that pin should belimited to 30 mA. The 120 mA maximum package input current rating limits the number of pins that can safely exceed the powersupplies with an input current of 30 mA to four.

(4) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, JA and the ambient temperature,TA. The maximum allowable power dissipation at any temperature is P D = (TJmax TA)/JA or the number given in the AbsoluteMaximum Ratings, whichever is lower.

(5) The human body model is a 100 pF capacitor discharged through a 1.5 k resistor into each pin.(6) See AN450 Surface Mounting Methods and Their Effect on Product Reliability or the section titled Surface Mount found in any post

1986 National Semiconductor Linear Data Book for other methods of soldering surface mount devices.

Operating Ratings (1) (2)

Operating Temperature Range TMIN TA TMAX40C TA +85C

Supply Voltage (V+ = VA+ = VD+) +4.5V to +5.5V

|VA

+ VD

+| 100 mV

VREF+ 0V to VA+

VREF 0V to (VREF+ 1V)

VREF (VREF+ VREF) 1V to VA+

VREF Common Mode Voltage Range[(VREF+) (VREF)] / 2 0.1 VA+ to 0.6 VA+

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions forwhich the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, seethe Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristicsmay degrade when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND, unless otherwise specified.



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Operating Ratings (1) (2) (continued)A/DIN1, A/DIN2, MUXOUT1 and MUXOUT2 Voltage Range 0V to VA+

IN Common Mode Voltage Range[(VIN+) (VIN)] / 2 0V to VA+

Package Thermal Resistance

Part Number Thermal Resistance (JA)

ADC12(H)030CIWM 70C/W

ADC12032CIWM 64C/W

ADC12034CIN 42C/W

ADC12034CIWM 57C/W

ADC12H034CIMSA 97C/W

ADC12(H)038CIWM 50C/W

NOTE: Some of these devices may be obsolete or on Lifetime Buy status. Check our web site for productavailability.



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Converter Electrical Characteristics

The following specifications apply for V+ = VA+ = VD+ = +5.0 VDC, VREF+ = +4.096 VDC, VREF = 0 VDC, 12-bit + sign

conversion mode, fCK = fSK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, fCK = fSK = 5 MHz for

the ADC12030, ADC12032, ADC12034 and ADC12038, RS = 25, source impedance for VREF+ and VREF 25, fully-

differential input with fixed 2.048V common-mode voltage, and 10(t CK) acquisition time unless otherwise specified. Boldface

limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25C.(1) (2) (3)

Typical Limits UnitsSymbol Parameter Conditions (4) (5) (Limits)

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 12 + sign Bits (min)

ILE Integral Linearity Error After Auto Cal (6) (7) 1/2 1 LSB (max)

DNL Differential Non-Linearity After Auto Cal 1 LSB (max)

Posit ive Ful l-Scale Error After Auto Cal (6) (7) 1/2 3.0 LSB (max)

Negative Full-Scale Error After Auto Cal (6) (7) 1/2 3.0 LSB (max)

After Auto Cal (8) (7)Offset Error 1/2 2 LSB (max)

VIN(+) = VIN () = 2.048V

DC Common Mode Error After Auto Cal (9) 2 3.5 LSB (max)

TUE Total Unadjusted Error After Auto Cal (6) (10) (11) 1 LSB

Resolution with No Missing Codes 8-bit + sign mode 8 + sign Bits (min)INL Integral Linearity Error 8-bit + sign mode (6) 1/2 LSB (max)

DNL Dif ferential Non-Li nearity 8-bit + si gn mode 3/4 LSB (max)

Positive Full-Scale Error 8-bit + sign mode (6) 1/2 LSB (max)

Negative Full-Scale Error 8-bit + sign mode (6) 1/2 LSB (max)

8-bit + sign mode, after Auto ZeroOffset Error 1/2 LSB (max)

VIN(+) = VIN() = + 2.048V(10)

8-bit + sign mode after Auto ZeroTUE Total Unadjusted Error 3/4 LSB (max)(6) (10) (11)

Multiplexer Chan-to-Chan Matching 0.05 LSB

Power Supply Sensitivity V+ = +5V 10%, VREF = +4.096V

(1) Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above VA+or 5V below GND will not damage this device. However, errors in the conversion can occur (if these diodes are forward biased by morethan 50 mV) if the input voltage magnitude of selected or unselected analog input go above V A+ or below GND by more than 50 mV. Asan example, if VA+ is 4.5 VDC, full-scale input voltage must be 4.55 VDC to ensure accurate conversions.

(2) To guarantee accuracy, it is required that the VA+ and VD+ be connected together to the same power supply with separate bypasscapacitors at each V+ pin.

(3) With the test condition for VREF (VREF+ VREF) given as +4.096V, the 12-bit LSB is 1.0 mV and the 8-bit LSB is 16.0 mV.(4) Typical figures are at TJ = TA = 25C and represent most likely parametric norm.(5) Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).(6) Positive integral linearity Error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes

through positive full-scale and zero. For Negative Integral Linearity Error, the straight line passes through negative full-scale and zero(see Figure 6 Figure 7).

(7) The ADC12030 family's self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will result in a maximum repeatability uncertainty of 0.2 LSB.

(8) The human body model is a 100 pF capacitor discharged through a 1.5 k resistor into each pin.(9) The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels

shorted together.(10) Offset error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the worst-case value of the

code transitions between 1 to 0 and 0 to +1 (see Figure 8).(11) Total unadjusted error includes offset, full-scale, linearity and multiplexer errors.



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Converter Electrical Characteristics (continued)







Offset Error 0.5 1 LSB (max)+ Full-Scale Error 0.5 1.5 LSB (max) Full-Scale Error 0.5 1.5 LSB (max)

Integral Linearity Error 0.5 LSB

Output Data from 12-Bit +10 LSB (max)(see Table 6) (12)

Conversion of Offset 10 LSB (min)

Output Data from 12-Bit 4095 LSB (max)(see Table 6) (12)

Conversion of Full-Scale 4093 LSB (min)

UNIPOLAR DYNAMIC CONVERTER CHARACTERISTICS

fIN = 1 kHz, VIN = 5 VP-P, VREF+ = 5.0V 69.4 dB

S/(N+D) Signal-to-Noise Plus Distortion Ratio fIN = 20 kHz, VIN = 5 VP-P, VREF+ = 5.0V 68.3 dB

fIN = 40 kHz, VIN = 5 VP-P, VREF+ = 5.0V 65.7 dB

3 dB Ful l Power Bandwidth VIN = 5 VP-P, where S/(N+D) drops 3 dB 31 kHz

DIFFERENTIAL DYNAMIC CONVERTER CHARACTERISTICS

fIN = 1 kHz, VIN = 5V, VREF+ = 5.0V 77.0 dB

S/(N+D) Signal-to-Noise Plus Distortion Ratio fIN = 20 kHz, VIN = 5V, VREF+ = 5.0V 73.9 dB

fIN = 40 kHz, VIN = 5V, VREF+ = 5.0V 67.0 dB

3 dB Ful l Power Bandwidth VIN = 5V, where S/(N+D) drops 3 dB 40 kHz

REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS

CREF Reference Input Capacitance 85 pF

A/DIN1, A/DIN2 Analog InputCA/D 75 pFCapacitance

A/DIN1, A/DIN2 Analog InputVIN = +5.0V or VIN = 0V 0.1 1.0 A (max)Leakage Current

GND 0.05 V (min)CH0CH7 and COM Input Voltage

(VA+) + 0.05 V (max)

CH0CH7 and COM InputCCH 10 pFCapacitance

CMUXOUT MUX Output Capacitance 20 pF

On Channel = 5V and Off Channel = 0V 0.01 0.3 A (min)Off Channel Leakage CH0CH7and COM Pins (13) On Channel = 0V and Off Channel = 5V 0.01 0.3 A (max)

On Channel = 5V and Off Channel = 0V 0.01 0.3 A (max)On Channel Leakage CH0CH7and COM Pins (13) On Channel = 0V and Off Channel = 5V 0.01 0.3 A (min)

MUXOUT1 and MUXOUT2 LeakageVMUXOUT = 5.0V or VMUXOUT = 0V 0.01 0.3 A (max)Current

RON MUX On Resistance VIN = 2.5V and VMUXOUT = 2.4V 850 1150 (max)

RON Matching Chan-to-Chan VIN = 2.5V and VMUXOUT = 2.4V 5 %Chan-to-Chan Crosstalk VIN = 5 VP-P, fIN = 40 kHz 72 dB

MUX Bandwidth 90 kHz

(12) The 12-Bit Conversion of Offset and 12-Bit Conversion of Full-Scale modes are intended to test the functionality of the device.Therefore, the output data from these modes are not an indication of the accuracy of a conversion result.

(13) Channel leakage current is measured after the channel selection.



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DC and Logic Electrical Characteristics






Typical (4) Limits (5) UnitsSymbol Parameter Conditions(Limits)

CCLK, CS, CONV, DI, PD AND SCLK INPUT CHARACTERISTICS

VIN(1) Logical 1 Input Voltage V+ = 5.5V 2.0 V (min)

VIN(0) Logical 0 Input Voltage V+ = 4.5V 0.8 V (max)

IIN(1) Logical 1 Input Current VIN = 5.0V 0.005 1.0 A (max)

IIN(0) Logical 0 Input Current VIN = 0V 0.005 1.0 A (min)

DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS

V+ = 4.5V, IOUT = 360 A 2.4 V (min)VOUT(1) Logical 1 Output Voltage

V+ = 4.5V, IOUT = 10 A 4.25 V (min)

VOUT(0) Logical 0 Output Voltage V+ = 4.5V, IOUT = 1.6 mA 0.4 V (max)

VOUT = 0V 0.1 3.0 A (max)IOUT TRI-STATE

Output CurrentVOUT = 5V 0.1 3.0 A (max)

+ISC Output Short Circuit Source Current VOUT = 0V 14 6.5 mA (min)

ISC Output Short Circuit Sink Current VOUT = VD+ 16 8.0 mA (min)

POWER SUPPLY CHARACTERISTICS

Digital Supply Current Awake 1.6 2.5 mA (max)ADC12030, ADC12032, ADC12034 and CS = HIGH, Powered Down, CCLK on 600 AADC12038 CS = HIGH, Powered Down, CCLK off 20 A

ID+Digital Supply Current Awake 2.3 3.2 mAADC12H030, ADC12H032, ADC12H034 CS = HIGH, Powered Down, CCLK on 0.9 mAand ADC12H038 CS = HIGH, Powered Down, CCLK off 20 A

Awake 2.7 4.0 mA (max)IA+ Positive Analog Supply Current CS = HIGH, Powered Down, CCLK on 10 A

CS = HIGH, Powered Down, CCLK off 0.1 A

Awake 70 AIREF Reference Input Current CS = HIGH, Powered Down 0.1 A

(1) Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above VA+or 5V below GND will not damage this device. However, errors in the conversion can occur (if these diodes are forward biased by morethan 50 mV) if the input voltage magnitude of selected or unselected analog input go above V A+ or below GND by more than 50 mV. Asan example, if VA+ is 4.5 VDC, full-scale input voltage must be 4.55 VDC to ensure accurate conversions.

(2) To guarantee accuracy, it is required that the VA+ and VD+ be connected together to the same power supply with separate bypasscapacitors at each V+ pin.

(3) With the test condition for VREF (VREF+ VREF) given as +4.096V, the 12-bit LSB is 1.0 mV and the 8-bit LSB is 16.0 mV.(4) Typical figures are at TJ = TA = 25C and represent most likely parametric norm.(5) Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).



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AC Electrical Characteristics


conversion mode, tr = tf = 3 ns, fCK = fSK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, fCK = fSK= 5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R S = 25, source impedance for VREF+ and VREF

25, fully-differential input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified.

Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25C.(1)

ADC12H030/2/4/8 ADC12030/2/4/8 UnitsTypicalSymbol Parameter Conditions Limits Limits (Limits)(2)

(3) (3)

fCK Conversion Clock (CCLK) 10 8 5 MHz (max)Frequency 1 MHz (min)

Serial Data Clock SCLK Frequency 10 8 5 MHz (max)fSK 0 Hz (min)

40 40 % (min)Conversion Clock Duty Cycle

60 60 % (max)

40 40 % (min)Serial Data Clock Duty Cycle

60 60 % (max)

12-Bit + Sign or 12- 44(tCK) 44(tCK) (max)44(tCK)Bit 5.5 8.8 s (max)tC Conversion Time

21(tCK) 21(tCK) (max)8-Bit + Sign or 8-Bit 21(tCK)

2.625 4.2 s (max)6(tCK) 6(tCK) (min)

6(tCK)7(tCK) 7(tCK) (max)6 Cycles

Programmed 0.75 1.2 s (min)

0.875 1.4 s (max)

10(tCK) 10(tCK) (min)10(tCK)

11(tCK) 11(tCK) (max)10 CyclesProgrammed 1.25 2.0 s (min)

1.375 2.2 s (max)tA Acquisition Time

(4)



2.375 3.8 s (max)



4.375 7.0 s (max)

4944(tCK) 4944(tCK) 4944(tCK) (max)tCKAL Self-Calibration Time

618.0 988.8 s (max)

76(tCK) 76(tCK) 76(tCK) (max)tAZ Auto Zero Time

9.5 15.2 s (max)

2(tCK) 2(tCK) 2(tCK) (min)

3(tCK) 3(tCK) (max)Self-Calibration or Auto ZerotSYNC Synchronization Time from DOR

0.250 0.40 s (min)0.375 0.60 s (max)

DOR High Time when CS is LowtDOR Continuously for Read Data and 9(tSK) 9(tSK) 9(tSK) (max)

Software Power Up/Down 1.125 1.8 s (max)

(1) Timing specifications are tested at the TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge. TRI-STATE outputvoltage is forced to 1.4V.

(2) Typical figures are at TJ = TA = 25C and represent most likely parametric norm.(3) Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).(4) If SCLK and CCLK are driven from the same clock source, then tA is 6, 10, 18 or 34 clock periods minimum and maximum.



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AC Electrical Characteristics (continued)


conversion mode, tr = tf = 3 ns, fCK = fSK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, fCK = fSK= 5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R S = 25, source impedance for VREF+ and VREF

25, fully-differential input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified.


ADC12H030/2/4/8 ADC12030/2/4/8 UnitsTypicalSymbol Parameter Conditions Limits Limits (Limits)(2)

(3) (3)

8(tSK) 8(tSK) 8(tSK) (max)tCONV CONV Valid Data Time

1.0 1.6 s (max)



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Timing Characteristics


conversion mode, tr = tf = 3 ns, fCK = fSK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H03, fCK = fSK =

5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, RS = 25, source impedance for VREF+ and VREF 25,

fully-differential input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified.



Hardware Power-Up Time, Time from PD Falling Edge totHPU 140 250 s (max)EOC Rising Edge

Software Power-Up Time, Time from Serial Data ClocktSPU 140 250 s (max)Falling Edge to EOC Rising Edge

tACC Access Time Delay from CS Falling Edge to DO Data Valid 20 50 ns (max)

Set-Up Time of CS Falling Edge to Serial Data Clock RisingtSET-UP 30 ns (min)Edge

tDELAY Delay from SCLK Falling Edge to CS Falling Edge 0 5 ns (min)

t1H, t0H Delay from CS Rising Edge to DO TRI-STATE RL = 3k, CL = 100 pF 40 100 ns (max)

tHDI DI Hold Time from Serial Data Clock Rising Edge 5 15 ns (min)

tSDI DI Set-Up Time from Serial Data Clock Rising Edge 5 10 ns (min)

50 ns (max)tHDO DO Hold Time from Serial Data Clock Falling Edge RL = 3k, CL = 100 pF 25 5 ns (min)

tDDO Delay from Serial Data Clock Falling Edge to DO Data Valid 35 50 ns (max)

DO Rise Time, TRI-STATE to High RL = 3k, CL = 100 pF 10 30 ns (max)tRDO

DO Rise Time, Low to High RL = 3k, CL = 100 pF 10 30 ns (max)

DO Fall Time, TRI-STATE to Low RL = 3k, CL = 100 pF 12 30 ns (max)tFDO

DO Fall Time, High to Low RL = 3k, CL = 100 pF 12 30 ns (max)

tCD Delay from CS Falling Edge to DOR Falling Edge 25 45 ns (max)

Delay from Serial Data Clock Falling Edge to DOR RisingtSD 25 45 ns (max)Edge

CIN Capacitance of Logic Inputs 10 pF

COUT Capacitance of Logic Outputs 20 pF

(1) Timing specifications are tested at the TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge. TRI-STATE outputvoltage is forced to 1.4V.

(2) Typical figures are at TJ = TA = 25C and represent most likely parametric norm.(3) Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).



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Figure 5. Transfer Characteristic



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Figure 6. Simplified Error Curve vs. Output Code without Auto Calibration or Auto Zero Cycles



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Figure 7. Simplified Error Curve vs. Output Code after Auto Calibration Cycle



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Figure 8. Offset or Zero Error Voltage



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Typical Performance CharacteristicsThe following curves apply for 12-bit + sign mode after Auto Calibration unless otherwise specified. The performance for 8-bit

+ sign mode is equal to or better than shown. (1)

Linearity Error Change Linearity Error Change

vs. Clock Frequency vs. Temperature

Linearity Error Change Linearity Error Change

vs. Reference Voltage vs. Supply Voltage

Full-Scale Error Change Full-Scale Error Change


Full-Scale Error Change Full-Scale Error Change


Offset or Zero Error Change Offset or Zero Error Change


(1) With the test condition for VREF (VREF+ VREF) given as +4.096V, the 12-bit LSB is 1.0 mV and the 8-bit LSB is 16.0 mV.



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Typical Performance Characteristics (continued)The following curves apply for 12-bit + sign mode after Auto Calibration unless otherwise specified. The performance for 8-bit

+ sign mode is equal to or better than shown. (1)

Offset or Zero Error Change Offset or Zero Error Change


Analog Supply Current Digital Supply Current

vs. Temperature vs. Clock Frequency

Digital Supply Current

vs. Temperature



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Typical Dynamic Performance CharacteristicsThe following curves apply for 12-bit + sign mode after Auto Calibration unless otherwise specified.

Bipolar Spectral Response Bipolar Spectral Response

with 1 kHz Sine Wave Input with 10 kHz Sine Wave Input





Bipolar Spurious Free Unipolar Signal-to-Noise RatioDynamic Range vs. Input Frequency

Unipolar Signal-to-Noise Unipolar Signal-to-Noise

+ Distortion Ratio + Distortion Ratio

vs. Input Frequency vs. Input Signal Level



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Typical Dynamic Performance Characteristics (continued)The following curves apply for 12-bit + sign mode after Auto Calibration unless otherwise specified.

Unipolar Spectral Response Unipolar Spectral Response






Test Circuits

Figure 9. DO TRI-STATE (t1H, tOH)

Figure 10. DO except TRI-STATE



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Figure 11. Leakage Current

Timing Diagrams

Figure 12. DO Falling and Rising Edge

Figure 13. DO TRI-STATE Falling and Rising Edge

Figure 14. DI Data Input Timing

Figure 15. DO Data Output Timing Using CS



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SCLK

DO

tACC

tSD

tHDO tDDO

tHDO tDDO

2.4V2.4V 2.4V0.4V0.4V

tSET-UP

tCD

0 1 2 3 4 n

CS

DOR

EOC


Figure 16. DO Data Output Timing with CS Continuously Low

Figure 17. ADC12038 Auto Cal or Auto Zero

Note: DO output data is not valid during this cycle.

Figure 18. ADC12038 Read Data without Starting a Conversion Using CS



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Figure 19. ADC12038 Read Data without Starting a Conversion with CS Continuously Low

Figure 20. ADC12038 Conversion Using CS with 8-Bit Digital Output Format



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Figure 21. ADC12038 Conversion Using CS with 16-Bit Digital Output Format

Figure 22. ADC12038 Conversion with CS Continuously Low and 8-Bit Digital Output Format



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Figure 23. ADC12038 Conversion with CS Continuously Low and 16-Bit Digital Output Format

Figure 24. ADC12038 Software Power Up/Down Using CS with 16-Bit Digital Output Format



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A D C 12 03 0 , A D C 12 03 2 , A D C 12 03 4A D C 12 03 8 , A D C 12H 03 0 , A D C 1 2 H 03 2A

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Adc 12034