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ADAS System Design Enablement – From zero Defects to zero Accidents
Robert Schweiger Director Automotive Solutions, EMEA 10/20/2016 AESIN Conference 2016 Birmingham
2 © 2016 Cadence Design Systems, Inc. All rights reserved.
Agenda
• Market Dynamics
• ADAS System Design Enablement
• ADAS SoC Design
• Verification, Integration & Prototyping
• Summary
3 © 2016 Cadence Design Systems, Inc. All rights reserved.
Automotive Megatrends Dilemma
Reduce
Emissions
Enhance
Safety
4 © 2016 Cadence Design Systems, Inc. All rights reserved.
ADAS Market Observations and Trends
• Sensor –For autonomous driving Vision, Lidar and Radar sensors are needed
–Radar will get precision and feature enriched
–Sensor fusion is key for robustness and safety of ADAS
• Computing –Vision-based ADAS systems cannot be done with uC!
–Everybody wants to deploy Deep Learning (CNN)
–Vision computing will evolve to cognitive computing
–Both leading to drastic increase in performance requirements for future ADAS SoCs
• Technology –Current ADAS SoCs are designed at 22nm and below
–Power consumption of ADAS systems is a major challenge!
5 © 2016 Cadence Design Systems, Inc. All rights reserved.
Vertical Integration driven by ADAS Autonomous driving leading to paradigm shifts in design chain
• Moving down the supply chain –GM acquires Cruise Automation (ADAS)
–Ford and Baidu are investing 150M$ into Velodyne (Lidar)
–Continental buys automotive Lidar biz from ASC (Lidar)
–Audi develops zFAS (Central ADAS platform)
• Moving up the supply chain –Google has developed a self-driving car
–Samsung invests in nuTonomy (self-driving taxis)
–nvidia develops Drive PX (ADAS ECU)
– Infineon buys startup Innoluce to gain Lidar expertise
–Ambarella acquires automotive vision firm VisLab
6 © 2016 Cadence Design Systems, Inc. All rights reserved.
Impact on Automotive Supply Chain?
OEM
Tier1
Semi
ECU
2
ECU
1
F1 F2 F3
ECU
3
SoC
Domain ECU
Functions
implemented
on uCs
ECU functions
consolidated in
SoC
One ECU - one function one ECU / SoC - many functions!
Functions
7 © 2016 Cadence Design Systems, Inc. All rights reserved.
Moving the Integration Point from ECU to SoC
High-Integration
ECU
Functional
ECU
Consolidation
Physical
Miniaturisation
Task:
- Adv. node SoC Design
- SiP, MCM
- High-speed PCB Design
- SI, PI Analysis
Task:
- HW/SW Co-design
- High-level Synthesis
- Functional Verification
- Safety Verification
System
Design & Verification
System
Implemention
ADAS
8 © 2016 Cadence Design Systems, Inc. All rights reserved.
System Design Enablement Smart Product design across the supply chain
Partnerships with Ecosystem Leaders
Mobile Consumer Cloud
Datacenter
Automotive Medical ● ● ●
CHIP (Core EDA)
Design and implementation
IP/SoC verification
Software drivers
SYSTEM INTEGRATION System analysis
HW-SW verification
Software applications
Software development
PACKAGE & BOARD PCB design
Package design
PCB and package analysis IP
9 © 2016 Cadence Design Systems, Inc. All rights reserved.
Comprehensive SoC IP Solution Cadence Silicon Proven IP in Advanced Nodes
Memory and Storage IP Interface IP AMS/Analog IP Peripheral IP Processor IP
Applications
Processor
Custom
Logic Memory
DDR/LPDDR WIDE IO
HBM, HMC
SD/SDIO/
eMMC, UFS
NAND,ONFI,
Toggle
Ethernet
PCIe ®
USB
SSIC
Systems
Peripherals MIPI
HDMI, MHL,
DP/eDP M-PCIe™
ADC
DAC
PVT
LDO
POR
PLL
DLL
Tensilica ®
Communications
Customer Optimized
Embedded DSP
Vision / Imaging
Audio / Voice / Speech
GPU
Embedded Control
Cadence integration optimized IP for complex SoC development
VIP support for all major protocols and memory models
ASIL-B Safety and Automotive Qualification Readiness
10 © 2016 Cadence Design Systems, Inc. All rights reserved.
Tensilica Scalable Processing Platform Based on Xtensa architecture for customization / optimization
Tensilica Xtensa Architecture Providing the Most Efficient Processors in Multiple Markets
Tensilica Optimization Platform
Fully automated HW & SW tools generation
Custom ISA Application Specific
• High Performance
• Energy efficient
• Application specific
data types
HiFi Audio/Voice/Speech
• Encode & Decode
• Voice trigger
• Noise Reduction
• Post-Processing
• 150+ Codecs
ConnX Communications
• Narrow to wide band
Wireless
• LTE/5G, WiFi
• Smart Grid
• Radar
Fusion IoT/Multi Purpose
• Scalable DSP
• Always-alert
• Sensor fusion /
processing
• Audio/Video/Speech
• Comm’s/Security
Vision Computer Vision /
Imaging
• Image processing
and analytics
• Video Pre- Post
Processing
• CNN
• Lidar
11 © 2016 Cadence Design Systems, Inc. All rights reserved.
ADAS Computation Types
Vision Radar
Audio
Radar
Radar
Radar Vision
Vision
Vision
Vision
Vision
Vision Vision
Vision
Vision Audio
Vision
Audio
Radar Front Collision Avoidance
Braking
Adaptive Cruise Control
360 degree Hazard Awareness
Rear Collision Detection
Passive Vision
Rear View Camera
Vision Enhancement
Auto Dimming Headlights
Blind Spot Detection
360 View
Parking Assist
Lane Detection and Following
Sign Recognition
Traffic Signal Recognition
Rain, Snow, /Fog Removal
Pedestrian Tracking
/Avoidance
Eye Focus Detection
Driver Monitoring
Vehicle Detection/Avoidance
Fusion
Radar, LIDAR, Image
correlation
System Functional Safety
System Data Control
Fusion DSP HiFi DSP ConnX DSP
incl. V2X
Active Vision (LiDAR)
Adaptive Cruise Control
Collision Avoidance
Blind Spot Detection
Audio
Rear Object Detection
Parking Assist/Auto
Park
Voice Recognition
Cabin Noise Reduction
Emergency
Recognition
Spatial Audio for
Warnings
Radar
Vision DSP
12 © 2016 Cadence Design Systems, Inc. All rights reserved.
Why use Tensilica Vision Processor vs. GPU/CPU?
• Tensilica Vision: 20x-30x less energy than GPU/CPU at better performance levels
– 1 IVP-EP @ 600MHz performs better than 4 GPU cores at 1.2GHz
– 1 IVP-EP consumes 340mW power vs. 3 Watts for 4 GPU cores at 1.2GHz for face detection
0
400
800
1200
1600
2000
Host CPU (4 cores) Host CPU (4 cores) + 3-pipe GPU (4-core)
IVP
(mj)
Per
Fra
me
CPU/GPU Offload Energy Comparison: Noise Reduction
13 © 2016 Cadence Design Systems, Inc. All rights reserved.
SW Development Tools & Ecosystem for Imaging / Vision Applications
• Familiar programming model
• 1000 optimized library functions
• CNN library
• OpenVX and OpenCV-based library functions
• OpenCL
Libraries
• High-performance Sobel, Median, Gaussian filters
• CNN: Convolution, ReLU
• SIFT, SURF, Harris Corner: Detection algorithm
• HOG, HAAR: Object detection and classification
• Lucas-Kanade: Optical flow
Algorithms
• RTL, EDA scripts
• Cycle accurate Instruction Set Simulator (ISS)
• Fast Function Simulator (TurboXIM)
• System C system modeling (XTSC)
• RTL ready for FPGA
Integration
• Eclipsed based IDE GUI
• Xtensa C/C++ (XCC) Compiler with auto-vectorization
• GNU Software Toolkit (Assembler, Linker, Debugger, Profiler)
• RTOS (XTOS)
Development
Environment
14 © 2016 Cadence Design Systems, Inc. All rights reserved.
Image Video Software Partner ECO System
• Video Image Stabilization (IVP32)
• Low light video processing
• Future: Face Detection, Face Recognition
• Super-Resolution Zoom, HDR
• Camera processing
• Open CV/VX Libraries
• ADAS software suite
• People Detection
• Face Sensing, Face Beautification
• Gesture Engine
• WDR (Wide Dynamic Range)
• Super Video Image Stabilization
• Super Resolution
• Image Filtering
• Neural Networking Face Detection
• Gesture Engine
• Face Detection
• Computer Vision Apps.
• Computer Vision Suite
• Software ISP
• 3rd Party Development Support
• Full software Camera (ISP)
• 3rd Party Development Support
• Dual Camera Depth Map Imaging
• 3D Imaging, Low-Light,
• Virtual Aperture
• Open CL for DSP
• Augmented Reality
• Neural Networking Face Detection
• ADAS suite
• Object Detection
• Face Detection
• System integrator
• Dual Camera Computational
Imaging
• Fusion Digital Zoom
• Fusion Imaging and Depth
Map
• Advanced Noise Reduction
• Video and image signal
processing
© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are trademarks of Cadence Design Systems,
Inc. in the United States and other countries. All other trademarks are the property of their respective owners and are not affiliated with Cadence.
Fully deterministic,
and reliable RTOS
15 © 2016 Cadence Design Systems, Inc. All rights reserved.
We have the highest scoring CNN algorithm Based on the German Traffic Sign Recognition Benchmark
• Artificial intelligence – Machine learning
– Analyze big data
– High-performance computing
– Leverage statistical methods
– Pattern recognition
– Automated decision making
CNN Convolutional Neural Networks
CNN - compares 51840 input signs with 43 trained signs
99.82% detection rate (human 99.22%)!
• Requirement: >1 TFLOPS @ 1W
• High-performance, low-power DSP
• Optimized ADAS platform (HW+SW)
German Traffic Sign Recognition Benchmark (GTSRB)
16 © 2016 Cadence Design Systems, Inc. All rights reserved. I/O IF incl. AutoEthernet Memory
IF
Lock-Step ARM A53: Object L.
Things2Do: ADAS SoC Architecture
4x Vision P6: Pixel Level
Tensilica
HEs: Pixel Level
Tensilica
17 © 2016 Cadence Design Systems, Inc. All rights reserved.
Cadence System Development Suite Virtual or FPGA prototyping, system simulation/verification, and emulation
Virtual Prototyping
Virtual System Platform
•Tensilica® SystemC models
•TLM 2.0 SystemC modeling
•Cycle accurate or fast functional at the transaction or pin level
•Early driver/firmware development
•Rich component model library
•Connection to hardware engines for hybrid co-execution
IP Sub-system Prototyping
RIPE3 FPGA IP Eval Board
• Low cost
• Single protocol validation
• Small sub-system demo
• Multi-slot HPC FMC for pluggable PHY-daughter cards
• Software/firmware drivers for interface IP
FPGA Prototyping
Protium™ Platform
• Early software development for sub-system in context of system environment
• FPGA prototyping environment compatible to Palladium® flow, allowing sub-system extension
• Multi-FPGA partitioning, clock management, memory mapping, SpeedBridge® support
• System validation
HW-SW Co-Verification
Palladium Platform
• Comprehensive verification computing platform from node to hub to cloud
• Scalability and flexibility up to 2.3 billion gates and 512 users
• Simulation acceleration
• Flexible resource allocation
• SpeedBridge adapter to high-speed interface to allow interface with real-world environment
Scaling from virtual to physical and from small to large
18 © 2016 Cadence Design Systems, Inc. All rights reserved.
ADAS Hardware Prototypes incl. application Software FPGA prototyping for System Verification and HW-SW Integration
360° Surround View
Apps
CPU
Automotive Head Unit
DDR DDRDDR
Audio/Video
Misc intf
Comm. SDIO
eMMC
Tensilica
IVP
DSPUSB
Tensilica
HiFi
DSP
Ethernet
PCIe
SATAGPS
BT
LTE
Touch
I2S
Slimbus
Sound
Wire
NFC
MIPI
Display
WiFi
Tensilica
BBP
DSP
Au
toE
AV
B s
witc
h
D-PHY
Analog
audio
BR-
PHY
BR-
PHY
AutoE
MAC
AutoE
MAC
Sound
Wire
MIPI
CSI
Tensilica
HiFi
Tensilica
IVP
Audio
Sub-system
Video
Sub-system
SoC
Platform
Lane Detection Pedestrian Detection
Audio/Video
over Ethernet
19 © 2016 Cadence Design Systems, Inc. All rights reserved.
Summary The automotive industry is facing radical changes
• ADAS requires high-performance, low-power SoCs
• Major re-tooling across the supply chain is needed
• Broad based partner for Automotive system enablement – Processor & application know-how for Vision, CNN, Radar, Lidar, V2X, Audio, Infotainment,
Wireless, ECU,…
– Sub-system platforms available with Hardware and Software
• Validated design flows, tools and IP to speed up ISO26262 product certification – Rich silicon proven IP Portfolio (ASIL-B ready)
© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, Palladium, SpeedBridge, and Tensiica are registered trademarks and Protium is a trademark of Cadence
Design Systems, Inc. in the United States and other countries. SystemC is a trademark of the Accellera Systems Initiative. All rights reserved. All other trademarks are the property of their respective
owners.