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ACPD Presentation at SiliconWorks ( Automated Custom Physical Design) . Cadence Korea May.13.2003SY.Lee. Agenda. What is ACPD? Virtuoso-XL VCP VCR PDK RoadMap. What is ACPD ? Automated Custom Physical Design. - PowerPoint PPT Presentation
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CADENCE CONFIDENTIAL
ACPD Presentation at SiliconWorks(Automated Custom Physical Design)
Cadence KoreaMay.13.2003 SY.Lee
CADENCE CONFIDENTIAL
Agenda
• What is ACPD?
• Virtuoso-XL
• VCP
• VCR
• PDK
• RoadMap
CADENCE CONFIDENTIAL
ACPD
What is ACPD ?Automated Custom Physical Design• Complete automated full custom layout methodology for digital,
analog and mixed technologies at all levels of the design hierarchy
• No compromises: Layout results are equal to manual full custom
• Low risk: Customer proven solution in use worldwide
• Provides a measurable and consistent productivity increase of 4X - 10X on average compared to current methods
Tools Methodology
CADENCE CONFIDENTIAL
CMOS ProcessLibrary withPcells. Virtuoso® Layout Editor
with Pcells
Diva DRC,LVS
Total time for Block Creation: typically 7 daysTotal time for Chip Assembly: typically 6 weeks
Many DRC/LVS loopsto fix errors
No connectivity
No constraints orautomated routing
Physical Handoff
Virtuoso® SchematicComposer
Manual Physical Design Layout Methodology
CADENCE CONFIDENTIAL
ACPD Methodology
Connectivity Driven Layout
Virtuoso® Schematic Composer
Virtuoso® Custom Placer (VCP)
Total time for Block Creation now - 1 day Vs 7 DAYS (7X)Total time for Chip Assembly now - 1 day Vs 6 WEEKS (30X)
CMOS ProcessLibrary withPcell’s.
Virtuoso® XL (VXL) and
ROD Pcells Constraint and Connectivity Based Editing
DIVA DRC/LVS
ConstraintDriven Correct-by-Construction Routing
Number of DRC/LVSErrors SignificantlyReduced
Virtuoso® Custom Router (VCR)
/Cadence Chip Assembly Router (CCAR)
Netlist
Automated Device Placement
Introduced in 1999
Process Design Kits (PDKs)
CADENCE CONFIDENTIAL
= DAYS Generation
= MONTHSPlacementGeneration Place
Routing Verification
Con
nect
ivity
& c
onst
rain
tsC
onne
ctiv
ity &
con
stra
ints
VirtuosoVirtuoso® XL Layout Editor XL Layout Editor•Custom PlacementCustom Placement•Interactive RoutingInteractive Routing
AssuraAssura®/Diva (DRC/LVS)/Diva (DRC/LVS)
VirtuosoVirtuoso® Schematic Composer Schematic Composer
• Provides consistent 100% LVS & DRC correct results using Connectivity & Constraints
• Generates faster more accurate devices using advanced interactive editing techniques
• Reduces the layout time dramatically with automated placement and interactive routing
• Maximizes custom layout productivity to deliver handcrafted quality in a fraction of the time
ACPD: METHODOLOGY AND PRODUCTS
CADENCE CONFIDENTIAL
Virtuoso-XLVirtuoso®-XL Layout Editor is the next-generation, connectivity- and constraint-driven layout design environment. A task-oriented design approach provides direct access to automated placement, routing, verification and a robust set of interactive layout editing utilities. This new physical design solution maximizes custom layout productivity to deliver handcrafted quality layout in a fraction of the time of traditional methodologies
• Provides a unified and consistent layout editing environment
• Includes full-function polygon editing for high-performance, handcrafted IC layout
• Automatically chains and folds transistors
• Provides fast cell-level layout
• Ensures increased productivity and correct-by-construction results
• Provides fast device manipulation with stretchable parameterized cells (Pcells)
DEVICE GENERATION
Pcells generated from netlist or schematic parameters
Pins generated from template
Rows displayed for preplacement
CADENCE CONFIDENTIAL
Connectivity driven - Netlist-Driven
• Alternate independent connectivity sources:
– schematic– netlist
• Similar use modes and capabilities
• Imported netlists managed by DM
Vsc
Netlist
* SPICE … *M01 2 3 gnd 27 W=2 L=3M02 3 5 g1 15 W=2u L=4uM03 4 5 g2 216 W=1u L=1uM04 5 6 g3 11 W=3u L=1.2uM05 5 6 g4 12 W=3u L=1uM12 3 5 g1 15 W=2u L=4uM13 4 5 g6 26 W=1u L=1uM14 5 6 g7 11 W=3u L=1.2uM15 5 6 g8 12 W=3u L=1u...
VXL
Edit, Place, Route...
CADENCE CONFIDENTIAL
Layout editing - Automatic Abutment
• DRC correct
• Constraint correct
• Technology independent
• Backward compatible
• Customizable
• Interactive
• Post-processor after placement
A
BA
(3) A and B aretransformed and snap to min dist.
B
(1) B is movedto overlap A
(2) metal pins touchand trigger abutment
BA
occur to both instances
(4) When A is moved away,reverse transformations
CADENCE CONFIDENTIAL
Composer Virtuoso XLEdit Place Route ...
Connectivity driven - Pick from Schematic
(1) Select unplacedcomponent from schematic
(1)
CBE link
(2) Drag mousepointer intolayout window
(2)
• Schematic reference
(3) Interactively place newlycreated object
(3)
• Constraint-driven interactive placement
• Multiple simultaneous selections
• Pre-placement as in schematic
CADENCE CONFIDENTIAL
Interactive Chaining & Folding (cont’d)
CADENCE CONFIDENTIAL
Stretchable pCells
CADENCE CONFIDENTIAL
Available in 4.4.6 3Q 2000
Automatic and interactive support in Virtuoso XL
Constraint-driven (physical placement constraints)
Row-based placement:
Transistor Devices
Custom and Std. Cells
Blocks
Area-based placement
Mixed mode placement
Virtuoso® custom placer (Vcp) - Overview
PLACEMENT RESULTS
Filler Cells
Standard Cells
Filler Cells
CADENCE CONFIDENTIAL
WE
– Show Timing/Length Rule Constraints: Displays length rule indicators as a path with a length rule is edited.
– Meter displays a negative number in green color if within the length rule limits. A positive number in Red color shows up when the path being created is outside length limits.
– Octagon shows the extent to which a path can be routed within the length rules.
CADENCE CONFIDENTIAL
Virtuoso® Custom Router
• Original and most proven IC shape-based area routing technology in the industry
• Provides connectivity- and constraint-driven interactive and automatic routing with online DRC/LVS checking
• Comprehensive set of routing constraints with hierarchical rule precedence
• Supports cross-probing and dynamic updating between schematic and layout
• Automated interactive and automatic power routing• Automated interactive bus routing
Wire
to W
ire
Wire
Sha
pe
Wire
to
Pin
Wire
to
Via
Wire
to K
eepo
ut
Via
to P
in
Path
Sea
rch
CADENCE CONFIDENTIAL
CADENCE CONFIDENTIAL
Point Tools VCD Solution
User 1
User 2
Virtuoso
VirtuosoUser 3
VXL
Pool of Tools
VXL
VCR/CCAR
DIVA
User 3
VCD Seat
User 1
VCD Seat
User 2
VCD Seat
99 year or TBLPDK (a) PDK (b)ACPD Methodology
Introduced in 1999
TBL only
VirtuosoVXL
VCR &ProuteDIVA &Assura
VCD
VCP
Methodology
Installation Internet
Training
Q1 2001
VCD SolutionVCD Solution
CADENCE CONFIDENTIAL
What is a baseline foundry PDK?
• For example CMOS logic – Composer logic symbol library
– N & P mos, resistor and capacitor Pcells
– Virtuoso XL/VCP/VCR Tech and display files
– Assura/Diva DRC/LVS decks (download from foundry site)
• Foundries– e.g. TSMC…., UMC… etc..
• Technologies– e.g. .18u, .25u…, Logic.., MS…., RF… etc..
• Tested with VCD methodology• Supported (maintenance available)• Price book orderable item
CADENCE CONFIDENTIAL
Virtuoso XLCustom Placer
Custom Router
Process data
Per FAB / Processe.g. TSMC .18 CMOS
(proprietary data)
Virtuoso SchematicComposer
SimulationModels
Spectre, Spectre RF
Virtuoso XL
VerificationRule decks
DIVA & Assura DRC/LVS
Technology File
Schematic Symbols
Simulation Models
Parameterized cells( Pcells)
Verification Decks
PDK Components
BuildPDK
Foundry
Foundry
PDK Tool Support
CADENCE CONFIDENTIAL
Cadence IC Design EnvironmentOpenAccess
SOCEncounter
Custom ICDesign
Cell-Based AMS/Custom3rd Party
Tool3rd Party
Tool3rd Party
Tool
Industry-Standard open-source model
Leverages industry knowledge on one
standard
Improved tool and flow interoperability
Standards Accelerate Technology DevelopmentAnd Reduce Costs
5.0 supports OpenAccess in Q1 03
CADENCE CONFIDENTIAL
LINUX OS SupportIC Solutions
Provide Enterprise class solutions through partnerships with HP, IBM and RedHat
Many digital solutions available now - remainder 4Q02
Custom IC solution available 1Q03
Physical verification rollout 3Q02 through 3Q03
CADENCE CONFIDENTIAL