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DAC 2003 June 2 - 6, 2003 Anaheim, CA

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Cover Page Table of Contents Author Index

General Chair’s WelcomeWelcome to the 40th Design Automation Conference (DAC) and the magical city of Anaheim. Each year,thousands of engineers attend DAC to learn of the latest developments in electronic design and ElectronicDesign Automation (EDA) – and how they affect each other. DAC brings together designers, EDA developers, analysts, marketers, consultants, managers, executives,professors and students. This makes it a great place to meet others who are working on the same andrelated problems, to learn about new developments, to meet people who use what you develop or developwhat you use, to learn about needs and trends and to renew old friendships. It is an exciting and fast-pacedweek where the benefits are limited only by your desire, and time.The technical program presents the latest developments in EDA tools and design methodologies. Powermanagement is the major emphasis this year – in papers, a panel, Monday’s tutorial and the hands-ontutorial. Other hot topics are: deep submicron issues, embedded system design and verification and thedesign of complex, high-performance ASICs. New this year are 5 papers covering highlights from ISSCC.The keynote speakers are Sir Robin Saxby, Chairman of ARM Holdings plc, who will look to the future,and Professor Alberto Sangiovanni-Vincentelli, who will look back over DAC’s 40 years. DAC full-conference registrants will receive a DVD containing 40 years of DAC proceedings.Over 190 companies will be at DAC this year, 25 of them making their debut. Many of these companieswill also have demo suites. The DAC Pavilion on the exhibit floor will provide panel sessions, interviewsand live video feed of some of the technical program. It will also provide a preview of the new combinedbooth-suite layout that will debut at DAC 2004. We will continue the coffee carts introduced last year. Newthis year on the floor is a Micro-Brew party from 4 to 6 pm on Monday, hosted by the exhibitors and ice-cream carts on Tuesday.This year, in cooperation with the Fabless Semiconductor Association (FSA), DAC introduces formanagers and executives a Management Focus program on Tuesday. It consists of the keynote (Sir RobinSaxby), two sessions on the economics of design and the EDA Business Forum ™ Lunch, organized byAKI PR.This year’s Technical Program received a record number of 628 paper submissions. The 61 members ofthe technical program committee, co-chaired by Luciano Lavagno and Limor Fix and helped by over 600reviewers, had to make very difficult decisions. The final program consists of 152 papers in 38 sessions,9 special sessions and 8 panels and it promises to be one of the best programs ever.An event like DAC doesn’t just happen. We wish to express our appreciation to all authors, speakers,reviewers, session organizers, moderators, panelists, session chairs, keynote speakers and committeemembers. Also to the dedicated members of the DAC Executive Committee, the Technical ProgramCommittee and the Exhibitor Liaison Committee. MP Associates Inc, the conference managers, aredevoted to the success of DAC. We are grateful for the support of our sponsors (ACM/SIGDA, IEEECircuits and Systems Society and the EDA Consortium) and for the technical co-operation of the IEEESolid State Circuits Society And, finally, to all DAC attendees – we are sure you will have a great week at DAC; enriching, fulfillingand exciting.

Ian GetreuGeneral Chair40th Design Automation Conference

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PROCEEDING OF THE 40TH DESIGN AUTOMATION CONFERENCE®

The Association for Computing Machinery1515 Broadway

New York, New York 10036

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Table of Contents

General Chair’s Welcome ..........................................................................................................................i Executive Committee..............................................................................................................................xix Technical Program Committee ............................................................................................................xxi Panel Sub-Committee.......................................................................................................................... xxiii Student Design Contest Judges........................................................................................................xxiv

Exhibitor Liaison Committee .............................................................................................................xxiv Opening Keynote Address – Sir Robin Saxby ................................................................................xxv Thursday Keynote Address – Alberto L. Sangiovanni-Vincentelli ........................................... xvii Marie R. Pistilli Women in EDA Achievement Award ...................................................................xxix Phil Kaufman Award ............................................................................................................................xxix 2003 IEEE Fellows ................................................................................................................................xxix IEEE CAS Society Awards...................................................................................................................xxix Mac Van Valkenburg Award ...........................................................................................................xxix

Emanuel R. Piore Award..................................................................................................................xxix Guillemin-Cauer Award ...................................................................................................................xxix CAD Transactions Best Paper Award ...............................................................................................xxx VLSI Transactions Best Paper Award ...............................................................................................xxx ACM/SIGDA Distinguished Service Award ......................................................................................xxx 2002 DAC P.O. Pistilli Undergraduate Scholarships .....................................................................xxx Design Automation Conference Graduate Scholarships ............................................................xxxi DAC 2003 Student Design Contest Winners ............................................................................... xxxii Reviewers ............................................................................................................................................. xxxiii 2004 Call for Papers .............................................................................................................................xxxv

SESSION 1: Special Session — Real Challenges and Solutions for Validating System-on-Chip Chair: & Organizer: Wolfgang Rosenstiel (University of Tubingen)

1.1 High Level Formal Verification of Next-Generation Microprocessors ...........................1 T. Schubert (Intel Corporation)

1.2 Verification Strategy for Integration 3G Baseband SoC ....................................................7 Y. Mathys, A. Châtelain (Motorola)

1.3 Improvements in Functional Simulation Addressing Challenges in Large, Distributed Industry Projects ................................................................................11 K.-D. Schubert (IBM Corporation)

SESSION 2: Panel — Reshaping EDA for Power.....................................................................15 Chair: Jan Rabaey (University of California at Berkeley) Organizers: Dennis Sylvester, David Blaauw (University of Michigan) Panelists: K. Bernstein (IBM Corporation), J. Frenkil (Sequence Design Incorporated), M. Horowitz (Stanford University), W. Nebel (Oldenburg University), T. Sakurai (University of Tokyo), A. Yang (Apache Design Solutions)

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SESSION 3: Design for Manufacturability and Global Routing Chair: Martin Wong (University of Illinois) Organizers: Charles J. Alpert, Dennis Sylvester, Raymond Nijssen

3.1 A Cost-Driven Lithographic Correction Methodology Based on Off-the-Shelf Sizing Tools ..................................................................................................16 P. Gupta, A. B. Kahng (University of California at San Diego), D. Sylvester, J. Yang, (University of Michigan at Ann Arbor)

3.2 Performance-Impact Limited Area Fill Synthesis ..............................................................22 Y. Chen (University of California at Los Angeles), P. Gupta, A. B. Kahng (Univiversity of California at San Diego)

3.3 Improved Global Routing through Congestion Estimation.............................................28 R. T. Hadsell, P. H. Madden (State University of New York)

3.4 Microarchitecture Evaluation With Physical Planning .....................................................32 J. Cong, A. Jagannathan, G. Reinman, M. Romesis (University of California at Los Angeles)

SESSION 4: Design Analysis Techniques Chair: Michael Kishinevsky (Intel Corporation) Organizers: Ahmed A. Jerraya, Steven Haynal

4.1 Energy-Aware Design Techniques for Differential Power Analysis Protection .........36 L. Benini (Università di Bologna), A. Macii, E. Macii (Politecnico di Torino), E. Omerbegovic (BullDAST s.r.l.), M. Poncino (Università di Verona), F. Pro (BullDAST s.r.l.)

4.2 A Timing-Accurate Modeling and Simulation Environment for Networked Embedded Systems .......................................................................................42 F. Fummi (Università di Verona), P. Gallo (Telecom Italia Laboratory), S. Martini, G. Perbellini, M. Poncino (Università di Verona), F. Ricciato (Telecom Italia Laboratory)

4.3 Application of Design Patterns for Hardware Design .......................................................48 R. Damaševicius, G. Majauskas, V. Štuikys (Kaunas University of Technology)

SESSION 5: Embedded Hardware Design Case Studies Chair: Chris Rowen (Tensilica, Incorporated) Organizers: Grant E. Martin, Kurt Keutzer, Pai Chou

5.1 A Fully-Programmable Memory Management System Optimizing Queue Handling at Multi Gigabit Rates ................................................................................54 G. Kornaros, I. Papaefstathiou, A. Nikologiannis, N. Zervos (Ellemedia Technologies)

5.2 Design Flow for HW/SW Acceleration Transparency in the ThumbPod Secure Embedded System .....................................................................60 D. Hwang, P. Schaumont, Y. Fan, A. Hodjat, B.-C. Lai, K. Sakiyama, S. Yang, I. Verbauwhede (University of California at Los Angeles)

5.3 Design Techniques for Sensor Appliances: Foundations and Light Compass Case Study .............................................................................................66 J. L. Wong, S. Megerian, M. Potkonjak (University of California at Los Angeles)

SESSION 6: Special Session — Emerging Design and Tool Challenges in RF and Wireless Applications Chair: Georges Gielen (Katholieke University) Organizer: Limor Fix

6.1 Seamless Multi-Radio Integration Challenges U. Barkai (Intel Corporation)

6.2 RF Front End Application and Technology Trends ...........................................................73 P. W. Hooijmans (Philips Research Laboratories)

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6.3 4G Terminals: How are We Going to Design Them?.........................................................79 J. Craninckx, S. Donnay (IMEC)

6.4 New Techniques for Non-Linear Behavioral Modeling of Miocrowave/RF ICs from Simulation and Nonlinear Microwave Measurements ............................................85 D. E. Root, J. Wood (Agilent Technologies), N. Tufillaro (Agilent Laboratories)

SESSION 7: Panel — COT-Customer Owned Trouble...........................................................91 Chair: Bob Dahlberg (Reshape Incorporated) Organizers: Shishpal Rawat (Intel Corporation) & Jen Bernier (Armstrong Kendall) Panelists: G. Gloski (eSilicon Corporation), A. Khan, (Cadence Design Systems, Incorporated), K. Patel (Azanda Network Devices), P. Ruddy (Cisco Systems), N. Sherwani (Intel Corporation), R. Vasishta (LSI Logic Corporation)

SESSION 8: Power Grid Analysis and Optimization Chair: Sani Nassif (IBM Corporation) Organizers: Jen Bernier, Shishpal Rawat

8.1 Random Walks in a Supply Network .....................................................................................93 H. Qian (Unviersity of Minnesota), S. R. Nassif (IBM Austin Research Laboratories), S. S. Sapatnekar (University of Minnesota)

8.2 A Static Pattern-Independent Technique for Power Grid Voltage Integrity Verification ..................................................................................................................99 D. Kouroussis, F. N. Najm (University of Toronto)

8.3 Power Network Analysis Using an Adaptive Algebraic Multigrid Approach ............105 Z. Zhu, B. Yao, C.-K. Cheng (University of California at San Diego)

8.4 Power Grid Reduction Based on Algebraic Multigrid Principles.................................109 H. Su, E. Acar, S. R. Nassif (IBM Austin Research Laboratories)

8.5 On-chip Power Supply Network Optimization using Multigrid-based Technique ...113 K. Wang, M. Marek-Sadowska (University of California at Santa Barbara)

SESSION 9: Low-Power Embedded System Design Chair: Rajesh K. Gupta (University of California at San Diego) Organizers: Diederik Verkest, Taewhan Kim

9.1 Scalable Modeling and Optimization of Mode Transitions Based on Decoupled Power Management Architecture ................................................119 D. Li, Q. Xie, P. H. Chou (University of California at Irvine)

9.2 Optimal Voltage Allocation Techniques for Dynamically Variable Voltage Processors .................................................................................................125 W.-C. Kwon (Samsung Electronics Company), T. Kim (Korea Advanced Institute of Science & Technology)

9.3 Energy Reduction Techniques for Multimedia Applications with Tolerance to Deadline Misses ......................................................................................131 S. Hua, G. Qu, S. S. Bhattacharyya (University of Maryland at College Park)

9.4 Xtream-Fit: An Energy-Delay Efficient Data Memory Subsystem for Embedded Media Processing .........................................................................................137 A. Ramachandran, M. F. Jacome (University of Texas at Austin)

SESSION 10: Cyclic and Non-Cyclic Combinational Circuit Synthesis Chair: Victor Kravets (IBM Corporation) Organizers: Marek Perkowski, Soha Hassoun

10.1 A New Enhanced Constructive Decomposition and Mapping Algorithm..................143 A. Mishchenko (University of California at Berkeley), X. Wang, T. Kam (Intel Corporation)

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10.2 Large-Scale SOP Minimization Using Decomposition and Functional Properties......................................................................................................149 A. Mishchenko (University of California at Berkeley), T. Sasao (Kyushu Institute of Technology)

10.3 Generalized Cofactoring for Logic Function Evaluation................................................155 Y. Jiang, S. Matic, R. K. Brayton (University of California at Berkeley)

10.4 Making Cyclic Circuits Acyclic .............................................................................................159 S. A. Edwards (Columbia University)

10.5 The Synthesis of Cyclic Combinational Circuits .............................................................163 M. D. Riedel, J. Bruck (California Institute of Technology)

SESSION 11: Managing Leakage Power Chair: Siva Narendra (Intel Corporation) Organizers: Marek Perkowski, Soha Hassoun

11.1 Accurate Estimation of Total Leakage Current in Scaled CMOS Logic Circuits Based on Compact Current Modeling .....................................................169 S. Mukhopadhyay, A. Raychowdhury, K. Roy (Purdue University)

11.2 Analysis and Minimization Techniques for Total Leakage Considering Gate Oxide Leakage ........................................................................................175 D. Lee, W. Kwong, D. Blaauw, D. Sylvester (University of Michigan)

11.3 Distributed Sleep Transistor Network for Power Reduction.........................................181 C. Long (University of Wisconsin at Madison), L. He (University of California at Los Angeles)

11.4 Implications of Technology Scaling on Leakage Reduction Techniques .................187 Y-F. Tsai (Penn State University), D. Duarte (Intel Corporation), N. Vijaykrishnan, M. J. Irwin (Penn State University)

11.5 Static Leakage Reduction through Simultaneous Threshold Voltage and State Assignment .............................................................................................191 D. Lee, D. Blaauw (University of Michigan)

SESSION 12: Panel — Emerging Markets: Design Goes Global............................................195 Chair: C.-F. Chan (Synopsys, Incorporated) Organizers: Deirdre Hanford, Jian Yue Pan, Narendra Shenoy Panelists: M. Mehendale (Texas Instruments), A. Vasudevan (Wipro Technologies), S. Wei (Beijing Datang Telecom Ltd.), Wei-Ping Liu CEC (Huada Electronics Design Company, Ltd.)

SESSION 13: Timing-Oriented Placement Chair: Ralph Otten (Eindhoven University of Technology) Organizers: Deirdre Hanford, Jian Yue Pan, Narendra Shenoy

13.1 Timing Optimization of FPGA Placements by Logic Replication ................................196 G. Beraudo, J. Lillis (University of Illinois at Chicago)

13.2 Delay Budgeting in Sequential Circuit with Application on FPGA Placement .........202 C.-Y. Yeh, M. Marek-Sadowska (University of California at Santa Barbara)

13.3 Multilevel Global Placement with Retiming .......................................................................208 J. Cong, X. Yuan (University of California at Los Angeles)

13.4 Force Directed Mongrel with Physical Net Constraints .................................................214 S.-W. Hur (Donga University), T. Cao, K. Rajagopal, Y. Parasuram, A. Chowdhary, V. Tiourin (Intel Corporation), B. Halpin (Syracuse University, Intel Corporation)

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SESSION 14: Model Order Reduction Chair: Ying (Frank) Liu (IBM Corporation) Organizers: C. Y. Roger Chen, Carl Sechen

14.1 Realizable Parasitic Reduction Using Generalized Y-∆ Transformation ...................220 Z. Qin (Synopsys, Incorporated), C.-K. Cheng (University of California at San Diego)

14.2 Realizable RLCK Circuit Crunching ....................................................................................226 C. S. Amin, M. H. Chowdhury, Y. I. Ismail (Northwestern University)

14.3 Efficient Model Order Reduction Including Skin Effect..................................................232 S. Mei, C. Amin, Y. I. Ismail (Northwestern University)

14.4 Model Order Reduction of Nonuniform Transmission Lines Using Integrated Congruence Transform...........................................................................................................238 E. Gad, M. Nakhla (Carleton University)

SESSION 15: Issues in Partitioning & Design Space Exploration for Codesign Chair: Nikil Dutt (University of California at Irvine) Organizer: Sachin S. Sapatnekar

15.1 Partial Task Assignment of Task Graphs under Heterogeneous Resource Constraints ................................................................................................................................244 R. Szymanek, K. Kuchcinski (Lund University)

15.2 Dynamic Hardware/Software Partitioning: A First Approach .......................................250 G. Stitt, R. Lysecky, F. Vahid (University of California at Riverside)

15.3 Automatic Application-Specific Instruction-Set Extensions under Microarchitectural Constraints .................................................................................256 K. Atasu, L. Pozzi, P. Ienne (Swiss Federal Institute of Technology Lausanne (EPFL))

15.4 Instruction Encoding Synthesis for Architecture Exploration using Hierarchical Processor Models .................................................................................262 A. Nohl, V. Greive, G. Braun, A. Hoffmann (CoWare, Incorporated), R. Leupers, O. Schliebusch, H. Meyr (Aachen University of Technology (RWTH))

SESSION 16: Special Session — Nano Technology: Design Implications and CAD Challenges Chair: Rolf Ernst (Technical University of Braunsweig) Organizers: Xiaobo Sharon Hu, Wolfgang Porod

16.1 Quantum-dot Cellular Automata: Computing by Field Polarization ...........................268 G. H. Bernstein (University of Notre Dame)

16.2 Recent Advances and Future Prospects in Single-Electronics ...................................274 C. Wasshuber (Texas Instruments)

16.3 Manipulation and Characterization of Molecular Scale Components ........................276 I. Amlani, R. Zhang, J. Tresek, L. Nagahara, R. K. Tsui (Motorola)

SESSION 17: Panel — Mixed Signals on Mixed-Signal: the Right Next Technology ...............................................................................................278 Chair: Rob A. Rutenbar (Carnegie Mellon University) Organizers: James Spoto, Rob A. Rutenbar Panelists: Raminderpal Singh (IBM Corporation), K. Johnson (Cadence Design Systems, Incorporated), P. Kempf (Jazz Semiconductor), T. Meng (Stanford University, Atheros Communications), R. Rofougaran (Broadcom), J. Spoto (Applied Wave Research)

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SESSION 18: Simulation Coverage and Generation for Verification Chair: Umberto Rossi (STMicroelectronics) Organizers: Hikeung T. Ma, Shin-ichi Minato

18.1 Coverage-Oriented Verification of Banias .........................................................................280 A. Gluska (Intel Corporation)

18.2 Coverage Directed Test Generation for Functional Verification using Bayesian Networks ......................................................................................................286 S. Fine, A. Ziv (IBM Research Laboratory in Haifa)

18.3 Dos and Don’ts of CTL State Coverage Estimation ........................................................292 N. Jayakumar, M. Purandare, F. Somenzi (University of Colorado at Boulder)

18.4 Constraint Synthesis for Environment Modeling in Functional Verification ............296 J. Yuan, K. Albin (Mototola Inc.), A. Aziz (University of Texas at Austin), C. Pixley (Synopsys, Incorporated)

SESSION 19: Tool Support for Architectural Decisions in Embedded Systems Chair: Grant E. Martin (Cadence Design Systems, Incorporated) Organizers: Grant E. Martin, Kurt Keutzer, Pai Chou

19.1 Automatic Communication Refinement for System Level Design ..............................300 S. Abdi, D. Shin, D. Gajski (University of California at Irvine)

19.2 CoCo: A Hardware/Software Platform for Rapid Prototyping of Code Compression Technologies...................................................................................306 H. Lekatsas, J. Henkel, S. Chakradhar, V. Jakkula, M. Sankaradass (NEC Laboratories America, Incorporated)

19.3 A Tool for Describing and Evaluating Hierarchical Real-Time Bus Scheduling Policies ........................................................................................................312 T. Meyerowitz, C. Pinello, A. Sangiovanni-Vincentelli (University of California at Berkeley)

SESSION 20: New Topics in Logic Synthesis Chair: Shigeru Yamashita (NTT Communication Science Laboratories) Organizers: Marek Perkowski, Steven M. Nowick

20.1 A Transformation Based Algorithm for Reversible Logic Synthesis .........................318 D. M. Miller (University of Victoria), D. Maslov, G. W. Dueck (University of New Brunswick)

20.2 An Arbitrary Two-qubit Computation in 23 Elementary Gates Or Less .....................324 S. S. Bullock, I. L. Markov (University of Michigan at Ann Arbor)

20.3 Verilog HDL, Powered by PLI: a Suitable Framework for Describing and Modeling Asynchronous Circuits at All Levels of Abstraction ............................330 A. Saifhashemi, H. Pedram (Amirkabir University of Technology)

20.4 On-Chip Logic Minimization ..................................................................................................334 R. Lysecky (University of California at Riverside), F. Vahid (University of California at Riverside)

SESSION 21: Special Session — Coping with Variability: The End of Deterministic Design Chair: Michael Orshansky (University of California at Berkeley) Organizer: Kurt Keutzer

21.1 Parameter Variations and Impact on Circuits and Microarchitecture ........................338 S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, V. De (Intel Laboratories)

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21.2 Death, Taxes and Failing Chips ............................................................................................343 C. Visweswariah (IBM Thomas J. Watson Research Center)

21.3 Computation and Refinement of Statistical Bounds on Circuit Delay .......................348 A. Agarwal, D. Blaauw (University of Michigan), V. Zolotov (Motorola), S. Vrudhula (University of Arizona at Tucson)

SESSION 22: Panel — Fast, Cheap and Under Control: The Next Implementation Fabric ........................................................................................................354 Chair: Abbas El Gamal (Stanford University) Organizers: John Cohn,, Andrew B. Kahng Panelists: I. Bolsens (Xilinx, Incorporated), A. Broom (AMI), C. Hamlin (LSI Logic), P. Magarshack (STMicroelectronics), Z. Or-Bach (eASIC), L. Pileggi (Carnegie Mellon University)

SESSION 23: Testbench, Verification and Debugging: Practical Considerations Chair: Michael Beaver (iReady Corporation) Organizers: Carl Pixley, Rajeev Ranjan

23.1 Using a Formal Specification and a Model Checker to Monitor and Direct Simulation..............................................................................................................356 S. Tasiran (Koç University), Y. Yu (Microsoft Research), B. Batson (Intel Corporation)

23.2 Advanced Techniques for RTL Debugging .......................................................................362 Y.-C. Hsu, B. Tabbara, Y.-A. Chen, F. Tsai (Novas Software Incorporated)

23.3 Behavioral Consistency of C and Verilog Programs Using Bounded Model Checking ........................................................................................................................368 E. Clarke, D. Kroening, K. Yorav (Carnegie Mellon University)

23.4 Re-Use-Centric Architecture for a Fully Accelerated Testbench Environment .......372 R. Henftling, A. Zinn, M. Bauer, M. Zambaldi, W. Ecker (Infineon Technologies AG)

SESSION 24: Delay and Noise Modeling in the Nanometer Regime Chair: Vasant Rao (IBM Corporation) Organizers: Chandu Visweswariah, Narendra V Shenoy

24.1 An Effective Capacitance Based Driver Output Model for On-Chip RLC Interconnects ...................................................................................................................376 K. Agarwal, D. Sylvester, D. Blaauw (University of Michigan)

24.2 Delay and Slew Metrics Using the Lognormal Distribution ..........................................382 C. J. Alpert, F. Liu, C. Kashyap, A. Devgan (IBM Corporation)

24.3 Blade & Razor: Cell and Interconnet Delay Analysis Using Current-Based Models ................................................................................................386 J. F. Croix (Silicon Metrics Corporation), D. F. Wong (University of Illinois at Urbana-Champaign)

24.4 Non-Iterative Switching Window Computation for Delay-Noise ..................................390 B. Thudi, D. Blaauw (University of Michigan)

SESSION 25: Modeling Issues in the Design of Embedded Systems Wolfgang Rosenstiel (University of Tubingen) Organizers: Annette Reutter, Donatella Sciuto

25.1 Architecture-Level Performance Evaluation of Component-Based Embedded Systems .................................................................................................................396 J. T. Russell, M. F. Jacome (University of Texas at Austin)

25.2 An IDF-based Trace Transformation Method for Communication Refinement........402 A. D. Pimentel, C. Erbas (University of Amsterdam)

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25.3 Schedulers as Model-Based Design Elements in Programmable Heterogeneous Multiprocessors ........................................................408 J. M. Paul, A. Bobrek, J. E. Nelson, J. J. Pieper, D. E. Thomas (Carnegie Mellon University)

25.4 A Complexity Effective Communication Model for Behavioral Modeling of Signal Processing Applications ......................................................................................412 S. Kiran, M. N. Jayram (Indian Institute of Technology Delhi), P. Rao, S. K. Nandy (Indian Institute of Science)

SESSION 26: Special Session — How Application/Technology Evolutions Will Shape Classical EDA? Chair & Organizer: Ahmed Jerraya (TIMA Laboratory)

26.1 Leading-Edge and Future Design Challenges-Is the Classical EDA Ready? ...........416 G. Spirakis (Intel Corporation)

26.2 How to Make Efficient Communication, Collaboration, and Optimization from System to Chip ..............................................................................417 A. Matsuzawa (Tokyo Institute of Technology)

26.3 System-on-Chip Beyond the Nanometer Wall ..................................................................419 P. Magarshack, P. G. Paulin (STMicroelectronics)

26.4 Panel Discussion of Special Session 26: Platform Based Design vs. Network on Chip

SESSION 27: SAT and BDD Algorithms for Verification Tools Chair: Robert Damiano (Synopsys, Incorporated) Organizers: Carl Pixley, Hikeung T. Ma, Shin-ichi Minato

27.1 A Hybrid SAT-Based Decision Procedure for Separation Logic with Uninterpreted Functions ...............................................................................................425 S. A. Seshia, S. K. Lahiri, R. E. Bryant (Carnegie Mellon University)

27.2 Symbolic Representation with Ordered Function Templates.......................................431 A. Goel (Carnegie Mellon University), G. Hasteer (Innologic Systems), R. E. Bryant (Carnegie Mellon University)

27.3 A Signal Correlation Guided ATPG Solver and Its Applications for Solving Difficult Industrial Cases ..................................................................................436 F. Lu, L.-C. Wang, K.-T. Cheng (University of California at Santa Barbara), J. Moondanos, Z. Hanna (Intel Corporation)

27.4 Solving the Latch Mapping Problem in an Industrial Setting .......................................442 K. Ng (University of British Columbia), M. R. Prasad, R. Mukherjee, J. Jain (Fujitsu Laboratories of America)

SESSION 28: Elements of Functional and Performance Analysis Chair: Rolf Ernst (Technical University of Braunschweig) Organizers: Annette Reutter, Margarida Jacome

28.1 Static Analysis of Transaction-Level Models....................................................................448 G. Agosta, F. Bruschi, D. Sciuto (Politecnico di Milano Italy)

28.2 Enabling Scheduling Analysis of Heterogeneous Systems with Multi-Rate Data Dependencies and Rate Intervals .................................................454 M. Jersak, R. Ernst (Technical University of Braunschweig)

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28.3 Automatic Trace Analysis for Logic of Constraints ........................................................460 X. Chen, H. Hsieh (Uniersity of California at Riverside), F. Balarin, Y. Watanabe (Cadence Berkeley Laboratories)

28.4 Accurate Timing Analysis by Modeling Caches, Speculation and Their Interaction ...............................................................................................................466 X. Li, T. Mitra, A. Roychoudhury (National University of Singapore)

SESSION 29: Nonlinear Model Order Reduction Chair: Luca Daniel (Massachusetts Institute of Technology) Organizer: Kartikeya Mayaram

29.1 NORM: Compact Model Order Reduction of Weakly Nonlinear Systems..................472 P. Li, L. T. Pileggi (Carnegie Mellon University)

29.2 Analog and RF Circuit Macromodels for System-Level Analysis................................478 X. Li, P. Li, Y. Xu, L. T. Pileggi (Carnegie Mellon University)

29.3 Piecewise Polynomial Nonlinear Model Reduction.........................................................484 N. Dong, J. Roychowdhury (University of Minnesota)

29.4 A TBR-based Trajectory Piecewise-Linear Algorithm for Generating Accurate Low-order Models for Nonlinear Analog Circuits and MEMS .....................490 D. Vasilyev, M. Rewieński, J. White (Massachusetts Institute of Technology)

SESSION 30: Novel Techniques in High-Level Synthesis Chair: Christophe Wolinski (Los Alamos National Laboratory) Organizers: Gila Kamhi, Krzysztof Kuchcinski

30.1 Toward Efficient Static Analysis of Finite-Precision Effects in DSP Applications via Affine Arithmetic Modeling.......................................................496 C. F. Fang, R. A. Rutenbar, M. Püschel, T. Chen (Carnegie Mellon University)

30.2 Automating the Design of an Asynchronous DLX Microprocessor............................502 M. Amde (Indian Institute of Technology), I. Blunno (Politecnico di Torino), C. P. Sotiriou (FORTH)

30.3 High-Level Synthesis of Asynchronous Systems by Data-Driven Decomposition.............................................................................................508 C. G. Wong, A. J. Martin (California Institute of Technology)

30.4 Using Estimates from Behavioral Synthesis Tools in Compiler-Directed Design Space Exploration .............................................................514 B. So, P. C. Diniz, M. W. Hall (University of Southern California at Los Angeles)

SESSION 31: Mixed-Signal Design and Simulation Chair: Alan Mantooth (University of Arkansas) Organizer: David Allstot

31.1 A 16-Bit Mixed-Signal Microsystem with Integrated CMOS-MEMS Clock Reference .......................................................................................................................520 R. M. Senger, E. D. Marsman, M. S. McCorquodale, F. H. Gebara, K. L. Kraver, M. R. Guthaus, R. B. Brown (University of Michigan)

31.2 Fractional-N Frequency Synthesizer Design at the Transfer Function Level Using a Direct Closed Loop Realization Algorithm..............................................526 C. Y. Lau, M. H. Perrott (Massachusetts Institute of Technology)

31.3 Characterizing the Effects of Clock Jitter Due to Substrate Noise in Discrete-Time ∆/Σ Modulators..........................................................................................532 P. Heydari (University of California at Irvine)

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31.4 Computation of Noise Spectral Density in Switched Capacitor Circuits using the Mixed-Frequency-Time Technique....................................................................538 V. Vasudevan, M. Ramakrishna (Indian Institute of Technology)

31.5 Symbolic Analysis of Analog Circuits with Hard Nonlinearity .....................................542 A. Manthe, Z. Li, C.-J. R. Shi (University of Washington)

SESSION 32: Panel — Nanometer Design: Place Your Bets............................................546 Chair: Andrew B. Kahng (University of California at San Diego) Organizers: Gloria Nichols, Bing Sheu Panelists: S. Borkar (Intel Corporation), J. Cohn (IBM Corporation), A. Domic (Synopsys, Incorporated), P. Groeneveld (Magma Design Automation), L. Scheffer (Cadence Design Systems, Incorporated), Christophe Frey (STMicroelectronics)

SESSION 33: Novel Self-Test Methods Chair: Janusz Rajski (Mentor Graphics Corporation) Organizers: Tim Cheng, TM Mak

33.1 A Scalable Software-Based Self-Test Methodology for Programmable Processors..............................................................................................548 L. Chen (University of California at San Diego), S. Ravi, A. Raghunathan (NEC Laboratories America, Inc.), S. Dey (University of California at San Diego)

33.2 A Scan BIST Generation Method Using A Markov Source and Partial Bit-Fixing...............................................................................................................554 W. Li, C. Yu, S. M. Reddy (University of Iowa), I. Pomeranz (Purdue University)

33.3 Seed Encoding with LFSRs and Cellular Automata ........................................................560 A. A. Al-Yamani, E. J. McCluskey (Stanford University)

33.4 Efficient Compression and Application of Deterministic Patterns in a Logic BIST Architecture .................................................................................................566 P. Wohl, J. A. Waicukauski, S. Patel, M. B. Amin (Synopsys, Incorporated)

33.5 Ultimate Low Cost Analog BIST ...........................................................................................570 M. Negreiros, L. Carro, A. A. Susin (Universidade Federal do Rio Grande do Sul)

SESSION 34: Technology Mapping, Buffering, and Bus Design Chair: John Lillis (University of Illinois) Organizers: Charles J. Alpert, Dennis Sylvester, Raymond Nijssen

34.1 Gain-Based Technology Mapping for Discrete-Size Cell Libraries .............................574 B. Hu (University of California at Santa Barbara), Y. Watanabe, A. Kondratyev (Cadence Berkeley Laboratories), M. Marek-Sadowska (University of California at Santa Barbara)

34.2 An O(nlogn) Time Algorithm for Optimal Buffer Insertion ............................................580 W. Shi, Z. Li (Texas A&M University)

34.3 Optimum Positioning of Interleaved Repeaters in Bidirectional Buses ....................586 M. Ghoneima, Y. Ismail (Northwestern University)

34.4 Synthesizing Optimal Filters for Crosstalk-cancellation for High-Speed Buses.....592 J. Ren, M. Greenstreet (University of British Columbia)

SESSION 35: Compilation Techniques for Reconfigurable Devices Chair: Ryan Kastner (University of California at Santa Barbara) Organizers: Jens Palsberg, Scott Hauck

35.1 Fast Timing-driven Partitioning-based Placement for Island Style FPGAs ..............598 P. Maidee, C. Ababei, K. Bazargan (University of Minnesota)

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35.2 Global Resource Sharing for Synthesis of Control Data Flow Graphs on FPGAs..604 S. O. Memik, G. Memik, R. Jafari, E. Kursun (University of California at Los Angeles)

35.3 Compiler-Generated Communication for Pipelined FPGA Applications ...................610 H. E. Ziegler, M. W. Hall, P. C. Diniz (University of Southern California at Los Angeles)

35.4 Data Communication Estimation and Reduction for Reconfigurable Systems .......616 A. Kaplan, P. Brisk (University of California at Los Angeles), R. Kastner (University of California at Santa Barbara)

SESSION 36: Architectural Power Estimation and Optimization Chair: Vijay Narayanan (Penn State University) Organizer: Chaitali Chakrabarti

36.1 Clock-Tree Power Optimization based on RTL Clock-Gating.......................................622 M. Donno (BullDAST s.r.l.), A. Ivaldi (Politecnico de Torino), L. Benini (Università di Bologna), E. Macii (Politecnico di Torino)

36.2 Low-Power Design Methodology for an On-chip Bus with Adaptive Bandwidth Capability ...................................................................................628 R. Bashirullah (North Carolina State University), W. Liu (University of California at Santa Cruz), R. K. Cavin (Semiconductor Research Corporation)

36.3 Power-Aware Issue Queue Design for Speculative Instructions .................................634 T. Moreshet, R. I. Bahar (Brown University)

36.4 State-Based Power Analysis for Systems-on-Chip .........................................................638 R. A. Bergamaschi (IBM Thomas J. Watson Research Center), Y. W. Jiang (University of California at Berkeley)

SESSION 37: Panel — Libraries: Lifejacket or Straitjacket...............................................642 Chair: Carl Sechen (University of Washington) Organizers: Chandu Visweswariah, Gerard Mas Panelists: B. Chappel (Intel Corporation), J. Hogan (Artisan Components, Incorporated), A. Moore (TSMC), T. Nakamura (STARC), G. Northrop (IBM Corporation), A. Thakar (Synopsys, Incorporated)

SESSION 38: Techniques for Reconfigurable Logic Applications Chair: Michael Butts (Cadence Design Systems, Incorporated) Organizers: Majid Sarrafzadeh, Scott Hauck

38.1 Switch-Level Emulation ..........................................................................................................644 A. Ejlali, S. G. Miremadi (Sharif University of Technology)

38.2 Designing Fault Tolerant Systems into SRAM-based FPGAs ......................................650 F. Lima (Universidade Federal do Rio Grande do Sul & Universidade Estadual do Rio Grande do Sol), L. Carro, R. Reis (Universidade Estadual do Rio Grande do Sul)

38.3 Determining Appropriate Precisions for Signals in Fixed-Point IIR Filters ..............656 J. Carletta, R. Veillette, F. Krach, Z. Fang (University of Akron)

SESSION 39: Test and Diagnosis for Complex Designs Chair: Rathish Jayabharathi, (Intel Corporation) Organizers: Seiji Kajihara, TM Mak

39.1 Test Generation for Designs with Multiple Clocks ..........................................................662 X. Lin, R. Thompson (Mentor Graphics Corporation)

39.2 Enhancing Diagnosis Resolution for Delay Defects Based Upon Statistical Timing and Statistical Fault Models ................................................................668 A. Krstic, L.-C. Wang, K.-T. Cheng (University of California at Santa Barbara), J.-J. Liou (Tsing-Hua University), T. M. Mak (Intel Corporation)

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39.3 Using Embedded Infrastructure IP for SOC Post-Silicon Verification .......................674 Y. Huang, W.-T. Cheng (Mentor Graphics Corporation)

39.4 Using Satisfiability in Application-Dependent Testing of FPGA Interconnects.......678 M. B. Tahoori (Stanford University)

SESSION 40: Special Session — Highlights of ISSCC: High-Speed Heterogenous Design Techniques Chair: Paul Zuchowski (IBM Microelectronics) Organizers: Limor Fix, Luciano Lavagno

40.1 Design of a 10GHz Clock Distribution Network Using Coupled Standing-Wave Oscillators ....................................................................................................682 F. O'Mahony (Stanford University), C. P. Yue (Aeluros, Incorporated), M. A. Horowitz, S. S. Wong (Stanford University)

40.2 Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL ...............................................................................................................688 J. G. Maneatis, J. Kim, I. McClatchie (True Circuits, Incorporated), J. Maxey, M. Shankaradas (Texas Instruments Incorporated)

40.3 A Reconfigurable Signal Processing IC with Embedded FPGA and Multi-Port Flash Memory ................................................................................................691 M. Borgatti, L. Calì, G. De Sandre, B. Forêt, D. Iezzi, F. Lertora, G. Muzzi, M. Pasotti, M. Poles, P.L. Rolandi (STMicroelectronics)

SESSION 41: Special Session — Highlights of ISSCC and The Design of State-of-the-Art Microprocessors Chair: Noel Menezes (Intel Corporation) Organizers: Limor Fix and Luciano Lavagno

41.1 Physical Synthesis Methodology for High Performance Microprocessors ..............696 Y.-H. Chan (IBM Server Group), P. Kudva, L. Lacey, G. Northrop (IBM Thomas J. Watson Research Center), T. Rosser (IBM Server Group)

41.2 A 1.3GHz Fifth Generation SPARC64 Microprocessor ...................................................702 H. Ando, Y. Yoshida, A. Inoue, I. Sugiyama, T. Asakawa, K. Morita, T. Muta, T. Motokurumada, S. Okada, H. Yamashita, Y. Satsukawa, A. Konmoto, R. Yamashita, H. Sugiyama (Fujitsu Ltd.)

41.3 A 1.5GHz Third Generation Itanium® 2 Processor............................................................706 J. Stinson, S. Rusu (Intel Corporation)

SESSION 42: Panel — Formal Verification — Prove It or Pitch It...................................710 Chair: Rajesh Gupta (University of California at San Diego) Organizers: Shishpal Rawat (Intel Corporation), Sandeep Shukla (Virginia Technology) Panelists: B. Bailey (Mentor Graphics Corporation), D. Beece (IBM Corporation), M. Fujita (Tokyo University), C. Pixley (Synopsys, Incorporated), J. O’Leary (Intel Corporation), F. Somenzi (University of Colorado at Boulder)

SESSION 43: High Frequency Interconnect Modeling Chair: Charlie C. P. Chen (University of Wisconsin) Organizers: Bernard N Sheehan, Byron L. Krauter

43.1 Algorithms in Fastlmp: A Fast and Wideband Impedance Extraction Program For Complicated 3-D Geometries .......................................................................712 Z. Zhu, B. Song, J. White (Massachusetts Institute of Technology)

43.2 Vector Potential Equivalent Circuit Based on PEEC Inversion ....................................718 H. Yu, L. He (University of California at Los Angeles)

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43.3 On-chip Interconnect-Aware Design and Modeling Methodology, Based on High Bandwidth Transmission Line Devices .................................................724 D. Goren, M. Zelikson, R. Gordin, I. A. Wagner, A. Barger, A. Amir, B. Livshitz, A. Sherman (IBM Haifa Research and Development Laboratories), Y. Tretiakov (IBM Design Automation), R. Groves, J. Park (IBM SiGe Model Development), D. Jordan, S. Strang, R. Singh, C. Dickey, D. Harame (IBM Design Automation)

43.4 An Adaptive Window-Based Susceptance Extraction and its Efficient Implementation...........................................................................................728 G. Zhong, C.-K. Koh, V. Balakrishnan, K. Roy (Purdue University)

SESSION 44: Novel Approaches in Test Cost Reduction Chair: Yervant Zorian (Virage Logic) Organizers: Erik Jan Marinissen, Seiji Kajihara

44.1 Test Application Time and Volume Compression through Seed Overlapping ........732 W. Rao (University of California at San Diego), I. Bayraktaroglu (Sun Microsystems), A. Orailoglu (University of California at San Diego)

44.2 Test Cost Reduction for SOCs Using Virtual TAMs and Lagrange Multipliers ........738 A. Sehgal (Duke University), V. Iyengar (IBM Microelectronics), M. D. Krasniewski, K. Chakrabarty (Duke University)

44.3 A Cost-Effective Scan Architecture for Scan Testing with Non-Scan Test Power and Test Application Cost ...............................................................................744 D. Xiang, S. Gu, J.-G. Sun (Tsinghua University), Y.-L. Wu (Chinese University of Hong Kong)

44.4 On Test Data Compression and n-Detection Test Sets..................................................748 I. Pomeranz (Purdue University), S. M. Reddy (University of Iowa)

SESSION 45: Retargetable Tools for Embedded Software Chair: Heinrich Meyr (RWTH) Organizers: Anand Raghunathan, Lothar Thiele

45.1 A Retargetable Micro-architecture Simulator ...................................................................752 W. S. Mong, J. Zhu (University of Toronto)

45.2 Instruction Set Compiled Simulation: A Technique for Fast and Flexible Instruction Set Simulation .............................................................................758 M. Reshadi, P. Mishra, N. Dutt (University of California at Irvine)

45.3 Automated Synthesis of Efficient Binary Decoders for Retargetable Software Toolkits ......................................................................................764 W. Qin, S. Malik (Princeton University)

SESSION 46: Special Session — ASIC Design in Nanometer Era - Dead or Alive? Chair: Nancy Nettleton (Sun Microsystems) Organizers: Abhijit Dharchoudhury, Sachin S. Sapatnekar

46.1 Designing Mega-ASICs in Nanogate Technologies.........................................................770 D. E. Lackey, P. S. Zuchowski, J. Koehl (IBM Microelectronics Division)

46.2 Architecting ASIC Libraries and Flows in Nanometer Era ............................................776 C. Bittlestone, A. Hill, V. Singhal, N. V. Arvind (Texas Instruments Incorporated)

46.3 Exploring Regular Fabrics to Optimize the Performance-Cost Trade-Off † ...............782 L. Pileggi, H. Schmit, A. J. Strojwas, P. Gopalakrishnan, V. Kheterpal, A. Koorapaty, C. Patel, V. Rovner, K. Y. Tong (Carnegie Mellon University)

46.4 Pushing ASIC Performance in a Power Envelope ...........................................................788 R. Puri, L. Stok (IBM Thomas J. Watson Research Center), J. Cohn (IBM Microelectronics), D. Kung, D. Pan (IBM Thomas J. Watson Research Center), D. Sylvester, A. Srivastava, S. Kulkarni (University of Michigan)

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SESSION 47: Floorplanning and Placement Chair: Carl Sechen (University of Washington) Organizers: C. Y. Roger Chen, Ralph Otten

47.1 An Algebraic Multigrid Solver for Analytical Placement with Layout Based Clustering...............................................................................................794 H. Chen, C.-K. Cheng (University of California at San Diego), N.-C. Chou (Mentor Graphics Corporation), A. B. Kahng (University of California at San Diego), J. F. MacDonald, P. Suaris (Mentor Graphics Corporation), B. Yao, Z. Zhu (University of California at San Diego)

47.2 Wire Length Prediction based Clustering and its Application in Placement............800 B. Hu, M. Marek-Sadowska (University of California at Santa Barbara)

47.3 Dynamic Global Buffer Planning Optimization Based on Detail Block Locating and Congestion Analysis........................................................806 Y. Ma, X. Hong, S. Dong, S. Chen, Y. Cai (Tsinghua University), C. K. Cheng (University of California at San Diego), J. Gu (University of Hong Kong)

47.4 Multilevel Floorplanning/Placement for Large-Scale Modules Using B*-trees ........812 H.-C. Lee (Synopsys, Incorporated), Y.-W. Chang (National Taiwan University), J.-M. Hsu (National Center for High-Performance Computing), H. H. Yang (Intel Corporation)

SESSION 48: Advances in SAT Chair: Per Bjesse (Synopsys, Incorporated) Organizers: Karem A. Sakallah, Rajeev Ranjan

48.1 Checking Satisfiability of a Conjunction of BDDs ...........................................................818 R. Damiano, J. Kukula (Synopsys, Incorporated)

48.2 Learning from BDDs in SAT-based Bounded Model Checking....................................824 A. Gupta, M. Ganai (NEC Laboratories America, Incorporated), C. Wang (University of Colorado at Boulder), Z. Yang, P. Ashar (NEC Laboratories America, Incorporated)

48.3 A Fast Pseudo-Boolean Constraint Solver........................................................................830 D. Chai (University of California at Berkeley) A. Kuehlmann (Cadence Berkeley Laboratories)

48.4 Shatter: Efficient Symmetry-Breaking for Boolean Satisfiability.................................836 F. A. Aloul, I. L. Markov, K. A. Sakallah (University of Michigan)

48.5 SAT-Based Unbounded Symbolic Model Checking ........................................................840 H.-J. Kang, I.-C. Park (KAIST)

SESSION 49: Novel Design Methodologies and Signal Integrity Chair: Sharad Mehrotra (Sun Microsystems) Organizers: Abhijit Dharchoudhury, Noel Menezes

49.1 Design of a 17-million Gate Network Processor using a Design Factory..................844 G.-E. Descamps, S. Bagalkotkar, S. Ganesan, S. Iyengar, A. Pirson (Silicon Access Networks Incorporated)

49.2 Hybrid Hierarchical Timing Closure Methodology for a High Performance and Low Power DSP ................................................................................................................850 K. Shi (Synopsys, Incorporated), G. Godwin (Texas Instruments, Incorporated)

49.3 Statistical Estimation of Leakage-Induced Power Grid Voltage Drop Considering Within-Die Process Variations ...........................................................856 I. A. Ferzli, F. N. Najm (University of Toronto)

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49.4 Temporofunctional Crosstalk Noise Analysis ..................................................................860 D. Chai (University of California at Berkeley), A. Kondratyev (Cadence Berkeley Laboratories), Y. Ran (University of California at Santa Barbara), K. H. Tseng (Cadence Design Systems, Incorporated), Y. Watanabe (Cadence Berkeley Laboratories), M. Marek-Sadowska (University of California at Santa Barbara)

49.5 Static Noise Analysis with Noise Windows .......................................................................864 K. Tseng, V. Kariat (Cadence Design Systems, Incorporated)

SESSION 50: Memory Optimization for Embedded Systems Chair: Marcello Lajolo (NEC Corporation) Organizer: Anand Raghunathan

50.1 Embedded Intelligent SRAM..................................................................................................869 P. Jain, G. E. Suh, S. Devadas (Massachusetts Institute of Technology)

50.2 Improved Indexing for Cache Miss Reduction in Embedded Systems ......................875 T. Givargis (University of California at Irvine)

50.3 Memory Layout Techniques for Variables Utilizing Efficient DRAM Access Modes in Embedded System Design ...................................................................881 Y. Choi, T. Kim (Korea Advanced Institute of Science & Technology Research Center)

50.4 Interprocedural Optimizations for Improving Data Cache Performance of Array-Intensive Embedded Applications ......................................................................887 W. Zhang, G. Chen, M. Kandemir (Pennsylvania State University), M. Karakoy (Imperial College)

SESSION 51: Special Session — Design Automation for Quantum Circuits Andreas Kuehlmann (Cadence Berkeley Laboratories) Organizers: Soha Hassoun, Igor L. Markov

51.1 Tutorial: Basic Concepts in Quantum Circuits.................................................................893 J. P. Hayes (University of Michigan)

51.2 Designing and Implementing Small Quantum Circuits and Algorithms ....................894 B. Travaglione (University of Cambridge)

SESSION 52: Energy-Aware System Design Chair: Sujit Dey (University of California at San Diego) Organizers: Kaushik Roy, Luca Benini

52.1 A Survey of Techniques for Energy Efficient On-Chip Communication....................900 V. Raghunathan, M. B. Srivastava (University of California at Los Angeles) R. K. Gupta (University of California at San Diego),

52.2 Extending the Lifetime of a Network of Battery-Powered Mobile Devices by Remote Processing: A Markovian Decision-based Approach................................906 P. Rong, M. Pedram (University of Southern California at Los Angeles)

52.3 Energy-Aware MPEG-4 FGS Streaming..............................................................................912 K. Choi (University of Southern California at Los Angeles), K. Kim (Seoul National University), M. Pedram (University of Southern California at Los Angeles)

52.4 A Low-Energy Chip-Set for Wireless Intercom.................................................................916 M. J. Ammer, M. Sheets, T. Karalar, M. Kuulusa, J. Rabaey (University of California at Berkeley)

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SESSION 53: Budgeting, Simulation and Statistical Timing Chair: Louis Scheffer (Cadence Design Systems, Incorporated) Organizers: Kenneth L. Shepard, Sudhakar Bobba

53.1 Optimal Integer Delay Budgeting on Directed Acyclic Graphs ....................................920 E. Bozorgzadeh, S. Ghiasi (University of California at Los Angeles), A. Takahashi (Tokyo Institute of Technology), M. Sarrafzadeh (University of California at Los Angeles)

53.2 Optimizations for a Simulator Construction System Supporting Reusable Components............................................................................................................926 D. A. Penry, D. I. August (Princeton University)

53.3 Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits ....932 J. A. G. Jess (Eindhoven University of Technology), K. Kalafala (IBM Microelectronics Division), S. R. Naidu, R. H. J. M. Otten (Eindhoven University of Technology), C. Visweswariah (IBM Thomas J. Watson Research Center)

SESSION 54: Interconnect Noise Avoidance Methodologies & Slew Rate Prediction Chair: Sani Nassif (IBM Corporation) Organizers: Byron L. Krauter, Sachin S. Sapatnekar

54.1 Interconnect and Noise Immunity Design for the Pentium® 4 Processor ..................938 R. Kumar (Intel Corporation)

54.2 Crosstalk Noise in FPGAs......................................................................................................944 Y. Ran, M. Marek-Sadowska (University of California at Santa Barbara)

54.3 Simple Metrics for Slew Rate of RC Circuits Based on Two Circuit Moments.........950 K. Agarwal, D. Sylvester, D. Blaauw (University of Michigan)

54.4 Post-Route Gate Sizing for Crosstalk Noise Reduction.................................................954 M. R. Becer (Motorola, Incorporated), D. Blaauw (Universiyt of Michigan Ann Arbor), I. Algor, R. Panda, C. Oh, V. Zolotov (Motorola), I. N. Hajj (University of Illinois Urbana-Champaign)

SESSION 55: Analog Design Space Exploration Chair: Richard Shi (University of Washington) Organizer: Georges G. Gielen

55.1 Performance Trade-off Analysis of Analog Circuits by Normal-Boundary Intersection........................................................................................958 G. Stehr, H. Graeb, K. Antreich (Technical University of Munich)

55.2 Support Vector Machines for Analog Circuit Performance Representation.............964 F. De Bernardinis, M. I. Jordan, A. Sangiovanni-Vincentelli (University of California at Berkeley)

55.3 Efficient Description of the Design Space of Analog Circuits......................................970 M. del Mar Hershenson (Barcelona Design, Incorporated)

55.4 Architectural Selection of A/D Converters ........................................................................974 M. Vogels, G. Gielen (Katholieke Universiteit Leuven)

Author Index ..........................................................................................................................................978

TECHNICAL PROGRAM CO-CHAIR (METHODS)Limor Fix Intel Semiconductors Ltd. PO Box 498 Haifa, 31000 Israel (972) 4-8655256limor.fix@intel.com

NEW INITIATIVES CHAIRIvo Bolsens Xilinx, Inc. 2100 Logic Dr. San Jose, CA 95124 (408) 626-5931 ivo.bolsens@xilinx.com

TUTORIAL CHAIREllen M. Sentovich Cadence Berkeley Labs. 2001 Addison St., 3rd Fl. Berkeley, CA 94704 (510) 647-2807ellens@cadence.com

ELECTRONIC MEDIA CHAIRSteven P. Levitan Univ. of Pittsburgh, Dept. of EE 348 Benedum Eng. Hall Pittsburgh, PA 15261 (412) 648-9663steve@ee.pitt.edu

TECHNICAL PROGRAMCO-CHAIR (TOOLS)Luciano Lavagno Cadence Berkeley Labs. 2001 Addison St., 3rd Fl. Berkeley, CA 94704 (510) 647-2810luciano@cadence.com

PAST CHAIRBryan AcklandAgere Systems, Inc.101 Crawfords Corner Rd. Rm. 4E-508 Holmdel, NJ 07733-1900 (732) 949-7248 bda@agere.com

PANEL CHAIRDavid Blaauw Univ. of Michigan Dept. of EECS 1301 Beal Ave. Ann Arbor, MI 48109-2122(734) 763-4526blaauw@umich.edu

EDA INDUSTRY CHAIRWilliam H. Joyner, Jr. Semiconductor Research Corp. PO Box 12053 Research Triangle Park, NC 27709 (919) 941-9472joyner@src.org

Executive CommitteeGENERAL CHAIRIan GetreuAmbric Inc.1225 NW Nurray Rd., Ste. 202Portland, OR 97229(503) 644-1544getreu@aol.com

VICE/FINANCE CHAIRSharad MalikPrinceton Univ., Dept. of EE Princeton, NJ 08544(609) 258-4625 sharad@ee.princeton.edu

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PUBLICITY CHAIRNanette Collins 37 Symphony Rd., Unit ABoston, MA 02115 (617) 437-1822 nanette@nvc.com

ASIA/S. PACIFICREPRESENTATIVEHidetoshi Onodera Kyoto Univ. Dept. of C/CE Sakyo-ku Kyoto 606-8501Japan (81) 75-753-5314onodera@i.kyoto-u.ac.jp

IEEE CAS REPRESENTATIVEGiovanni De Micheli Stanford Univ. Gates CS Bldg., Rm. 333 Stanford, CA 94305-9030 650) 725-3632nanni@galileo.stanford.edu

CONFERENCE MANAGERKevin LepineMP Associates, Inc.5305 Spine Rd., Ste. ABoulder, CO 80301(303) 530-4562kevin@dac.com

EUROPE/MIDDLE EASTREPRESENTATIVEAhmed A. Jerraya TIMA Lab. 46, Avenue Felix Viallet Grenoble Cedex, France F-38031 (33) 476-574759 ahmed.jerraya@imag.fr

ACM/SIGDAREPRESENTATIVERobert Walker Kent State Univ. Dept. of CS 351 Math & CS Bldg. Kent, OH 44242(330) 672-9105walker@cs.kent.edu

EDA CONSORTIUMREPRESENTATIVELarry EberleSynopsys, Inc.700 E. Middlefield Rd.Mountain View, CA 94043-4033(650) 584-4418leberle@synopsys.com

EXHIBITS MANAGERLee WoodMP Associates, Inc.5305 Spine Rd., Ste. ABoulder, CO 80301(303) 530-4562lee@dac.com

Executive Committee (cont.)

xx

Charles J. Alpert IBM Corp. Austin, TX

David Allstot Univ. of Washington

Seattle, WA

Luca Benini Deis Univ. Di Bologna

Bologna, Italy

Sudhakar Bobba Sun Microsystems

Sunnyvale, CA

Jo Dale Carothers Univ. of Arizona

Tucson, AZ

Chaitali Chakrabarti Arizona State Univ.

Tempe, AZ

C. Y. Roger Chen Syracuse Univ. Syracuse, NY

Tim Cheng Univ. of California Santa Barbara, CA

Pai H. Chou Univ. of California

Irvine, CA

Anirudh Devgan IBM Corp. Austin, TX

Abhijit Dharchoudhury Intel Corp. Austin, TX

Marco Di Natale Univ. of Pisa Pisa, Italy

Masahiro Fujita Univ. of Tokyo Tokyo, Japan

Georges G. Gielen Katholieke Univ. Leuven, Belgium

Soha Hassoun Tufts Univ.

Medford, MA

Scott Hauck Univ. of Washington

Seattle, WA

Steve Haynal Intel Corp.

Hillsboro, OR

Margarida F. JacomeUniv. of Texas

Austin, TX

Ahmed A. Jerraya TIMA

Grenoble Cedex, France

Seiji Kajihara Kyushyu Institute of Tech.

Iizuka, Japan

Gila Kamhi Intel Corp.

Haifa, Israel

Imin Kao State Univ. of New York

Stony Brook, NY

Kurt Keutzer Univ. of California

Berkeley, CA

Taewhan Kim KAIST

Daejon, Republic of Korea

Byron L. Krauter IBM Corp. Austin, TX

Krzysztof Kuchcinski Lund Institute of Tech.

Lund, Sweden

Technical Program CommitteeLimor Fix

Technical Program Co-ChairIntel Semiconductors Ltd.

limor.fix@intel.com

Luciano LavagnoTechnical Program Co-Chair

Cadence Berkeley Labs.luciano@cadence.com

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Hikeung T. Ma Synopsys, Inc.

Mountain View, CA

Enrico Macii Politecnico Di Torino

Torino, Italy

Jan MadsenTechnical Univ. of Denmark

Lyngby, Denmark

T. M. Mak Intel Corp.

Santa Clara, CA

Erik Jan Marinissen Philips Research Labs.

Eindhoven, The Netherlands

Grant E. Martin Cadence Design Systems, Inc.

Berkeley, CA

Kartikeya Mayaram Oregon State Univ.

Corvallis, OR

Renu Mehra Synopsys, Inc.

Mountain View, CA

Noel Menezes Intel Corp.

Hillsboro, OR

Shin-Ichi Minato NTT Network Innovation Labs.

Yokosuka-Shi, Japan

Raymond Nijssen Magma Design Automation, Inc.

Cupertino, CA

Steven Nowick Columbia Univ. New York, NY

Altan OdabasiogluSynopsys, Inc.

Austin, TX

Ralph H.J.M. Otten Delft Univ. of Technology

Delft, The Netherlands

Jens Palsberg Purdue Univ.

West Lafayette, IN

Marek Perkowski KAIST

Daejeon, Republic of Korea

Carl Pixley Synopsys, Inc. Hillsboro, OR

Anand Raghunathan NEC Corp.

Princeton, NJ

Rajeev Ranjan Real Intent

Santa Clara, CA

Annette Reutter Robert Bosch GmbH Reutlingen, Germany

Kaushik Roy Purdue Univ.

West Lafayette, IN

Karem A. Sakallah Univ. of Michigan

Ann Arbor, MI

Sachin S. Sapatnekar Univ. of Minnesota Minneapolis, MN

Majid Sarrafzadeh Univ. of California Los Angeles, CA

Donatella Sciuto Politecnico Di Milano

Milano, Italy

Carl Sechen Univ. of Washington

Seattle, WA

Bernard Sheehan Mentor Graphics Corp.

Wilsonville, OR

Narendra V. Shenoy Synopsys, Inc.

Bangalore, India

Technical Program Committee (continued)

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Kenneth L. Shepard Columbia Univ. New York, NY

Dennis Sylvester Univ. of Michigan

Ann Arbor, MI

Lothar Thiele ETH Zurich

Zuerich, Switzerland

Diederik Verkest IMEC

Leuven, Belgium

Kees Vissers Chameleon Systems Inc.

San Jose, CA

Chandu Visweswariah IBM Corp.

Yorktown Heights, NY

Sarma Vrudhula Univ. of Arizona

Tucson, AZ

Jacob White Massachusetts Institute of Tech. Cambridge, MAShane Bell

Intel Corp.

Dennis Brophy Model Technology, a Mentor Graphics Co.

Portland, OR

John Cohn IBM Microelectronics

Essex Junction, VT

Deirdre HanfordSynopsys, Inc.

Mountain View, CA

Peter HardeeCoWare, Inc.

Santa Clara, CA

Andrew B. Kahng Univ. of California at San Diego

La Jolla, CA

Gerard MasSTMicroelectronics

Crolles Cedex, France

Shishpal S. Rawat Intel Corp.

Folsom, CA

Rob A. Rutenbar Carnegie Mellon Univ.

Pittsburgh, PA

Kazuo YanoHitachi Central Research Lab.

Tokyo, Japan

Technical Program Committee (continued)

Panel Sub-Committee

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Shane BellIntel Corp.

Shrewsbury, MA

Charles ChenUniv. of Wisconsin

Madison, WI

James GoodmanEngim Canada, Inc.Ottawa, ON Canada

Payam HeydariUniv. of California

Irvine, CA

Rhonday Kay GaedeUniv. of Alabama

Huntsville, AL

John LockwoodWashington Univ.

St. Louis, MO

John LongDelft Univ. of Tech.

Delft, The Netherlands

Grant E. MartinCadence Berkeley Labs.

Berkeley, CA

Siva G. NarendraIntel Labs.

Hillsboro, OR

Patrick R. ShultzUniv. of Mannheim

Mannheim, Germany

Kenneth YangUniv. of CaliforniaLos Angeles, CA

Donna CastilloCadence Design Systems, Inc.

San Jose, CA

Nanette CollinsBoston, MA

Larry EberleSynopsys, Inc.

Mountain View, CA

Ian Getreu Portland, OR

William H. Joyner, Jr.Semiconductor Research Corp.

Research Triangle Park, NC

Darby Mason-MerchantXilinx, Inc.

San Jose, CA

Mark MillerTera Systems, Inc.

Campbell, CA

Tom Minot Golden Gate Tech.

San Jose, CA

Gabe MorettiEDN Worldwide/Reed Electronics Grp.

Venice, FL

Steve Pollock Anasift Technology, Inc.

San Jose, CA

Mindy Powers CoWare, Inc. San Jose, CA

Lee Wood MP Associates, Inc.

Boulder, CO

Student Design Contest JudgesDAC/ISSCC SDC Co-Chairs

David GreenhillSun Microsystems

Sunnyvale, CA

Steve LevitanUniv. of Pittsburgh

Pittsburgh, PA

Alan MantoothUniv. of ArkansasFayetteville, AR

DAC/ISSCC SDC Judges

Exhibitor Liaison Committee

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Opening Keynote Address

Sir Robin SaxbyChairmanARM Holdings plcCambridge, UK

<100nm...A Giant Leap for Mankind?

Moore's Law is predicted to continue its relentless pace for the next 15 or so years. By a series of smallsteps we have 100Mtr of ASIC capacity available today, and will have more than 1 billion within the nextfive years. The product opportunities presented by this opportunity will change our lives ... However withevery new opportunity come some new challenges. Rapidly escalating mask charges and wafer fabricationcosts will cause the shape of the semiconductor industry to change. The shake down of lead playersfocused on wafer foundry and others focused on IP building blocks will continue. The approach to totalsystem design will need to change with verification and validation becoming the biggest bottlenecks.

Design, long considered as a negligible amortized cost, has started to compete with fabrication costs! Butwhilst fabrication costs are rising as a square law, design costs are rising with at least a cubic law! For anindustry where FAB costs have dominated, this shift of emphasis over the next few years will shake thefoundations of our entire industry. What giant leap is required, how will the global landscape alter, whatare the emerging applications and can we take advantage of all those available transistors?

Biography: Sir Robin Saxby was involved in the founding of ARM and served as Chairman, President andChief Executive Officer since joining the company full-time in February 1991. In October 2001, he split therole of chairman and chief executive officer, becoming Executive Chairman while Warren East took on therole of Chief Executive Officer. Besides directing ARM, Robin was also appointed to the board of Glotelplc as a non-executive director in April 1999. Prior to this, he worked for five years for European SiliconStructures SA (ES2), where he was Vice-President of Northern Europe, Managing Director ES2 Limited andPresident of its USA affiliate US2. Between 1984 and 1986, Robin was Chief Executive Officer ofHenderson Security Systems Limited and before that, spent eleven years with Motorola Semiconductors ina variety of sales, marketing and engineering management roles. His early career was in design anddevelopment with Rank Bush Murphy and PyeTMC. Robin also served as Chairman of the OpenMicroprocessor Initiative Advisory Group, a European Union panel set up to advise on collaborative R&Dactivity in Europe. In 2000, Robin was awarded an honorary Doctorate D.Eng from Liverpool University.He was also appointed a visiting professor to his old Department of Electronics at the University. In July2001, he was awarded an honorary Doctorate D.Tech from Loughborough University. He was awarded aKnighthood in the 2002 New Year Honours for services to the Information Technology industry.

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Thursday Keynote Address

Alberto L. Sangiovanni-VincentelliProfessorUniv. of California, Berkeley, CA

The Tides of EDA

Giovan Battista Vico, a philosopher and historian who lived across the XVII and XVIII centuries, was the first tonote in his masterpiece “Scienza Nuova” (New Science) that the history of man and his endeavors follow a cyclicalpattern. Economies, as well as the power of nations, have exhibited a clear and cyclical behavior and EDA has notescaped this fundamental law. EDA technology advances have oscillated between verification and synthesis, theperception in the mind of the electronic design community of EDA has been rising and falling in a regular pattern,EDA companies have risen and declined, the consideration of the financial community for EDA has beenperiodically increasing and decreasing, and the algorithms used in EDA have swung from general purposetechniques borrowed from mathematics, computer science, operation research, and artificial intelligence, to ad hoctechniques that leverage the nature of the specific design problem to be solved. Yet, valuable sediment has beendeposited by these tides over the years. I will show that progress is achieved when new methodologies crystallize,with new tools and techniques acting as catalysts, that the construction of layers of abstraction are the steps thathave helped us reach new heights, that the progress of EDA technology has slowed down just when complexityhas reached levels never seen before. I will argue that the designer community must leave its traditional shores,under attack by the swarm of killer transistors, and sail towards a new world where transistors have been tamed.The EDAand the design communities must plan and build together the sturdy ships needed to traverse these stormyseas. The risks of this expedition must be born in equal parts by these two communities if we wish to reach theland of opportunity that technology unveils. The lack of systematic collaboration within the EDA community, andamong the EDA community and its various customers, poses a serious threat to the recovery of the electronicindustry. We cannot let this happen!Biography: Alberto Sangiovanni Vincentelli is Professor of Electrical Engineering and Computer Sciences at theUniversity of California at Berkeley where he has been on the faculty since 1976. He is a co-founder of Cadenceand Synopsys, the two leading companies in the area of Electronic Design Automation. He is the Chief TechnologyAdvisor of Cadence and sits on the Board of Directors of Cadence. He also sits on the boards of Sonics, Accentand Softface. He is a member of the HP Strategic Technology Advisory Board. He has consulted for a number ofcompanies including IBM, Intel, ATT, GTE, GE, Harris, Nynex, DEC, HP, Kawasaki Steel, Fujitsu, Sony, Hitachi,ST, Alcatel, BMW, Daimler-Chrysler, Magneti-Marelli, Bull. He is the Scientific Director of PARADES, aEuropean Group of Economic Interest funded in 1996 by Cadence, Magneti-Marelli, and ST. In 1981 he received the Distinguished Teaching Award of the University of California and in 1995 the worldwideGraduate Teaching Award of the IEEE (a Technical Field award for “inspirational teaching of graduate students”).He has received three Best Paper Awards (1982, 1983 and 1990) and a Best Presentation Award (1982) at theDesign Automation Conference, three best paper awards from the International VLSI conference, and is the co-recipient of the Guillemin-Cauer Award (1982-1983), the Darlington Award (1987-1988), and the Best PaperAward of the Circuits and Systems Society of the IEEE (1989-1990). He was the recipient of the 2001 EDAKaufman Award and of the 2002 Aristotle Award of the SRC. He is the author of over 600 papers and fifteen booksin the area of design methodologies and tools Dr. Sangiovanni-Vincentelli has been a fellow of the Institute ofElectrical and Electronics Engineers since 1982 and a Member of the National Academy of Engineering.

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Marie R. Pistilli Women in EDA Achievement AwardKaren Bartleson - Director of Interoperability, Synopsys, Inc., Mountain View, CAFor her significant contributions in helping women advance in the field of EDA technology.

Phil Kaufman AwardSponsored by IBM Corporation

The award honors an individual who has contributed to creating or driving technology advances that have hadmeasurable impact on the productivity of design engineers. The 2002 recipient:

Ronald Roher - Magma Design Automation, Cupertino, CA & Neolinear Inc., Pittsburhg, PA

2003 IEEE FellowsJohn Maxwell Cohn - IBM Microelectronics, Essex Junction, VTFor contributions to the development of CAD tools and design methodology for high-performance customintegrated circuits.

Rolf Ernst - Technical Univ. of Braunschweig, Braunschweig, GermanyFor contributions to hardware/software co-design and embedded system design automationAndreas Kuehlmann - Cadence Berkeley Labs., Berkeley, CAFor the development of formal equivalence checking technology and its successful application tomicroprocessor and ASIC designs.Sachin Suresh Sapatnekar - University of Minnesota, Minneapolis, MNFor contributions to the optimization of timing and layout in VLSI circuits.

IEEE CAS Society AwardsMac Van Valkenburg Award

Alan N. Willson, Jr. - University of California, Los Angeles, CAFor Major contributions to theory, design methods, and hardware implementation of nonlinear circuits anddigital signal processing algorithms, to graduate educations, and for leadership in the CAS Society.

Emanuel R. Piore AwardSponsored by IBM Corporation

Giovanni DeMicheli - Professor, Department of Electrical Engineering, Stanford University, Stanford, CAFor contributions to computer-aided synthesis of digital systems.

Guillemin-Cauer AwardSampled-Function Weighted Order Filters, IEEE Transactions on Circuits and Systems Part II: Analog andDigital Signal Processing, vol. 49, no. 1, pp. 1-10, January 2002.

Rui J. P. de Figueiredo - University of California, Irvine, CARemzi oten - Conexant Systems, Inc. Newport Beach, CA

Awards

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CAD Transactions Best Paper AwardAn Efficient Graph Representation for Arithmetic Circuit Verification, IEEE Transactions on Computer AidedDesign of Integrated Circuits and Systems, vol. 20, no. 12, pp. 1443-1454, December 2001.

Yirng-An Chen - Novas, Inc., San Jose, CaliforniaRandal E. Bryant - Carnegie Mellon University, Pittsburgh, Pennsylvania

VLSI Transactions Best Paper AwardA Clock Power Model to Evaluate Impact of Architectural and Technology Optimizations, IEEE Transactionson Very Large Scale Integration (VLSI) Systems, vol. 10, no. 6, pp. 844-855, December 2002.

David E. Duarte - Intel Corporation, Hillsboro, OregonN. Vijaykrishnan - Pennsylvania State University, University Park, PennsylvaniaMary Jane Irwin - Pennsylvania State University, University Park, Pennsylvania

The Association for Computing Machinery/Special Interest Group on Design Automation (ACM/SIGDA) presents its

Distinguished Service AwardJames Plusquellic - University of Maryland, Baltimore, MDFor exemplary service to ACM/SIGDA and the Design Automation Conference as director of the UniversityBooth program.

The P. O. Pistilli Undergraduate Scholarshipsfor Advancement in Computer Science and Electrical Engineering

The P. O. Pistilli Undergraduate Scholarships for Advancement in Computer Science and Electrical Engineering Theobjective of the P. O. Pistilli Scholarship program is to increase the pool of professionals in Electrical Engineering,Computer Engineering and Computer Science from under-represented groups (women, African American, Hispanic,Native American, and physically challenged). In 1989, ACM Special Interest Group on Design Automation (SIGDA)began providing the program. Beginning in 1993, the Design Automation Conference provided the funds for thescholarship and SIGDA continues to administer the program for DAC. DAC normally funds two or more $4000scholarships, renewable up to 5 years, to graduating high school seniors. In 1999 the IEEE Circuits and Systems Societyalso began to sponsor these scholarships.

The 2003 winners will be announced at the Conference. The 2002 winners were:

Sophy Zheng - attending the University of ChicagoJennifer Tietz - attending Purdue UniversityTaylor Schreck - attending Iowa StateYoo-Jin Kim - attending University of Texas at AustinJuan Chen - attending Carnegie Mellon UniversityElaine Louie - attending Rice UniversityYen Ling (Jenny) Liu - attending Cornell University

For more information about the P. O. Pistilli scholarship, please contact Dr. Cherrice Traver, ECE Dept., UnionCollege, Schenectady, NY 12308. email: traverc@union.edu

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Design Automation Conference Graduate Scholarships

Each year the Design Automation Conference sponsors several $24,000 scholarships to support graduateresearch and study in Design Automation (DA), with emphasis in “design and test automation of electronicand computer systems.” Each scholarship is awarded directly to a university for the Faculty Investigatorto expend in direct support of one or more DA graduate students.

The criteria for granting such a scholarship expanded in 1996 to include financial need. The criteria are:the academic credentials of the student(s); the quality and applicability of the proposed research; theimpact of the award on the DA program at the institution; and financial need. Preference is given toinstitutions that are trying to establish new DA research programs.Profs. Ramesh Karri, Dariusz Czarkowski, Thanos Stouraitis, Polytechnic University, Brooklyn, NY

Students: Kaijie Wu, Piyush MishraConcurrent Error Detection in Very Deep Sub-Micron VLSIProf. Sung Kyu Lim, Georgia Institute of Tech., Atlanta, GA

Students: Kyoung-Keun Lee, Jacob Rajkumar Minz, Pun Hang ShiuChip/Package Co-Design of Physical Layout for Fast and Reliable System-On-Packages

Information on next year’s DAC scholarship award program will be available on the DAC web page:http://www.dac.com.

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DAC 2003 Student Design Contest Winners

Operational Category:

1st Place A Computationally Efficient ASIC Implementation for the (Best Overall) Decoding of Space-Time Block Codes

Enver Cavus, Babak Daneshrad - Univ. of California, Los Angeles, CA

2nd Place A Low-Energy Chip-Set for Wireless Intercom (Session 52.2)Josie Ammer, Michael Sheets, Tufan C. Karalar, Mika Kuulusa, Jan Rabaey - Univ. of California, Berkeley, CA

3rd Place Energy-Aware Design of a Real-Valued FFTAlice Wang, Anantha Chandrakasan - Massachusetts Institute of Tech., Cambridge, MA

Conceptual Category:

1st Place A 16-Bit Mixed-Signal Microsystem with Integrated CMOS-MEMS Clock Reference (Session 31.1)Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Richard B. Brown - Univ. of Michigan, Ann Arbor, MI

2nd Place An Integrated Thermally-Based Microflow SensorMasoud Agah, Yang Li, Robert M. Senger, Kensall D. Wise -Univ. of Michigan, Ann Arbor, MI

Honorable Mention:

Towards A Button-Sized 1024-Site Wireless Cortical Microstimulating Array (Operational)Maysam Ghovanloo, Khalil Najafi - Univ. of Michigan, Ann Arbor, MI

Design Flow for HW/SW Acceleration Transparency in the ThumbPod SecureEmbedded System (Conceptual) (Session 5.1)David Hwang, Patrick Schaumont, Yi Fan, Alireza Hodjat, Bo Cheng Lai, Kazuo Sakiyama, Shenglin Yang, Ingrid Verbauwhede - Univ. of California, Los Angeles, CA

Analog Turbo Decoder Implemented in SiGe BiCMOS Technolgy (Conceptual)Wei Huang, Vinay Igure, Garrett Rose, Yan Zhang, Mircea Stan - Univ. of Virginia, Charlottesville, VA

Design of a High Performance Security Coprocessor (Conceptual)Yunqing Chen, Jun Cheng, Tsung Hsing Hu, Jerry Kao - Univ. of Michigan, Ann Arbor, MI

ReviewersA total of 491 manuscripts were submitted to the 2003 DAC. The Conference Executive and Technical ProgramCommittees wish to acknowledge the time and effort spent by the following people who reviewed thesemanuscripts and returned the review forms completed. Our thanks to all of those who participated and contributedto the success of the Conference.

Magdy AbadirAmit AgarwalDavid Allstot

Charles J. AlpertIuliana BacivarovFrancisco BaratSandro Bartolini

Robert BattenShabbir Batterywala

Michael BeattieLuca Benini

Michel BerkelaarSarvesh Bhardwaj

Per BjesseSudhakar Bobba

Aimen BouchhimaBruno BougardEri Brockmeyer

Mat BrownDennis BrylowSlava Bulach

Bogdan CarbunarJo Dale CarothersFrancky Catthoor

Eduard CernyWander O. Cesario

Meeyoung ChaChaitali ChakrabartiKuang-Chien ChenC.Y. Roger Chen

Tim ChengEli Chiprout

Aruna ChittorYoonseo Choi

Kaviraj ChopraPai H. Chou

Umakanta ChoudhuryEui-Young Chung

Ki-Seok ChungPasquale CocchiniRobert DamianoFlorentin DartuKenneth Davis

Geert DeconinckChristophe Del-Toso

Anirudh DevganAbhijit Dharchoudhury

Marco Di NataleAjit DingankarMonica Donno

Mohamed-Anouar DziriWolfgang EberleStephen EdwardsMarco EscalanteMasahiro Fujita

Paolo GaiVijay GangaramJoachim Gerlach

Georges G. GielenFlavius GruainMatt Guthaus

Pavan HanumoluRan Ha

Kevin HarerSoha HassounScott Hauck

John HavlicekSteve Haynal

Wolfgang HeinleJoerg Henkel

Yoshinobu HigamiStefaan HimpePei-Hsin Ho

Jin HouMilos Hrkic

Yutao Hu

Alessandro IvaldiMadhu Iyer

Mahesh A. IyerMargarida F. JacomeErik Jan Marinissen

Geert JanssenRathish Jayabharathi

Murali JayapalaAhmed A. Jerraya

Seiji KajiharaGila KamhiImin KaoEric Karl

Himanshu KaulPawel KentopfKurt KeutzerHyungil Kim

Sunil KimTaewhan Kim

Desmond KirkpatrickMichael Kishinevsky

Alfred KoelblVolodymyr Kratyuk

Byron L. KrauterVictor KravetsLobna Kriaa

Angela KrsticKrzysztof Kuchcinski

Prabhakar KudvaWocheol Kwon

Chong-Min KyungGauthier Lafruit

Mark LavinHarold Levy

Jipeng LiStan Liao

Lars LiebmannJacky Lin

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Giuseppe LipariFrank Liu

Xiang-Guang LiuChun-Gi Lyuh

Di MaZhe Ma

Hikeung T. MaAlberto MaciiEnrico MaciiJan Madsen

Hamid MahmoodiT.M. Mak

Freddy MangNazanin Mansouri

Pol MarchalTheo Marescaux

Gergana MarkovaAndrew MartinGrant E. Martin

Kartikeya MayaramSteven R. McMaster

Renu MehraBingfeng MeiNoel Menezes

Shin-ichi MinatoAlan Mishchenko

Yukiya MiuraMaher Mneimneh

Un-Ku MoonIn-Ho MoonMayur Naik

Krishna NandivadaNaren Narasimhan

Sani NassifGabriela NicolescuRaymond Nijssen

Steven NowickAdrian Nunez-Aldana

Altan OdabasiogluJan Oetjens

John O'LearyChee-Kian Ong

Ralph H.J.M. OttenAndrea PacelliJens Palsberg

Atanas ParashkevovIn-Cheol Park

Ganapathy ParthasarathySrinivas Patil

Marek PerkowskiJose Pineda de Gyvez

Carl PixleySofie Pollin

Massimo PoncinoFabrizio Pro

Anurag PulincherryVijay Raghunathan

Anand RaghunathanVishwa RamanRajeev Ranjan

Ravishankar RaoAnnette ReutterMichael RiepeKaushik RoyJeroen Rutten

Karem A. SakallahSabino Salerno

Sachin S. SapatnekarAdriano SarmentoMajid SarrafzadehPrashant SawkarPrashant SaxenaDonatella Sciuto

Carl SechenJewon Seo

Nikhil SharmaBernard SheehanHossein Sheini

Narendra V. ShenoyKenneth L. Shepard

Kuncheol ShinThomas R. Shiple

Robert ShreeveJose Silva

Eli SingermanXiaoyu Song

Ashish SrivastavaTed StanionMartin StarkKen StevensRob Sumners

Dennis SylvesterRadoslaw Szymanek

Ludovic TambourGabor Temes

Zvi TeremShashidhar Thakur

Lothar ThieleLukas Van Ginneken

Moshe VardiSven VerdoolaegeDiederik VerkestBart Vermeulen

Kees VissersChandu Visweswariah

Harald VrankenSarma VrudhulaYongtao WangJacob WhiteHannah Yang

Kai YangPeng YangJin Yang

Seung-Moon YooSungjoo Yoo

Wassim YoussefJun Yuan

Roberto ZafalonJinsong ZhangYunshan Zhu

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Reviewers (continued)

41st DESIGN AUTOMATION CONFERENCE®San Diego Convention Center, San Diego, CA • June 7-11, 2004

CALL FOR PAPERSDAC is the premier conference devoted to Design Automation (DA) and the application of DA tools in designing electronic systems. Fivetypes of submissions are invited: regular papers, special topic sessions, panels, tutorials, and design contest entries. Submissions should besubmitted electronically to www.dac.com. Panel and Tutorial suggestions are due NO later than November 3, 2003, 5:00 PM MST; allothers are due NO later than November 24, 2003, 5:00 PM MST.

Authors are invited to submit original technical papers describing recent and novelresearch or engineering developments in all areas of design automation. Topics ofinterest include, but are not limited to:DESIGN TOOLS TRACK:The Design Tools track (T) is devoted to contributions to the research anddevelopment of design tools and their supporting algorithms. Focus is on innovationof specific modeling, analysis and optimization techniques.T1.1 Electrical-level circuit and timing simulationT1.2 Discrete simulationT1.3 Static timing analysis and timing verificationT1.4 Power analysis and estimationT2.1 Testing, fault modeling and simulation, TPG, test validation and DFTT2.2 Transaction-level, RTL and gate-level modeling and validation: simulation,

equivalence checking, functional formal (and semi-formal) verification.

T3.1 RT-level design partitioning, physical floorplanning and placementT3.2 Global and detailed routing T3.3 Module generation, sizing and library optimizations, physical verification T4.1 Technology-independent, combinational logic synthesisT4.2 Technology-dependent logic synthesis, library mapping, cell-based-design,

interactions between logic design and layoutT4.3 Sequential and asynchronous logic synthesis and optimizationT4.4 System, logic and physical synthesis techniques for

reconfigurable computingT4.5 High-level synthesisT5.1 Interconnect and package modeling and extraction T5.2 Signal integrity and reliability analysisT5.3 Analog, mixed-signal, MEMS and/or RF design toolsT5.4 System-in-package design and integration toolsT5.5 Design for yield robustness; design-to-manufacturing interfaceT6.1 IP protection and reuse for designs, tools, and algorithmsT6.2 Frameworks, intertool communication, design environments and databasesDESIGN METHODS TRACK:The Design Methods track (M) deals with innovative methodologies for the designof electronic circuits and systems, as well as creative experiences with designautomation in state-of-the-art designs. Submissions for this track will be judged onhow innovatively tools are combined into a new methodology that is effectivelyapplied to real-world design problems. Papers focusing on algorithmic advances inmodeling, analysis and optimization should be submitted to the design tools track.

Design methodologies and case studies for specific design tasksM1.1 Design entry and specificationM1.2 Electrical-level simulation and modelingM1.3 Discrete simulation and modeling M1.4 Static timing and performance analysisM1.5 Functional design verificationM1.6 Testing, test generation and debuggingM1.7 Physical design, module generation, design for manufacturingM1.8 Logic synthesis, including interaction with physical synthesisM1.9 High-level and architectural synthesis

Design methodologies and case studies for specific application domains and platforms

M2.1 Overall design flows and methodologies for specific design applicationsM2.2 Configurable computing, FPGAs and rapid prototypingM2.3 Deep sub-micron: signal integrity, interconnect modeling and extractionM2.4 High-performance design: timing, clocking and power distributionM2.5 Low power designM2.6 Analog, mixed signal, and RF designM2.7 Process technology development, extraction, modeling and new devicesM2.8 MEMS, sensors, actuators

Integration and management of DA systemsM3.1 Management of DA systems, design interfaces, standardsM3.2 Distributed, networked, and collaborative designM3.3 Intellectual property, design re-use and design libraries

EMBEDDED SYSTEMS TOPICS:Embedded Systems are characterized by mixed hardware and software componentswith limited processing, I/O and storage resources. The increasing role played bysoftware components and their associated support introduces a host of new systemdesign issues. To focus on these, the 41st DAC will have embedded systemssessions covering both the "tools" and the "methods" aspects of the following topics:E1 Low-power design: compilation, scheduling and partitioningE2 Embedded software: retargetable compilation, memory/cache optimization,

real-time single-processor schedulingE3 HW/SW co-design: specification, modeling, co-simulation and

performance analysis, system-level scheduling and partitioningE4 Hardware and software platform design: IP-based design, communication

design, embedded HWE5 Case studies

All DAC Submissions must be made electronically using PDF format NO laterthan November 24, 2003, 5:00 PM MST. Reference the DAC web page(www.dac.com) for instructions on electronic submissions. Please submit 1PDF file:The paper should contain an abstract of approximately 60 words clearly stating thesignificant contribution, impact and results of the submission. The paper should beformatted in double columns with a minimum 10pt font, not to exceed 6 pagesincluding all figures, tables and references (format templates are available on theDAC web site for your convenience, but are not required). Submissions exceedingthe 6 page limit, fonts smaller than 10pt, or identifying the authors or their affiliationwill be automatically rejected. The following information will be needed when submitting your paper:• Name, affiliation, and complete address for each author• A designated contact person including his/her phone #, fax #, and email address • A designated presenter, should the paper be accepted• A list of topic numbers preceded by the letter T (Tools Track), M (Methods

Track), or E (Embedded Systems Topic) ordered by relevancy, most clearlymatching the content of the paper

• The following statement: “All appropriate organizational approvals for thepublication of this paper have been obtained. If accepted, the author(s) willprepare the final manuscript in time for inclusion in the ConferenceProceedings and will present the paper at the Conference”.

• Authors of accepted papers must sign a copyright release form for their paper.Authors must also provide MPAssociates a copy of their presentation materialsand grant permission for the publication of the presentation and presentationmaterials on the DAC web site.

To permit a blind review, do not include name(s) or affiliation(s) of theauthor(s) on the manuscript, abstract or bibliographic citations. The paperswill be reviewed as finished papers. Preliminary submissions will be at adisadvantage. Notice of acceptance will be emailed to the contact person byMarch 12, 2004.

Panel and tutorial suggestions should not exceed two pages, should describe thetopic and intended audience, and should include a list of suggested participants.Tutorial suggestions must include a bulleted outline of covered topics. DACreserves the right to restructure submitted panel and tutorial suggestions, includingparticipants. Panel and tutorial suggestions may be electronically submitted byNovember 3, 2003.

Students are invited to submit descriptions of original electronic designs, eithercircuit level or system level. Submissions should contain the title of the project, a60-word abstract and a complete description of the design, not exceeding 4000words. The submission should clarify the originality, distinguishing features, andmeasured performance of the design. Two categories of designs are eligible forawards, operational and conceptual. For operational designs, proof-of-implementation is required, while for conceptual designs, complete simulation isnecessary. Designs must have taken place as part of the students' work at theuniversity and must have been completed after June 2002. Submitted designs shouldnot have received awards in other contests. Selected designs will be presented at theconference. These submissions must be electronically submitted NO LATERTHAN December 12, 2003 (5:00pm MST).

TOPICS OF INTEREST

REQUIREMENTS FOR SUBMISSIONS

PANELS, TUTORIALS, SPECIAL TOPICS

STUDENT DESIGN CONTEST

FOR INFORMATION CALL: 303-530-4333

Author/Panelist Index

A Ababei, C.......................................598 Abdi, S...........................................300 Acar, E...........................................109 Agarwal, A. ...................................348 Agarwal, K. ...........................376, 950 Agosta, G.......................................448 Albin, K.........................................296 Algor, I. .........................................954 Aloul, F. A. ...................................836 Alpert, C. J. ...................................382 Al-Yamani, A. A...........................560 Amde, M. ......................................502 Amin, C. S.............................226, 232 Amin, M. B. ..................................566 Amir, A. ........................................724 Amlani, I. ......................................276 Ammer, M. J. ................................916 Ando, H. ........................................702 Antreich, K....................................958 Arvind, N. V..................................776 Asakawa, T....................................702 Ashar, P. ........................................824 Atasu, K.........................................256 August, D. I. ..................................926 Aziz, A. .........................................296

B Bagalkotkar, S...............................844 Bahar, R. I. ....................................634 Bailey, B........................................710 Balakrishnan, V.............................728 Balarin, F.......................................460 Barger, A. ......................................724 Bashirullah, R................................628 Batson, B. ......................................356 Bauer, M........................................372 Bayraktaroglu, I. ...........................732 Bazargan, K...................................598 Becer, M. R. ..................................954 Beece, D. .......................................710 Benini, L..................................36, 622 Beraudo, G. ...................................196 Bergamaschi, R. A. .......................638 Bernier, J. ........................................91 Bernstein, G. H. ............................268 Bernstein, K. ...................................15 Bhattacharyya, S. S. ......................131 Bittlestone, C.................................776 Blaauw, D...... 15, 175, 191, 348, 376,

390, 950, 954 Blunno, I........................................502

Bobrek, A. .....................................408 Bolsens, I.......................................354 Borgatti, M. ...................................691 Borkar, S. ..............................338, 546 Bozorgzadeh, E. ............................920 Braun, G. .......................................262 Brayton, R. K. ...............................155 Brisk, P. .........................................616 Broom, A.......................................354 Brown, R. B. .................................520 Bruck, J. ........................................163 Bruschi, F. .....................................448 Bryant, R. E...........................425, 431 Bullock, S. S..................................324

C Cai, Y. ...........................................806 Calì, L............................................691 Cao, T............................................214 Carletta, J.......................................656 Carro, L. ................................570, 650 Cavin, R. K....................................628 Chai, D. .................................830, 860 Chakrabarty, K. .............................738 Chakradhar, S................................306 Chan, Y.-H. ...................................696 Chang, Y.-W. ................................812 Chappel, B.....................................642 Châtelain, A. ..................................... 7 Chen, G. ........................................887 Chen, H. ........................................794 Chen, L..........................................548 Chen, S. .........................................806 Chen, T..........................................496 Chen, X. ........................................460 Chen, Y. ..........................................22 Chen, Y.-A. ...................................362 Cheng, C.-K. .........105, 220, 794, 806 Cheng, K.-T...........................436, 668 Cheng, W.-T..................................674 Choi, K. .........................................912 Choi, Y. .........................................881 Chou, N.-C. ...................................794 Chou, P. H. ....................................119 Chowdhary, A. ..............................214 Chowdhury, M. H. ........................226 Clarke, E........................................368 Cohn, J...........................354, 546, 788 Cong, J.....................................32, 208 Craninckx, J. ...................................79 Croix, J. F......................................386

D Damaševičius, R. ............................48 Damiano, R. ..................................818 De Bernardinis, F. .........................964 De Sandre, G. ................................691 De, V. ............................................338 del Mar Hershenson, M. ...............970 Descamps, G.-E. ...........................844 Devadas, S.....................................869 Devgan, A. ....................................382 Dey, S. ...........................................548 Dickey, C.......................................724 Diniz, P. C. ............................514, 610 Domic, A. ......................................546 Dong, N. ........................................484 Dong, S..........................................806 Donnay, S........................................79 Donno, M. .....................................622 Duarte, D. ......................................187 Dueck, G. W. ................................318 Dutt, N...........................................758

E Ecker, W........................................372 Edwards, S. A. ..............................159 Ejlali, A. ........................................644 Erbas, C. ........................................402 Ernst, R..........................................454

F Fan, Y. .............................................60 Fang, C. F......................................496 Fang, Z. .........................................656 Ferzli, I. A. ....................................856 Fine, S............................................286 Forêt, B..........................................691 Frenkil, J..........................................15 Frey, C. .........................................546 Fujita, M........................................710 Fummi, F. ........................................42

G Gad, E............................................238 Gajski, D. ......................................300 Gallo, P............................................42 Ganai, M........................................824 Ganesan, S.....................................844 Gebara, F. H. .................................520 Ghiasi, S. .......................................920 Ghoneima, M. ...............................586 Gielen, G. ......................................974 Givargis, T.....................................875

978

Gloski, G. ........................................91 Gluska, A.......................................280 Godwin, G.....................................850 Goel, A. .........................................431 Gopalakrishnan, P. ........................782 Gordin, R.......................................724 Goren, D........................................724 Graeb, H. .......................................958 Greenstreet, M...............................592 Greive, V. ......................................262 Groeneveld, P................................546 Groves, R.......................................724 Gu, J. .............................................806 Gu, S..............................................744 Gupta, A. .......................................824 Gupta, P.....................................16, 22 Gupta, R. .......................................900 Guthaus, M. R. ..............................520

H Hadsell, R. T. ..................................28 Hajj, I. N........................................954 Hall, M. W. ...........................514, 610 Halpin, B. ......................................214 Hamlin, C. .....................................354 Hanna, Z........................................436 Harame, D. ............................278, 724 Hasteer, G......................................431 Hayes, J. P. ....................................893 He, L......................................181, 718 Henftling, R...................................372 Henkel, J........................................306 Heydari, P......................................532 Hill, A............................................776 Hodjat, A. ........................................60 Hoffman, A. ..................................262 Hogan, J.........................................642 Hong, X. ........................................806 Hooijmans, P. W.............................73 Horowitz, M. ...........................15, 682 Hsieh, H.........................................460 Hsu, J.-M.......................................812 Hsu, Y.-C. .....................................362 Hu, B. ....................................574, 800 Hua, S. ...........................................131 Huang, Y. ......................................674 Hur, S.-W. .....................................214 Hwang, D. .......................................60

I Ienne, P..........................................256 Iezzi, D. .........................................691 Inoue, A.........................................702 Irwin, M. J. ....................................187 Ismail, Y........................226, 232, 586

Ivaldi, A.........................................622 Iyengar, S. .....................................844 Iyengar, V......................................738

J Jacome, M. F.........................137, 396 Jafari, R. ........................................604 Jagannathan, A. ...............................32 Jain, J. ............................................442 Jain, P. ...........................................869 Jakkula, V......................................306 Jayakumar, N. ...............................292 Jayram, M. N.................................412 Jersak, M. ......................................454 Jess, J. A. G. ..................................932 Jiang, Y. ................................155, 638 Johnson, K.....................................278 Jordan, D. ......................................724 Jordan, M. I. ..................................964

K Kahng, A. B. .....................16, 22, 794 Kalafala, K. ...................................932 Kam, T...........................................143 Kandemir, M. ................................887 Kang, H.-J. ....................................840 Kaplan, A. .....................................616 Karakoy, M. ..................................887 Karalar, T. .....................................916 Kariat, V........................................864 Karnik, T. ......................................338 Kashyap, C. ...................................382 Kastner, R......................................616 Kempf, P. ......................................278 Keshavarzi, A................................338 Khan, A. ..........................................91 Kheterpal, V. .................................782 Kim, J. ...........................................688 Kim, K...........................................912 Kim, T. ..................................125, 881 Kiran, S. ........................................412 Koehl, J. ........................................770 Koh, C.-K. .....................................728 Kondratyev, A.......................574, 860 Konmoto, A...................................702 Koorapaty, A.................................782 Kornaros, G.....................................54 Kouroussis, D..................................99 Krach, F.........................................656 Krasniewski, M. D. .......................738 Kraver, K. L. .................................520 Kroening, D...................................368 Krstic, A. .......................................668 Kuchcinski, K. ..............................244 Kudva, P........................................696

Kuehlmann, A. ..............................830 Kukula, J. ......................................818 Kulkarni, S. ...................................788 Kumar, R. ......................................938 Kung, D. ........................................788 Kursun, E.......................................604 Kuulusa, M....................................916 Kwon, W.-C. .................................125 Kwong, W. ....................................175

L Lacey, L.........................................696 Lackey, D. E..................................770 Lahiri, S. K....................................425 Lai, B.-C..........................................60 Lau, C. Y. ......................................526 Lee, D. ...................................175, 191 Lee, H.-C.......................................812 Lekatsas, H....................................306 Lertora, F.......................................691 Leupers, R. ....................................262 Li, D. .............................................119 Li, P. ......................................472, 478 Li, W..............................................554 Li, X. .....................................466, 478 Li, Z. ......................................542, 580 Lillis, J. ..........................................196 Lima, F. .........................................650 Lin, X. ...........................................662 Liou, J.-J........................................668 Liu, F. ............................................382 Liu, W. ..........................................628 Livshitz, B. ....................................724 Long, C..........................................181 Lu, F. .............................................436 Lysecky, R. ...........................250, 334

M Ma, Y.............................................806 MacDonald, J. F............................794 Macii, A...........................................36 Macii, E. ..................................36, 622 Madden, P. H. .................................28 Magarshack, P.......................354, 419 Maidee, P.......................................598 Majauskas, G...................................48 Mak, T. M. ....................................668 Malik, S. ........................................764 Maneatis, J. G................................688 Manthe, A......................................542 Marek-Sadowska, M............113, 202,

574, 800, 860, 944 Markov, I. L. .........................324, 836 Marsman, E. D. .............................520 Martin, A. J. ..................................508

979

Martini, S.........................................42 Maslov, D......................................318 Mathys, Y.......................................... 7 Matic, S. ........................................155 Matsuzawa, A. ..............................417 Maxey, J. .......................................688 McClatchie, I.................................688 McCluskey, E. J. ...........................560 McCorquodale, M. S.....................520 Megerian, S. ....................................66 Mehendale, M. ..............................195 Mei, S. ...........................................232 Memik S. O. ..................................604 Memik, G. .....................................604 Meng, T. ........................................278 Meyerowitz, T...............................312 Meyr, H. ........................................262 Miller, D. M. .................................318 Miremadi, S. G..............................644 Mishchenko, A......................143, 149 Mishra, P. ......................................758 Mitra, T. ........................................466 Mong, W. S. ..................................752 Moondanos, J. ...............................436 Moore, A. ......................................642 Moreshet, T. ..................................634 Morita, K. ......................................702 Motokurumada, T. ........................702 Mukherjee, R.................................442 Mukhopadhyay, S. ........................169 Muta, T..........................................702 Muzzi, G........................................691

N Nagahara, L...................................276 Naidu, S. R. ...................................932 Najm, F. N...............................99, 856 Nakamura, T..................................642 Nakhla, M......................................238 Nandy, S. K...................................412 Narendra, S....................................338 Nassif, S. R..............................93, 109 Nebel, W. ........................................15 Negreiros, M. ................................570 Nelson, J. E. ..................................408 Ng, K. ............................................442 Nichols, G. ....................................546 Nikologiannis, A. ............................54 Nohl, A..........................................262 Northrop, G. ..........................642, 696

O Oh, C. ............................................954 Okada, S. .......................................702 O’Leary, J......................................710

O’Mahony, F.................................682 Omerbegovic, E. .............................36 Orailoglu, A. .................................732 Or-Bach, Z. ...................................354 Otten, R. H. J. M. ..........................932

P Pan, D. ...........................................788 Panda, R. .......................................954 Papaefstathiou, I..............................54 Parasuram, Y.................................214 Park, I.-C. ......................................840 Park, J. ...........................................724 Pasotti, M. .....................................691 Patel, C. .........................................782 Patel, K. ...........................................91 Patel, S...........................................566 Paul, J. M.......................................408 Paulin, P. G. ..................................419 Pedram, H......................................330 Pedram, M.............................906, 912 Penry, D. A....................................926 Perbellini, G. ...................................42 Perrott, M. H. ................................526 Pieper, J. J. ....................................408 Pileggi, L. T...........354, 472, 478, 782 Pimentel, A. D...............................402 Pinello, C.......................................312 Pirson, A........................................844 Pixley, C................................296, 710 Poles, M.........................................691 Pomeranz, I. ..........................554, 748 Poncino, M. ...............................36, 42 Potkonjak, M...................................66 Pozzi, L. ........................................256 Prasad, M. R..................................442 Pro, F. ..............................................36 Purandare, M.................................292 Puri, R............................................788 Püschel, M.....................................496

Q Qian, H. ...........................................93 Qin, W. ..........................................764 Qin, Z. ...........................................220 Qu, G. ............................................131

R Rabaey, J. ................................15, 916 Raghunathan, A.............................548 Raghunathan, V.............................900 Rajagopal, K..................................214 Ramachandran, A..........................137 Ramakrishna, M............................538 Ran, Y. ..................................860, 944

Rao, P. ...........................................412 Rao, W...........................................732 Ravi, S. ..........................................548 Raychowdhury, A. ........................169 Reddy, S. M. .........................554, 748 Reinman, G. ....................................32 Reis, R. ..........................................650 Ren, J.............................................592 Reshadi, M. ...................................758 Rewieński, M. ...............................490 Ricciato, F. ......................................42 Riedel, M. D..................................163 Rofougaran, R. ..............................278 Rolandi, P. L. ................................691 Romesis, M. ....................................32 Rong, P..........................................906 Root, D. E........................................85 Rosser, T. ......................................696 Rovner, V. .....................................782 Roy, K. ..................................169, 728 Roychoudhury, A..........................466 Roychowdhury, J. .........................484 Ruddy, P..........................................91 Russell, J. T...................................396 Rusu, S. .........................................706 Rutenbar, R. A. ............................ 496

S

Saifhashemi, A. .............................330 Sakallah, K. A. ..............................836 Sakiyama, K. ...................................60 Sakurai, T. .......................................15 Sangiovanni-Vincentelli, A. .312, 964 Sankaradass, M. ............................306 Sapatnekar, S. S. .............................93 Sarrafzadeh, M..............................920 Sasao, T. ........................................149 Satsukawa, Y.................................702 Schaumont, P. .................................60 Scheffer, L.....................................546 Schliebusch, O. .............................262 Schmit, H.......................................782 Schoellkopf, J.-P. ..........................546 Schubert, K.-D. ...............................11 Schubert, T. ....................................... 1 Sciuto, D........................................448 Sechen, C.......................................642 Sehgal, A. ......................................738 Senger, R. M. ................................520 Seshia, S. A. ..................................425 Shankaradas, M.............................688 Sheets, M.......................................916 Sherman, A....................................724 Sherwani, N.....................................91

980

Shi, C.-J. R. ...................................542 Shi, K.............................................850 Shi, W............................................580 Shin, D...........................................300 Singh, R.........................................724 Singhal, V......................................776 So, B. .............................................514 Somenzi, F. ...........................292, 710 Song, B..........................................712 Sotiriou, C. P.................................502 Spirakis, G.....................................416 Spoto, J. .........................................278 Srivastava, A. ................................788 Srivastava, M. B............................900 Stehr, G. ........................................958 Stinson, J. ......................................706 Stitt, G. ..........................................250 Stok, L. ..........................................788 Strang, S. .......................................724 Strojwas, A. J. ...............................782 Štuikys, V........................................48 Su, H..............................................109 Suaris, P.........................................794 Sugiyama, H..................................702 Sugiyama, I. ..................................702 Suh, G. E. ......................................869 Sun, J.-G........................................744 Susin, A. A. ...................................570 Sylvester, D. .............15, 16, 175, 376,

788, 950 Szymanek, R. ................................244

T Tabbara, B.....................................362 Tahoori, M. B................................678 Takahashi, A. ................................920 Tasiran, S.......................................356 Thakar A........................................642 Thomas, D. E. ...............................408 Thompson, R.................................662 Thudi, B.........................................390 Tiourin, V......................................214

Tong, K. Y. ...................................782 Travaglione, B...............................894 Tresek, J. .......................................276 Tretiakov, Y. .................................724 Tsai, F............................................362 Tsai, Y-F. ......................................187 Tschanz, J......................................338 Tseng, K. ...............................860, 864 Tsui, R. K. .....................................276 Tufillaro, N......................................85

V Vahid, F.................................250, 334 Vasilyev, D....................................490 Vasishta, R. .....................................91 Vasudevan, A. ...............................195 Vasudevan, V. ...............................538 Veillette, R. ...................................656 Verbauwhede, I. ..............................60 Vijaykrishnan, N. ..........................187 Vincentelli, A. S....................312, 964 Visweswariah, C. ..................343, 932 Vogels, M......................................974 Vrudhula, S. ..................................348

W Wagner, I. A..................................724 Waicukauski, J. A. ........................566 Wang, C.........................................824 Wang, K. .......................................113 Wang, L.-C............................436, 668 Wang, X. .......................................143 Wasshuber, C. ...............................274 Watanabe, Y..................460, 574, 860 Wei, S. ...........................................195 White, J. ................................490, 712 Wohl, P..........................................566 Wong, C. G. ..................................508 Wong, D. F....................................386 Wong, J. L. ......................................66 Wong, S. S. ...................................682

Wood, J. ..........................................85 Wu, Y.-L. ......................................744

X Xiang, D. .......................................744 Xie, Q. ...........................................119 Xu, Y. ............................................478

Y Yamashita, H.................................702 Yamashita, R.................................702 Yang, A. ..........................................15 Yang, H. H. ...................................812 Yang, J.............................................16 Yang, S............................................60 Yang, Z..........................................824 Yao, B. ..................................105, 794 Yeh, C.-Y. .....................................202 Yorav, K........................................368 Yoshida, Y. ...................................702 Yu, C. ............................................554 Yu, H. ............................................718 Yu, Y. ............................................356 Yuan, J...........................................296 Yuan, X. ........................................208 Yue, C. P. ......................................682

Z Zambaldi, M..................................372 Zelikson, M. ..................................724 Zervos, N.........................................54 Zhang, R........................................276 Zhang, W.......................................887 Zhong, G. ......................................728 Zhu, J.............................................752 Zhu, Z. ...........................105, 712, 794 Ziegler, H. E..................................610 Zinn, A. .........................................372 Ziv, A. ...........................................286 Zolotov, V. ............................348, 954 Zuchowski, P. S. ...........................770

981