Achieving the Best Thermal Performance for

GaN-on-Diamond

J. Pomeroya*, M. Bernardonia, A. Saruaa, A. Manoia, D.C. Dumkab, D.M. Fanningb, M. Kuballa AH.H. WILLS PHYSICS LABORATORY, UNIVERSITY OF BRISTOL, BRISTOL, BS8 1TL, UK BTRIQUINT SEMICONDUCTOR, INC., 500 W. RENNER ROAD, RICHARDSON, TX, 75080, USA

*James.Pomeroy@bristol.ac.uk

1 H.4 CSICS 2013 Monterey

• Aim: Optimize thermal resistance in GaN-on-Diamond through measurement and modelling

• Review state-of-the-art GaN-on-Diamond transistor versus GaN-on-SiC

• Novel thermal resistance measurement:

• Substrate thermal conductivity

• Interfacial thermal resistance

• Validated transistor model for identifying

thermal bottle necks in GaN-on-Diamond

• Summary

Outline

2 H.4 CSICS 2013 Monterey

Thermal resistances near the HEMT channel:

GaN epilayer

+ GaN/substrate interface

+ Substrate

High RF output power density in GaN-based HEMTs requires improved thermal management

Motivation

3 H.4 CSICS 2013 Monterey

Multifinger GaN HEMT

thermal image

D G S

GaN

Substrate

heat

1µm

Thermal conductivity can be improved up to 5×, replacing SiC->diamond

- interface

Review: GaN-on-Diamond State-of-the-art

H.4 CSICS 2013 Monterey 4

40%

@15W

/mm

0 5 10 15

0

50

100

150

200

250

300

Tem

pera

ture

channel tr

em

pera

ture

ris

e [

oC

]

Power density [W/mm]

• Advantage over GaN-on-SiC already demonstrated: 10.8°Cmm/W (D.C. Dumka, F.4 CSICS 2013)

• How can we improve GaN-on-Diamond even further?

Peak channel temperature derived

from Raman measurement

100µm, 2 Finger HEMT

Historical Development

H.4 CSICS 2013 Monterey 5

GaN

Diamond

AlGaN

Using experimental feedback to aid design

GaN

κ≈160 W/mK

κ≈16 W/mK

GaN

Si

Diamond

AlGaN T.L.

0 5 10 15 20

0

50

100

150

200

GaN/Si

GaN/Tr. layer/Diamond

GaN/Diamond

Te

mp

era

ture

ris

e [

oC

]

Power density [W/mm]

GaN transistors originate from GaN-

on-Si growth

GaN-on-diamond Including

transition layer

Current design, T.L. removed

2x100µm HEMT comparison

Lets examine thermal resistance in more detail

Raman measured temperature

interlayer

Thermal Resistance Components

H.4 CSICS 2013 Monterey 6

1µm GaN

25nm dielectric

95 µm polycrystalline

diamond

Increasing thermal

conductivity along growth

direction

TBReff?: Effective thermal resistance of interface region, including dielectric + diamond nucleation layer (<100 nm)

κdiamond ?: Thermal conductivity depends on grain size. “Bulk” thermal conductivity measurements may be misleading for device modelling

160 W/mK

-> Aim: Separate these thermal resistance contributions

Raman Thermography Depth Mapping

7 H.4 CSICS 2013 Monterey

0.1 1 10 1000

50

100

150

200

250

Log. Depth [m]

Tem

per

atu

re r

ise

[oC

]

contact

GaN TBReff -

Substrate

Confocal depth mapping through transparent uniform materials

TBReff

Substrate thermal conductivity

Ungated transistor as a uniform heat source

Temperature gradient->thermal parameters

GaN substrate

Raman temperature mapping through polycrystalline diamond is challenging: Light absorption and stress variation

-200 -150 -100 -50 0 5040

60

80

100

120

140

160

mes

a ed

ge

cen

tre

Tem

per

aure

[oC

]Position [microns]

Surface Temperature Profile

H.4 CSICS 2013 Monterey 8

Polycrystalline Diamond

GaN

F.E. model of ungated HEMT ¼ cross section

Diamond thermal conductivity

+ GaN/diamond interface TBReff

Fit finite element model by adjusting two parameters:

contact

contact

mesa map

GaN

Diamond interface

• For highest accuracy, we measure the temperature in the uniform GaN layer, rather than the diamond.

-200 -150 -100 -50 0 5040

60

80

100

120

140

160

180

Measurement

Simulation

GaN

tem

per

atu

re [

Deg

. C]

Position [microns]

• Opaque diamond

• Effective diamond substrate thermal conductivity = 710±40 W/mK

• 70% increase over SiC

• GaN/diamond TBReff = 2.7±0.3 ×10-8 m2K/W

• Comparable to typical GaN-on-SiC TBR

Thermal Resistance Measurement

9 H.4 CSICS 2013 Monterey

3.36W

contact

contact

mesa map

Will result in lower transistor thermal resistance than GaN-on-SiC...

Validating Thermal Model

H.4 CSICS 2013 Monterey 10

0.1 1 10

60

80

100

120

140

160

180

Inte

rfac

e

DiamondTe

mp

erat

ure

[D

eg. C

]

Depth [m]

GaN

Simulation

GaN measurement

Diamond measurement

GaN

Diamond

Self consistency between measurement and model

contact

GaN

25nm dielectric

Probed region

1µm

0.5µm

Measurement

3.36W

Opaque diamond enables

measured diamond temperature

to be compared to model

Model input parameters are fixed

• Effective thermal conductivity < bulk thermal conductivity

• Effective thermal conductivity is relevant for transistor modelling

“Effective” Substrate Thermal Conductivity

H.4 CSICS 2013 Monterey 11

0.1 1 10

60

80

100

120

140

160

180

Inte

rfac

e

Diamond

Tem

per

atu

re [

Deg

. C]

Depth [m]

GaN

Simulation

GaN measurement

Diamond measurement

Region of highest sensitivity Lower

Higher

~30µm

contact

GaN

Thermal conductivity gradient

2-D-like heat diffusion

Wafer 2: Higher Grade Diamond

12 H.4 CSICS 2013 Monterey

0 20 40 60 80 100-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8Diamond

s

tre

ss [G

Pa

]

Depth [microns]

GaN

Image taken though diamond substrate

GaN surface temperature mapping approach can still be applied with high accuracy

Raman temperature mapping though translucent diamond is difficult, due to stress variations

• 1200 W/mK effective diamond thermal conductivity

• Thicker 50nm interlayer (w.r.t opaqe wafer), resulting in a 40% higher interface thermal resistance

Wafer 2: Thermal Measurement

H.4 CSICS 2013 Monterey 13

-140 -120 -100 -80 -60 -40 -20 0 20 4020

40

60

80

100

120

140

160 Measurement

Simulation

Ga

N t

em

pe

ratu

re [

De

g.

C]

Position [microns]

4.72W

contact

contact

mesa map

What is the relationship between interface thermal resistance, substrate thermal conductivity and transistor thermal resistance?

Transistor Thermal Model

14 H.4 CSICS 2013 Monterey

0.1 1 10 100

0

20

40

60

80

100

120

140

160

180

200

220

240

260

Tem

pera

ture

ris

e [

oC

]

Depth [m]

Measurement:

GaN Diamond

Simulation:

diamond

Rinterface

W/mK o

Cm2/W

710 2.7x10-8

GaN-on-SiC

GaN Diamond

Source Drain

Gate

GaN

Diamond

interface

1 µm

Opaque diamond wafer, 2×100µm HEMT, Pdiss = 15.3 W/mm

40%

Raman probe

Model validation: Agreement with measured temperatures

Parameters obtained

earlier

0.1 1 10 100

0

20

40

60

80

100

120

140

160

180

200

220

240

260

Tem

pera

ture

ris

e [

oC

]

Depth [m]

Measurement:

GaN Diamond

Simulation:

diamond

Rinterface

W/mK o

Cm2/W

710 2.7x10-8

1400 2.7x10-8

710 0

Reducing Transistor Thermal Resistance

15 H.4 CSICS 2013 Monterey

S

GaN

diamond

G D GaN-on-SiC GaN Diamond

Use validated transistor model to explore thermal resistance components

Current GaN-on-diamond

Increasing diamond thermal conductivity

OR decreasing interface thermal resistance

Eliminating GaN/Diamond interface resistance reduces transistor thermal resistance by a further 35%

• A 40% reduction in channel thermal resistance has been demonstrated for current GaN-on-diamond transistors versus GaN-on-SiC

• A further 35% reduction in transistor thermal resistance could be achieved by reducing the GaN/diamond interface thermal resistance

• A methodology has been developed for characterising the thermal resistance components of GaN-on-Diamond:

• Effective diamond thermal conductivity 750-1200 W/mK

• GaN/Diamond interfacial thermal resistance 2.7±0.3 ×10-8 m2K/W for 25 nm interlayer

Acknowledgement: This work is supported by the DARPA Near Junction Thermal Transport (NJTT) Program, monitored by Dr. Avi Bar Cohen, Dr. Joe Maurer and Dr. Jonathan Felbinger of DARPA. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of DARPA.

Summary

16 H.4 CSICS 2013 Monterey