AC/DC/AC Converters: Two-Level and Multilevel VSI · AC/DC/AC Converters: Two-Level and Multilevel VSI Page 25 Socrates – Erasmus Visit Main Features - Modular topologies. Very

AC/DC/AC Converters: Two-Level and Multilevel VSIPage 1

Socrates – Erasmus Visit

AC/DC/AC Converters:Two-Level and Multilevel VSI

Josep PouAntoni Arias



Outline

1. Two-Level Inverter2. Multilevel Inverters

- Cascade H-Bridge Inverter- Flying-Capacitor Inverter- Diode-Clamped Inverter

3. Back-to-Back Connection



Outline






1. Two-Level Three-Phase Inverter

Grid-connected inverter

2dcv

)0(dcv

C2

C2

as bs cs

as bs cs

+

−2dcv

)(a)(b

)(c

0av0bv0cv

cba eee ,,

)(n

L R

cba iii ,,

dci pi

pR

CiRpi



⎪⎪⎪

⎩

⎪⎪⎪

⎨

⎧

+++=

+++=

+++=

00

00

00

nccc

c

nbbb

b

naaa

a

veiRdtdiLv

veiRdtdiLv

veiRdtdiLv

Modeling the AC Side

( ) ( ) 0000 3 ncbacbacba

cba veeeiiiRdt

iiidLvvv +++++++++

=++

( )3

0000

cbacban

eeevvvv ++−++=

0=++ cba iii

0av0bv0cv

cba eee ,,

)(n

L R

cba iii ,,



( )

( )

( )⎪⎪⎪

⎩

⎪⎪⎪

⎨

⎧

−−−=

−−−=

−−−=

00

00

00

1

1

1

ncccc

nbbbb

naaaa

veiRvLdt

di

veiRvLdt

di

veiRvLdt

di

( )

( )

⎪⎪⎪

⎩

⎪⎪⎪

⎨

⎧

−−=

−−−==

−−−==

∫∫

∫∫

bac

nbbbbb

naaaaa

iii

dtveiRvL

dii

dtveiRvL

dii

00

00

1

1

Modeling the AC Side



Matlab-Simulink Model



Modeling the DC Side

⎪⎪⎩

⎪⎪⎨

⎧

=

=−−=

p

dcRp

dcpRpdcC

Rvi

dtdvCiiii

⎟⎟⎠

⎞⎜⎜⎝

⎛−−= p

p

dcdc

dc iRvi

Cdtdv 1

dcv

+

−

dci pi

pR

CiRpi

C



∫∫ ⎟⎟⎠

⎞⎜⎜⎝

⎛−−== dti

Rvi

Cdvv p

p

dcdcdcdc

1




Converter

⎪⎪⎪

⎩

⎪⎪⎪

⎨

⎧

++=

−=

−=

−=

ccbbaap

dccc

dcbb

dcaa

isisisi

vsv

vsv

vsv

)21(

)21(

)21(

0

0

0

2dcv

)0(dcv

C2

C2

as bs cs

as bs cs

+

−2dcv

)(a)(b

)(c

0av0bv0cv

ai

pi

bici






Modulation (Sinusoidal PWM)



Control

qvΔ

dvΔ

di

*DCV Voltage

Controller

Current Controller

Current Controller

0* =qI

qi

DCv

LE

*dI

Lω

Lω-

dv

qv

Voltage Oriented Control (VOC)



Simulation Program



Simulation Results

Main data: VLRMS=400V, f=50Hz, L=6mH, R=0.1Ω, C=2200μF, Vdc*=750 V, fs=5kHz.

Particular data: Rp=100Ω, Idc=0, Iq*=0

0 0.02 0.04 0.06 0.08 0.1 0.12-400

-200

0

200

400

600

800

Time (s)

vdc

ea eb ec

ia*10 ib*10 ic*10(V),

(A)



Simulation Results


Particular data: Rp=10kΩ, Idc=10A, Iq*=0

0 0.02 0.04 0.06 0.08 0.1 0.12-400

-200

0

200

400

600

800

Time (s)

(V),

(A)

vdc

ea eb ec

ia*10 ib*10 ic*10



Simulation Results


Particular data: Rp=10kΩ, Idc=0, Iq*=20A

0 0.02 0.04 0.06 0.08 0.1 0.12-400

-200

0

200

400

600

800

vdc

ea eb ecia*10 ib*10 ic*10

(V),

(A)



Outline






• Multilevel inverters can provide more than two voltage levels at the outputs.

• Main advantages compared with the two-level inverter:- high quality of the output voltage spectra and - larger voltages that can be handled.

• Suitable for high-power applications.

• Main multilevel topologies:- (1) cascade H-bridge inverter,- (2) floating-capacitor inverter, and- (3) diode-clamped inverter.

2. Multilevel Inverters



(1) Cascade H-Bridge Inverters

0

VDC VDC VDC

VDC VDC VDCaC C C b c

C C C



sH0a sHa va0

off off 0

off on +VDC

on off -VDC

on on 0

sL0a

sH0a sHa

sLa

VDC aC

VDC

C VDC

C b c

0

sL0a

sH0a sHa

sLa

VDC aC

VDC

C VDC

C b c

0

0 V

sL0a

sH0a sHa

sLa

VDC aC

VDC

C VDC

C b c

0

+VDC

sL0a

sH0a sHa

sLa

VDC aC

VDC

C VDC

C b c

0

-VDC

sL0a

sH0a sHa

sLa

VDC aC

VDC

C VDC

C b c

0

0 V

0offoff

off on +VDC

on off -VDC

on on 0

Control functions: sH0a and sHa

Three-Level Basic Structure



0

VDC VDC VDC

VDC VDC VDCaC C C b c

C C C

n= 2h+1 n: number of output levels (per phase)h: number of cascaded H cells

Even Number of Levels



sH20a sH2a

sH10a sH1a

VDC

VDC aC

C

0

sH10a sH1a va0

off off 0off on +VDCon off -VDCon on 0off off +VDCoff on +2VDCon off 0on on +VDCoff off -VDCoff on 0on off -2VDCon on -VDCoff off 0off on -VDCon off +VDCon on 0

sH20a sH2a

off offoff offoff offoff offoff onoff onoff onoff onon offon offon offon offon onon onon onon on

Cascaded Five-Level Inverter



0 2 4 6 8 10 12 14 16 18 20

2 VDC

1.5 VDC

VDC

0.5 VDC

0

-0.5 VDC

-VDC

1.5 VDC

-2 VDC

Time (ms)

sH20a sH2a

sH10a sH1a

VDC

VDC aC

C

0

Modulation Techniques

Example: Sinusoidal PWM (SPWM) in a Five-Level Inverter



Main Features

- Modular topologies. Very interesting for practical implementation.

- Main drawback: isolated DC voltage sources are required.- Isolation is not necessary for applications such as active

filtering and reactive compensation. In those cases, capacitors are used to provide DC voltages. Their voltages have to be controlled using redundant states of the converter.

- As many unities as necessary can be connected in cascade. Therefore, any AC voltage level can be achieved.



(2) Flying-Capacitor (FC) Multilevel Inverter

0

C

a

VDC

b c

Cf vfa

Cf vfb

Cf vfc

Three-level Topology



Cf

VDC 2DCV

DCV

sH2

sL2

sH1

sL1

a

0

iaiCf1

C

Imbricate Cells

C

VDC Cf

aia

0

2DCV

DCV

sH2

sL2

sH1

sL1

- Each leg of the converter is made up from a set of cells (imbricate cells). The output voltage is synthesized by connecting a number of cells (capacitors) in series.

- SHi and SLi, with i = {1, 2}, must be in opposite states to avoid short-circuits.



0

C

a

VDC

Cf1Cf2

b

Cf1 Cf2

c

Cf1Cf2

FC Four-Level Topology



C Cf(n-2) Cf1

VDC

...

...

...

1−nVDC

12

−nVDC

DCVnn

12

−−

DCV

sH(n-1)

sL(n-1)

sH(n-2)

sL(n-2)

sH3

sL3

sH2

sL2

sH1

sL1

a

0

iaiCf1iCf 2

Cf 2

iCf(n-2)

Imbricate Cells in an n-level FC Inverter

• Voltages on the floating capacitors are different.



• FC multilevel topologies require a large number of capacitors, specially in high-order structures (n>3).

• Precharge of the flying capacitors is required.

• Voltages on the flying capacitors can be controlled. Each leg regulates the voltages on their capacitors independently of the others.

Main Features



(3) Diode-Clamped Inverters

ic

ib

ia

i1

0

1 (NP)

2

c

b

a

CvC1

vDC

vC2 C

Three-level diode-clamped inverter =

Neutral-Point-Clamped (NPC) Inverter



2

0

abc

VDC

vC2

1

C vC1

C vC2

0

1

2

c

b

aia

ib

ic

sc0

sc2

sc1

sb0

sb2

sb1

sa0

sa1

sa2

CvC1

VDC

C

Functional diagram

NPC Inverter

Two consecutive switches must be in on-state

2

0

abc

VDC

vC2

1

C vC1

C vC2

0

1

2

c

b

aia

ib

ic

sc0

sc2

sc1

sb0

sb2

sb1

sa0

sa1

sa2

CvC1

VDC

C

2

0

abc

VDC

vC2

1

C vC1

C vC2

0

1

2

c

b

aia

ib

ic

sc0

sc2

sc1

sb0

sb2

sb1

sa0

sa1

sa2

CvC1

VDC

C

2

0

abc

VDC

vC2

1

C vC1

C vC2

0

1

2

c

b

aia

ib

ic

sc0

sc2

sc1

sb0

sb2

sb1

sa0

sa1

sa2

CvC1

VDC

C

Operation principles



CvC2

vC1

VDC

C

2

1

0a b c

0

vC1

Time, t

A low-frequency oscillation may appear in the neutral-point (NP) voltage.

Neutral-Point Voltage Oscillations



-180 -150 -30 0 60 1500.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.95

1

Mod

ulat

ion

Inde

x, m

Current Phase Angle, ϕ (Degrees)

-90 -60 30 90 120 180-120

Oscillation Area

NP Voltage Oscillations



Current Phase Angle (Degrees)

2NPnVΔ

Modulation Index m

2NPnVΔ

-150 -100 -50 0 50 100 1500

0.005

0.01

0.015

0.02

0.025

0.03

m=1

m=0.9

m=0.8

m=0.7

m=0.6

Current Phase Angle (Degrees)

CfIVV

RMS

NPNPn 22

Δ=

Δ

Normalized amplitude of the NP voltage ripple (ΔVNPn /2):ΔVNP /2 : amplitude of the NP voltage rippleIRMS: RMS output currentf: line frequencyC: value of the DC-link capacitors

Voltage Oscillation Amplitude



Four-Level Diode-Clamped Inverter

vC1

0

VDC

C

1

2

3

vC2 C

vC3 C

a b c

Four-level topology



Four-Level Multilevel Inverter

0 10 20 30 40 50 60-400

-200

0

200

400

600

800 vC1

vC2

vC3

ia ib ic

Time (ms)

vab / 3

0 10 20 30 40 50 60-400

-200

0

200

400

600

800

Time (ms)

vC1

vC2vC3

ia ib ic

vab / 3

0 10 20 30 40 50 60-400

-200

0

200

400

600

800

Time (ms)

vC1

vC2

vC3

ia ib ic

vab / 3

Example operating under unity power factor

m=0.4 m=0.5 m=0.6

J. Pou, R. Pindado, and D. Boroyevich, “Voltage-Balance Limits in Four-Level Diode-Clamped Converters With Passive Front Ends,” IEEE Trans. Ind. Electron., vol. 52, no. 1, pp. 190-196, Feb. 2005.

Voltage balance problems



Limits of Voltage Balance

ϕπ cos3

=m

Four-Level Converter

n-Level Converter (n→∞)

UnstableArea

-180 -150 -30 0 60 1500.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.95

1

Mod

ulat

ion

Inde

x, m

Load Current Angle (Degrees)

-90 -60 30 90 120 180-120

M. Marchesoni and P. Tenca, “Theoretical and practical limits in multilevel MPC inverters with passive front ends,”in Proc. EPE’01, Graz, Austria, Aug. 2001.



Outline






AC-DC-AC NPC-Based System

(NP)

CvC2

vC1C

rVd

st

a

b

c

Wind-Turbine NPC Converter Grid-Connected NPC Converter

vr

vs

vt

3*Lgiwt ig

Multipole Synchronous Wind Turbine

ElectricalGrid

Back-to-back-connected NPC converters. Example of application to MPSG wind turbines.



-180 -150 -30 0 60 1500.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.95

1

Out

put M

odul

atio

n In

dex,

mo

Output Phase Current Angle, ϕo (Degrees)

-90 -60 30 90 120 180-120

Passive Front End

mi=0.5mi=0.6mi=0.7mi=0.8mi=0.9

mi=0.5mi=0.6mi=0.7mi=0.8mi=0.9

Conditions: constant output current (IRMSo=ct.), unity input power factor (ϕi=0o, 180o), and 100% efficiency (η=1).

-180 -150 -30 0 60 1500.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.95

1

Out

put M

odul

atio

n In

dex,

mo


-90 -60 30 90 120 180-120

Passive Front End

mi=0.5mi=0.6mi=0.7mi=0.8mi=0.9

mi=0.5mi=0.6mi=0.7mi=0.8mi=0.9

-180 -150 -30 0 60 1500.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.95

1

Out

put M

odul

atio

n In

dex,

mo


-90 -60 30 90 120 180-120

Passive Front End

mi=0.5mi=0.6mi=0.7mi=0.8mi=0.9

mi=0.5mi=0.6mi=0.7mi=0.8mi=0.9

Voltage-balance Improvements



Matlab-Simulink Simulation Platform



0 0.05 0.1 0.15 0.2 0.25 0.3

Time, s

vr vs vt

0-400

-200

0

200

400

(V)

0 0.05 0.1 0.15 0.2 0.25 0.3

Time, s

Real Angle

0 0

2

4

6

8 Detected Angle

0 0.05 0.1 0.15 0.2 0.25 0.3-50 -25

0 25 50 75

100

Time, s

Vdc/10

ir is it

(V),(A)

(rad)

Two-phase voltage dip process with a fifth harmonic

Utility Voltages

Positive-Sequence Phase Angle

Utility Currents and DC-Link Voltage

Simulation Results



Remarks

• Multilevel topologies can be applied to high-power wind-turbine systems. They are expected to be extensively used when the wind turbines rated power reaches about 10 MW.

• Among the multilevel topologies, the three-level NPC is the most produced used nowadays. An important drawback of this topology is the voltage oscillations that may appear in the NP under some operating conditions.

• The back-to-back connection of NPCs forms an AC/DC/AC system. In such a configuration the NP voltage oscillations become significantly attenuated.

Documents

AC/DC/AC Converters: Two-Level and Multilevel VSI · AC/DC/AC Converters: Two-Level and Multilevel VSI Page 25 Socrates – Erasmus Visit Main Features - Modular topologies. Very