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VHDL 의 이해와 실습

2000 년 1 학기 Computer Architecturehttp://www.cs.hongik.ac.kr/~yhchoi

(classes links)

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Introduction

VHDL VHSIC(Very High Speed Integrated Circuit) Hardware Descriptio

n Language

VHDL 의 특성 Device-Independent Design Benchmarking Capabilities Quick Time-to-Market and Low Cost

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Introduction

Using VHDL for design synthesis Define the design requirement Describe the design in VHDL Simulate the source code Synthesize, optimize, and fit(place and route) the design Simulate the post-layout design model Program the device

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Introduction

Design Idea

Behavioral Design

Data Path Design

Logic Design

Physical Design

Manufacturing

Chip or Board

Flow Graph, Pseudo Code

Bus & Register Structure

Gate Wirelist, Netlist

Transister List, Layout

A digital system design process.

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VHDL Syntax

Design entity 설계의 최소단위 Entity & Architecture Package Library Configuration declaration

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Entity

Declaration. Entity 는 설계의 component 의 이름과 input/output port interface를 정의하고 동작에 필요한 parameter 를 전달한다 . 내부 동작을 고려하지 않고 외부적인 모습만을 설계한다 .

Format.Entity entity_name is generic (parameter_list); port(parameter_list); declaration;begin statementsEnd entity_name;

Entity OR2 is port(I1,I2 : in bit; O : out bit);End OR2;

I1

I2

O2

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Entity

Generic To design parameterized components, for which the size and featu

res sets may be defined by values of the instant parameters. Ports

Entity 의 I/O 를 표현 . Data type : Bit, Bit_vector, Byte, integer, IEEE std_logic_1164. Mode : in, out, inout, buffer, linkage

In : input signal Out : output signal Inout : in + out Buffer : entity 의 결과 signal 을 다시 입력으로 이용 , 외부입력

불가

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Entity

Declaration 여러 Architecture 에서 공통으로 사용되는 것들을 선언 .

ExampleLibrary ieee;Use ieee.std_logic_1164.all;Entity add4 is generic ( bit_size : positive); port(a,b : in std_logic_vector(bit_size downto 0); ci : in std_logic; sum : out std_logic_vector(bit size downto 0); co : out std_logic);End add4;

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Architecture

Architecture bodies An architecture describes the contents of an entity 하나의 entity 선언에 여러 개의 architecture 사용 가능

FormatArchitecture arch_name of entity_name is declarationBegin internal behavior descriptionEnd arch_name;

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Architecture

Behavioral Description 시스템의 동작을 Algorithm level 에서 H/W 와 관계없이 표현

Architecture behavioral of eqcomp4 isBegin comp: process (a, b) begin equals <= ‘0’; if a = b then equals <= ‘1’; end if; end process comp;End behavioral;

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Architecture

Dataflow Description 시스템을 자료의 흐름에 맞추어 설계

Architecture dataflow of eqcomp4 isBegin equals <= ‘1’ when (a=b) else ‘0’;End dataflow;

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Architecture

Structural Description 각각의 구조를 component 로 나타내고 이들간의 연결로 시스템을 표현 .

Architecture structural of eqcomp4 isBegin signal x : std_logic_vector(0 to 3); u0 : xnor2 port map (a(0), b(0),x(0)); u1 : xnor2 port map (a(1), b(1),x(1)); u2 : xnor2 port map (a(2), b(2),x(2)); u3 : xnor2 port map (a(3), b(3),x(3)); u4 : and4 port map (x(0), x(1),x(2), x(3),equals);end structural;

ab

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Statements

Sequential statements 내부의 동작을 순차적으로 표현 Process Statements 이용 각각의 process 문은 concurrent 하게 동작

Concurrent statements 시스템의 동작표현 시 이용

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Sequential Statements

Wait Statements Wait on signal_list; -- signal_list : process 의 sensitive list Wait until condition; -- condition 이 true 일때까지 wait Wait for time; -- time 만큼의 시간동안 wait Wait; -- 수행 중지

Signal Assignment Statements Signal_name <= value -- no delay time(delta delay) Signal_name <= value after delay_time;

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Sequential Statements

If statements

If cond1 then statement1Elsif cond2 then statement2Else statement3End if;

ProcessBegin if x = ‘0’ and y=‘0’ then z <= ‘1’ after 3ns; elsif x = ‘X’ or y = ‘X’ then z <= ‘1’ after 3ns; else z <= ‘0’ after 3ns; end if; wait on x,y;End process;

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Sequential Statements

Case StatementsCase 수식 is

when value1 => statement1;when value2 => statement2;when others => statement3;

end case;

ProcessBegin case sel is when “00” => z <= in0 after 5ns; when “01” => z <= in1 after 5ns; when “10” => z <= in2 after 5ns; when “11” => z <= in3 after 5ns; wait on sel;End process;

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Data Objects

Constant,signal,variable Constant : 선언할 때 값을 정한 뒤 , 바꿀 수 없다 . Signal : 값 대입시 미래의 어느 시점에 값이 바뀐다 . Variable : 값이 그 즉시 대입된다 .

Constant Delay : Time := 5ns;Variable va : Integer;Signal Clock, Set Clear : bit;

va := 30;Set <= ‘1’;

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Design Example

MUX 4x1Library IEEE;Use IEEE.std_logic_1164.all;Entity mux is port ( a,b,c,d : in std_logic_vector(3 downto 0); s : in std_logic(1 downto 0); x : out std_logic_vector(3 downto 0));End mux;Architecture archmux of mux isBegin x <= a when (s = “00”) else b when (s = “01”) else c when (s = “10”) else d;End archmux;

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Design Example

Test bench for MUX 4x1 (2bit)

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Design Example

8-bit RegisterLibrary IEEE;Use IEEE.std_logic_1164.all;Entity reg_logic is port ( d : in std_logic_vector(0 to 7); reset, init clk : in std_logic; q : out std_logic_vector(0 to 7));End reg_logic;

Architecture archreg2 of reg_logic isBegin process(clk, reset) begin if (reset = ‘1’) then q <= “00000000”; elsif (clk’event and clk = ‘1’) then if (init <= ‘1’) then q <= “11111111”; else q <= d; end if; end if; end process;