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ABC130 “BOTTOM SIDE” 30/04/13 F. Anghinolfi/K. Swientek PIO_REC PIO_REC160 SIOGND BC_padN CLK_PadN COM_LZERO_PadN LONERTHREE_padN 200 PIO_INP_RAW_PULLD OWN DGNFETProt padDisable_RegA padDisable_RegD padShuntCtrl SIOGND 250 SIOGND 250 SIOGND To FE To BE Chip edge 3150 um um BC_padP CLK_PadP COM_LZERO_PadP LONERTHREE_padP x40 um MA GNDD
Citation preview
F. Anghinolfi/K. Swientek 1
ABCN Pad ring
V8.0
30/04/13
Final ABC130 pads distribution
y
x
7602.18 um
3146.16 um
4 off fiducials added
Fiducials are 95µm x 95µm (Ball bond pad)
1 2
34
6.8mm x 7.9mm (x,y)
ABC130 – Pad ring and Fiducials
3
3387.82
ABC130 “BOTTOM SIDE”
30/04/13F. Anghinolfi/K. Swientek
PIO
_REC
160
PIO
_REC
160
200
PIO
_REC
160
PIO
_REC
160
SIO
GND
200
20025
0
BC_p
adN
CLK_
PadN
COM
_LZE
RO_P
adN
LON
ERTH
REE_
padN
200
200
PIO
_IN
P_RA
W_P
ULL
DO
WN
PIO
_IN
P_RA
W_P
ULL
DO
WN
DGN
FETP
rot
padD
isabl
e_Re
gA
padD
isabl
e_Re
gD
padS
hunt
Ctrl
SIO
GND
250
250
SIO
GND
250
250
SIO
GND
250
250
200
200
To FE To BE
Chip edge
3150 um 530.82 um
BC_p
adP
CLK_
PadP
COM
_LZE
RO_P
adP
LON
ERTH
REE_
padP
423.03
40x40 um MA
GNDD
GNDD
GNDD
GNDD
4
ABC130 “RIGHT SIDE” (but represented horizontal to match the paper or.)
30/04/13 F. Anghinolfi/K. Swientek
Follow up on next slide --
PIO
_TRC
VR16
0
PIO
_TRC
VR16
0
200
200
111
PIO
_IN
P
PIO
_IN
P
PIO
_IN
P
PIO
_IN
P
PIO
_IN
P
padID (5)
XoffL
B
Data
LB
111
PIO
_IN
P_PD
111
111
SIO
DVSS
PIO
_REC
160
200
SIO
GND
111
111
111
111
Fast
CLK_
PadP
padT
erm
To “Bottom” side
Chip edge
111
111
1710 um
Abut left pad of next slide
14+377 = 391 um
0 1 2 3 4
XoffL
Data
L
Fast
CLK_
PadN
DVSS
GNDD
5
ABC130 “RIGHT SIDE” (but represented horizontal to match the paper or.)
30/04/13 F. Anghinolfi/K. Swientek
Follow up on next slide --
Digital Power/Ground (6 pads) Left GroupSI
OGN
D
SIO
VDD
SIO
DVDD
SIO
GND
SIO
VDD
SIO
DVDD
7*111 = 777 um
SIO
DVSS
DVSS
BR
GNDD
VDDD
DVDD
GNDD
VDDD
DVDD
DVSS
Special Unit
Abut left pad of next slide
All Power ri
ngs
cut (B
FMOAT)
DVSSBR is NOT treated as a regular pad.
Distance from last supply here, DVSS to DVSSA in the next slide is 162 um
111
111
111
6
ABC130 “RIGHT SIDE” (but represented horizontal to match the paper or.)
30/04/13 F. Anghinolfi/K. Swientek
Follow up on next slide --
Analog Power/Ground (16 pads)
SIO
GND
SIO
GND
SIO
VDD
SIO
DVDD
17*111+162 = 2049
GNDI
T
GNDA
VDDA
AVDD
SIO
DVSS
DVSS
A
Abut left pad of next slide
All Power ri
ngs cut (B
FMOAT)
SIO
DVSS
DVSS
A
GNDI
T
SIO
GND
SIO
GND
SIO
VDD
SIO
DVDD
GNDI
T
GNDA
VDDA
AVDD
SIO
GND
SIO
GND
SIO
VDD
SIO
DVDD
GNDI
T
GNDA
VDDA
AVDD
SIO
GND
SIO
GND
SIO
VDD
SIO
DVDD
GNDA
VDDA
AVDD
162
111
111
7
ABC130 “RIGHT SIDE” (but represented horizontal to match the paper or.)
30/04/13 F. Anghinolfi/K. Swientek
SIO
GND
SIO
VDD
SIO
DVDD
Digital Power/Ground (9 pads) Right groupSI
OGN
D
SIO
VDD
SIO
DVDD
SIO
GND
SIO
VDD
SIO
DVDD
8*111+126= 1014 um
GNDD
VDDD
DVDD
GNDD
VDDD
DVDD
GNDD
VDDD
DVDD
PIO
_DRV
160
PIO
_DRV
160
200
200
111
PIO
_TRC
VR16
0
PIO
_TRC
VR16
0
200
200
111
SIO
GND
111
111
SIO
DVSS
111
Data
outF
C1_P
adN
DATR
XOFF
R
Chip edge
To “Top” side
1577 um 368+14=382 um
Data
outF
C1_P
adP
DATR
B
XOFF
RB
Data
outF
C2_P
adN
Data
outF
C2_P
adP
SIO
DVSS
111
111
126
111
111
DVSS
DVSS
GNDD
8
ABC130 “TOP SIDE”
30/04/13 F. Anghinolfi/K. Swientek
SIO
GND
SIO
VDD
SIO
GND
PIO
_IN
P_PD
SIO
DVDD
SIO
GND
GNDD
VDDD
GNDD
abcu
p_pa
d
VDDD
GNDD
Chip edge
1233.82
PIO
_IN
PRS
TB_p
ad
PIO
_IN
P_PD
PIO
_IN
P_PD
SIO
BPU
08_B
_out
put
PIO
_IN
P_PD
SIO
BPU
08_B
_out
put
PIO
_AN
A
Scan
Enab
le
Scan
_in_
CLK
Scan
_in_
BC
Scan
_out
_CLK
Scan
_out
_BC
SIO
GND
SIO
VDD
VDDD
GNDD
TEST
COM
SIO
GND
GNDD
SIO
GND
GNDD
SIO
GND
GNDD
Analogue PadsAttached to the Analogue FE blockPower rails break
423.03 111
111
111
111
111
111
111
111
111
111
111
111
111
111
306
111
319
3387.82
2290
40x40 um MA
ANA
ANA
AMUX
OU
T
TEST
RES
228.
14 111
6.8mm x 7.9mm (x,y)
ABC130 – Placement on reticle
12.0320
.4<=21
<=20
6.8
7.9
6.8
7.9
6.6652.8
20.4
0.2 (arbitrary)0.
2 (a
rbitr
ary)
1.8
19.03
TDCpix
ABC130
TDCpix_demo
ABC130
20130412
2 ABC130 per reticle, 60 “good” reticles per wafer
6.8mm x 7.9mm (x,y)
ABC130 – Pads list
F. Anghinolfi/K. Swientek 11
Ashley’s Old
4 slides
30/04/13
rather old
y
x
6mm x 7.9mm (x,y)
200µm
250µm
250µm
200µm
200µm250µmLVDS Rx placed on
200µm pitch
Gnd pad, placed 250µm from LVDS pads (between centres)
450µm250µm
3650µm
BC RLCK L0_COM R3_L1FE_GND
GND Pad
700µm
Pads placed on 125µm pitch
A B C
A: REG_AB: REG_DC: ShuntCtrl
ABC130 Bottom Edge – Left Side
Unless indicated ALL bond pads are 95µm x 190µm
VSS (spare) pad omitted - but assume this GND serves the function?
y
x
200µm
300µm
125µm
125µm
200µm
125µm
125µm
200µm
150µm
125µm
XoffL
DataL
FC_CLK
TERM
Chip IDx
Chip IDx
Remaining Pad assignment as prescribed by Francis
125µm
Pads step and repeat at 125µm pitch
Fiducial 3
6mm x 7.9mm (x,y)
ABC130 Bottom Edge – Bottom left corner
y
x
200µm
125µm125µm
200µm
125µm125µm
200µm
FC1
FC2
DataR
XoffR
G
Remaining PAD assignment as prescribed by Francis
PG
P
275µm
125µm
125µm
200µm
150µm
125µm125µm
125µm
Pads step and repeat at 125µm pitch
Fiducial 2
6mm x 7.9mm (x,y)
ABC130 Bottom Edge – Top right corner
y
x
7660µm
3875µm 120µm
120µm
4 off fiducials added
Fiducials are 95µm x 95µm (Ball bond pad)
1 2
34
6mm x 7.9mm (x,y)
ABC130 – Fiducial Detail