A429 Users Manual

8/11/2019 A429 Users Manual

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SBS Avionics Technologies2400 Louisiana Boulevard, NE

AFC Building 5, Suite 600

Albuquerque, NM 87110-4316

Fax: 505-875-0400

Email: [email protected]

http://www.sbs-avionics.com

800-SBS-1553 or 505-875-0600

Applies to model:

A429-PC8, 429-PC16, A429-PC104

A429-cPCI, A429-PCI, A429-PCMCIA, A429-V2

ARINC 429

User s Manual


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ARINC 429 Users Man u al

1998 SBS Technologies, Incorporated. All rights reserved.

ARINC 429 Reference Manual Version 2.0

This document is the intellectual property of SBS Technologies, Inc. (SBS), and contains proprietary

and confidential information. Use, disclosure, and reproduction is permitted only under the terms of

a software license agreement or explicit written permission of SBS. You should not use this document

or it's contents until you have read and agreed to the applicable software license agreement.

This document and its contents are provided as is, with no warranties of any kind, whether express

or implied, including warranties of design, merchantability and fitness for a particular purpose, or

arising from any course of dealing, usage or trade practice.

In no event will SBS be liable for any lost revenue or profits or other special, indirect, incidental and

consequential damage, even if SBS has been advised of the possibility of such damages, as a result

of the usage of this document and the software for which this document describes. The entire liability

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by this document of any part thereof. Please see the applicable software license agreement for full

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RESTRICTED RIGHTS LEGEND

Use, duplication, or disclosure by the Government is subject to restrictions set forth in subparagraph

(c)(1)(ii) of the rights in Technical Data and Computer Software clause at DFARS 252.227-7013.

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SBS Technologies, Inc. and its logo are trademarks of SBS Technologies, Inc. All other brand names

and product names contained herein are trademarks, registered trademarks, or trade names of their

respective holders.


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Tab le o f Co n t en t s i

1: Overview & Startup............................................................................................. 1-1

Co n ve n t io n s ...... . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . 1-2

Arc h ite ct ur e Ove rvie w ....... . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . 1-3

De sig n Rev iew ....... . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . 1-4

2: Control Registers................................................................................................. 2-1

Har d w a re Co n t ro l Reg ist e rs ...... . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . 2-2

Mem o ry Acc e ss ...... . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . 2-9

So ft w ar e Co n t ro l Reg iste rs (ARINC 429 P ro ce ssin g Co nt ro l). . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . 2-11

Sys t e m Clo ck Re g ist e rs ...... . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . 2-20

3: Device Management Firmware Reference.................................................... 3-1

Mo d ule St a rt u p/Te st ...... . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . 3-1

A429 So ft w ar e Do w nlo ad Ins t ru ct ion s . . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. 3-2

Ext e rn a l Trig g e rs ...... . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . 3-11

Ext e rn a l Clo ck...... . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . 3-15

Int e rru pt Ma n a g e m e n t ...... . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . 3-16

4: Transmitter Firmware Reference..................................................................... 4-1

Co n t ro l Blo ck St ru ct u re ...... . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . 4-2

P er iod ic Co m m an d Blo ck Str uc t ur e . . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. 4-8

Ape riod ic Co m m an d Blo ck St ruc t ure . . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. 4-15Ch a n n e l Wra p Ope ra t io n s ...... . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . 4-17

Do ub le-Bu ffe r Tra n sm it Blo ck Fe a t u re ...... . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . 4-20

5: Receive Management Firmware Reference .................................................. 5-1

Rec e ive Da t a St ru ct ur e ...... . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . 5-2

Firm w a re Op e ra t ion ...... . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . 5-9

Co n t ro llin g Op e ra t ion ...... . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . 5-10

6: Bus Monitoring Firmware Reference.............................................................. 6-1

Se q ue n t ial Mon ito rin g ...... . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . 6-2

Glo b a l Re g ist e rs ...... . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . 6-3

Ch a n n e l Reg ist e rs ...... . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . 6-4Filte r Tab le ...... . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . 6-6

Glob al a nd Cha n ne l Seq ue nt ial Mo nit o r Bu ffe rs . . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. 6-8

Mo n ito r B uf fe r Wo rd s ...... . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . 6-10

Trig g e rin g ...... . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . 6-14

A: PCMCIA Socket Controller Setup ...................................................................... A-1

Int ro d u ct io n ...... . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . A-1

Ge n e ra l Ca rd Se rvic e s Info rm a t io n ...... . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . A-2

Ta b l e o f Co n t e n t s


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ii Tab le o f Co n t en t s

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B: Card Specific Information................................................................................. B-1

Mod u le Spe cifi ca t io n s ...... . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . B-2

De sig n Rev iew ....... . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . B-8

Mem o ry Org a n iza t io n ...... . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . B-11

C: A429 Standard Interface Libraries.................................................................... C-1

Co m pile r Issu e s ...... . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . C-1

Libra ry Ref er e nc e Tab le o f Co n t e nt s . . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . . C-2

Dev ice Man ag em en t an d Lo w Lev e l Ro ut ine s . . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . . C-5

BITMan a g e m e n t Ro ut ine s ...... . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . C-33

Rec e ive Man a g e m e n t Ro u t ine s...... . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . C-34

Tra n sm it Man a g e m e n t Ro u t ine s ...... . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . C-42

Mon ito r Man ag em e nt Rou t ine s . . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . C-51

Int e rru pt Man ag e m en t Rou t ine s . . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . . C-62

D: Operating System Specific Information......................................................... D-1

E: ARINC 429 Standard Unit Test............................................................................ E-1

Libra ry Ref er e nc e Tab le o f Co n t e nt s . . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . . E-1

Un it Te st App licat ion ...... . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . E-2

Sa m ple App lica t ion s ...... . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . E-14

F: An ARINC 429 Commentary................................................................................ F-1

P re fa ce ...... . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . F-1

Ab o ut t h e ARINC Org a n iza t ion ...... . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . F-2

Int ro d uc t ion To ARINC 429 ....... . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. F-3

Elec t rica l Elem e n t s ...... . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . F-6

Wo rd An d Pro t o co l Met h o d s ...... . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . F-10

Sum m a ry ...... . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . .. . . . . . . . F-19


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1- 1

The multichannel ARINC 429 Interface (A429) provides concurrent simulation

of multiple transmit channels, monitoring of multiple receive channels, sequen-

tial monitoring, advanced interrupt services, and high-speed host operations.

The microprocessor design incorporates the latest in DSP processor technology

to provide the most flexible, open designed ARINC 429 device in the industry.

The chapters in this manual provide an overview of ARINC architecture and

design along with detailed instructions for starting up and programming the

A429 device. The specific chapters are:

Overview & Startup

Control Registers

Device Management Firmware Reference

Transmitter Firmware Reference

Receive Management Firmware Reference

Bus Monitoring Firmware Reference

Overview &Startup

This chapter serves as an introduction and basic outline of the rest of the

manual.

ControlRegisters

This chapter details the processes (host commands) and control registers which

allow the host application program to control hardware and data structures for

ARINC 429 processing. The host command set syntax and key software control

registers for managing ARINC 429 processing are described, and hardware reg-

isters that are directly accessible from the PC (i.e., CSR, and 48-bit clock) are

detailed in this subsection.

DeviceManagement

FirmwareReference

This chapter details the processes for setting up and general operation of theA429 transmitters and receivers.

TransmitterFirmwareReference

This chapter details the data structures associated with simulating A429 mes-

sages. It explains the definition and management of Transmit command blocks

and their associated data buffers. Command blocks are linked to allow for flex-

ible and accurate A429 simulation.

1: Over view & St ar t up


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1-2 Ov erv ie w & St ar t u p

Do c: 429 ref 01.fm , ve r 2.0, 1 Jun 1999, 09:35

ReceiveManagement

FirmwareReference

The A429 hardware has a sophisticated data structure for real-time monitoring

of ARINC 429 traffic. This chapter shows how to set up individual current value

tables for monitoring. These current value tables are ideal for real-time host pro-

cessing. All current value tables are time-stamped with a 48-bit, 1-sec clock

value.

Bus Monitor ingFirmwareReference

This chapter provides information on how to perform monitoring functions for

the A429 data bus.

1.1 Convent ions

The following conventions appear in this document. These conventions may dif-

fer from those used in other SBS publications. The subsections listed below de-

scribe each convention in more detail:

Typographic Conventions

Symbols

1.1.1 Typographic Conventions

The table below shows the typographic conventions used in this document.

Element Use in body text for: Use in procedures for:

Italic

Document, chapter, section, and

topic titles and cross references.

Emphasis.

Filenames, directory paths

Bold

(Not used in body text.)

Controls, dialogs, menus, and

text or numeric fields that appear

on the screen.

Keys on your keyboard.

Courier Roman

Code examples.

Library function calls.

Simulating the appearance of

screens.

Courier Bold

Emphasizing lines of code.

Commands and other

information that you type as

given.

Angle brackets, e.g.,

Enclosing variable information

that you type in place of a

dummy variable.

Enclosing variable information

that you type in place of a

dummy variable.


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Arch it e ct u re Overv iew 1-3

1.1.2 Symbols

The following symbols appear throughout our manuals.

Warning:

P a r a g r a p h s n e x t t o t h is s ym b o l c o n t a in in f o r m a t io nc r it i c a l t o m o d u le o p e r a t i o n , o r t o y o u r s a f e t y .

Note:

P a r a g r a p h s n e x t t o t h is s ym b o l c o n t a in in f o r m a t io n

im p o r t a n t t o m o d u le o p e r a t i o n .

Tip:

P a r a g r a p h s n e x t t o t h is s y m b o l c o n t a in u s e f u l t i p s .

Cross Reference:

P a r a g r a p h s n e x t t o t h i s s y m b o l c o n t a in

c r o s s r e fe r e n c e s t o a r e la t e d c h a p a t e r o r p a g e i n t h is m a n u a l.

Software Cross Reference:

P a r a g r a p h s n e x t t o t h is s y m b o l

c o n t a in c r o s s re f e r e n c e s t o s o f t w a r e m e d ia in c lu d e d w it h

t h i s p r o d u c t .

1.2 Ar chit ect ur e Over view

The A429 device interfaces host computer systems to multiple ARINC 429

buses.

The A429 architecture uses a DSP processor to handle ARINC 429 simulation

and monitoring tasks. Low-level processes control simulated ARINC 429 mes-

sages, and monitor ARINC 429 messages for protocol verification. High level

processing is responsible for moving ARINC 429 message packets in real-time

to and from data buffers that you define. Your application program defines and

manages Transmit, Receive, and Monitor data structures in a main memory area

where the A429 reads and stores ARINC 429 messages.

Transmit, Receive, and Monitor data structures and host command program-

ming are controlled by the hosts application program. Through memory data

structures and command sets, the host controlling program may direct ARINC

429 data for real-time processing.


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1-4 Ov erv ie w & St ar t u p

Do c: 429 ref 01.fm , ve r 2.0, 1 Jun 1999, 09:35

NOTE: Th e c h ap te r s e n t it l e d Con t ro l Reg ist e rs,

Dev ice M an-agem en t Fi rm w a re Refe rence

, Transm i t t e r Fi rm w are Refe r -ence

,

Rece ive Managem ent Fi rm w are Refe rence

,

a n d

Bu sM on i to r i ng F irm w a re Re fe renced e t a il t h e h o s t i n t e r f a c e t oth e A429-P C a p p l ic a t io n c o n t ro l s t ru c t u re s .

1.3 Design Review

The design of the A429 incorporates an open systems philosophy. The A429 is

a generic processing engine (the DSP processor and most of the hardware clock

and control circuits are software programmable) that can be configured through

various application programs. This manual explains the application program

(firmware) SBS has designed for optimal ARINC 429 bus processing and sim-

ulation. In this application, processing for each of the four, eight, or sixteen

channels is performed independently through host-defined Transmit, Receive,

and Monitoring data structures (detailed in later chapters). The board's design

allows for custom programs (written by the customer or SBS) to correlate data

between channels, or provide advanced processing to off-load the host system.

For all boards except cPCI, PCI, and PCMCIA, you need to set address DIP

switches in order for the host to access the board. For the PC8, PC16, and

PC104, you use the switches to set the boards base I/O register. For the V2, the

switches are used to set the boards base address and address mode. Other host

settings for interrupt level and vectors are software programmable and are de-

tailed later in theChapter 2: Control Registers

chapter.


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2- 1

The sections in this chapter provide a review of control registers. Control regis-

ters provide key setup information used by the host and A429 system (i.e., set-

ting the board's control and status register). In host programmed control

registers, information processing remains unchanged during activation of A429

processing for the respective channels.

The first section describesHardware Control Registers

. The hardware control reg-

isters provide the following module functions to the host:

A429 reset and operation control

Host interrupt control

DSP interrupt control

A429 memory access control

TheMemory Access

section describes the I/O port reads and writes to necessary

to access A429 memory. TheSoftware Control Registers (ARINC 429 Processing

Control)

section describes the holds and parameters which define interrupt

queues, transmit and receive operations, and sequential monitor control.

Note:

All ad d re sse s an d d a t a v a lu e s a re i n h e xad e c i m a l .

2: Con t ro l Regist er s


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2-2 Co n t ro l Re gist e rs

Do c: a 429 ref 02.fm , ver 2.0, 1 Jun 1999, 09:35

2.1 Ha rdw a r e Co ntr o l Re giste rs

Table 2.1.1lists the hardware control registers. Detailed discussions for each

register follow the table.

Table 2.1.1: Hardw are Con t ro l Regist ers

PC8

PC16

PC104

V2

cPCI/PCI

PCMCIA

Name

Word Addr

Byte Addr

(in hex)

Description

CSR00

000

Control/Status Register. Key regis-

ter for proper initialization and op-

eration of the A429.

CSR204

008

PC16 Control/Status Register 2.

Key register for proper initialization

and operation of the PC16 Device 2.

CSR 2000040000

Control/Status Register. Key regis-ter for proper initialization and op-

eration of the A429.

CSR01

002

I/O Control/Status Register. Key

register for proper initialization and

operation of the PCM.

ADRS_PORT01

002

Address Port for host access to the

devices RAM. This register con-

tains 16 bits corresponding to word

addresses 0000h to FFFFh.

DATA_PORT02

004

Data Port 1 for reading/writing to

Device 1 RAM.

ADRS_PORT201

002

Address Port 2 for host access to the

PC16 Device 2 RAM. This register

contains 16 bits corresponding to

word addresses 0000h to FFFFh.

DATA_PORT202

004

Data Port 2 for reading/writing to

PC16 Device 2 RAM.

BASE_ADR01

002

Memory Base Address Register.

Register used to set the memory

base address of the board in the

PC104 hosts memory area.

INTV_A429

(r/w)

01

002

Bits 0-7 of this register set the

VMEbus interrupt vector for A429

user-selected interrupts for the V2.

Bit 0 is the least-significant bit.

INTV_A429

Gen Inter

(wo)

02

004

Write any data to this register to

cause a VMEbus interrupt (having

the vector specified by word ad-

dress 01h) to occur. This is used for

factory testing but may also used by

the user to verify proper VME ISR

operation.

PLD_DNLD

(wo)

00

000

PLD Download Register. Register

downloads the PLD data.


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Hard w ar e Co n t r o l Re gist e rs 2-3

2.1.1 I/O Control/Status Register

I/O Control/Status Register (CSR) contains bits which control module opera-

tion, and PC and DSP interrupts. Except where otherwise noted, the host has

both read and write access to the CSR bits.

Note:

Th e f o llo w in g t a b l e is u se d f o r t h e P C 8 an d th e P C 16.

Table 2.1.2: PC8/ PC16 Device 1 Co n t ro l / St at u s Regist er

Bit No. Function Description

0 Window Select 10 = lower 128k bytes

1 = upper 128k bytes

1 Reserved

2 Auto Increment 1When set to 1, causes the address port(ADRS_PORT1) to increment to the next word

address with each access to the data port, read or

write.

3 PC Interrupt Enable0 = PC Interrupts disabled

1 = PC Interrupts enabled

4 Interrupt Level Select 0 These bits determine the PC interrupt priority level

to be used by the board. This level is used by all in-

terrupts:

000 = No Interrupt100 = IRQ10

001 = IRQ5101 = IRQ11

010 = IRQ7110 = IRQ12

011 = IRQ9111 = IRQ15

5 Interrupt Level Select 1


7Interrupt Pending (RO)

Interrupt Clear (WO)

0 = No interrupt pending, 1 = Interrupt pending

0 = No function, 1 = Clears pending interrupt

8

Dual Device (ro)

Signal 1 (wo)

[0 = 2nd device not present, 1 = 2nd device present

(PC16)]

0 = No function, 1 = Signal processor 1 (future use

only)

9 Run 0 = Firmware Stop, 1 = Firmware Run

10-15 Reserved


12/244



Table 2.1.3: PC16 Device 2 Co n t ro l / St at u s Regist er


0 Window Select 20 = lower 128k bytes

1 = upper 128k bytes

1 Reserved

2 Auto Increment 1

When set to 1, causes the address port

(ADRS_PORT2) to increment to the next word ad-

dress with each access to the data port, read or

write.

3 PC Interrupt Enable0 = PC Interrupts disabled

1 = PC Interrupts enabled

4 Reserved

5 Reserved

6Interrupt Pending 1 (ro)

Interrupt Clear 1 (wo)

0 = No Interrupt 1 pending, 1 = Interrupt 1 pending

0 = No function, 1 = Clears pending Interrupt 1

7Interrupt Pending 2 (ro)

Interrupt Clear 2 (wo)

0 = No Interrupt 2 pending, 1 = Interrupt 2 pending


8Dual Device (ro)

Signal 1 (wo)

0 = 2nd device not present, 1 = 2nd device present

0 = No function, 1 = Signal processor 2 (future use

only)

9 Run 2 0 = Firmware Stop, 1 = Firmware Run

10-15 Reserved


13/244


Table 2.1.4: PC104 Co n t ro l / St at u s Regist er


0 Channel Enable0 = memory accesses ignored

1 = memory accesses acknowledged

1 Select 0 Memory Bit selection bit 0

2 Select 1 Memory Bit selection bit 1

3 PC104 Host Interrupt Enable0 = PC104 Host Interrupts disabled

1 = PC104 Host Interrupts enabled

4 Interrupt Level Select 0 These bits determine the PC interrupt priority level

to be used by the board. This level is used by all in-

terrupts:

000 = No Interrupt100 = IRQ10

001 = IRQ5101 = IRQ11

010 = IRQ7110 = IRQ12

011 = IRQ9111 = IRQ15



7Interrupt Pending (ro)

Interrupt Clear (wo)

0 = No interrupt pending, 1 = Interrupt pending


8

Signal (ro)

Select 0* (wo)

0 = No function, 1 = Signal processor (future use

only)

0 = Select 0 is set, 1 = Select 0 is not set

9 Run 0 = Firmware Stop, 1 = Firmware Run

10-15 Reserved


14/244



Table 2.1.5: V2 Co n t ro l / St at u s Regist er

Table 2.1.6: V2 CSR In t erru p t Leve l Select Bit s


0 Run0 = firmware stop

1 = firmware run

1 Code Location Select

0 = load from data RAM

1 = load from FLASH memory

2 ReservedReserved for factory test purposes. SET THIS BIT

TO 0 WHEN WRITING TO THE CSR.

3 VMEbus Interrupt Enable

0 = clear

1 = enable interrupt

When this bit is enabled, an interrupt can be gener-

ated by the V6 with the corresponding vector in

register word offset 01h.



0 = no interrupt

1 = interrupt pending (read)

/clear interrupt (write)

Read this bit to determine whether a VMEbus in-

terrupt is pending. Set this bit to clear the interrupt.

5-7

Interrupt Level Select 0 Interrupt

Level Select 1 Interrupt Level Select

2

These bits determine the VMEbus interrupt

priority level to be used by the V2 board.

This level is used by all interrupts.

8-15 Reserved Reserved for future use

CSR

Bit No.

Bit

Function

Interrupt level

(s e t b it s 5-7 a s illu s t r a t e d b e low f or t he d e s i re d in t e r ru p t le ve l )

level 0 level 1 level 2 level 3 level 4 level 5 level 6 level 7

5Interrupt Level

Select 00 1 0 1 0 1 0 1

6Interrupt Level

Select 00 0 1 1 0 0 1 1

7Interrupt Level

Select 00 0 0 0 1 1 1 1


15/244


Table 2.1.7: V2 Hardw are Co n t ro l Regist ers

Table 2.1.8: cPCI/ PCI Co n t ro l / St at u s Regist er

NameWord AddrByte Addr

(in hex)

Description

INTV_A429

(r/w)

01

002

Bits 0-7 of this register set the VMEbus interrupt vector for A429

user-selected interrupts for the V2. Bit 0 is the least-significant bit.

INTV_A429

Gen Inter

(wo)

02

004

Write any data to this register to cause a VMEbus interrupt (having

the vector specified by word address 01h) to occur. This is used for

factory testing but may also used by the user to verify proper VME

ISR operation.


0 Run 0 = firmware stop1 = firmware run

1 DSP Startup Mode0 = load from data RAM

1 = load from FLASH memory

2 Reserved

3 cPCI/PCI Interrupt Enable0 = cPCI/PCI Interrupts disabled

1 = cPCI/PCI Interrupts enabled

4-6 Reserved



0 = no interrupt

1 = interrupt pending (read)

/clear interrupt (write)

Read this bit to determine whether a host

interrupt is pending. Set this bit to clear the

interrupt.


Note: Ex c ep t w h e r e o t h e r w i se n o t e d , t h e h o s t h a s b o t h r e a d a n d w r it e a s s e ss t o t h eSER bits.


16/244



Table 2.1.9: PCM CIA I/ O Co n t ro l / St at u s Regist er Bit s

Table 2.1.10: PCM CIA Dow n lo ad Regist er


0 Run0 = firmware stop

1 = firmware run

1 Select 0 Memory WIndow selection bit 0

2 Select 1 Memory WIndow selection bit 1


5 Program Enable 1 = Enable board for DSP programming

6 PMC host Interrupt Enable0 = PCM host interrupts disabled

1 = PCM host interrupts enabled


Interrupt Clear (ro)

0 = No interrupt pending, 1 = An interrupt is pending



Note:E xc e p t w h e r e o t h e r w i s e n o t e d , t h e h o s t h a s b o t h r e a d a n d w r it e a c c e s s t o t h eCSR bi ts .


0 PLD Data Holds value of PDL data bit being stored

1 PLD Clock Clock bit used to store PLD data

2 PLD Reset0 = PLD

1 = Normal operation

3 PLD Output Enable0 = Disable output

1 = Enable output



17/244

M em o ry Access 2-9

2.2 Memory Access

Tab le 2.2.1: Mem o ry Base Ad d ress Regist er (BASE_ADR) fo r PC104

Table 2.2.2: Device1 (2) Mem o ry Add ress Regist er (ADRS_PORT1(2)) fo r t h ePC8/ PC16

Table 2.2.3: Ext ern al Ou t p u t Por t Regist er (DATA_PORT1 (2))fo r t h e PC8/ PC16

BIt Function Description

0 Address 16 Address Line 16 Compare Value








8 Enable Change 0 Must write as 1 to allow change of address

9 Enable Change 1 Must write as 0 to allow change of address10-15 Reserved --

PC8

PC16


0-15Output Address

(ro)

Provides address for access to device 1 RAM

(ADRS_PORT1 and ADRS_PORT2 for the PC16)

PC8

PC16


0-15Input/Output

Data (ro)

Provides data to/from RAM (DATA_PORT1 and

DATA_PORT2 for the PC16)


18/244

2- 10 Con t r o l Reg ist e r s


For the PC8 and PC16, memory access is accomplished through I/O port reads

and writes. The PC8 has two and the PC16 has four 16-bit I/O ports provided

for accessing A429 memory (seeTable 2.2.2andTable 2.2.3).

To access a PC8 or the first device on a PC16

1. Lo a d t h e a d d r e s s t h a t is t o b e w r it t e n t o o r r e a d f r o m in t o AD RS _P ORT

(ADRS_P ORT1 o f De vice 1 fo r t he P C16).

2. Rea d o r w rite t o DATA_P ORT(DATA_P ORT1 of Dev ice 1 fo r t he P C16) to ac ce ss

m em ory a t th e ad d ress sp ecifi ed by ADRS_PORT(ADRS_PORT1 of Device 1 for

th e P C16).

3. To a c c e s s D e vic e 2 o f t h e P C 16, w r i t e t h e a d d r e s s t o b e a c c e s s e d t o

ADRS_PORT2 an d rea d o r w rite th e d at a t o o r fro m DATA_PORT2.

In t he PC8, b i t 0 o f t he CSR (CSR1 an d CSR2 of th e P C16) selec t s th e up per o r

low er 128 k ilo by te s o f A429 m em ory . Use th is b i t t o a cce ss th e fu l l 256

kilo by te s o f m em o ry . In t he PC16, use CSR1 bi t 0 to acc ess t he fu l l 256 ki lo by te so f D ev ic e 1 m em o r y a n d u s e C SR2 b it 0 t o a c c e s s t h e f u l l 256 kilo b y t e s o f

D ev ic e 2 m e m o r y .

Note:Ad d re ss es 0000h -07FFh a nd 10000h-107FFh a re re -s e r v e d f o r i n t e r n a l u s e b y t h e d e v ic e .

4. Set b it 2 of th e CSR to 1 t o ca use ADRS_PORT(ADRS_PORT1 of De vice 1 fo r t he

P C 16) t o a u t o m a t i c a lly in c r e m e n t t o t h e n e x t w o r d l o c a t i o n w it h e a c h a c c e s s

o f t h e DATA_P ORT(DATA_P ORT1 o f De vice 1 fo r t h e P C16).

Th is a llo w s a c c e s s t o a r a n g e o f A429 d e v ic e m e m o r y w it h o u t h a v in g t o u p d a t e

AD RS_P O RT w it h ea c h m em o r y r ea d o r w r it e .

5. For t he PC16 yo u ne ed to se t b i t 2 o f CSR2 to 1 to cau se ADRS_PORT2 to

a u t o m a t i c a lly in c r e m e n t t o t h e n e x t w o r d lo c a t io n w it h e a c h a c c e s s o f t h e

DATA_PORT2.

To access A429 memory, complete the following steps:

1. Se t t h e I/O ba s e a d dr es s t o a n a v a i la b le lo c a t io n be t w een 000h a n d 7F Fh .

Note: In t he P C16, co m ple te s t eps 2-5 fo r eac h de vice (Device

1 a n d 2). To a cc e ss De vice 1, us e CSR1, ADRS_P ORT1, a n dDATA_P ORT1. To a c c e ss De vic e 2, us e CSR2, ADRS_P ORT2, a n d

DATA_P ORT2.


19/244

Sof t w are Con t ro l Reg ist e rs (ARINC 429 Processing Con t ro l ) 2 -11

2. S e t t h e d e v i ce m e m o r y w in d o w s e le c t b i t (b i t 0) in t h e C SR t o 0 f o r w in d o w

1 o r 1 fo r w in d o w 2.

3. If des i r ed , s e t t h e a u t o - in c r em en t b i t (b i t 2) t o 1 t o a u t o m a t i c a l ly in c r em en t

t h e a d d re ss in ADRS_P ORT.

4. Wr it e t h e a d d r e s s o f t h e A429 m e m o r y lo c a t io n t h a t is t o b e a c c e s s e d t o

ADRS_PORT.

5. Write to or re ad f ro m DATA_PORTto acc ess A429 m em ory a t t he ad dre ss

sp e cifi e d b y ADRS_P ORT.

2.3 Soft w are Contr ol Registers (ARINC 429 Processing Contr ol)

The Software Control Registers table contains parameters and pointers to vari-

ous data structures required for successful operation of the A429 devices firm-

ware.

Note: To ac c e ss a ll s ix te e n c h an n e l s o f th e b o a rd , th e p a ram -e t e r s a n d d a t a s t r u c t u re s d e s c r ib e d in t h i s t a b le m u s t b e d e -

fi ne d fo r bo t h de vices o f th e A429-PC16. For Device 1, ac ces s

th e pa ram et ers a nd da t a s t ruc t ures t h ro ug h DATA_PORT1.

Fo r D e vic e 2, a c c e s s t h e p a r a m e t e r s a n d d a t a s t r u c t u r e s

t h ro u g h DATA_P ORT2.


20/244



Table 2.3.1: So ft w are Co n t ro l Regist ers - D16 Access

Name(host

access)

Word

AddrByte Addr

(in hex)

Description

General Control Registers

CMD

(wo)

880

1100

Commands the start of ARINC 429 bus processing. Write a non

zero value to this register to start bus processing. Write a zero to

this register to halt bus processing.

RESP

(ro)

881

1102

This word continuously increments in response to CMD not set to

zero. This provides a simple check that the firmware is running.

While counting, this word should never be equal to zero (zero is

skipped in the counting).

DVTYPE

(ro)

842

1084

Device Type. Indicates the total number of channels available on

the A429 device.

RXCNT

(ro)

843

1086

Receive Count. Indicates the total number of receivers available.

This value should match the value set during start-up in offset800h.

TXCNT

(ro)

844

1088

Transmit Count. Indicates the total number of transmitters avail-

able. This value should match the value set during start-up in offset

801h.

CHCPTR884

1108

Channel control pointer. Points to the base of the channel control

table. CHCPTR contains a value of 900h.

BTCSR

(r/w)

885

110A

Bus traffic control/status. Set this register to a nonzero value to re-

set the bus traffic word count (BTWCNT) to "0". This register will

be cleared to "0" when the word count has been reset.

GFLAG

(r/w)

886

110C

Global Flag. This register is the global control register for all

transmit blocks. Set bit 0 of this register to a 1 to cause the Endof Command Interrupt NOT to occur when the NO-OP bit is set.

System Clock Registers

SCLOW

(r/w)

896

112C

The firmware uses an internal 48-bit, 1-microsecond timer.

Contains the least significant 16 bits.

SCMID

(r/w)

897

112EContains the middle 16 bits of the system timer.

SCHIGH

(r/w)

898

1130

SCHIGH contains the most significant 16 bits of the system timer.

CCW

(r/w)

899

1132

Clock Control Word. Each bit corresponds to an action. Bit 0: read

timer and update SCHIGH, SCMID, and SCLOW, send interruptcode 7 when update is valid; Bit 1: read timer and update SCHIGH,

SCMID, and SCLOW, no interrupt; Bit 2: reset internal timer with

values stored in SCHIGH, SCMID, and SCLOW. Updates and re-

sets are done within 100 microseconds.


21/244


Interrupt Registers

IQRSP

(r/w)

89B

1136

Interrupt Queue Response flag word: Set IQRSP=FFFFh to process

interrupts. Set IQRSP=0001h when processing is complete.

IQPTR1 *

(r/w)

89C

1138

Offset to Interrupt Queue 1. This queue is processed by the host

computer.

IQPTR2 *

(r/w)

89D

113A

Offset to Interrupt Queue 2. This is the queue which is currently

active. The host should NOT process this queue.

IQCNT1

(ro)

89E

113C

Contains the number of entries in Interrupt Queue 1. This is used

by the host computer's ISR to process the IQPTR1 queue.

IQCNT2

(wo)

89F

113E

Contains the number of entries in Interrupt Queue 2.

Warning:D o no t a c c e s s t h i s r e g i s t e r w hi le t h e A429de vice i s proce ss ing ARINC 429 da ta .

IQNUM

(r/w)

8A0

1140

Defines the maximum number of entries per interrupt queue. If the

number of entries exceeds the value in IQNUM, an interrupt over-

flow will occur. The default value for this register is "4".

Transmit Operation Registers

Addresses are offsets from the base of each channel control table. Channel control tables

start at 900h and have a length of 1Fh. Therefore, channel 1 table occupies 900h to 91Fh,

channel 2 table occupies 920h to 93Fh, etc.

CHTYPE

(ro)Offset 00

Channel type. This word defines whether the control table is being

used for a receiver or transmitter channel. If this register contains

0h, the channel is a receiver; if this register contains FFFFh, the

channel is a transmitter.

CMDBCW

(r/w)Offset 01

Command block control word. This word governs transmit and

command block operations for a specific channel. Set bit 0 of

CMDBCW to 1 to halt processing of the command block upon

completion of the current command block. Set bit 1 of CMDBCW

to 1 to cause the channel to operate at 100 KHz. Set bit 1 to 0

to cause the channel to operate at 12.5 KHz. Set bit 3 of CMDBCW

to 1 to enable Channel Wrap. Set bit 3 of CMDBCW to 0 to

disable Channel Wrap. Set bit 4 of CMDBCW to 1 to enable

Channel Wrap Error Injection. Set bit 4 of CMDBCW to 0 to

disable Channel Wrap Error Injection.

CBIPTR

(r/w) Offset 02

Command block initial pointer. This location is continuously mon-

itored by the A429's firmware. When CBIPTR is nonzero, the

firmware sets this pointer to zero and executes a chain of command

blocks beginning at the offset defined in CBIPTR.

CBCPTR

(ro)Offset 03

Command block current pointer. This location points to the current

location in the command block structure. This pointer is zero until

processing of a command block structure begins.

CBLPTR

(ro)Offset 04

Command block last pointer. This location indicates the last com-

mand block that was executed before a halt occurred.

Name

(hostaccess)

Word

AddrByte Addr

(in hex)

Description


22/244



MNFCNT

(r/w)Offset 05

Minor frame count. This value determines the number of minor

frames to be executed for each major frame.

MNCNT(ro)

Offset 06 Minor count. This value indicates the current minor frame beingprocessed.

MJFCNT

(r/w)Offset 07

Major frame count. This value determines the number of major

frames to execute before halting command block processing. Set

MJFCNT to "0" for continuous operation.

MJCNT

(ro)Offset 08

Major count. This value indicates the current major frame being

processed.

CBCTMP

(ro)Offset 09

Temporary command block current pointer. This register is used

for A-periodic block processing. This value is only used by the

A429 firmware.

TXHPAM(r/w)

Offset 0A

Transmit high priroity asynchronous message. This control register

allows the transmission of additional block(s) within a minor frameor transmit block whenever there is DEAD bus time. Program the

high priority command block pointed to by TXHPAM (Ah).

TXLPAM

(r/w)Offset 0B

Transmit low priority asynchronous message.This control register

allows the transmission of additional block(s) within a minor frame

or transmit block whenever there is DEAD bus time. Program the

low priority command block pointed to by TXLPAM (Bh), then

program TXLPAT (Ch) register with the time required to execute

the block.

TXLPAT

(r/w)Offset 0C

Transmit low priority asynchronous time. This register is used with

TXLPAM and contains the amount of time required to execute the

message block.

LFRAME

(ro)Offset 0D

Low frame. This register contains the least significant 16 bits of

the 48-bit time at which the last minor frame type command was

processed.

MFRAME

(ro)Offset 0E

Middle frame. This register contains the middle 16 bits of the 48-

bit time at which the last minor frame type command was pro-

cessed.

HFRAME

(ro)Offset 0F

High frame. This register contains the most significant 16 bits of

the 48-bit time at which the last minor frame type command was

processed.

CWPTR

(r/w)Offset 10

Channel Wrap Pointer. Used for channel wrap feature and consists

of LMASK, HMASK, and TXWCNT for each label.

BTWCNT

(ro)Offset 12

Bus traffic word count. The value in this register increments for

each word received or transmitted. A word count is provided for

each channel.

CHLED

(ro)Offset 13

Channel Activity Indicator. Indicates bus activity for a specific

channel: 0000h = not active, 00FFh = active, FF00h = transmitting

with errors.

Name

(hostaccess)

Word

AddrByte Addr

(in hex)

Description


23/244


Command Block Pointer Locations

Addresses are offsets from the base of each command block

CMDTYP Offset 0 Command type. This register specifies the type of command and actionto take. 0 = minor frame type, 1 = transmit type.

MFLTME

(r/w)Offset 01

Minor frame low time. This register contains the lower 16 bits of the

time, in microseconds, allotted for a minor frame.

MFHTME

(r/w)Offset 02

Minor frame high time. This register contains the upper 16 bits of the

time, in microseconds, allotted for a minor frame.

SCLTME

(r/w)Offset 01

Schedule low time. This register contains the lower 16 bits of the time,

in microseconds, that must expire before the transmit command block

is processed. The time is referenced from the minor frame.

SCHTME

(r/w)Offset 02

Schedule high time. This register contains the upper 16 bits of the

time, in microseconds, that must expire before the transmit command

block is processed. The time is referenced from the minor frame.

TBCNT

(r/w)Offset 03

Transmit buffer count. This register is associated with the transmit

type command and indicates the number of words to transmit. Each

value to be transmitted requires three 16-bit words. The first word is

the control word, followed by the lower 16 bits of the ARINC data

word, followed by the upper 16 bits of the ARINC data word. There-

fore, the total length of the transmit buffer is TBCNT * 3.

TXWCNT

(r/w)N/A

Transmit word control. Use this register to inject errors on and control

a transmitted data word. Set one of four bits to 1 to inject the follow-

ing errors: Bit 0: Parity Disable, Bit 1: Generate Even Parity, Bit 2: En-

able Bit Errors, Bit 3: Add/Subtract a Bit, and Bit 5: Transmit sync.

TXWCNT is stored with the data word in the transmit data buffer as

the first 16-bit word in the 3-word block. Bits 12-14: Used to program

interword gap (0-15) bit times. Bit 10: 0 = default or sustain gap time,1 = set gap time.

TDBPTR

(r/w)Offset 04

Transmit data buffer pointer. This value is associated with the transmit

type command and points to the base of the transmit buffer for the as-

sociated command block.

WRDCNT

(ro)Offset 05

Word count. This register is associated with the transmit type com-

mand and indicates the current location in the transmit data buffer.

START

(r/w)Offset 06

Start frame. This register indicates which minor frame a transmit type

command block will begin executing.

REPRTE

(r/w)

Offset 07

Repetition Rate. This register indicates how often to process a transmit

type command block after the START condition is met. If REPRTE=2,

processing of the command block will occur every other time the asso-

ciated command block is accessed. If no minor frame structure is de-

fined, set this value to "0".

LNKPTR

(r/w)Offset 0B

Link Pointer. This value points to the next command block. If LNKP-

TR equals zero, processing of the command structure for that channel

will halt.

Name

(hostaccess)

Word

AddrByte Addr

(in hex)

Description


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Receive Registers

Addresses are offsets from the base of each channel control table. Channel control tables

start at 900h and have a length of 1Fh. Therefore, channel 1 table occupies 900h to 91Fh,channel 2 table occupies 920h to 93Fh, etc.

CHTYPE Offset 00

Channel type. This word defines whether the control table is being

used for a receiver or transmitter channel. If this register contains

0h, the channel is a receiver; if this register contains FFFFh, the

channel is a transmitter.

RCVCW

(r/w)Offset 01

Receive control word. This word contains eight bits used for con-

trolling receiver operations.

Bit 0 1=run, 0=halt

Bit 1 1=100KHz, 0=12.5KHz

Bit 2 1=interrupt on error, 0=no interrupt

Bit 3 1=sort by SDI/label, 0= sort by label Bit 4 1=channel monitor halted (RO), 0=channel monitor

running

Bit 5 1=restart channel monitor, 0=don't restart

Bit 6 1=force channel monitor swap, 0=no swap

Bit 7 1=interrupt on channel monitor swap, 0=no interrupt

Bit 8 1=swap current value table, 0=no swap

Bit 9 Interrupt on current value swap.

Bit 12 1=channel wrap enabled, 0=channel wrap disabled

CVBPTR

(r/w)Offset 02

Current value buffer pointer. This register contains the pointer to

the base of the receive current value buffer. The current value buff-

er is a buffer where the most current data for each received word is

stored by SDI, label, or both. Use this pointer to service the currentvalue table.

CTBPTR

(ro)Offset 03

Current time buffer pointer. If nonzero, a 48-bit time stamp is sup-

plied for received data. The time stamps are sorted by SDI, label,

or both. Use this value to service the current time table.

GFTPTR

(r/w)Offset 04

Global Filter Pointer. This register contains an offset to a table of

128 or 512 words arranged by SDI, label number, or both. Entries

in this table govern interrupts and sequential monitoring for each

possible receive SDI, label, or both. The bits in each word in the

table determine the following: Bit 0: Sequential Monitor Enable,

Bit 1: Interrupt on Label, Bit 2: Disable Parity Checking, and Bit

3: Buffer Swap on Label.

CFTPTR

(r/w)Offset 05

Channel filter pointer. This register contains an offset to a table of128 or 512 words arranged by SDI, label number, or both. Entries

in this table govern interrupts and sequential monitoring for each

possible receive SDI, label, or both. Bits in each word in the table

are as follows: bit 0-channel monitor enable, bit 3-buffer swap on

label.

N o t e : i f pa r i t y d i s a b l e is s e t f o r t h e g l o b a l s e q ue n t i a lm o ni t o r , pa r i t y c he c k wi l l a u t o m a t i c a l ly be d i s a b l e d fo rt h e c h a n n e l m o n i t o r s .

Name

(hostaccess)

Word

AddrByte Addr

(in hex)

Description


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CVAPTR(r/w) Offset 06

Current value active pointer. This register contains a pointer to the

currently active current value buffer. To get the current values, set

bit 8 of RCVCW to a "1'. This will cause the pointers CVBPTR andCVAPTR, as well as CVTPTR and CTAPTR, to swap. Bit 8 of

RCVCW will be set to 0 when it is safe to read the current values.

Always read from the buffer pointed to by CVBPTR.

CTAPTR

(r/w)Offset 07

Current time active pointer. This register contains a pointer to the

currently active current time buffer. (see discussion of CVAPTR

for servicing procedures)

CWTX

(r/w)Offset 08

Channel wrap transmitter. Used for channel wrap feature, desig-

nates which transmitter data will be channel wrapped to. Valid

transmit channels are 2 thru 8.

LABCNT(ro) Offset Ah

Label counter. This register contains an offset table to a table of

256 words arranged by Label number. Entries in this table provide

a counter for each time the Label is encountered. (Used by PASSfor frequency calculation between received labels on the same

channel.)

* CMIPTR

(r/w)Offset Bh

Channel monitor initial pointer. This register contains a pointer to

the base of the channel monitor. This value must be initialized to a

nonzero value prior to writing a nonzero value to the CMD register.

CMCPTR

(ro)Offset Ch

Channel monitor current pointer. This register contains a pointer to

the currently active channel monitor buffer. Received data is stored

in this buffer.

CMLPTR

(ro)Offset Dh

Channel monitor last pointer. This register contains a pointer to the

last monitor buffer filled. Data in this buffer is safe to read.

CMCNT

(r/w)Offset Eb

Channel monitor count. This register contains a value indicatingthe monitor swap count. This value is incremented each time a

channel monitor swap occurs. It can be initialized to any value.

This value will roll over to 0000h once FFFFh swaps occur.

CMCNT is stored in the channel monitor buffer at offset 4 when a

swap occurs.

BTWCNT

(ro)Offset 12

Bus traffic word count. The value in this register increments for

each word received or transmitted. A word count is provided for

each channel.

CHLED

(ro)Offset 13

Channel Activity Indicator. Indicates bus activity for a specific

channel: 0000h = not active, 00FFh = active, FF00h = receiving

with errors.

Name

(hostaccess)

Word

AddrByte Addr

(in hex)

Description


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Figure 2.3.1gives a pictorial representation of the software control registers.

Sequential Monitor Registers

GMCWRD

(r/w)

8A9

1152

Global monitor control word. This word governs sequential mon-

itoring on a global level. The bits determine the following:

Bit 0 Monitor Halted Bit 3 Interrupt on Swap

Bit 1 Restart Monitor Bit 4 Buffer Overflow

Bit 2 Force Buffer Swap

* GMIPTR

(r/w)

8AA

1154

Global monitor initial pointer. Points to the base of the first se-

quential monitor buffer. This pointer must be a nonzero value prior

to writing a nonzero value to the CMD register.

GMCPTR

(ro)

8AB

1156

Global monitor current pointer. Points to the base of the currently

active sequential monitor buffer.

GMLPTR

(ro)

8AC

1158

Global monitor last pointer. Points to the base of the last sequential

monitor buffer that was accessed.

GMCNT

(r/w)

8AD

115A

Global Monitor Buffer Counter.

Trigger Registers

TRGCW

(r/w)

8A3

1146

Trigger control word. This value defines the trigger location and

indicates trigger activity:

0=triggering stopped 2=trigger at middle

1=trigger at start 3=trigger at end

TGIPTR

(r/w)

8A4

1148

Trigger initial pointer. Indicates the base offset of the first trigger

control block. This value must be nonzero for trigger operation.

TGCPTR

(ro)

8A5

114A

Trigger current pointer. Indicates the base offset of the currently

active trigger control block.TGLPTR

(ro)

8A6

114C

Trigger last pointer. Indicates the base offset of the last trigger con-

trol block that was accessed.

XTCWD

(r/w)

8B0

1160

External trigger control word. This value governs external triggers

1, 2 and 3. The bits determine the following:

Bit 0 Enable External Triggers

Bit 1 External Trigger 1 Select

Bit 2 External Trigger 2 Select

Bit 13 Enable Trigger IN for External Clock (Wait for External

Trigger).

Bit 14 Enable Clock Master

0=Master 2=Slave

Bit 15 Enable External ClockLEGEND:

* Entry required for proper firmware operation

r/w = read/write, ro = read only, wo = write only

Word offset locations between 840h and AFFh that are not described in this table are re-

served. Accessing these locations produces unpredictable results.

Name

(hostaccess)

Word

AddrByte Addr

(in hex)

Description


27/244


Figure 2.3.1: Sof t w are Con t ro l Regist ers

8FFh

8AEh

CMD

RESP

RESERVED

RESERVED

CHCPTR

BTCSR

|

RESERVED

APPL PROD CODE

APPL VER NUM

DVTYPE

RXCNT

TXCNT

BRDMOD

|

|

RESERVED

SCLOW

SCMID

SCHIGH

CCW

RESERVED

IQRSP

IQPTR1

IQPTR2

IQCNT1

IQCNT2

IQNUM

RESERVED

RESERVED

TRGCW

TGIPTR

TGCPTR

TGLPTR

RESERVED

RESERVED

GMCWRD

GMIPTR

GMCPTR

GMLPTR

XTCWD

RESERVED

|

880h

840h

845h

884h

896h

89Bh

8A3h

8A0h

8A9h

8B0h

87Fh

CH1TBL

|

CH2TBL

|

CH3TBL

|

CH4TBL

|

CH5TBL

|

CH6TBL

|

CH7TBL

|

CH8TBL

|

900h

920h

940h

960h

980h

9A0h

9C0h

9E0h

A00h

871h

870h

LSTEND

LSTST

GFLAG886h

GMCNT

PC104

PC8/cPCI-8/PCI-8/

PC16/V2


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2.4 Syst em Clo ck Regist er s

2.4.1 Clock Control Word (CCW), SCHIGH, SCMID, SCLOW

To obtain the latest time information, set bit 1 of the clock control word (CCW)

to 1. This causes the firmware to calculate the current 48-bit system time and

update the SCHIGH, SCMID, and SCLOW registers. When it has updated these

registers, the firmware clears CCW, indicating to the user that the time update is

complete. The firmware completes this action within 100 microseconds after bit

1 of CCW is set to 1. Set bit 0 to 1 (instead of bit 1) to cause the firmware

to update the time registers and interrupt (with interrupt code 7) the host imme-

diately after the time update is complete.

SCHIGH, SCMID, and SCLOW may also be used to preset the 48-bit system

time. Load SCHIGH, SCMID, and SCLOW with the desired time and then setbit 2 of the CCW to 1. The firmware will set the system time to these values

and then will clear the CCW.

2.4.2 Bus Traffic Control/Status Register (BTCSR)

Set this register to a nonzero value to reset the bus traffic word count

(BTWCNT) to 0. This register will be cleared to 0 when the word count has

been reset.

2.4.3 Hardware Reset

If the hardware reset button on the host system is pressed, the CSR is reset and

firmware execution is halted. At this point, memory is still intact and may be ac-

cessed. After a hardware reset, the firmware must be restarted (see the Module

Startup/Test subsection) and memory will be cleared at this time.


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M o du le St ar t u p / Test 3-1

3.1 Mo dule St ar t up/Test

Note: Th is se c t io n d e sc r ib e s t h e s t e p s re q u ire d to in i t ia l iz eDevice 1 o f t he A429 PC-16. To init ialize De vice 2, repe at t he

pro ce d ure s, sub st i tut ing CSR2, ADRS_P ORT2, an d

DATA_P ORT2 f o r CS R1, ADRS_P ORT1, a n d DATA_P ORT1.

Th is se c t io n a l so d e sc r ib e s t h e s t e p s re q u ire d to in i t ia l iz eDevice 1 o f t he A429 V2. To ini t ial ize Device 2, rep ea t t he

p r o c e d u r e s .

3.1.1 A429 Initialization Steps

Prior to startup, the A429 module must be properly installed in the host comput-

er system. Once installation is accomplished, the A429 is ready to be configured

and initialized for ARINC 429 operations. The startup procedure consists of

several steps which must be completed in the proper sequence. The followingtable outlines these steps and gives the related manual section or subsection.

3 : De v i c e Man ag e m e n t Fi r m w ar e R e f e r e n c e

Step Procedure Related Section or Subsection

1 Set up the base I/O address Section 2.2: Memory Access

2 Set up the memory mode and memory

base address

Section 2.1: Hardware Control Registers

3 Download the firmware code Section 3.1: Module Startup/Test

4 Start up the module in BIT mode and

run tests if desired

Section 3.1: Module Startup/Test

5 Switch to application program mode Section 3.1: Module Startup/Test6 Program control registers for each

channel

Chapter 2: Control Registers

7 Enable bus processing Section 3.1: Module Startup/Test


30/244

3- 2 De vice Man ag emen t Firmw ar e Re f er en ce


The control/status register is always accessible to the host. Program the control/

status register anytime during A429 operation.

Cross Reference: See Section 2.1.1: I/O Control/Status Registerf o rm o r e d e t a i ls a b o u t e a c h o f t h e s e p r o c e d u r e s .

3.2 A429 Software Download Instruct ions

The A429 requires all firmware code to be downloaded prior to initializing ap-

plication data structures. One ASCII file contains all the firmware code in one

ASCII file.

The data in the download file is structured as 16-bit words. The first sixteen

words make up the file header, containing product and version information. Theseventeenth word in the file contains a word count value (N), for the first half of

the data in the file (SeeFigure 3.2.1).

Figure 3.2.1: A429 Dow nlo ad Fi le Form at

End of File

Firmware File

16 Header Words

Word Count N

Word 1

Word 2

Word N

Word Count P

.

..

A429-PC Memory

Offset 800h

Offset 800h + N

Offset 2C00h

Offset 2C00h + P

Offset 12C00h

Offset 12C00h + X

Word 1

Word 2

Word P

.

.

.

Word 1

Word 2

Word X

.

.

.


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A429 So f t w ar e Dow n lo ad In st r u ct i o n s 3-3

3.2.1 Downloading the Firmware from a File

To download the firmware code to the A429, complete the following steps:

1. Op e n t h e fi r m w a r e c o d e fi le (t e x t m o d e ).

2. Read t he run b it in th e CSR (b it 9 for P C-8, PC-16, PC-104 o r b it 0 for V2, cPCI ,

PCI) o f t he I/O Cont ro l Reg is ter (CSR) to ver i fy tha t t he in t ern a l pro ce ssor is

n o t r u n n in g . (If r eq u i red , w r it e a 0 t o t h i s b i t t o h a l t p r o c es s in g . )

Cross Reference: See Chapter 2: Control Registerso f t h is m a n u a l.

3. Write a d a t a va lue o f 000Ah t o o f f se t 0FFFFh.

4. Re a d a n d s kip t h e fi r s t s ix t e e n w o r d s in t h e fi r m w a r e fi le .

5. Re a d t h e n e x t w o r d . Th is is t h e w o r d c o u n t , N.

6. Re a d t h e n e x t w o r d f ro m t h e fi le a n d w r it e t h e w o r d t o m e m o r y, s t a r t in g a t

o ffse t 00800h.

7. C o n t in u e r e a d i n g t h e fi le , w r it i n g t h e d a t a , a n d in c r e m e n t i n g t h e a d d r e s s

u n t i l N w o r d s h a v e b e e n r e a d a n d w r it t e n .

8. Af t e r t h e N t h w o r d is p r o c e s s e d , r e a d t h e n e x t w o r d . Th is is t h e w o r d c o u n t , P.

9. Re p e a t s t e p s 5 a n d 6 w i t h a s t a r t in g o f f s e t o f 02C 00h u n t il P w o r d s h a v e b e e n

r e a d a n d w r it t e n .

10. Af t e r t h e P t h w o r d i s p ro c e s s e d , r e p e a t S t e p s 5 a n d 6 w it h a s t a r t in g a d d r e s s

o f 1 0800h u n t il t h e en d o f t h e fi le i s r ea c h ed .

PC8 and PC16 Note: To a c c e s s m em o r y a dd r es s es 1 0000h a n da b o v e , s e t b it 0 o f t h e C SR t o 1 .

3.2.2 Instructions for Downloading the PLD and Firmware Files

The PCMCIA requires all PLD data and firmware code to be downloaded prior

to initializing application data structures. The PLD data and firmware code is

contained in three files. The PLD data file is in a binary format and the firmwarecode files are in an ASCII format.


32/244



Downloadingthe PLD Dat a

Use the PLD Download Register (I/O Port 0) to download the PLD data to the

PCMCIA:

1. Res e t t h e P LD by s e t t in g b i t s 2 a n d 3 o f t h e P LD Do w n lo a d Reg is t e r t o 1 . Wa i t

a p p r o x im a t e ly 100 m i llis ec o n d s t o a l lo w t h e P LD t o r es e t it s e l f .

2. Se t b i t 2 t o 0 t o b eg in do w n lo a d in g (lea v e b it 3 eq u a l t o 1 ).

3. Op en t h e P LD da t a fi le (b in a r y m o de ).

4. U s in g t h e I/O C o n t r o l/S t a t u s R eg i s t e r , v e r if y t h a t t h e in t e r n a l p r o c es s o r is n o t

r u n n i n g .

5. S t a r t in g a t t h e b e g in n i n g o f t h e fi le , re a d o n e b y t e a t a t im e , u n t il t h e v a l u e s

o b t a in ed f r o m t w o c o n s ec u t iv e r ea d s a r e F F h a n d F 2h . Th is va lu e , FF F2h , is t h e

p r e a m b le a n d t h e fi r st v a lu e t o b e d o w n lo a d e d .

Note: Ea c h v a lu e is d o w n lo a d e d o n e b i t a t a t im e , b e g i n n in gw it h t h e m o s t s ig n ifi c a n t b it o f t h e p r e a m b le . Th r e e w r it e i n -

s t ru c t i o n s ( s te p s f, g, a n d hb e lo w ) m u s t b e p e r fo r m e d t od o w n l o ad e a c h b i t . Th e P LD D o w n l o ad R e g is te r c o n s i s t s o f

f o u r b it s :

b i t 3Ou t p u t En ab le - a l w ays se t th is b i t t o 1

b i t 2Re se t - a l w ays se t th is b i t t o 0

b i t 1 Clo c k - t o g g le t h i s b it f ro m 0 (s te p f) t o 1 (s t ep g) to 0( s te p h)

b i t 0D a t a - s e t t h is b it e q u a l t o t h e v a lu e o f t h e b it b e in g

d o w n l o a d e d

6. Wr it e a 4 -b i t v a lu e t o t h e P LD D o w n lo a d Reg is t e r a s f o l lo w s : s e t b it 3 t o 1 , s e t

b i t 2 t o 0 , se t b i t 1 t o 0 , a n d s e t b i t 0 e q u a l t o t h e v a lu e o f t h e b i t b e i n g

d o w n lo a d e d (Wh e n d o w n lo a d i n g t h e m o s t s ig n i fi c a n t b it o f t h e p r e a m b le ,

th is value w ill b e 1001).

7. Wr it e a 4 -b i t v a lu e t o t h e P LD D o w n lo a d Reg is t e r a s f o l lo w s : s e t b it 3 t o 1 , s e t




8.Wr it e a 4 -b i t v a lu e t o t h e P LD D o w n lo a d Reg is t e r a s f o l lo w s : s e t b it 3 t o 1 , s e t




9. Re p e a t S t e p s 6, 7, a n d 8 f o r e a c h o f t h e r e m a in in g b i t s in t h e p r e a m b l e .


33/244


10. Re a d t h e n e x t b y t e f r o m t h e P LD d a t a fi le .

11. Re p e a t S t e p s 6, 7, a n d 8 f o r e a c h b it , b e g in n i n g w it h t h e m o s t s i g n i fi c a n t .

12. C o n t in u e r e a d in g b y t e s f r o m t h e P LD d a t a fi le a n d w r it i n g b i t s t o t h e P LD

D o w n lo a d Re g is t e r u n t i l t h e e n d o f t h e fi le is r e a c h e d .

3.2.3 Downloading the Firmware Code

Complete the following steps to download the firmware code to the PCMCIA:

1. Op en t h e b o o t lo a d er c o d e ASCII t e x t fi le (boo t l oad . t x t ).

2. U s in g t h e I /O C o n t r o l/S t a t u s R eg i s t e r, v e r if y t h a t t h e in t e r n a l p r o c es s o r is n o t

r u n n in g a n d t h e p r o g r a m e n a b l e b it is s e t t o 1 .

3. Rea d t h e fi r s t 1 6-b i t h e x a de c im a l w o r d f r o m t h e ASCII fi le .

4. S t a r t in g a t o f f se t 0 000h , w r it e t h e d a t a w o r d t h a t w a s r e a d i n St e p 3 .

5. C o n t in u e r e a d i n g t h e fi le , w r it i n g t h e d a t a , a n d in c r e m e n t i n g t h e a d d r e s s

u n t i l t h e e n d o f t h e fi le is r e a c h e d .

6. Op e n t h e t e x t fi le code . t x t .

7. Rep e a t S t e p s 2 a n d 3.

8. S t a r t in g a t o f f s e t 0 100h , r ep ea t S t ep 3 .

9. Re p e a t S t e p 5.

3.2.4 Instructions for Starting the Firmware

After powering-up or resetting the PCMCIA module, first download the code/

data files per the software download instructions. Upon completion of the down-

load, perform the following procedure to start up the PCMCIA:

1. Write FFFFh t o th e BITSta tu s reg is te r (o f f se t 83Bh) .

2. Write 0001h t o t he I/O Cont ro l/Sta t us Reg is ter to s t a r t t he P CMCIA fi rm w are .

3. Rea d t h e B IT St a t u s r eg is t e r a n d w a i t f o r t h e v a lu e t o eq u a l 0000h , in d ic a t in g

t h a t t h e p o w e r-u p t e s t s h a v e c o m p le t e d .

4. Rea d t h e B IT t o t a l e r r o r c o u n t (o f f s e t 83C h ). Th e v a lu e w ill be n o n z e r o if e r r o r s

w e r e d e t e c t e d .

5. Af t e r t h i s p r o c e du r e is c o m p le t ed , t h e P C MC IA is in B IT m o de a w a i t in g a

c o m m a n d . Eit h e r s e l e c t B IT t e s t s t o b e p e r f o r m e d o r i n it i a liz e t h e b o a r d f o r

1553 op era t ion s .


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3.2.5 Downloading the Firmware from Flash

Note:This pro ce d ure o nly a pp lies t o t he A429 cPCI-8, P CI-8, an d V2.

After powering-up or resetting the V2, cPCI-8, or PCI-8 module, complete thefollowing steps to start up the module using the flash memory:

1. Wr it e 0002h t o t h e C SR (o f f s e t 0) t o r es e t t h e h a r dw a r e .

2. Write 000Ah to o ffse t 0FFFFh.

3. Write FFFFh t o th e BITSta tu s reg is ter (o f f se t 83Bh) .

4. Wr it e 0 003h t o t h e C SR t o s t a r t t h e fi r m w a r e .

5. Rea d t h e B IT St a t u s r eg is t e r a n d w a i t f o r t h e v a lu e t o eq u a l 0000h , in d ic a t in g

t h a t t h e p o w e r-u p t e s t s h a v e c o m p l e t e d .

6. Rea d t h e B IT t o t a l e r r o r c o u n t (o f f s e t 83C h ).

Note:Th e v a l u e w ill b e n o n z e ro if e r ro r s w e re d e t e c t e d . If an o n z e ro v a l u e o c c u rs , c o n t a c t S B S Te c h n o l o g ie s .

Note:Co n fi g u r a t io n o f fl a s h d o w n lo a d c a n b e v e r ifi e d a t o f f -se t s 0x800 (nu m be r o f re ce ivers) an d 0x801 (num be r o f t ran s-

m i t t e r s ) .

After this procedure has been completed, the V2, cPCI, and PCI are in BIT

mode awaiting a command. Either select BIT tests to be performed or initialize

the board for ARINC operations.

3.2.6 Reprogramming the Flash Memory

The flash memory on the V2, cPCI-8, or PCI-8 may be reprogrammed, provid-

ing firmware updates at your site without the need for PROM replacements. The

procedure is similar to the two methods of module startup previously described

in Section 3.2.1: Downloading the Firmware from a Fileand Section 3.2.5:Downloading the Firmware from Flash. Complete the following steps:

1. P e r fo r m a S o f t w a r e Do w n lo a d w it h t h e n e w c o d e t o b e p r o g r a m m e d .

2. Pe r fo rm a Mod ule St a r t up - Da t a RAM Mod e. This w ill ver i fy tha t t he c od e is

lo a d e d i n t o t h e b o a r d m e m o r y b e f o r e r e p r o g r a m m i n g t h e F LAS H.

3. P e r fo r m t h e S o f t w a r e Do w n lo a d w it h t h e n e w c o d e t o b e p r o g r a m m e d .


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4. P e r f o r m a M o du le S t a r t u p - F la s h Mo d e u s in g t h e f o llo w in g s t ep s :

a. In d i c a t e t h e n u m b e r o f r e c e iv e r s in o f f se t 0F808h a n d t h e n u m b e r o f

t r a n s m it t e r s in o f f s e t 0 F809h . If a v a l id c o n fi g u r a t io n i s en t e r ed , o f f s e t

0F80Ah w i ll c lea r, and th e p roc ess w i ll com plete . If an inva l id

c o n fi g u r a t io n is en t e r ed , o f f s e t 0 F 80Ah w ill eq u a l B AD Dh , a n d t h e

pro ce ss w i ll f a il .

b. Write 0002h t o th e CSR (o f f se t 0 fo r th e V2 an d 20000h for t he cP CI an d

P C I) t o r e s e t t h e h a r d w a r e .

c. Write C0DEh to Pro g ram Com m an d Reg is ter 1 (o f f se t 0FC00h).

d. Write 1234h t o P rog ram Com m an d Reg is ter 2 (o f f se t 0FC01h).

e. Write FFFFh t o th e BITSta tu s Reg is te r (o f f se t 83Bh) .

f. To s t a r t t h e fi r m w a r e , w r it e 0003h t o t h e C SR.

g. Rea d t h e B IT St a t u s Reg is t e r a n d w a i t f o r t h e v a lu e t o e q u a l 0000h ,

in d i c a t in g t h a t t h e p o w e r-u p t e s t s h a v e c o m p l e t e d .

Note:Co m p le t i o n o f St e p g r e q u ir e s u p t o fi v e s e c o n d s .

h. Rea d bo t h P r o g r a m C o m m a n d Reg is t e r s (o f f s e t s 0 FC 00h a n d 0 FC 01h ).

Note:Th e v a l u e s w ill b e n o n z e ro i f fl a sh p ro g ram m in g e r ro r sw e r e d e t e c t e d .

Note:F la s h m e m o r y w ill c o n t a in o n ly o n e c o n fi g u r a t io nb a se d u p o n v a l u e s e n t e re d a t 0xF808h (n u m b e r o f r e c e iv e r s )

an d 0xF809h (n u m b e r o f t r an sm it t e r s ) o f f se t s . In o rd e r t o

c h a n g e c o n fi g u r a t io n s , fl a s h m e m o r y m u s t b e r e p ro -

g r a m m e d .

The procedures inSection 3.2.6: Reprogramming the Flash Memoryrepro-

grams the flash memory with the new code. The new code restarts the device.

After this procedure is completed, the device is in BIT mode awaiting a com-

mand.

3.2.7 Module Startup/Channel Assignments

Start up theA429

After powering-up or resetting the A429 module, first download the firmware

code per the software download instructions inSection 3.2.1: Downloading the

Firmware from a File.Upon completion of the download, perform the following

procedure to start up the A429:


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1. F o r t h e P C -8 a n d P C -16 o n ly, s e lec t Mem o r y Win d o w 1 by w r it in g 0000h t o t h e

I/O Con t ro l reg is te r (CSR).

2. Write 0200h fo r th e P C8, PC16, and PC104; and 0001h fo r th e V2, cP CI, and PCI

t o s t a r t t h e A429 fi r m w a r e .

3. Rea d t h e E NC DEC St a t u s r eg is t e r (o f f s e t 802h ) a n d w a i t f o r t h e v a lu e t o eq u a l

B AD Dh , in d i c a t in g t h a t t h e d e v ic e i s in c h a n n e l c o n fi g u r a t io n m o d e .

4. In d i c a t e t h e n u m b e r o f r e c e iv e r s in o f f se t 8 00h a n d t h e n u m b e r o f

t r a n s m i t t e r s in o f f s e t 8 01h . If a v a l id c o n fi g u r a t io n is en t e r ed , t h e ENCD EC

St a t u s r eg is t e r w ill c l ea r t o 0000h a n d t h e p r o c e s s w ill c o m p le t e .

Note:Th e t o t a l n u m b e r o f a v a ila b l e c h a n n e l s c a n b e r e a d f r o mo f f s e t 803h i f s t ep s 1 t h r o u g h 3 w er e s u c c es s f u l . All e ig h t c h a n n e l s

m u s t b e c o n fi g u r e d f o r e it h e r r e c e iv e o r t r a n s m i t .

5. F o r ex a m p le , t o c o n fi g u r e t h e A429 de v ic e f o r 2 r ec e iv e c h a n n e l s a n d 6

t r a n s m i t c h a n n e l s , w r it e a 2 t o o f f s e t 8 00h a n d a 6 t o o f f s e t 8 01h (s ee Ta b le3.2.1). Th e A429 fi r m w a r e d es ign a t es w h ic h c h a n n e l s w ill o p er a t e a s r ec e iv e

c h a n n e ls a n d w h ic h w ill o p e r a t e a s t r a n s m i t c h a n n e l s , b a s e d o n t h e v a lu e s

en t e r ed in o f f s e t s 8 00h a n d 8 01h . Th e r e c e iv e c h a n n e l s a r e a lw a y s a s s ign e d t o

t h e l o w e r c h a n n e l n u m b e r s .

6. Read th e Xil inx Dow nloa d St a t us Reg is te r (o f f se t 812h). A va lue o f C0DEh (or

0x 86B f o r t h e V2) in d ic a t es d o w n lo a d w a s s u c c e s s f u l.

7. Rea d t h e B ITSt a t u s r eg is t e r (o f f s e t 8 3B h ) a n d w a i t f o r t h e v a lu e t o e q u a l 0000h ,

in d i c a t in g t h a t t h e p o w e r-u p t e s t s h a v e c o m p le t e d .

8. Rea d t h e B IT t o t a l e r r o r c o u n t (o f f s e t 83C h ).

Note: Th e v a l u e w ill b e n o n z e ro i f e r ro r s w e re d e te c t e d . If an o n z e ro v a l u e o c c u rs , c o n t a c t S B S Te c h n o l o g ie s .

Tab le 3.2.1: ENCDEC Co nfigu rat io n Reg iste r

After you complete this procedure, the A429 is in BIT mode awaiting a com-

mand. Either select BIT tests to be performed or initialize the board for ARINC

429 operations.

16-bit Register Offset (Hex) Register Description

800 Number of Receivers

801 Number of Transmitters

802 ENCDEC Status

803 Total Number of Channels


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3.2.8 BIT Test Registers

Table 3.2.2contains a summary of the registers used to perform BIT tests.

Table 3.2.2: BIT Test Operat ion al Regist ers

Perform ing AllBIT Test s

Complete the following steps to perform all BIT tests:

1. Write 0000h to t he BITTo t al Erro r Coun t Reg is te r (o ffse t 83Ch).

2. Write FFFFh t o th e Selec t ed Tes t Reg is ter (o f f se t 83Dh).

3. Write 0002h to th e BITCo nt ro l Reg is te r (o ffse t 83Ah).

4. Rea d t h e B IT C o n t r o l R eg i s t e r (o f f s e t 83Ah ) a n d w a i t f o r a t e s t c o m p le t e

indicat ion (value=00000h).

5. Read th e BITTot a l Error Co un t Reg is ter (o f f se t 83Ch).

Note: Th e v a l u e w ill b e n o n z e ro i f e r ro r s w

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A429 Users Manual