A Visual Language for Describing Instruction Sets and Generating Decoders Trevor Meyerowitz, Jonathan Sprinkle, Alberto Sangiovanni-Vincentelli E-mail:

A Visual Language for Describing Instruction Sets and Generating

Decoders

Trevor Meyerowitz, Jonathan Sprinkle, Alberto Sangiovanni-Vincentelli

E-mail: {tcm, sprinkle, alberto}@eecs.berkeley.edu

OOPSLA Workshop On Domain Specific ModelingOctober 24th, 2004

etropolis

October 24, 2004 2004 OOPSLA Workshop on DSME

Modeling Overview

Goals Accurate software performance modeling

for a variety of processors and instruction sets.

Reuse and retarget trace-driven microarchitectural models

Automate the retargeting

Retargeting Requires Building Cross Compiler Modifying the ISS to generate traces Creating a trace-reader for the

microarchitectural model

Microarch Model

Fetch Process

Execute Process

ProgramCode

Tool Flow

Inst.Trace

Functional ISS

ExecStatistics

Microarch.ModelMicroarch.Model

Trace Interface

Disassembler


A Sample Instruction Set (ARM)

C Code Assembly Code Instruction Word ( binary)

x = x + 1; add r1, r1, 1 11110010100000010001000000000001

Compilation

Simulation

ARM Instruction Set Specification <excerpt>

Disassembly


ISA_ML: Overview

Main Parts A Visual Instruction Set Description Language

Used to describe the encoding and operand usage of instructions Written using GME*, a UML-based environment for constructing domain specific modeling

environments Generates a C++-based disassembler and trace-interface code for the given model ISA

description

Key Features: Two high level models

ISA State: Register Files, Memories, Program Counter, etc. Instructions: Encoding and operand fields of each instruction

Intuitive Visual Interface Leverages Hierarchy + Compact Representation Extensive Error Checking Easier to Retarget to Output Other Formats (e.g. verilog, nML, etc)

*GME website: http://www.isis.vanderbilt.edu/projects/gme/


Outline

BackgroundParadigm and Semantics

ISA State Instructions

Instructions and OperandsSample Instruction Group

Language RulesInterpreter ImplementationFinal Words


ISA_ML Paradigm

ConstantValue<<Atom>>

Value : field

InstAnchor<<Atom>>

AnchorPoint : field

InstAnchorFCO<<FCO>>

InstField<<FCO>>

InstEnd<<Atom>>

InstBegin<<Atom>>

ReferenceBase<<FCO>>

RefType : enumWrite : boolNumOps : field

InstructionGroup<<Model>>

NumBits : field

PC_Binding<<Reference>>

PC_id : field

OrderingConnection<<Connection>>

ISA_ML_Model<<Model>>

ZeroBitIsFirst : bool

StateElement<<FCO>>

AddressBits : fieldSuffix : fieldWordSize : field

ISA_State<<Model>>

MemReference<<Reference>>

MemoryOrIO<<Atom>>

AllowOffset : boolBaseAddress : field

RegisterFile<<Atom>>

RegReference<<Reference>>

ImmediateValue<<Atom>>

Signed : bool

Instruction<<Model>>

IsBaseInst : boolIsIllegalInst : boolModifiesPC : boolOperator : field

BitfieldField<<FCO>>

BitEncoding : fieldSingleEncoding : boolNumBits : field

1..*

1..*

0..*

0..*

dst0..*src0..*

0..1

0..*

0..*

1

1

0..*

0..*

1


ISA State

InstAnchor<<Atom>>

AnchorPoint : field


InstField<<FCO>>

InstEnd<<Atom>>

InstBegin<<Atom>>




NumBits : field


PC_id : field



StateElement<<FCO>>


ISA_State<<Model>>


MemoryOrIO<<Atom>>





Signed : bool


IsBaseInst : boolModifiesPC : boolOperator : field



0..*

0..*

dst0..*src0..*

0..1

0..*

0..*

1

1

0..*

0..*

1

1..*

1..*

One or more memories or I/O’s with their addressing

and word sizes.

One or more memories or I/O’s with their addressing

and word sizes.

Reference to the register used as the

program counter

Reference to the register used as the

program counterOne or more register file with their addressing and

word sizes.

One or more register file with their addressing and

word sizes.


Instructions and Operands

ConstantValue<<Atom>>

Value : field

InstAnchor<<Atom>>

AnchorPoint : field


InstField<<FCO>>

InstEnd<<Atom>>

InstBegin<<Atom>>




NumBits : field


PC_id : field



ZeroBitIsFirst : bool

StateElement<<FCO>>


ISA_State<<Model>>


MemoryOrIO<<Atom>>





Signed : bool


IsBaseInst : boolIsIllegalInst : boolModifiesPC : boolOperator : field



1..*

1..*

0..*

0..*

dst0..*src0..*

0..1

0..*

0..*

1

1

0..*

0..*

1

Instruction Anchors

Instruction Instances and Subtypes

Core Operands

Ordering Connection


Sample Instructions: Base Instruction

RdRm RnReg-Base InstEndConfigBase

InstBegin

Instruction 0…1 2...5 6…9 10..13 14..17 18..21 22..23 24..27 28..31

Arith Base 11 xxxx Rm Rn xxxx xxxx xx xxxx Rd

Add 11 0111 Rm Rn xxxx xxxx xx config Rd

Subtract 11 0001 Rm Rn xxxx xxxx 00 config Rd

MAC 11 0011 Rm Rn Rmac xxxx xx xxxx Rd

SubtractAdd

InsReg

InsCon

ArithmeticBase

MultiplyAccumulate


Sample Instructions: MAC

Ins

Reg

Ins

Con

ArithmeticBaseBeginConstants Rmac

Instruction 0…1 2...5 6…9 10..13 14..17 18..21 22..23 24..27 28..31


Add 11 0111 Rm Rn xxxx xxxx xx config Rd

Subtract 11 0001 Rm Rn xxxx xxxx 00 config Rd

MAC 11 0011 Rm Rn Rmac xxxx xx xxxx Rd

RdRm RnReg-Base InstEndConfigBase

InstBeginRmac

BeginConstants

Multiply Accumulate


Language Rules

Enforced by Constraints (via OCL)1. The operands of an instruction must have unique names. 2. Each instruction has a unique name, and uniquely named operands3. Each reference operand must be non-null4. Each operand has at most one incoming and one outgoing connection

Enforced at Interpreter Run-time1. Fully deterministic ordering within an instruction.2. All operands must be connected in directed acyclic line segments.3. All actual instructions must have the same bit-width4. Only instances and subtypes of base instructions are allowed in other

instructions5. The operands of an instruction must be consistent with the encoding

of the instruction (i.e. their bit-field sizes must be less than or equal to the number of don’t cares (x’s) in the instruction’s bit field)


Outline

Background Paradigm and Semantics Interpreter Implementation

Interpreter Flow Generated Files Interpreter Results

Final Words


Interpreter Flow

1. Instruction Processing/Parsing Get encodings (base/actual instructions) Check language rules Create internal representation from network

2. Consistency Check No actual instruction encodings overlap

bit-by-bit comparison of the encoded instructions

3. Data Structure Synthesis Instruction data structures/unions Decoding masks/signatures Disassembler and Trace Reader Base Code


Example Generated Files

//bitfield

// =110011xxxxxxxxxxxxxxxxxxxxxxxxxx

typedef struct _MAC_struct {

unsigned dummy0 : 2;

unsigned BeginConstants : 4; // Pos:29

unsigned Rm : 4; // Pos:25

unsigned Rn : 4; // Pos:21

unsigned Rmac : 4; // Pos:17

unsigned dummy1 : 10;

unsigned Rd : 4; // Pos:3

} MAC_struct;

#define MAC_MASK 0xfc000000

#define MAC_SIG 0xcc000000

MAC Structure, Mask, and Signature

// the union of ALL of the

// instruction field structures

typedef union _insts {

unknowni_struct unknown_inst;

MAC_struct MAC_inst;

SUB_struct SUB_inst;

ADD_struct ADD_inst;

} insts;

Union for Decoding Instructions

Note: The interpreter also generates specific files for Disassembling and Trace Interfacing.


ISA_ML Results

MIPS Integer Subset

PowerPC Integer Subset

ARM (approximate)

Base Instructions 11 11 6

Actual Instructions 55 91 26

Illegal Instructions 0 0 5

Hours to Enter (appox.) 8 6 6

Header File (# lines) 1357 2134 759

Significant use of instances and subtypes improves productivity.


Final Words

Conclusions Succinct DSME for describing ISA’s and their encodings

Flexible and intuitive syntax and semantics Extensive static + run-time error checking

Synthesis of disassembler and trace interface code GME has enabled rapid design of ISA_ML

SW-Engineering Framework Extensive Infrastructure Support (Language, GUI, Interpreter) Potential Improvements

• More customizable types + input methods• API support to ease code generation (for C/C++, etc).

Future Work Expansion of Language and Features

E.g. Richer operands, multiple bit-length instructions Addition of execution semantics Connection to other targets

E.g. metropolis, architecture description languages, hardware description languages


Thank You!!!


Dual Process ARM Microarchitectural Models

Models Pipeline delays Result and Issue delays

Doesn’t Model Interrupts, Exceptions, Non-Ideal Memory Value dependent execution times (e.g.

multiplication)

Stalling Behavior Operation Stall

Fetch: stall until notified Execute: execute until stall is resolved, then

notify fetch Branch Stall/Mispredict

Fetch: insert X-bubbles Execute: execute normally

Trace Entry: PC, Instuction Word, Instruction Executes

PIPE is a custom MOC with bounded FIFO’s

Higher Performance than YAPI

Fetch Process

Execute Process

Base Model (Code)

Strongarm

(Additional Code)

Xscale (Additional Code)

Changes to ISS (c++)

1110 150 150

Metamodel files

832 191 197

Total 1942 341 347

Code Complexity Statistics

Model Performance (Cycles/Sec on a 700 MHz Xeon)

Metropolis Model

SystemC Model

YAPI perf.

~1500 ~60000

PIPE perf.

~2240 -

2-Process Model

ARM ISS

Microarch.Model

ProgramCode

Inst.Trace

Exec Statistics

Tool Flow


Bitfield Operands

NumBitsEncodingSingleEncoding

Anchors AnchorPoint

Connection Specifies the ordering of bitfields

Begin Anchor End Anchor Custom Anchor

Instruction Memory Ref Immediate Constant Register Ref

Ordering Connection

State Elements WordSizeAddress Bits

Program Counter

Source Register

ISA_ML Instruction Elements

ISA_ML State Elements


Addition

Sample Instructions: Other Instructions

Instruction 0…1 2...5 6…9 10..13 14..17 18..21 22..23 24..27 28..31


Addition 11 0111 Rm Rn xxxx xxxx xx config Rd

Subtractraction 11 0001 Rm Rn xxxx xxxx 00 config Rd

Multiply Accumulate 11 0011 Rm Rn Rmac xxxx xx xxxx Rd

ConfigBeginConstants

Ins

Reg

Con

Ins

ArithmeticBase

Subtraction

Ins

Reg

Ins

Con

ArithmeticBaseBeginConstants

Config

Ins

Reg

Ins

Con

ArithmeticBaseBeginConstants Rmac

Multiply Accumulate


Constraints

InstAnchor<<Atom>>

AnchorPoint : field

BitfieldSizeMustBePositive

AnchorPointRange


AllOperandsMustHaveDifferentNames

AllElementsMustHaveDifferentNamesOneDest

OneSource

Reference_Binding_not_null

InstField<<FCO>>

InstEnd<<Atom>>

InstBegin<<Atom>>




NumBits : field


PC_id : field



StateElement<<FCO>>


ISA_State<<Model>>


MemoryOrIO<<Atom>>





Signed : bool


IsBaseInst : boolModifiesPC : boolOperator : field




ICONS/Scratch

Documents

A Visual Language for Describing Instruction Sets and Generating Decoders Trevor Meyerowitz, Jonathan Sprinkle, Alberto Sangiovanni-Vincentelli E-mail: