A Triple-mode Continuous-Time Sigma-Delta Modulator With Switched-Capacitor Feedback DAC

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER 2003 2069

A Triple-Mode Continuous-Time�� ModulatorWith Switched-Capacitor Feedback DAC for a

GSM-EDGE/CDMA2000/UMTS ReceiverRobert H. M. van Veldhoven

Abstract—Time jitter in continuous-time �� modulators is aknown limitation on the maximum achievable signal-to-noise-ratio(SNR). Analysis of time jitter in this type of converter shows thata switched-capacitor (SC) feedback digital-to-analog converter(DAC) reduces the sensitivity to time jitter significantly. In thispaper, an and continuous-time fifth-order �� modulatorwith 1-bit quantizer and SC feedback DAC is presented, whichdemonstrates the improvement in maximum achievable SNRwhen using an SC instead of a switched-current (SI) feedbackcircuit.

The modulator is designed for a GSM/CDMA2000/UMTSreceiver and achieves a dynamic range of 92/83/72 dB in200/1228/3840 kHz, respectively. The intermodulation distanceIM2, 3 is better than 87 dB in all modes. Both the andmodulator consumes a power of 3.8/4.1/4.5 mW at 1.8 V. Processedin 0.18- m CMOS, the 0.55-mm2 integrated circuit includes aphase-locked loop, two oscillators, and a bandgap.

Index Terms—Mobile communication, telecommunicationreceiver, intermediate frequency (IF) conversion, GSM, EDGE,CDMA2000, UMTS, sigma-delta analog-to-digital converter(ADC), sigma-delta modulator, switched-capacitor (SC) dig-ital-to-analog converter (DAC), reduced jitter sensitivity.

I. INTRODUCTION

T HE diversity in mobile communication standards requiresthe integration of multimode receiver architectures on sil-

icon to reduce cost and application dimensions. In order to shareanalog circuits in the different modes, it is necessary to alignsignal levels and noise densities. The analog-to-digital converter(ADC) must adapt to the required channel bandwidth in eachmode. In [1], [2] modulators have been demonstrated for adual-mode receiver. This paper presents amodulator, whichcan convert the intermediate frequency (IF) signals in a GSM,EDGE, CDMA2000, and UMTS receiver into the digital do-main.

The receiver architecture and the required dynamic ranges inthe different modes are discussed in Section II. Although contin-uous-time modulators are known to be very power efficient,the maximum achievable signal-to-noise ratio (SNR) is limiteddue to their sensitivity to time jitter. The time jitter sensitivityof both a continuous-time modulator with switched current(SI) and switched-capacitor (SC) feedback circuit is analyzedin Section III. The implementation of the modulator circuits is

Manuscript received April 8, 2003; revised June 30, 2003.The author is with Philips Research Laboratories, 5656 AA Eindhoven, The

Netherlands (e-mail: [email protected]).Digital Object Identifier 10.1109/JSSC.2003.819165

Fig. 1. Triple-mode receiver architecture.

described in Section IV. Section V and VI present the experi-mental results and the conclusions, respectively.

II. RECEIVER ARCHITECTURE AND DYNAMIC RANGE

OF THE ADC

The receiver architecture used, which is shown in Fig. 1, issimilar to the structure described in [3]. An RF front-end con-verts the antenna signal down to the IF frequency— zero-IF forUMTS and CDMA2000 and low-IF (100 kHz) for GSM andEDGE. The IF signals are fed to anand modulator.The dynamic range requirement of the modulator is determinedby the amount of prefiltering in front of the modulator whichattenuates large out-of-band interferers. To reduce the requireddynamic range of the modulators, a passive first-order filter isimplemented in front of the modulator. To avoid expensive dis-crete analog channel filters, a high dynamic range of the modu-lator is still required. This way, most of the channel filtering canbe implemented digitally.

Table I summarizes the specifications on bandwidth and dy-namic range in the different modes, from which the maximumallowed noise density can be derived. Because the modulator hasto cope with the IF signals of four different systems, bandwidthand sample frequency has to be adapted to be able to achieve ahigh dynamic range at minimum power consumption. To assurereusability of circuits, the maximum ADC input level providedby the front-end is set to 1 differential in all modes. Fur-thermore, because GSM and EDGE bandwidths and dynamicranges required are very close, it is decided to combine thesetwo standards in one ADC mode.

0018-9200/03$17.00 © 2003 IEEE

2070 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER 2003

Fig. 2. SNR limitation due to jitter on the pulse width (SI).

TABLE IADC REQUIREMENTS IN THEDIFFERENTMODES

Table I indicates that UMTS-mode has the highestbandwidth, which implies high bandwidth circuits, whileGSM-mode requires the lowest noise density and determinespower consumption due to the low impedances required toachieve this low noise density. Although the combination of theforegoing contradicts the low power receiver solution neededin present-day telecom terminals, the few decibels overhead indynamic range in UMTS- and CDMA2000-mode can reducethe required analog prefiltering in front of the ADC even more,and minimize cost.

Continuous-time modulators are chosen for the ADCtopology because of their high dynamic range and built in anti-alias filter. The bandwidth of these type of converters can bescaled easily by changing the coefficients and sample frequency.A major disadvantage of continuous-time modulators is theirsensitivity to time jitter, which will be analyzed in the next sec-tion.

III. SNR LIMITATION DUE TO TIME JITTER

IN MODULATORS

A major concern in continuous-time modulators is thedegradation of the SNR due to time jitter. Imprudent design ofthe clock circuitry, which generates the feedback-D/A clock,will induce too much time jitter on the DAC feedback pulse andwill degrade the performance of the modulator.

In this section two different ways in which time jitter influ-ences the performance of a modulator will be discussed.First the degradation of the SNR due to time jitter on the pulse

width will be calculated for an SI and an SC feedback DAC.Secondly the SNR limitation due to time jitter on the pulse po-sition is presented.

A. Pulse Width Jitter in a Continuous-Time 1-BitModulator

In this subsection, the time jitter calculations on pulse widthjitter in [4] will be extended. Pulse width jitter is the constantlychanging integrated charge per clock cycle of the feedback pulsedue to time jitter on the clock.

1) Pulse Width Jitter in a Continuous-Time 1-Bit Modu-lator With SI DAC: In Fig. 2(a) the waveform in an SI DAC isdisplayed. When there is time jitter present on the clock this willcause timing errors with variance causing a variation onthe pulse width. The variance of the error chargetransferredper clock cycle can be calculated by

(1)

where is the amplitude of the feedback current. To reducethe intersymbol interference (ISI) [4] a return-to-zero (RTZ) in-terval in the DAC feedback pulses can be used. In Fig. 2(b) thefeedback pulse in a switched current feedback DAC of a con-tinuous-time modulator is shown for RTZ (a) andRTZ (b) in which is the non-return-to-zero (NRTZ)interval. When RTZ is used, the feedback pulse has to have anamplitude inversely proportional toto assure that the amountof integrated feedback charge is constant, and the gain inthe feedback path is RTZ independent. This increases the mag-nitude of because of the times larger amplitude feedbackpulses. The NRTZ interval can be added to (1) which leads to

(2)

A disadvantage of the RTZ interval is the higher clock frequencyneeded to create the RTZ interval. When RTZ , the feed-back pulse is two times shorter in time, and to feedback the sameamount of charge , the pulse has to be twice the amplitude.The error charge due to time jitter is expected to be two timeshigher compared to the RTZ pulses.

Formula (2) is only true when it is assumed that the timejitter on the output clock of the oscillator is independent of itsoutput frequency. For every clock generator or oscillator [with

VAN VELDHOVEN: A TRIPLE-MODE CONTINUOUS-TIME MODULATOR 2071

or without a phase-locked loop (PLL)], which generates a fixedfrequency the following is true:

(3)

If the oscillator output frequency is divided by two itcan be seen that the jitter increases with , assumingthat the noise contribution (time jitter) caused by the divider isinsignificant. In case of RTZ the feedback pulse is twotimes shorter in time, and to feedback the same amount of charge

, the pulse has to be twice the amplitude. Intuitively onewould think that the performance degradation due to time jitterwould be two times higher compared to the RTZ pulses.However, this is not the case when looking at (3). To be able tocreate the RTZ pulses, a clock with twice the frequencyhas to be used. This clock has times less time jitter, and thusit can be generally written that

(4)

If the oscillator output frequency is chosen two times higher,is multiplied by which in this case is 0.707.

This means that (2) changes into

(5)

when the performance of the oscillator as a function of its outputfrequency is also taken into account in the ADC design process.

The power of a sinewave with amplitudeis . The max-imum signal amplitude at the input of the modulator is dBcompared to the DAC current levels, so . Thesignal charge per sample period can be calculated with

(6)

The maximum SNR is the maximum signal power divided bythe noise power in the signal band. Assuming that the noisepower that is introduced by time jitter is white, the maximumachievable SNR due to pulse width jitter is

(7)

Formula (7) is extended withwhen compared to (13) and (14)presented in [4].

2) Pulse Width Jitter in a Continuous-Time 1-Bit Modu-lator With SC DAC: To reduce the degradation on the SNR dueto time jitter on the clock, an SC feedback circuit can be used toimplement the feedback DAC of the modulator.

The feedback current in the SC DAC is shown in Fig. 3. Theintegrated feedback charge is the same as in the switchedcurrent example , because the same amount

Fig. 3. SNR limitation due to jitter on the pulse width (SC).

of charge has to be fed back to the input to assure the same gainfrom input to output of the modulator.

From Fig. 3, it can be seen that the error charge due to clockjitter is now dependent on the settling-time constantof theDAC. When it is assumed that , the variance of theerror charge transferred per clock cycle can be approximated by

(8)

where is the capacitor voltage, andis the resis-tance in which the capacitor is discharged. Generallyis deter-mined by switch resistance and the equivalent input impedanceof the integrator stage.

From Fig. 3, the integrated feedback charge per clock periodcan be calculated

(9)

The signal charge per clock period can be calculated inthe same way (6) is derived

(10)

With defined as

(11)

which gives the number of settling time constants rel-ative to . Now the SNR limitation due to pulse width jitter ina modulator with SC feedback can be calculated using (8) and(10)

(12)

Formula (12) can be rewritten using (11) as

(13)


Fig. 4. �SNR as function of� and�.

Fig. 5. SNR limitation due to jitter on the pulse position.

With constant OSR, time jitter, sample frequency and RTZ in-terval, the improvement from a switched current to SC feedbackDAC is given by

SNR dB

(14)

The improvement is only dependent on the multiplication ofand , which gives the effective settling of the SC DAC. Thiscan also be seen intuitively, because whenand the SC current would settle completely. This would give aninfinite improvement in achievable SNR, because pulse widthjitter is eliminated completely. In the case of andthe improvement would be 16 dB. In Fig. 4, (14) is plotted as afunction of and .

B. Pulse Position Jitter in a Continuous-Time 1-BitModulator

In [4] it is stated that due to time jitter on the clock the po-sition of the feedback pulse is shifted in time while keeping itsintegrated feedback charge constant. The effect is demon-strated in Fig. 5. The SI or SC feedback pulse is shifted over atime by the time jitter on the clock. The formula that canbe used to calculate the degradation in SNR due to this effect isrepeated here.

(15)

Fig. 6. SNR limitation in UMTS mode.

where is the input signal frequency and is the variance ofthe jitter on the clock.

At high input frequencies the degradation is the most severe,so substituting the ADC channel bandwidth for gives theworst case scenario. The time jitter on the clock is representedby . Pulse position jitter is assumed to have the same effecton both SI and SC feedback modulators.

C. SNR Limitations in UMTS Mode

In Fig. 6, all SNR limiting contributions are shown for UMTSmode. The solid horizontal line represents the maximum achiev-able SNR due to quantization and thermal noise, which are de-termined by the ADC design and chosen such a way that powerconsumption is minimized. The SNR limitation due to pulse po-sition jitter is independent of the modulator design parametersbecause the bandwidth of the modulator is fixed and the timejitter is determined by the PLL and reference oscillator.

For the switched current implementation the SNR limitationSNR due to pulse width jitter is also given in Fig. 6.

When thermal-, quantization- and jitter noise is added, the max-imum achievable SNRSNR as a function of time jittercan be calculated, which is also plotted in Fig. 6, and is domi-nated by the pulse width jitter at realistic time jitter values. Ascan be seen from the figure, time jitter values lower than 4 psare needed to achieve the SNR of 70 dB needed for our UMTSapplication.

The same calculation is done for the modulator with SCfeedback DAC. The SNR limitation due to pulse width jitterSNR is beyond the pulse position SNR limitation

which, in the SC feedback DAC case, limits the maximumachievable SNRSNR .

The difference SNR in SNR limitation due to pulse widthjitter for SC and SI is also displayed in Fig. 6, and is 24 dB using(14) with and . Because pulse position jitterfor the SC DAC is dominant, the effective improvement whengoing from an SI DAC to an SC DAC is SNR . The effectiveimprovement SNR for low time jitter values is limited bythe thermal and quantization noise and for high time jitter valuesfully dependent on the pulse position jitter.

IV. I MPLEMENTATION OF THE MODULATOR

Fig. 7 shows the block diagram of the modulator. A fifth-order feedforward loopfilter is implemented with two complex


Fig. 7. Block diagram of the 1-bit fifth-order feedforward�� modulator.

Fig. 8. Capacitors with NMOS in NWELL devices.

conjugate poles to suppress the quantization noise at the edgeof the signal band. The design and corresponding AC transferfunction of the loopfilter is similar as described in [5].

A 1-bit quantizer is used together with a 1-bit inherentlylinear SC DAC. This way, the advantages of low-jitter sensitivityof SC modulators and high anti-alias suppression of con-tinuous-time modulators are combined like in [6]. Table Ishows the maximum achievable signal-to-quantization-noiseratio (SQNR) of the fifth-order modulator in all modes. Thesample frequencies in the GSM/CDMA2000/UMTS modesare 26/76.8/153.6 MHz, respectively. Without clock jitter,the theoretical SQNR in GSM/CDMA2000/UMTS mode is102/103/84 dB. Because the SQNR in all modes is at least10 dB better than required, thermal noise is dominant whichresults in the lowest power consumption.

A. Capacitors With NMOS in NWELL Devices

All capacitors of the modulator are implemented as NMOS inNWELL devices, which have a well defined absolute value andshow good matching. Because the NMOS in NWELL capacitorsare normally on devices, these capacitors show good linearity atlow bias voltages. A disadvantage of this type of capacitor is thelarge parasitic capacitance from NWELL to substrate. Capacitortype A (Fig. 8) uses two capacitors of which the gates are con-nected together and via a diode to the analog supply (VDDA), to

Fig. 9. Circuit diagram of the amplifier used in the first integrator.

Fig. 10. Scaling of the loop.

create a floating feedback capacitor. At start-up the diode pullsup the capacitor gates to the VDDA, to bias the capacitors intheir linear region. When the gates are charged to VDDA, thediode has a of zero volt and presents a high impedance.The NWELL terminals are the terminals of the capacitor. Theparasitic capacitors of nonfloating capacitor type B are shortedby substrate contacts and (external) ground connections.


Fig. 11. Input filter and SC feedback DAC.

B. Loopfilter Design

The circuit of the amplifier used in the first integrator shownin Fig. 9, uses a regulated NMOS cascode which compensatesfor the low output impedance of the input transistors, whichhave minimum channel length to achieve high speed. The gain-boost amplifier is biased with a resistor to avoid the need for anadditional common-mode circuit. The integrator stage achievesa DC gain of 80 dB.

The second–fifth integrator and feedforward coefficientsare implemented with scaled transconductances, similar asdescribed in [3]. The interface circuit to the comparator isdifferent because only one instead of two comparators is usedin this design.

The scaling of the loop filter is shown in Fig. 10. In theCDMA2000 mode, the switches numbered 2 are closed and ad-ditional capacitance is added to the output of the integrator. Inthe GSM-EDGE mode, the switches 2 and 3 are closed and,again, additional capacitance is switched to the integrator out-puts to increase the integrator time-constants further to get thedesired noise-shaping. The feedback transconductors are alsoscaled to move the complex-conjugate poles to the wanted fre-quencies.

To prevent the fifth-order slope of the quantization noiseshifting into the signal band due to process variations, thenotches created by the feedback transconductors are placed

% higher than their optimum frequency. Since the max-imum achievable SNR is not limited by the quantization noisein all three modes, additional margin is provided.

C. SC Feedback DAC

As concluded from Section III, to reduce the negative effectof pulse width jitter on the dynamic range of the converter, anSC feedback DAC is used.

In Fig. 11, the SC DAC circuit is shown in detail. The capaci-tors used in the DAC are of the semi-floating type A (see Fig. 8).In the first clock phase, the capacitors are charged to half thebandgap voltage by closing switches CL (switches CLNare open). In the second clock phase switches CLN are closed(switches CL are open) and the capacitors are discharged in adata-dependent way by closing switches D or DN depending on

Fig. 12. Block diagram of the prototype chip.

the output of the comparator. The DAC output current is sub-tracted from the input current and integrated on the capacitors ofthe first integrator. In GSM and CDMA2000 additional capaci-tors are switched on to keep a constant ratio between the inputresistance and the effective DAC feedback resistance, whichchanges proportional to . This is to have the cor-rect gain, as well as low enough noise, in all modes.

In each mode, the cutoff frequency of the prefilters (seeFig. 11) is adapted to the lowest value possible to achieve thehighest possible attenuation of out-of-band interferers.

V. EXPERIMENTAL RESULTS

The block diagram of the prototype chip is shown in Fig. 12.The chip is fabricated in a single poly, five metal layer dig-ital 0.18- m CMOS process. The IC includes two oscillators,a PLL and a bandgap. The oscillator frequency is 52 MHz inGSM-EDGE mode while in CDMA2000 and UMTS mode anoscillator frequency of 30.72 MHz is used. The PLL generatesthe sample frequencies of 76.8 and 153.6 MHz for CDMA2000and UMTS mode, respectively. In GSM-EDGE mode the PLLis not used and is powered down.

The die micrograph of a single triple-mode modulatoris shown in Fig. 13. The modulator operates from 1.6 to 2.9 Vwith only -dB SNR variation. Power consumption of boththe and modulator is 3.8 mW in GSM-EDGE, 4.1 mW inCDMA2000 and 4.5 mW in UMTS mode at 1.8-V supply.


Fig. 13. Micrograph of a single modulator.

Fig. 14. SNR as a function of input level.

Fig. 15. Image rejection and intermodulation in the UMTS mode.

In Fig. 14, the SNR as a function of the input signallevel is plotted. At full-scale input signals with frequenciesof 150/530/1700 kHz for GSM-EDGE/CDMA2000/UMTSmode, the peak SNR is 92/83/72 dB in bandwidths of200/1228/3840 kHz. The differential input swing is 1 inall measurements. In UMTS mode, a higher sample frequencyof 250 MHz had to be used, instead of the intended 153.6 MHz.The reason for this is a design error of the different clocks inDAC. The data is clocked into the DAC flip-flops before it isstable. By using the higher clock, the clock edge can be shiftedin time, to assure the data is clocked into the DAC flip-flops inthe right way.

Due to the higher frequency the SC DAC has a lower effectiveresistance than originally designed. Since thesample frequency is 1.6 times higher, the maximum input signalthat can be applied to the modulator is 1.6 differential.

Fig. 16. Image rejection and intermodulation in the CDMA2000 mode.

Fig. 17. Image rejection and intermodulation in the GSM–EDGE mode.

At this input signal, the measured dynamic range of theandcombination is 76 dB in 3.84 MHz.The measured and output spectra are shown in the left

spectra of Figs. 15–17. In all three modes the image rejection(IR) is 50 dB, which is limited by the amplitude and phase mis-match of the quadrature input signals generated by the arbitrarywaveform generator (AWG). The harmonic distortion visiblealso originates from the AWG. This is shown by the intermodu-lation (IM) measurements displayed at the right of Figs. 15–17.Two differential tones are generated by two separate channels ofthe AWG, and are combined with a resistive 50network. Thisway, no IM components are produced by the AWG. The mea-sured IM2 and IM3 distance is better than 87 dB in all modes,for two 6-dBFS input tones.

In Fig. 18 a measurement of the SNR in UMTS mode isdisplayed together with a number of calculated SNR curves


TABLE IIPERFORMANCESUMMARY OF THE MODULATOR

Fig. 18. Pulse width jitter measurement in the UMTS mode.

with different values for . The measured curve is numericallymapped on the calculated curves, from which it is concludedthat the of the modulator is 8.4. This is in good agreementwith the circuit simulation on the settling behavior of the SCDAC which predicted an value of 8.

Fig. 18 also shows the maximum achievable SNR for amodulator with a switched current DAC. It can be concludedfrom the figure that the choice to use an SC feedback DAC isvalid.

The performance of the modulator presented is summarizedin Table II.

VI. CONCLUSION

A quadrature fifth-order 1-bit modulator has been presentedthat combines the advantages of low-jitter sensitivity of SCmodulators and high anti-alias suppression of continuous-time

modulators. The combination effectively reduces the influ-ence of pulse width jitter on the dynamic range. Theandmodulators together achieve a dynamic range of 92/83/72 dBin a bandwidth of 200/1228/3840 kHz. The measured IM2 andIM3 distances are better than 87 dB and the IR performanceis limited to 50 dB by the measurement setup. This low-powerhigh-resolution triple-mode modulator reduces the amount of

prefiltering and AGC required in front of the ADC and thus en-ables a low-cost highly integrated receiver for telecom applica-tions.

ACKNOWLEDGMENT

The author would like to thank L. Breems for his support andE. C. Dijkmans for fruitful technical discussions about the A/Darchitecture and circuit design.

REFERENCES

[1] T. Burger and Q. Huang, “A 13.5-mW 185-M sample/s��-modulatorfor UMTS/GSM dual-standard IF reception,”IEEE J. Solid-State Cir-cuits, vol. 36, pp. 1868–1878, Dec. 2001.

[2] T. Salo, T. Hollman, and K. Halonen, “A dual-mode 80 MHz bandpass�� modulator for a GSM/WCDMA IF-receiver,” inIEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2002, pp. 218–219.

[3] R. H. M. van Veldhoven, K. Philips, and B. J. Minnis, “A 3.3 mW��modulator for UMTS in 0.18�m CMOS with 70 dB dynamic range in2 MHz bandwidth,” inIEEE Int. Solid-State Circuits Conf. Dig. Tech.Papers, Feb. 2002, pp. 222–223.

[4] E. J. van der Zwan and E. C. Dijkmans, “A 0.2 mW CMOS��modulator for speech coding,”IEEE J. Solid-State Circuits, vol. 31, pp.1873–1880, Dec. 1996.

[5] E. J. van der Zwan, K. Philips, and C. Bastiaansen, “A 10.7-MHzIF-to-baseband�� A/D conversion system for AM/FM radio re-ceivers,” IEEE J. Solid-State Circuits, vol. 35, pp. 1810–1819, Dec.2000.

[6] M. Ortmanns, Y. Manoli, and F. Gerfers, “A continuous-time sigma-delta modulator with reduced jitter sensitivity,” inProc. ESSCIRC, Sept.2002, pp. 287–290.

Robert H. M. van Veldhoven was born in Eind-hoven, The Netherlands, in 1972. He received theB.Sc. degree from the Eindhoven PolytechnicalCollege, Eindhoven, in 1996, and the M.Sc. degreefrom the Eindhoven University of Technology,Eindhoven, in 2002, both in electrical engineering.

In 1996, he joined the Mixed-Signal Circuitsand Systems group at Philips Research Labo-ratories, Eindhoven, where he worked on thedesign of high-resolution analog-to-digital anddigital-to-anlaog converters and associated circuits

for instrumentation, audio, and radio applications.

Documents

A Triple-mode Continuous-Time Sigma-Delta Modulator With Switched-Capacitor Feedback DAC