A STATIC COMPENSATOR MODEL FOR USE WITH ELECTROMAGNETIC TRANSIENTS SIMULATION PROGRAMS

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1398 IEEE Transactions on Power Dclivery, Vol. 5, NO. 3, July 1990

A STATIC COMPENSATOR MODEL FOR USE WITH ELECTROMAGNETIC TRANSIENTS SIMULATION PROGRAMS

A.M. Gole, Member Dept. of Electrical Engineering

University of Manitoba Winnipeg, Manitoba. CANADA. R3T 2N2

Abstract - A static var compensator (SVC) model based on state variable techniques is presented. This model is capable of being interfaced to a parent (or host) electromagnetic transients program, and a stable method of interfacing to the EMTDC program, in particular, is described. The model is primarily that of a thyristor controlled reactor (TCR) and a thyristor switched capacitor (TSC) . Capacitor switchings within the TSC have been handled in a novel way to simplify storage and computation time requirements. During thyristor switching, the child SVC model is capable of using a smaller timestep than the one used by the parent electromagnetic transients program: after the switching, the SVC model is capable of reverting back to a (larger) timestep compatible with the one used by the parent program. Other features that are considered include the modeling of a phase-locked- loop based valve firing system. The paper ends with the discussion of an application of this model in the simulation of a SVC controlling the ac voltage at the inverter bus of a back-to-back HVdc tie.

Keywords : Static compensator model, Transient simulation, Variable timestep, HVdc transmission.

INTRODUCTION

Some of the popular electromagnetic transients simulation programs [1,2] utilize the modeling algorithm proposed by Dommel [l], in which an inductor, capacitor, transmission line or other device is represented as a parallel combination of a resistor and a current source; the values of these depend on the past history of current and voltage in the device. This representation is used to solve for node voltages at any time t, based on known values from the previous simulation instant (t-At), At being the simulation timestep. This approach has the great advantage of simplicity, because an entire network can be quickly reduced to one containing resistors and current sources, and from which the network admittance matrix Y is readily constructed. There is no need for the user to actually write down the differential equations associated with the network to study its transient behaviour. There are two major disadvantages of this approach, however.

Firstly, it requires a relatively small timestep to avoid spikes (numerical) whenever switching due to convertor/compensator models within the network takes place. This requires a premium in terms of CPU time for the overall simulation. It is difficult to change the timestep dynami- cally during the simulation run, because that would mean re-calcula- tion of all resistor values and current sources and a re-inversion of the network matrix. (This may be possible if these electromagnetic transients programs are re-written, and this feature introduced, but that would entail a great deal of effort.) One approach to overcome this limitation is that used by the 'NETOMAC' simulation program [ 5 ] . In this approach the timestep is not changed but the history terms in the trapezoidal algorithm are interpolated and modified so that the simulation timestep can be synchronized with the switching instant.

Secondly, since the Dommel algorithm is not state variable based, it leads to a poorer conditioning of the network admittance matrix Y due to its unequal treatment of inductors and capacitors within the network. For example, the equivalent resistance associated with an inductor L is 2L/At, and for a capacitor C it is Atl2C. Thus, elements in the network admittance matrix for L and C are affected in opposite ways when At is reduced leading to a poorer conditioning of the V matrix. Although this

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algorithm usually works, at times this drawback may cause the system to show numerical instablity. A state variable formulation, on the other hand, always integrates the differential equations of the system and solves the equations for capacitor voltages and inductor currents, not for node voltages as in the Dommel method. Thus all the variables have the same dependance on the timestep, and the resulting matrices are better conditioned and less likely to give numerical instability. Another advantage of the state variable approach is that the dependence of the system matrices on the value of the timestep is directly proportional, and the timestep can be readily changed during a run. The major disadvantage, however, of the state variable approach is that it is difficult to write code for the automatic generation of the state equations given the network connectivity information; the Dommel algorithm, on the other hand, handles this with ease.

For the above mentioned reasons it was decided to use a compromise approach in modeling the static compensator and its associated external network by developing a stand-alone (child) state variable model for the static compensator, but retaining the powerful network modeling capabilities of the parent transients program for modeling the external network. The compensator model program interfaces as a Norton current source with the transient simulation program. The state variable based static compensator module results in a robust algorithm for calculating the currents and voltages internal to the static compensator, and also allows for features such as the introduction of a variable local timestep required for the switching elements to be modeled ade- quately. This approach is similar to that proposed by other authors [111 who have interfaced a dc convertor model in an electromagnetics transients program (EMTP) to a Transient Stability Program where the two programs run with different (though not variable) timestep; interfacing between programs was achieved by using Norton and Thevenin equivalents.

The authors' program differs from the NETOMAC approach and merely selects a smaller timestep which is a submultiple of the parent program's timestep. Also, unlike NETOMAC, the authors' approach uses a state variable based formulation which has the advantages mentioned earlier. In addition the authors' approach can be used to develop models which can be interfaced to electromagnetic transients simulation programs (such as EMTP or EMTDC) that do not have the time mesh shifting capability of NETOMAC.

Many authors [3 ,4 ] have successfully used state variable based modeling for HVdc convertors, but in their approaches even the associated external systems have been modeled in state variable form. These external systems cannot therefore be easily changed to a different topology (without rewriting the equations) as is possible with the Dommel method.

The following sections of this paper deal with details of modeling the SVC, the method of making a stable interface between the child model and the parent EMTDC (although the same could be done with EMTP, or any other programs based on the algorithm proposed by Dommel) and present some sample results. The paper concentrates on the modeling of the SVC itself because the bulk of the controls are simulated with the control system building blocks (EMTDC CSMF functions or EMTP TACS functions) of the parent program. Some modeling details of the phase-locked-loop (PLL) firing system used here, are also discussed because this is modeled internally in the SVC module. The paper concludes with the simulation of a SVC regulating the ac voltage bus at the inverter end of a back-to-back HVdc tie.

MODELING AND TESTING

The Basic Model

Figure 1 shows a schematic diagram of the SVC. The SVC transformer is modeled by nine coupled windings on the same core with three windings representing the primary winding, and three each representing the wye and delta secondaries. The special case of 3 single phase transformers can also be represented with the proper selection (of zeroes in the appropriate locations) of the inductance matrix.

0885-8977/90/0700-1398$01.00 0 1990 IEEE

Figure1 : SVC Circuit Diagram.

The TCR elements are connected in c Ita, with the thyristor switches modeled as changing resistances. The snubber circuik are modeled as R-C elements in parallel with the thyristors.

The TSC branches are modeled as capacitors. Regardless of the number of TSC branches in operation at a given time, all of these are represented together as an equivalent single capacitor per phase. The value of this equivalent capacitor and its initial voltage are adjusted when the TSC switching logic indicates the turning on or off of a capacitor bank. The advantage of this approach is that only one state variable per phase (6 phases in all) is required. With a TSC having many stages, each extra stage would increase the number of state variables by 6 (3 for the wye, and 3 for the delta), and the number of state variables would rapidly become very large. This approach is exact only if the TSC branch is comprized of a pure capacitance. It was decided not to include a series inductance (at this stage) because it would require each arm to be modeled separately. Since the aim was to obtain a model for relatively long duration studies (typically 100 -2000 ms), and since capacitors are switched only a few times in a simulation run. this was a small price to pay in making the program fast.

Saturation of the transformer is represented by flux-dependent current sources in parallel with the transformer windings. The flux is calculated from the integral of the voltage across the winding. A flux magnetizing -current relationship is then consulted to determine the extra magnetizing current that must be injected for that particular flux level. At present, there is no representation of the hysteresis loop, but there is a provision for the representation of some core losses via a selectable shunt resistor across each winding. The details of the equations used are presented in Appendix. These equations are obtained by graph theory techniques [ 6 ] . The state variables (variables to be integrated) are the primary, secondary-delta and secondary-wye currents ( ip , is,, isy); the TSC capacitor voltages (VCA. VCY) ; the TCR inductor currents (ii,, ii,) : and the snubber capacitor voltages (VSCA. vScy) Each of these except VCA. vcY and iiy have three state variable components, corresponding to each individual phase. Since the capacitors are connected in delta, the three voltages add up to zero, so that only two capacitor voltages can be chosen as independent state variables. Likewise, in the wye connected transformer secondary winding, the three currents sum to zero, thus allowing for only two independant state variables. One could have introduced a fictitious (large) resistance to ground at the neutral point to make the formulation more sym- metrical, with all three currents as state variables, but such solutions often lead to numerical problems. Instead, the algorithm is made more robust by eliminating variables when capacitor loops or inductor cutsets are present. Thus, the SVC model has 21 state variables in all.

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The matrices in the equation are functions of the states of the thyristors, and the appropriate entries are re-calculated whenever the firing logic requires the turning on or off of a thyristor. Also, the capacitor voltages and the capacitance values are initialized whenever the TSC operates.

Method of lntearation

The trapezoidal rule has been extensively used in electromagnetic transient programs [ 11. However, implementing it here would have entailed a matrix inversion every time a switching occurred, or whenever the timestep had to be changed. For this reason, an Adam’s second order closed formula [7] was used, the numerical stability of which is identical to that of the trapezoidal rule. Equations I A , 2A - 5A in the Appen- dix can be written as

where X is the state variable vector, and U the vector of inputs (primary voltages). To apply the chosen method of integration, the incre- ment in X is defined as

AX = [A.X(t -At) + B.u(t)]At (1 b)

x = A . X ( t ) + B . u ( t ) ( la )

Then the state vector estimate is updated as

Equation 1 b is re-evaluated with X(t - At) replaced by Xe,(t) , to find a new update X,,(t) , which is used to re-evaluate AX again, until there is negligible change in the updated Xe,(t) . In practice, for the range of timestep values used (25 - 50 ps), 3 iterations are found to be sufficient. Notice also, that no matrix inversions are involved. An application of the trapezoidal rule would have involved only one evaluation intead of 3, but would have required a matrix inversion, every time the value of matrix A changed with a switching or change of timestep.

Variable Timesteo for handlina thvristor switching

Since the simulation algorithm works with discrete timesteps, the zero crossing of a current often falls in-between two timesteps as in Figure 2a. When the turnoff of a thyristor in series with a current carrying inductor (such as in a TCR) is being simulated, there is the distinct possibility of a spurious voltage spike appearing in the thyristor and inductor voltages. Figures 3a(i) and (ii) show simulated TCR current and voltage waveforms respectively for a simple SVC system (Figure 6), with timestep A t = 50 ps.

Xe,(t) = X ( t - A t ) + A X (IC)

Figure 2a : Thyristor switchoff with Fixed Timestep.

At= Original Timestep 6t= Submultiple Timestep Dt= Catch-up Timestep St

Figure 2b : Thyristor switchoff with Variable Timestep.

Many solutions to this problem are possible, and one of them includes increasing the snubber capacitance but at the expense of excessive snubber circuit losses. Another way is to reduce the timestep, but this entails a heavy computer CPU time penalty, particularly because the smaller timestep may not be necessary while simulating the transient in between switching instants.

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b) Variable timestep with A t = 50 ps and fit = 10 ps ,

Figure 3 : TCR waveforms for fixed and variable timesteps.

The authors' approach to this problem is to use a smaller timestep where required (Figure 2) . Consider that the program has been operat- ing with timestep At (Figure 2a). At point t A , the current in an induc~ tor iL is positive, but at the next simulation instant tn , it is negative. If a thyristor in series with the inductor attempted to switch off at either tA or tg , a voltage spike would result because of the chopping of a large inductive current. When a change of sign in the current value i,, is detected, the program does not update the state variables, but re- verts back to point tA , and resumes simulation with a submultiple timestep St = At in (points tA1, tAz. ......... t A n etc.). The switching instant is now more finely straddled depending on the number of submultiple timesteps; a value of n between 2 to 5 is recommended. The thyristor switches off at time (say) t A j , which results in a smaller spurious voltage spike because the current magnitude being chopped. is smaller. The program then takes one more 'catchup' step Dt to come back in synchronism with the original sampling instant t B . The values of At and St are under the user's control. Figure 3b shows results from a re-simulation of the test but with At = 50 ps and St =10 ks : the voltage spike is no longer evident.

In the proposed method, the smaller timestep is used only where re^

quired. Since switchings within the child program are being more precisely simulated by this smaller timestep, it is more economical tnan changing the timestep for the entire program (parent plus child). In the case of EMTDC or EMTP (standard versions), it is not possible to use variable timestep anyway. As an assessment of the benefits and overhead of the use of the variable timestep strategy, the simulation time for a i o 0 ms run increased from 40.90 s to 43.26 s or roughly 5.5%, which is much smaller than the 500% increase in time which would have resulted if the timestep had been set to 10 ps throughout the run.

Modelina the Firina Svstem

The external control system controlling the compensator generates two signals: i) a firing angle order for the TCR, and ii) a capacitor switch oniswitch off order for the TSC. The exact instant of valve firing for the TCR is determined when a reference angle derived from a phase locked loop (PLL) equals the ordered angle. A built-in dq0-transformation based PLL, referred to as of the 'Transvektor' type [SI is provided as the default PLL. The user may replace it with his own model. To do this, the user must build his PLL model by selecting building blocks from the parent program control system functions, and provide1 2 ramps, in the correct time sequence, for firing the SVC thyristors.

Figure 4 shows a block diagram of this type of PLL. The three phase synchronising voltages derived from the commutating bus are Va. Vb and Vc. Using a 3-phase to 2-phase transformation, the direct and quadrature axes voltages, Valpha and Vbeta respectively, are derived according to the following equations'

Valpha = (213)Va - ( l i 3 )Vb - (l13)Vc Vbeta = (1 /43) (Vb - Vc)

12) (3)

- .~ ~~~ ~ .~ 1 ~ ~ p ~ p ~ . osc ~~

si"" c. ~ ~ - ~ U ~

v coq9

Figure 4 : Default built-in PLL

An Error signal is generated according to the following equation: Error = Valpha.VsinO - Vbeta.VcosO (4)

where 0 is the phase output of the VCO. The Error signal is acted upon by a PI controller with proportional gain K1 and integral gain K2. This IS followed by a VCO to derive a control signal Theta 0 for a Sine-Cosine Oscillator: the nominal frequency of the VCO is controlled by a reference voltage Uref; dynamic modulation of this reference voltage can be accomplished by the input AUref. The outputs of the Sine-Cosine Oscillator, VsinB and VcosO, are fed back to derive the Error, as indi- cated in equation (4 ) . The output of the VCO. which is limited between 0 and 180 degrees, generates the timing Sawtooth waveform 0 (derived as in eq.5). which is utilised to derive the firing pulses for the valves of the compensatoriconvertor.

0 = [ (Kl1s + K2) (Error) + Uref + AUref ] i s (5)

Twelve ramps for the 12 thyristor firings are generated from this basic ramp, and each is compared with the firing angle order. Thus it is even possible to modulate the firing angle order to provide controlled individ-

c) Sine of phase angle error 7- -7 U- 1 - 1 ,

i

- 1 I 0 1 0 7

1 8: t -~ - - I

oU d) Dhase A volts and Sine of VCO output

Figure 5 : PLL performance under single line to ground fault

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The value for R, is chosen to approximate the very short term behaviour of the SVC (for example R, = 21"/At where l" is the zero

sequence inductance of the SVC transformer). The exact value chosen is not too important because an extra current i , is injected to compen- sate for any errors introduced by R, . This compensation current is estimated from the most recent (and therefore stale by one timestep) voltage information available to the SVC model. If i, =V(t-At)/R, is added to Is(t) and injected into the parent program, a current. V(t)/Rc bleeds into R, and the current entering the rest of the system is Is( t ) + [V(t - At) -V(t)]/R,. Note that the second term of this current vanishes in the limit At + 0, and so the current has a value very nearly equal toI,(t), as was intended.

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ual phase firing such as may be required for, say damping a given harmonic in a system [ 9 ] . The PLL also shows improved immunity to system harmonics and rapidly regains a lock on phase following faults causing loss of synchronising voltage [ 131.

Figure 5, is a typical simulation of this PLL where a single phase to ground fault on Phase a reduced Va to zero. The following results are presented in Figure 5: (a) Va Single Phase AC voltage input signal (b) Valpha and Vbeta signals, (c) Error signal as defined by eq.(4) , (d) Va(fund) and VsinO signals. The fault resulted in a reduced magnitude for Valpha to one third of its original value, and no change in Vbeta. A second harmonic component is observed in the Error signal. These results are consistent with theoretical predictions. The synchronization of the fundamental component of Va, Va(fund), and VsinO signals is rapid and achieved in less than one cycle after the fault is removed (Figure 5d). Two-phase and three phase faults gave similar results.

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Modelina the Switchina of Caoacitors

A s discussed in the introduction, a novel method of modeling the thyristor switched capacitors has been used. The order of the model would quickly increase if each of the capacitor stages were modeled separately (6 new state variables per extra branch). Instead the switching onioff of a capacitor bank is carried out by re-adjusting the initial charge on the capacitors, and changing their capacitance values. This approach is exact only if there are no series inductances which are often present in practical TSCs. This simplification was deemed a worthwhile tradeoff between modeling detail and simulation speed since the primary objective of this model was to study power system transients.

Capacitors are switched on when the voltage difference between the system and the capacitor to be switched is a minimum. Capacitors are switched off only at a current zero.

Figure 7 shows (a) the 3-phase currents in the primary of the SVC transformer, (b) 3-phase secondary voltages of SVC transformer, (c) 3-phase capacitor currents in the delta TSC for the switching onioff a capacitor bank, (d) the reactive power supplied by the TSC together with the capacitor switching order (switch on at 20 ms and switch off at 60 ms). and (e) the capacitor votage in the simple test system of Figure 6. Note that the TCR pulses have been blocked so that only the transients associated with the capacitor switching are present. From Figure 7e, it is evident that a capacitor switch on occurs at a voltage zero (at 20 ms); also a capacitor switch off occurs at a current zero (Figure 7c) which corresponds to a maximum capacitor voltage (at 60 ms) , The voltages on switched off capacitors are caused to decay at a user specified rate (barely evident in Figure 7e). The detailed equations for capacitor switching are presented in the Appendix.

TCR TSC 1 7 %

1 1 i rn MVA T 7 3 M V A -r

1 Voltage decay 1 1

- -

- I- 4

Figure 6 : Test system for capacitor switching

lnterfacina to the Darent Simulation Proaram

The child SVC model is a separate stand alone subroutine written in FORTRAN. Consequently, features such as the variable timestep etc., can readily be introduced without impacting on the parent program. The only drawback is that the information between the SVC model and the parent program is exchanged at the end of a parent program timestep, and the calculations within that timestep by the SVC model and the parent program each have to work with one timestep old information about the other. Care is necessary to avoid numerical instability when interfacing the SVC model to the parent program. This instability may arise because the model interfaces to the parent program as a current source whose value is not affected by the results of the calculations in the parent program until one timestep later. Therefore for the duration of the present timestep, this current source appears like an incremental open circuit. Such 'open circuit' terminations have a destabilizing influence on the simulation particularly if they occur at the end of inductive branches [2], To get around this problem, a technique used before with success in interfacing machines and HVdc valve groups to transient simulation programs [2 ,10] is employed. Figure 8 shows the SVC current for some phase Is(t) calculated by the model for injection into EMTDC. A fictitous resistance to ground R, is introduced in the main program,so that there is no longer an open termination at this node and the numerical instability problem can be avoided.

kA a) Currents in primary of SVC transformer. 2.0 I

1 0

0 0

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b) Voltages on secondary (delta) of SVC transformer. kV(x lo2)

0 . 4 , 0 2

0 0

-0 2

k o ( x 0 2 ) c)TSC capacitor currents. 0.1

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d) Reactive power and capacitor switching

I uvn(x 103) 1 !nsta"ts. 0.2 I 1

~ ~ - - - - _ _ 0 0 J L C a p a c i t o r switchings

I - O b o I 0 1 t i m e

rv (x ,02) I e) TSC capacitor voltage. I 0.4 , I i

4 I -03!0 0.1

t i m e

Figure 7 : Capacitor switchings in system of Figure 6

I I t I I I L - - - - _ _ - _ - - - _ - - J i - _ - _ _ - _ _ - - _

Model EMTDC

Figure 8 : Interfacing to the EMTDC program

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In addition to this termination the phase voltages applied to the SVC model can also be estimated for the next timestep. For example if Va. Vb. and Vc are the most recent instantaneous values (with the com- mon zero sequence removed), then the SVC model uses Va' instead of Va where

(6) where w is the system frequency and At the timestep. This small cor- rection (which vanishes as At -, 0) is a good estimate of the expected value of Va one timestep later, and further reduces errors associated with the one timestep delay.

USE OF THE MODEL IN A SIMULATION STUDY

Figure 9 shows a 500 MW pole of a back-to-back HVdc tie between sending and receiving end systems of short circuit ratios (SCR) 4.5 and 2.5 respectively. (The tie rating is based on one pole of the Chateauguay link in Quebec). The rectifier side ac bus is rated at 315 kV and has 250 MVAR of harmonic filters, and the inverter ac bus is rated at 120 kV and also has 250 MVAR of filtering. In addition, a SVC rated at +167 (with 2 stages of switched capacitance) MVARi-100 MVAR is present at the inverter ac bus to regulate the voltage.

Va' = V, + [w.At(V, -Vb)][ 1 - (w.At) ]/1.732

Harmonic Filters

1 1 . 13, HP 7 SVC 1671l rad) l lOfl(iag1

MVA

Figure 9 : Back-to-back dc tie with SVC.

Harmonic Fillers

1 1 . 13. H r

The block diagram of the SVC controls is shown in Figure 10a [12 ] , and a steady state control characteristic typical of SVC model is shown in Figure 10 b. The SVC controls are identical to the compensator used at Chateauguay. It consists of a three phase bus voltage measurement block and a three phase current measurement block. These measurements are used to indicate the reactive power Qsvc of the compensator. The magnitude of the voltage measurement VL is used to derive a droop. This is followed by a block that adds the droop, proportional to the reactive current of the SVC, to the magnitude of the measured voltage. This signal is then filtered. The error between this filtered signal and the reference bus voltage Vref is passed through a PI controller that results in a reactive power order (BSVS) to the SVC. This order is split by the 'allocator' into a capacitor onioff signal for the TSC and a reactive power demand (BTCR) from the TCR. Hysteresis between capacitor stages is built into the model. A relationship representing the non-linear dependence between BTCR and the required firing angle cy

is consulted and the required cy-order passed on to the PLL-based firing system in the SVC model. All these control blocks are modeled with the control system modeling facilities of the parent program (CSMF in EMTDC). In addition there are the usual set of controls (based on Chateauguay tie) for the dc system which are similarly modeled but not described here. The HVdc convertors and the SVC are modeled as 12 pulse valve groups.

A r a m s

Comparator

pulses

Capacitor Allocator 7; 61 BSVS ONiOFF to TSC [ T 6 0 H z

Inductive Capacitive

Figure1 Ob : SVC Regulation Characteristic

Figures 11 & 1 2 show the system's response to a 8% voltage reduction of the equivalent source on the inverter side: this perturbation was selected to show essential features of the SVC behaviour. This perturbation is meant to simulate a 12 cycle remote three phase ac fault. During the fault period (0.05 s to 0.25 s in the simulation), the SVC switches on one more capacitor bank (Figure 1 l g ) in order to regulate the inverter ac voltage (Figures 11 a and b) . On removal of the undervoltage at 0.25s there is a subsequent transient overvoltage which is again regulated by the TSC switching off a capacitor bank and the TCR generating the appropriate inductive current (Figures 11 f,e). Also shown in Figure 11 are total demanded reactive power from the SVC (Figure 11 c) and the TCR firing angle cy (Figure 11 d) . Figures 11 e & f show the TCR and total SVC currents. The step change in TCR firing angle 01 when a capacitor is switched is a result of the action taken by the allocator (Figures l l d 8. 9). Figures 12a, b and c show the response of the dc system variables (dc current, dc voltage, rectifier firing angle and inverter extinction angle). The ramping down of the ordered dc current during the undervoltage is a consequence of certain dc control functions which are not discussed here.

The computer CPU time for the above example on a SUN 3/60 work- station with 8 MB memory is approximately 45 minutes for 1 second of real time using a 25 ps timestep. The simulation time for the SVC with a simple external system (similar to one shown in Figure 6) was 7 minutes 13 seconds for 1 second of real time using a 50 ps timestep.

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kV(x 103) a) Three phase AC volts at Invertor. I ! I I 1 0 2

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0 2 0 4 0 6 -0

1 6 -

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d e q r e e s ( x l o z ) ') I

Rectifier CY and Invertor y I I 1 0 4 ----- ~

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t * m e ( s J , ~ I

1 0 2 ) d) TCR firing angle CY . 1 6

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kA A detailed state variable based model of a SVC has been presented and modelina details of the firina control circuit and the novel treat- e) Three phase TCR currents.

t i m e ( s )

ment of capacitor switching are explained.

With proper care, models such as the one developed here can be interfaced to commercially available transient simulation programs and provide the benefits of a variable timestep and stable numerical performance. From the simulation example presented in the last section, it is evident that the model can be used succesfully in very detailed simulation studies.

Further work: The techniques presented here can also be used for detailed representation of other switching models such as an HVdc convertor.

ACKNOWLEDGEMENTS

This program was developed at IREQ where A.Gole was on sabbatical

for providing the facilities and to the University of Manitoba for approv- ing Dr.Gole's sabbatical leave. The financial assistance of NSERC Can- ada is also appreciated, The authors benefited greatly from numerous discussions with other IREQ research staff, and in particular they ex-

k~ f ) SVC currents in primary side of transformer.

-1- -~ . fi leave from the University of Manitoba. The authors are grateful to IREQ ttme(s)

g) Number of capacitor stages. , I I I I 4.0

Figure 11 : SVC waveforms for simulation study.

CONCLUDING REMARKS

The state variable technique is a powerful tool for modeling power electronic circuits, even though accomodating topological changes in these circuits means rewriting the state equations. The Dommel algorithm (used in popular electromagnetic transients programs) has the ability to accomodate such changes with ease, but often suffers from the numerical problems associated with poorly conditioned matrices. In addition, many of these modern programs do not allow the variable timestep feaure which economises computer CPU usage when simulating power electronic circuits. A technique has been presented in this paper which uses the advantages of both these techniques.

press special thanks to Alpha Oumar Barry and Lewis Vaughan.

REFERENCES

[ 1) Domme1,H.W. ,"Digital Computer Solution of Electromagnetic Transients in Single and Multiphase Networks", IEEE Trans. PAS, Vol. PAS-88,No.4. April 1969, pp 388-399. [2 ] D.A.Woodford, A.M.Gole and R.W.Menzies; "Digital Simulation of Dc Links and AC Machines", IEEE Trans. PAS, Vol. PAS-102, No.6, June 1983, pp 1616-1623. [3] M.D.Heffernan. K.S.Turner, J.Arrilaga and C.P.Arnold; "Compu- tation of AC-DC System Disturbances Part I " , IEEE Trans. PAS, Vol.

[4] K. R. Padiyar, Sadchidanand, A.G.Kothari, S.Bhattacharya and A.Srivastava; "Study of HVDC Controls through efficient Dynamic Digi- tal Simulation of Converters", .IEEE PES Winter Meeting, New York, Jan.29-Feb.5,1989. Paper No. 89 WM 113-2 PWRD. [ 5 ] K.H.Kruger. R.H.Lasseter,"HVDC Simulation Using NETOMAC", IEEE MONTECH '86 Conference, Montreal, 29 Sept.- 1 Oct. 1986, Pro- ceedings pp 47-50. [6 ] N.Balbanian and T.A.Bickert; "Linear Network Theory: Analysis, Properties, Design and Synthesis", Matrix Publishers,l981 . ISBN

[7] Robert W.Hornbeck; "Numerical Methods", c Quantum Publish- ers, Prentice Hall, 1975. pp 198-199.

PAS-100, N0.11, Nov.1981, pp 4341-4363.

0-916460-10, pp 104-147.

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[ 8 ] K.Bayer. H.Waldmann and M.Weibelzahl; "Field Oriented Closed Loop Control of a Synchronous Machine Using the New Transvektor Control System", Siemens Review, XXXIX,No.6, 1972, pp 220-223. [ 9 ] G.B.Mazur and R.W.Menzies; "Advances in the Determination of Control Parameters for Static Compensators", IEEE PES Winter Meet- ing, New York, Jan.29-Feb.5, 1989, Paper No. 89 WM 052-2 PWRD. [ 101 A.M.Gole, R.W.Menzies, D.A.Woodford and H.Turanli; "lm- proved Interfacing of Electrical Machine Models in Electromagnetic Transients Programs", IEEE Trans. PAS, Vol PAS-103, No.9, Sept.1984, pp 2446-2451. i l l ] J.Reeve and R.Adapa, "A new approach to Dynamic Analysis of AC Networks incorporating Detailed Modeling of DC systems - Parts I and 1 1 , " IEEE Trans. on Power Delivery, Vo1.3, No.4, Oct. 1988. [ 121 Static Compensators for Reactive Power Control, Editor R.M.Mathur, Canadian Electrical Association Publication, 1984. Ch. 5. [13] A.Gole, V.K.Sood and L.Mootoosamy, ' ' Validation and Analysis of Grid Control System using dqz Transformation for Static Cornpensa- tor Systems", Canadian Conference on Electrical and Computer Engi- neering, Sept. 17-20, 1989, Montreal, Canada.

APPENDIX

!sQ!xLd

V P = [ \ 'PI , "pi, vp31T

i p = Lip2, ip:? ip31T

- primary voltages,

- primary currents,

~ ' P \ = [ ~ S I I ~ V s 1 2 , \ s \ 3 1 T - delta secondary voltages,

v s \ =I"\, "srlr V r ~ 5 1 T - wye secondary voltages

"C_\ = [VC: "C2]T

(only two voltages linearly independant)

" C S = rVC4. VC51T

(only two voltages linearly independant)

\ 'Cs i = ['CY:. \'CS:. vCsj lT - Snubber capacitor voitages (delta),

" C s ? = [ \ C s i - vCs:, \.C16IT - Snubber capacitor voltages (wye) ,

- delta secondary capacitor volts.

- wye secondary capacitor volts,

ii, = i 1 2 . i131.r - TCR currents (delta winding),

ii, = [iii. i l l , i i J T

i > \ = [is . is:. is31T

- TCR currents (wye winding),

- secondary currents (delta)

i ' s ) = Li--. - secondary currents (wyej, - (only two currents linearly independent)

- secondary currents (wyej, i 5 , = [iCl. i,i]'

R - Loss resistor.

C I C:. C ; C i . C:. C ,

ri ri:. r i : r t l . r1:. r ~ - - Thyristor equivalent resistors L - TCR Inductor,

C> - Snubber Capacitor

R s - Snubber Resistor.

L , ~ . - - - - - - ' J - Transformer inductance matrix elements.

Summar4 of state variable eauat ioq

Using standard graph theory technlques [ h ] one obtains for the SVC equivalent clrcuit (Figure A l ) the following five state equations:

- TSC capacitors,

ip+ primary wye

secondary delta secondary wye

Figure A l : Equivalent circuit of SVC

(3.4)

(4.4)

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where

j + i 4.5.6

I + [ 4.5.6

is,chosen as a state variable equations 1A - 5A have the form 2 = + Bti with 6 = Cp which is the standard state variable form

Accountino for caoacitor Switching

Consider Figure A2 in which the capacitor CZ x of initial voltage \z xo is switched in parallel to capacitor C2 Initial voltages on capacitors C1, C2 and C3 are \ C I O $c?o and \c?r3 respectively The switching causes a charge Iq to trasfer from each capacitor to the next as in the figure Assuming q q? and ql to be the post-switching charges w e have

Aq = 91 - 9 1 0 = 9 2 - 9;" = 9 3 - 9 30 (7)

where s o = 9:o + c:, * $ 2 ~ 0 There are thus two independent equations

91 - 910 = 9 3 - 9 2 0 18al

9 2 - s i 0 = 9 3 - 9 3 0 (8b)

in the three unknowns q, q:and q Kirchoffs voltage law provides the third equation

\ , + \ 2 t \ ? = 0 19)

On solving for q 92and q; and adjusting the after switching volt ages on C1 C2 and C3. the values on the capacitors are also

changed C2 now becomes Ci = Ci + C : 1. Removing a capacitor bank

of value Cr is equivalent to adding a capacitance of value - c: 1

, "2AO

Data for the svstem used in simulation study

AC network equivalents Sending end 315 kV SCR 4 5 at 85 degrees damping angle

L l = 22 2 mH L2 = 95 4 mH, R = 13 1 ohms Receiving end 120 kV SCR 2 5 at 85 degrees damping angle

L1 = 10 49 mH L2 = 21 mH, R = 10 8 ohms

Convertor Transformers Sending end 315 kV 120 kV 610 MVA XL = 18 Receiving end 120 kV 120 kV. 610 MVA XL = 18 % Saturation (both) knee 1 2 pu. slope 0 4 pu

AC Filters Sending end: 11 th harmonic: R = 1.13 ohms, L = 27.4 mH, C = 2.12 UF 13 th harmonic: R = 0.25 ohms, L = 19.5 mH, C = 2.12 UF C = 2.4 uF.

Receiving end: 1 1 th harmonic: R = 0.163 ohms, L = 4 mH. C = 14.6 uF. 13 th harmonic: R = 0.14 ohms L = 2.85 mH, C = 14.6 uF. C = 16.58 uF.

svc Transformer 120 kV 12 65 kV 200 MVA X LD = X LY = 17 " 0 . X LDY =2 1 U. knee level = 1 2 pu Saturation slope 0 4 pu

TCR L = 22 mH (100 MVA ) TSC C= 202 UF stage [ 83 MVA)

DC system Rating 140 6 kV 506 MW. 3 6 kA Smoothing Reactor 34 mH on each side

BIOGRAPHIES

A.M.Gole (S'77,M'82) obtained the B.Tech.(E.E.) degree from the Indian Institute of Technology Bombay in 1978 and the Ph.D.degree in Electrical Enginnering from the University of Manitoba in 1982.

Dr. Gole is currently an Associate Professor in the Dept. of Electrical Engineering at the University of Manitoba. From Sept. 1988 to Aug.1989 he was on sabbatical leave at IREQ in Varennes, Quebec. His research interests include HVdc transmission, power system transients simulation and the use of optimization techniques.

Dr. Gole is a Registered Professional Engineer in the Province of Manitoba.

V.K.Sood (SM 1985) obtained the B.Sc. (1st Class Honours) degree in Electrical Engineering from University College, Nairobi (Kenya) in 1967, the M.Sc. degree from University of Strathclyde, Glasgow (Scotland) in 1969 and the Ph.D. degree from University of Bradford (England) in 1977.

From 1969-76, he worked at the Railway Technical Centre, Derby (UK) carrying out research in DC Choppers for rapid transit applications. Since 1976, he has been at the Hydro-Quebec research institute (IREQ) in Varennes, Quebec working with the HVdc analog simulator. His present research interests include HVdc transmission, Forced Commutation and analoginumerical simulation techniques.

Dr.Sood is Senior Member of the I.E.E.E. , Member of the I.E.E. and a Registered Professional Engineer in the Province of Quebec. He is also an Adjunct Associate Professor in the Department of Electrical and Computer Engineering at Concordia University.

Figure A2 : Switching on a Capacitor C 2 ~ in phase 2.

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Discussion

D. Povh and H. Tyll (Siemens AG, Dept. EV NP, P. 0. Box 3240, D- 8520 Erlangen, Germany):

A u t h o r s a r e t o be commented f o r a v e r y i n t e r - e s t i n g p a p e r on t h e m o d e l l i n g o f SVC i n t h e e l e c t r o m a g n e t i c t r a n s i e n t s i m u l a t i o n p r o g r a m p r e s e n t i n g new i d e a s t o i m p r o v e t h e EMTP and EMTDC p r o g r a m s . We u n d e r s t a n d t h a t t h e m a i n i s s u e o f t h e w o r k i s t o overcome t h e d i f f i c u l - t i e s a t t h e c a l c u l a t i o n s o f SVCs and HVDC i n t h e s e p r o g r a m s .

As m e n t i o n e d i n t h e p a p e r t h e p r o g r a m NETOMAC h a s i n c o n t r a r y t o o t h e r p r o g r a m s t h e a b i l i t y t o i n t e r p o l a t e t h e t i m e s t e p t o s w i t c h a t c u r - r e n t z e r o s a n d t o a d j u s t t h e f i r i n g i n s t a n t o f t h y r i s t o r s e x a c t l y a c c o r d i n g t o t h e i n s t a n t g i v e n b y t h e f i r i n g p u l s e c o n t r o l . The method used i n NETOMAC i s s u p e r i o r t o o t h e r methods and e n a b l e c a l c u l a t i o n o f SVC and HVDC w i t h o u t any r i s k s o f n u m e r i c a l i n s t a b i l i t i e s . T h i s h a s been a l s o v e r y i m p r e s s i v e d e m o n s t r a t e d i n t h e r e f e r e n c e 5 o f t h e p a p e r .

The a u t o m a t i c r e d u c t i o n o f t i m e s t e p when a p p r o a c h i n g c u r r e n t z e r o o r when h i g h f r e q u e n - c y o s c i l l a t i o n s o c c u r i n t h e c i r c u i t was f i r s t u s e d i n o u r p r o g r a m ADIEU / l / , w h i c h was p r e d e - c e s s o r o f NETDMAC and was u s e d i n o u r company f o r y e a r s . O u r e x p e r i e n c e s w i t h t i m e s t e p r e - d u c t i o n a r e , h o w e v e r , s i m i l a r t o t h e a u t h o r s ' . I t i s m o s t l y more c o n v e n i e n t t o c a l c u l a t e t h e t r a n s i e n t s c o n t i n u o u s l y w i t h t h e r e d u c e d s t e p . I n NETOMAC t h i s p o s s i b i l i l t y i s a l s o i n c o r p o - r a t e d .

An example o f use o f NETOMAC t o c a l c u l a t e S V C p e r f o r m a n c e i s shown i n F i g . 1 w h i c h i s t a k e n o u t o f r e f e r e n c e / 2 / . The SVC s i m u l a t e d con- s i s t s o f one TCR a n d t w o T S C b r a n c h e s o f d i f - f e r e n t r a t i n g s t o g e t h e r w i t h ac f i l t e r s on t h e s e c o n d a r y s i d e o f t h e m a i n t r a n s f o r m e r . The c o n t r o l o f t h e S V C was r e p r e s e n t e d v e r y d e - t a i l e d . F i g . l shows t h e c o m p a r i s o n o f NETOMAC c a l c u l a t i o n s and s i m u l a t o r (TNA) r e a d i n g s u s i n g o r i g i n a l c o n t r o l c u b i c l e s . The c a s e p r e - s e n t e d shows t h e l i n e a r change o f t h e SVC ad- m i t t a n c e and shows an e x c e l l e n t agreement b e t - ween measurements and c a l c u l a t i o n s .

To t h e a u t h o r s ' s u g g e s t i o n t o s i m u l a t e t h e S V C we h a v e f o l l o w i n g q u e s t i o n s :

( i ) How i s t h e SVC c o n t r o l r e p r e s e n t e d ? I s t h e n u m e r i c a l s o l u t i o n i n t h e c h i l d mo- d e l f o r t h e c i r c u i t and f o r t h e c o n t r o l i n t h e same s t e p ?

( i i ) I f more SVCs a r e c o n n e c t e d t o t h e n e t - work and p o s s i b l y t w o SVCs on t h e same ac b u s , a r e a n y a d d i t i o n a l measures p r o - v i d e d t o a v o i d i n s t a b i l i t y o r n u m e r i c a l o s c i l l a t i o n s b e t w e e n t h e SVCs?

( i i i ) The t r a n s i e n t s i n t h e TSC c a p a c i t o r c u r - r e n t s o f F i g . 7 c show r a t h e r s t r o n g dam- p i n g . Our e x p e r i e n c e i s based on f i e l d measurements t h a t t h e s e h a r m o n i c c u r - r e n t s o s c i l l a t e l o n g e r a n d h a v e i m p a c t on t h e c a p a c i t o r v o l t a g e . Does t h i s dam- p i n g r e s u l t f r o m t h e r e p r e s e n t a t i o n i n F i g . 8? How i s t h e l e a k a g e r e a c t a n c e o f

~ T C R 1$

'TSC2

Fig 1 Response of SVC lollowing admiltance characlerisbcpredelerinined by lhe cor!lrol NETOMAC calculations (a) andn!easurements on simulalor (b)

t h e t r a n s f o r m e r r e p r e s e n t e d w h i c h s h o u l d r e s u l t i n t r a n s i e n t T S C c u r r e n t s o f a p p r o x . h a r m o n i c o r d e r o f 4 .

( I V ) I t was u n d e r s t o o d t h a t t h e c h i l d m o d e l c a n be used o n l y f o r c a l c u l a t i o n o f S V C p e r f o r m a n c e i n t h e n e t w o r k b e c a u s e on t h e s e c o n d a r y s i d e o f t h e t r a n s f o r m e r an e q u i v a l e n t c i r c u i t i s used f o r c a p a c i - t o r s . Does i t mean t h a t t h e i m p o r t a n t s t u d i e s on s t r e s s e s a n d p e r f o r m a n c e a t t h e i n t e r n a l f a u l t s c a n n o t be done? Are t h e c o r r e s p o n d i n g v a l u e s o f T S C c u r r e n t s and s e c o n d a r y s i d e v o l t a g e s a l s o c a l c u - l a t e d ?

/1/ D. Povh B e r e c h n u n g von A u s g l e i c h s v o r g a n g e n i n e l e k t r i s c h e n N e t z w e r k e n i n s b e s o n d e r e z u r E r m i t t l u n g d e r Spannungsbeanspruchungen d e r V e n t i l e e i n e r Hochspannungs - G l e i c h -

s t r o m - U b e r t r a g u n g s - A n l a g e b e i E r d k u r z - sch lu l3 D i s s e r t a t i o n d e r T H D a r m s t a d t , 1 9 7 1

/ 2 / D. Poch; H. Tyll S t a t i c Var Compensators f o r H i g h - V o l t a g e Sys tems 11. Symposium o f S p e c i a l i s t s i n E l e c t r i c O p e r a t i o n a l a n d E x p a n s i o n P l a n n i n g ( 1 1 . SEPOPE), Sao P a u l o , August 1 9 8 9

Manuscript r ece ived February 28 , 1990.

Subroto Bhattacharya and Sachchidanand (ABB Advanced Systems Technology, Pittsburgh and University of Western Ontario, London, Canada): The authors are to be complimented for a well-written paper on a SVC model using the state variable approach. We would appreciate the authors' response to the following questions and comments:

1 . The state variable approach is suitable for handling event-driven systems. A switching event occurs when a thyristor current goes zero. To find the instant of current zero, the proposed algorithm restarts its simulation from the previous time value with a timestep (6t = Ath) which is an integer sub-multiple of the original timestep (At). With this procedure the current zero instant is approximated within a submultiple time interval (Figure 2b) and is not determined precisely. Also, we feel that this part of the algorithm is time consuming. The

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references [4, A, B] find the time instant (k) at which the current through a thyristor goes to zero between the two integration timesteps (tA and tB) by using linear interpolation of thyristor current. All other state-variables are interpolated to determine their values at k. This procedure does not result in any “numerical” abnormalities even when the original timestep (At) is kept around 2 electrical degrees (or approximately 100 ps for a 60 Hz system). Once is obtained the program can perform the “catchup” step. Have the authors tried some such approach and if so, what has been the experience? The child program is interfaced with any parent program by using Norton and Thevenin equivalents. Does the child program receive a Thevenin’s equivalent (i.e., a 3 phase voltage source and an impedance matrix) from the parent program on every timestep? Does the parent program wait for the child program to compute the current sources? It is mentioned in the text that the parent and the child programs use one timestep old information. Is there an inherent delay between the child and the parent program? In case of the EMTP any such interconnection between the parent (EMTP) and the child (non-linear or linear network elements) programs can be achieved as described in Sections 12.1.2.1 to 12.1.2.3 of [C] to avoid any delay if it may so exist. It is possible to run the child program with a larger timestep than the parent program? What factors prompted the authors to choose a timestep of 25 ps for the case shown in Figure 9? Did a larger timestep than 25 ps cause numerical instability?

As a final remark, the paper reinforces the use of state-variable approach for representing power semiconductor circuits using graph theory. Earlier, this approach has been used to model HVDC converters [4, A] and industrial converters [B]. The authors have made a comment in the paper about [4] with reference to which we would like to mention that the state- variable model of the HVDC converter proposed in [4] does not warrant representation of the associated external system (ac system or dc network) in the state-variable form. Hence, it is not a limitation of the modeling approach. Instead, it shows that a flexibility exists to model each subsystem (ac system, converter system and dc network) in any desired manner and to any desired degree of detail. Norton-Thevenin interface between power semiconductor circuits and an external system has been presented earlier [4,

References

K. R. Padiyar and Sachchidanand, “Digital simulation of multi- terminal HVDC system using a novel converter model”, IEEE Transaction on PAS, Vol. 102, June 1983, pp. 1624-1632. S. P. Yeotikar, S. R. Doradla and Sachchidanand, “Digital Simula- tion of a three phase AC-DC PWM converter-Motor system using a new state space converter model”, Proceedings of IEEE-Industry Applications meeting, 1986, pp. 672-679. H. W. Dommel, “ElectroMagnetic Transients Program Reference Manual (EMTP Theory Book)”, prepared for Bonneville Power Administration, Portland, OR, USA August 1986.

A.M.GOLE and YK.SOOD, (University of Manitoba, Winnipeg, Manitoba and Hydro-Quebec, Varennes, Quebec) : The authors thank the Discussers for their kind compliments, discussion and interest.

In response to the discussion by S.Bhattacharya and Sachchida- nand, we have the following comments: 1. The variable timestep feature described in the paper is only one alternative to get around the numerical instability problem due to switching of components. Other techniques exist, as noted by the discussers, but it should be pointed out that all methods whether interpo- lative or not, are never-the-less approximations as to the point of zero- crossing. The great advantage of the variable timestep feature described here is that it is simple and yet effective; moreover, it is to- tally contained within the child model where, incidentally, it is most needed. Furthermore, it permits the child program to be interfaced to

a standard parent program such as EMTP or EMTDC without any modification of the code in the parent program. We feel the variable timestep technique described here is a computationally efficient means to alleviating the numerical instability problem, although not completely overcoming it. The time overhead of the algorithm is estimated as below:

Using a typical value of 10 pS for the submultiple timestep and a 50 pS main timestep, an average number of 2.5 extra steps per cycle are required. Thus, for a 12 pulse converter 30 extra timesteps per cycle are required. At 60 Hz, one cycle has 333 timesteps; hence an average overhead of 30/333 i.e. 9% is required. We feel that this is quite accept- able. 2. Only the parent program receives a Norton Equivalent since the interfacing technique requires it only in one direction. 3. The problem of one timestep delay is inherent to the procedure of interfacing. One way to avoid this delay is to incorporate the child model within the parent, in which case the flexibility due to the child- parent relationship is lost. Another possibility is to iterate the parent- child solutions within one timestep, which is time-consuming. 4. In the present version, it is not possible to run the child program with a larger timestep than the parent timestep. This is, however, not a limitation of the method, and should a need exist then this could be implemented. 5. The choice of timestep of 25 pS for case shown in Figure 9 was determined by reasons of simulation faithfulness during commutation failures. Timesteps of 50 pSwere used and no numerical instability was apparent.

As a final remark, we agree with the discussers that the state variable technique is a powerful tool for developing robust models of power electronic elements such as the one described in the paper.

We are particularly pleased to acknowledge the discussion from Povh and Tyll to share their experience with NETOMAC and state variable modeling. It confirms that the straightforward application of Dommel Algorithm based programmes to simulate power electronic circuits has certain difficulties. The program NETOMAC has been one succesful approach to this problem ; here we have presented an alternative approach that has worked very well. It is encouraging to see also that their experience with state variable modelling is similar to ours. In response to their specific questions: 1. Only the innermost control loop - the phase locked loop based firing system - has been modeled inside the SVC child program and works in the same timestep. The other control system components (upto the generation of the (Y order in Figure 10a) have been modeled with the control system building blocks (CSMF) of the EMTDC parent program, where a one timestep delay is not critical. 2. The simulation also works well with more than one SVC on the same bus. Indeed, the case simulated in the paper is with one SVC and two HVDC converters on the same bus. We attribute the stability of the solution directly to the interfacing technique used. 3. The SVC transformer has been modeled with the entire 9x 9 matrix representing the coupling between all 9 windings; and so the leaka- ge impedance is modeled accurately. We do not attribute the extra damping (if any) to the interfacing technique used because the interface has been carefully designed to offset only the negative damping introduced by the numerical procedure. In our case (for the timestep used) the compensation resistor carried less than 0.3 % of the main current and hence should not contribute to the damping. If there is more damping we attribute it to the data used by us such as the quality factor of the SVC capacitor and the values of the snubber circuit elements, and not to the model itself. We can demonstrate less damping by changing this data. 4. All currents and voltages on both the primary and secondary si- des of the SVC transformer are calculated and are available for obser- vation. In addition, TCR and TSC thyristor voltages and currents are also similarly available as outputs. Although the model has been designed primarily for system side studies, certain faults that do not affect the circuit topology of the SVC can be studied. These include 1-1 short circuits and valve misfires. However, faults such as a secondary side I-g short circuit cannot be simulated because it would mean a change in circuit topology and a change in the state equations describing the circuit. The program could be modified to allow for such simulations but for the requirements of our simulations, we were not interested in doing so. At present the circuit topology must conform to that in Figu- re l a of the appendix.

Manuscript received March 29, 1990.

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