694 IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO. 5, MAY 2012

A Single-Photon Avalanche Diode in 90-nm CMOSImaging Technology With 44% Photon

Detection Efficiency at 690 nmEric A. G. Webster, Justin A. Richardson, Lindsay A. Grant, David Renshaw, and Robert K. Henderson

Abstract—A CMOS and back-side illumination-compatiblesingle-photon avalanche diode (SPAD) is reported in 90-nm imag-ing technology with a peak photon detection efficiency of ≈44% at690 nm and better than ≈20% at 850 nm. This representsan approximately eightfold improvement in near infrared sen-sitivity over existing CMOS SPADs. This result has importantimplications for optical communications, time-of-flight ranging,and optical tomography applications. The 6.4-µm-diameter SPADalso achieves the following: low dark count rates of ≈100 Hzwith ≈51-ps FWHM timing resolution and a low after-pulsingprobability of ≈0.375%.

Index Terms—Back-side illumination (BSI), CMOS, infrared,single-photon avalanche diode (SPAD).

I. INTRODUCTION

S INGLE-photon avalanche diodes (SPADs) are photon de-tectors which utilize the fact that p-n diodes can be stable

for a finite time above their breakdown voltage. When anincident photon with sufficient energy to liberate an electronarrives, avalanche multiplication of the photogenerated electronoccurs due to the high electric field. This produces a significantcurrent pulse signaling the time of arrival of a photon which canbe directly detected by CMOS logic.

Previous CMOS SPAD structures have spectral responseswhich peak in the blue green region [1]–[5]. This is because theactive region has been mostly formed by shallow source/drainimplants and n-well. Electron–hole pairs generated by long-wavelength photons cannot be sensed as they are formed deepin the substrate.

Manuscript received January 17, 2012; accepted January 31, 2012. Dateof publication March 16, 2012; date of current version April 20, 2012. Thiswork was supported by The University of Edinburgh and STMicroelectronics(R&D) Ltd., Edinburgh, U.K. The review of this letter was arranged by EditorC. Jagadish.

E. A. G. Webster and R. K. Henderson are with the Institute forIntegrated Micro and Nano Systems, School of Engineering, The Universityof Edinburgh, EH9 3JL Edinburgh, U.K. (e-mail: e.webster@ed.ac.uk;robert.henderson@ed.ac.uk).

J. A. Richardson is with Dialog Semiconductor, EH1 3DQ, U.K., andalso with the University of Edinburgh, EH8 9YL Edinburgh, U.K. (e-mail:justin.richardson@diasemi.com).

L. A. Grant is with STMicroelectronics (R&D), Ltd., EH12 7BF Edinburgh,U.K. (e-mail: lindsay.grant@st.com).

D. Renshaw is with The University of Edinburgh, EH8 9YL Edinburgh, U.K.(e-mail: david.renshaw@ee.ed.ac.uk).

Color versions of one or more of the figures in this letter are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/LED.2012.2187420

Fig. 1. Device structure.

Numerous applications demand high sensitivity in the redand near infrared (NIR), for example: range detection, fluo-rescence lifetime analysis, optical tomography, and fiber-opticcommunications. NIR is commonly used in ranging systemsbecause it is invisible. Biological fluorescence lifetime imagingand optical tomography would also benefit because longerwavelengths cause less cell damage and penetrate deep intotissue. An extension of the spectral response also allows SPADsto be tailored to optical fiber transmission windows such as850 nm for glass or 650 nm for polymer.

II. DEVICE STRUCTURE AND CMOS IMPLEMENTATION

The reported SPAD, quench resistor, and readout electronicsare fully integrated on chip. The device structure is shownin Fig. 1. The SPAD is of n-type construction, rather thanthe commonly used p-type device inside its own deep n-well(DNW) [1]–[4]. The high-field-multiplication region is thejunction between the DNW and a thin p-epitaxy on a low-resistivity p-substrate. A guard ring is formed by preventingp-well formation and using the natural retrograde implantationprofile of the DNW to create a sharp doping gradient at theplanar junction with the p-epitaxy. Implantation spreading anddiffusion of the implant ensure a low doping gradient at thesides which ensure a higher breakdown voltage and guard ringoperation. Additionally, p-well is placed on top of the activeSPAD junction to collect short-wavelength photoelectrons andbiased at the same potential as the cathode. The effectivenessof the guard ring in reducing the electric field around theperiphery of the device, without reducing the active area, isshown in Fig. 2. It is thought that further scaling of this virtualguard ring can be readily achieved to improve the device’s fillfactor.

0741-3106/$31.00 © 2012 IEEE

WEBSTER et al.: SPAD IN 90-NM CMOS IMAGING TECHNOLOGY WITH 44% PDE AT 690 NM 695

Fig. 2. Electric field (in arbitrary units) simulation performed with SynopsysSentaurus TCAD illustrating effectiveness of the new guard ring structure. Redand high contour density indicates high electric field.

Fig. 3. CMOS implementation.

Fig. 4. PDE of the device operating in Geiger mode at different applied biasesand dead times. The PDE of a 130-nm CMOS SPAD is plotted for comparisonpurposes [3].

The SPAD’s cathode is connected toVBD+VEB (breakdown+excess bias voltage) through a polysilicon resistor and is accoupled to subsequent digital CMOS logic to ensure dc com-patibility (Fig. 3). A two-metal-layer metal–oxide–metal fringecapacitor is used as a high-voltage-compatible coupling ele-ment. The drain–source subthreshold leakage current of an off-PMOS transistor is used to provide the dc bias voltage to theoutput buffer.

III. RESULTS

The SPAD was found to have a relatively low breakdownvoltage of ≈14.9 V. This gives some indication of the high-well-doping concentrations used in nanoscale processes.

Fig. 5. Total measured system jitter illustrating an expected timing responseimprovement with applied voltage.

The photon detection efficiency (PDE) of the SPAD mea-sured with front-side illumination is shown in Fig. 4 at threedifferent levels of excess bias, showing a different shape to aprevious 130-nm SPAD inside n-well [3]. The reduced responsein the blue/green region is due to the p-well on top of theactive region. The p-well successfully increases the wavelengthselectivity of the detector by biasing the spectral responsetoward red wavelengths. The fact that the device is not isolatedfrom the substrate suggests that a promising spectral responsecould be expected with back-side illumination.

The timing response of the device was measured with aPicoquant LDH-D-C 470-nm pulsed laser with a PDL800Ddriver. Care was taken to avoid photon pile up distorting themeasurement by attenuating the laser such that the SPAD firedonly on less than 5% of laser pulses, indicating single-photoncounting. The timing response of the device is shown in Fig. 5 atthree excess bias (VEB) levels. The results include the estimated≈60-ps laser and ≈30-ps output buffer chain jitters. Correctingfor these additional jitter sources yields SPAD jitters of 82-, 53-,and 51-ps FWHM at 15.26, 16.26, and 17.26 V, respectively.The expected exponential diffusion tail is also evident.

The dark count rate (DCR) of the detector compares favor-ably with previous CMOS SPADs, showing a typical DCR of≈100 Hz at low excess bias. The DCR versus voltage of threerandomly selected devices is plotted in Fig. 6. All show anexponential dependence on voltage, increasing to ≈10 kHz at≈ 2.4VEB on the worst measured device.

The trend of DCR against temperature for a median deviceis shown in Fig. 7. The low activation energies obtained for≈1.4- and ≈2.4-V excess biases are consistent with band-to-band tunneling. The 0.74-eV activation energy obtained at lowexcess bias and high temperature is consistent with diffusionand generation current. Moreover, the strong exponential de-pendence of DCR on applied bias apparent from Fig. 6 suggeststhat band-to-band tunneling is the dominant noise mechanismin the device at room temperature. This is also reasonable giventhe relatively low breakdown voltage of ≈14.9 V, which, whilehigh for 130- and 90-nm SPADs [3], [5], is much lower than

696 IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO. 5, MAY 2012

Fig. 6. DCR versus voltage plotted for three randomly selected devices.

Fig. 7. DCR versus temperature at three bias levels for device 12.

SPADs manufactured in HV CMOS or fully custom processes.Therefore, the DCR could potentially be improved further byreducing the doping concentration and raising the breakdownvoltage. However, this would involve custom fabrication steps,and generally, advanced CMOS technology is not, by default,qualified for high voltages.

To evaluate the after pulsing, an oscilloscope was set tomeasure the time between a primary pulse and a secondarypulse, if one occurred in a 100-ns time window. The devicewas set up with a 15-ns dead time at a total bias of 15.26 Vand left for approximately 14 h in the dark. This yieldedapproximately 4 million primary and 15 000 secondary pulsetriggers, giving a total after-pulsing probability of 0.375%.The exponentially distributed after-pulsing probability obtainedwith this technique is shown in Fig. 8 showing an 8-ns lifetime.The after-pulsing probability compares favorably with existingCMOS SPADs considering the comparatively short dead timeof the device [3]–[5].

Fig. 8. Histogram of the measured after-pulsing distribution obtained from≈ 4 × 106 primary dark count events illustrating a lifetime of ≈8 ns.

IV. CONCLUSION

To the best of the authors’ knowledge, the reported SPADhas the highest PDE in the red and NIR yet achieved inCMOS. The SPAD is compatible with low-resistivity sub-strate and thin-epilayer CMOS technology and back-side il-lumination imaging processes. The reported SPAD comparesfavorably with previous devices in other performance met-rics such as DCR, timing response, and after pulsing whilebeing implemented in the most advanced process node yet.The presented device opens up additional potential opportu-nities for SPADs as well as improved performance in existingapplications.

ACKNOWLEDGMENT

The authors would like to thank STMicroelectronics, Crolles,France, for fabricating the device. The authors would also liketo thank P. Boulenc at STMicroelectronics, Crolles, for theTCAD model information.

REFERENCES

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