A Single-Chip 900-MHz Spread-Spectrum Wireless Transceiver ...homepages.cae.wisc.edu/~ece734/references/00663558.pdf · Fig. 6. Measured log conformity at RSSI output over 80-dB input

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 4, APRIL 1998 535

A Single-Chip 900-MHz Spread-SpectrumWireless Transceiver in 1-m

CMOS—Part II: Receiver DesignAhmadreza Rofougaran, Glenn Chang,Student Member, IEEE, Jacob J. Rael,Student Member, IEEE, James

Y.-C. Chang, Maryam Rofougaran,Member, IEEE, Paul J. Chang, Masoud Djafari, Jonathan Min,Edward W. Roth, Asad A. Abidi,Fellow, IEEE, and Henry Samueli,Member, IEEE

Abstract—A 900-MHz direct-conversion receiver to detect afrequency-hopped carrier with frequency shift keying (FSK)modulation at 160 kb/s is integrated on the same chip as thetransmitter. The receiver combines a low-noise amplifier withdownconversion mixers and low-pass channel-select filters inquadrature channels. A digital correlating detector makes thedata decisions. The received signal is dehopped when it is down-converted. The cascade noise figure is 8.6 dB, and the cascadeIIP3 is �8.3 dBm. In active mode, the receiver takes 120 mAfrom 3 V.

I. INTRODUCTION AND SPECIFICATIONS

T HIS paper deals with the receiver section of an integratedfrequency-hopped spread-spectrum transceiver operating

in the 902–928 MHz industrial, scientific, and medical (ISM)band (Fig. 1). The transmitter section is described in thepreceding companion paper [1].

The receiver is designed for quarternary frequency-shiftkeying (4-FSK) modulation, communicating a maximum datarate of 160 kb/s at a symbol rate of 80 kHz. The peak signalenergy in the modulated baseband spectrum concentrates in thefrequency range of 80–160 kHz, while relatively little energylies at dc (Fig. 2). This enables use of a direct-conversion orzero-IF receiver [2]. This architecture eliminates all IF band-pass filters and therefore is the best candidate to implement afully integrated single-chip receiver. With reference to Fig. 1,an LNA drives twomixers, which downconvert the receivedsignal with quadrature phases of an LO synchronized tohopin frequencywith the same code as the sought user. The agilefrequency synthesizer in the transmitter section synthesizesthis hopping LO. Thus, this receiver downconvertsanddehopsthe received spread-spectrum signal in one set of mixers.An integratedlow-pass filterselects the desired channel, andfollowing that, alimiting amplifierboosts the received signal todrive a correlating digital detector. The receiver detects inputsignals as low as 1 V.

Manuscript received September 3, 1997; revised January 5, 1998.The authors are with the Integrated Circuits & Systems Laboratory, Elec-

trical Engineering Department, University of California, Los Angeles, CA90095-1594 USA.

Publisher Item Identifier S 0018-9200(98)02398-1.

Fig. 1. Block diagram of receiver section.

Fig. 2. Spectrum of 4-FSK modulation by pseudorandom data.

II. CIRCUIT BLOCKS

The various blocks of the receiver are described in depthin the following sections. In those cases where a prior journalpublication exists describes a certain block, the text here isbrief and summarizes only the salient features.

A. Low-Noise Amplifier and Mixers

The fully differential LNA consists of two common-gateFET’s with 30-nH on-chip inductor loads (Fig. 3). It has beenshown elsewhere [3] that when a 3-dB LNA noise figureis acceptable, the common-gate topology very convenientlyprovides a 50- input match without resorting to inductor

0018–9200/98$10.00 1998 IEEE

536 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 4, APRIL 1998

Fig. 3. Differential LNA, downconversion mixer, and mixer buffer.

degeneration [4]. The ratio of the load inductor impedance at900 MHz to 50 sets the LNA gain. If the loss in the inductor

is modeled by a series resistor and the capacitancedefines the tuned circuit at the drain, then it may be shown[3] that the voltage gain is

Gain (1)

where is the FET unity current-gain radian frequency.Thus, using large metal-2 spiral inductors whose

nH [3], and with the NMOS biased at of0.35 V where is about 4 GHz [3], a voltage gain of 20 dBcentered at 915 MHz is obtained. This is the voltage gain fromthe LNA input terminals when it is exactly matched to a 50-source,1 to the load inductors driving an on-chip capacitiveload. Unlike standalone LNA’s, this circuit finally drives acapacitive load,not 50

A dc feedback loop sets the common-gate bias voltageVG, and VC adjusts the LNA output common-mode level toenable direct coupling to the and mixers. Each double-balanced mixer consists of a linear transconductor, comprisingtwo common-source FET’s, followed by four commutatingswitch FET’s driving 1-k polysilicon resistor loads (Fig. 3).The PFET pull-up current sources are of large gate area tolower their input-referred flicker noise, which directly adds tothe RF input signal downconverted to zero IF. The voltageconversion gain of the mixer is nominally 0 dB.

The cascade double-sideband noise figure2 of the LNA andone mixer is 3 dB referred to the 50-input source. The totalinput IP3 is about 8 dBm. This LNA drains 11 mA from a3-V supply, and each mixer drains 2.5 mA.

B. Channel-Select Filter

The preselect filter after the antenna passes the entire ISMband (Fig. 1), which is amplified in the broadly tuned LNAand downconverted and dehopped in the mixers. A switched-capacitor (SC) filter [5] then selects the desired user’s channel,which is now centered at 0 Hz (Fig. 4). The specificationson channel-selection require a low-pass filter with a passband

1In the case of an imperfect match, the LNA insertion gain is defined asthe ratio of the signal voltage on the load inductor to half the voltage of the50- source driving the LNA input.

2DSB NF is the appropriate measure here because a direct conversionreceiver keeps the images of signal and noise separate in quadrature channels.See [3] for a more detailed justification.

Fig. 4. Block diagram of SC channel-select filter in context of receiverfront-end.

edge at 230 kHz, a stopband edge at 320 kHz, and a stopbandloss of 50 dB to suppress the adjacent channel [5]. This isrealized in a sixth-order elliptic filter, implemented here asa cascade of three biquadratic sections (Fig. 4). The clockfrequency of the elliptic filter is limited to 14.3 MHz so thatthe spread in values of the filter capacitor does not growprohibitively. A prefilter clocked at a higher rate must nowreject the channels at multiples of 14.3 MHz away fromthe desired channel, which will fall in the images of theelliptic filter’s passband. A second-order Butterworth low-passclocked at 57.2 MHz ( 4 14.3 MHz) is used as thisprefilter. In addition, the off-chip RF filter attenuates non-ISMband signals 57 MHz away from the desired channel by atleast 15 dB. Therefore, the cascade response of the RF filter,SC prefilter, and SC main filter is to provide a stopband lossof at least 52 dB, typically 65 dB, extending from 320 kHzto well beyond 60 MHz.

The active filter very often contributes the largest noise of allthe building blocks in an integrated direct-conversion receiver.This filter’s input-referred noise is lowered by strategicallydistributing gain in the first few biquads. Although gain inthe filter compromises its input IP3 (IIP3) because a smallerinput signal now saturates the last op amp in the cascade,it does lower noise. With a total voltage gain of 16(24dB) distributed as shown in Fig. 4, the filter’s input-referredvoltage noise spectral density is 40 nVHz The balancedfilter uses a total capacitance of 200 pF and drains 7 mA from3 V. For two input tones located 1 MHz in the stopband whoseintermodulation product falls in the filter passband, the IIP3is 7 V (rms).

The SC filter samples the output of the mixer buffer (Fig. 3),whose role is discussed in a later section. The on-chip 30-pFcapacitor differentially connected at the buffer output limitsthe noise bandwidth to about 1 MHz. Otherwise, widebandnoise at the mixer output will alias into the filter passbandafter sampling and raise the noise figure of the filter as wellas the receiver.

C. Limiting Amplifier and RSSI

The filter output is directly connected to a limiting amplifier.This circuit also synthesizes a logarithmic measure of theinput voltage [6]. The amplifier consists of a direct-coupledcascade of seven differential pairs, each with a voltage gain of12 dB (Fig. 5). The 84-dB gain is so large that in the absence

ROFOUGARAN et al.: SINGLE-CHIP 900-MHz SPREAD-SPECTRUM WIRELESS TRANSCEIVER IN 1-m CMOS—PART II 537

Fig. 5. Limiting amplifier and logarithmic received signal-strength indicator(RSSI). Individual circuits shown for input stage, seven core amplifiers incascade, and rectifier.

Fig. 6. Measured log conformity at RSSI output over 80-dB input signalrange and variation in group delay through limiting amplifier.

of an input signal, the amplifier output limits on its ownnoise. Full-wave rectifiers, each consisting of two unbalanceddifferential pairs [7] with a unidirectional current output, tapeach differential pair, and their outputs are summed in a 10-kon-chip resistor. This architecture implements the successive-detection algorithm [8], and the resulting near-logarithmicoutput voltage is used to indicate the strength of the receivedsignal (RSSI). Measurements on a standalone prototype verifythat over the 80-dB range of input signal, the RSSI outputconforms within 1 dB to an ideal logarithm (Fig. 6).

In a dc-coupled receiver, offsets, which are typically tensof millivolts, will overwhelm the received signal, which isonly fractions of a millivolt in the baseband section, and pinthe limiting amplifier output to one extreme or the other.DC feedback is therefore mandatory for proper operation.The feedback loop around this limiting amplifier suppressesoffset added by the mixer or filter, or which appears withinthe stages of the limiting amplifier. A low-pass filter in thefeedback loop measures the average value of the differentiallimited output, and a differencing stage subtracts this off fromthe differential input (Fig. 5). Although the limiting amplifieris nonlinear, the action of the dc suppressing feedback may

be roughly understood with a superposition argument. Thenegative feedback loop gain is 84 dB at dc, and the dominantpole in this loop, set by the off-chip and , is chosento roll off the loop gain to below 0 dB at the lowestsignalfrequency, 80 kHz. Suppose first that a small input signal isapplied to the limiting amplifier, such that all the limitingamplifier stages operate in the linear region. Then the linearfeedback loop suppresses the dc component by 84 dB withrespect to the signal, irrespective of dc accompanying theinput signal or arising within the limiting amplifier. If thesignal is larger, it will drive the later stages of the amplifierinto clipping. At first sight it may seem that this lowers therelative suppression of the dc offset, because fewer stages inthe cascade contribute linear amplification. However, now theoffset manifests itself in theduty cycleof the clipped outputsignal. In fact, the tendency of the loop to suppress dc offsetremains almost unchanged. It is found by simulation that theoutput duty cyclewith feedbackremains the same, whether theinput is a sinewave of amplitude 100V with an added offsetof 100 mV, or it is 1 V with the same offset.

A deviation from 50% in the duty cycle of the limiteroutput adversely affects the performance of the following datadetector. It lowers the correlation output from the detectorover a symbol period, as described in greater detail in thenext section, and thus the output SNR. One way to counteractthis is by using a large clipping level, because now toovercome a given offset, feedback imbalances the output dutycycle less. Clipping levels of 1 V are used here. Feedbackdoes not affect high frequency noise on the input signal,which randomly modulates the zero crossings of the clippedoutput.

The common-source differential differencing stage at thelimiting amplifier input (Fig. 5) can handle input offsets oflarger than 1 V. If such a large offset cuts off one inputFET, the other FET converts the (now single-ended) inputsignal to a differential swing at the loads plus an offset, thelimiting amplifier senses this, and feedback counteracts theoffset through the other half of the differencing input stage.

The limiting amplifier’s delay changes with input level(Fig. 6). At small inputs, the slope of the small-signal phaseversus frequency sets the group delay. At larger inputs, thelast stages in the cascade will slew-rate limit and prolongthe circuit delay. When a still larger signal drives all stagesinto slew-rate limiting, the delay is maximum. The groupdelay changes by 90 ns over the 80-dB logarithmic rangeof the circuit, with the greatest rate of change at smallinputs. The changing multipath interference pattern of a mo-bile user, or shadowing and fading, all cause the receivedsignal strength to fluctuate. The group delay characteristicwill convert these amplitude variations into phase fluctuations(AM-to-PM conversion) and potentially degrade the SNR inthe phase-sensitive FSK detector. Simulations show that evenin the unlikely event of a sudden drop of 80 dB in the receivedsignal strength, the AM-to-PM conversion in the limitingamplifier is so small that the detector SNR falls by only about0.2 dB.

The limiting amplifier is designed with a relatively widesmall-signal bandwidth of 10 MHz. As the preceding channel-


Fig. 7. Digital correlating detector for 4-FSK.

select filter has suppressed adjacent channels by morethan 52 dB beyond 320 kHz, the limiting amplifier’s ownnoise and wideband noise at the filter output occupy theexcess bandwidth from 320 kHz to 10 MHz. The extranoise is removed by the correlating detector, which is nowdescribed.

D. Correlating FSK Detector

In principle, FSK data may be fully recovered only frominformation on the sequence of zero-crossings of the modu-lated carrier. Each limiting amplifier in the quadrature channelsof this receiver drives the downconverted signal to binaryamplitude levels, but it preserves the information on zerocrossings. Following the limiting amplifier, a frequency dis-criminator or correlating detector can recover the modulation.The latter bases decisions by correlating the received signalwith the entire set of modulation frequencies (here), and in the sense that it minimizes the noise bandwidth,this is the optimal detector [9]. Because it operates on the 1-brepresentation of the input signal emerging from the limitingamplifier, the correlating detector is naturally implementedhere as a digital circuit [10] (Fig. 7). Its main purpose isto accurately locate the zero crossings of the downconvertedreceived waveform, so it clocks at a large multiple (88) ofthe symbol rate (80 kHz). Thus, the received signal is finelyquantized in time (88 levels) but only coarsely quantized inamplitude (two levels). At every clock cycle, an accumulator(digital integrator) increments or decrements the correlationbetween each 1-b limiting amplifier output and each of thetwo quadrature phases of locally generated noise-free 80 and160 kHz square waves. The detector estimates the correlationenergy from pairwise sums of the absolute values of the foursets of correlations, and at the end of each symbol periodit makes a one-of-four decision. Thus, it seeks the closestmatch between the received signal and the four possible FSKoffsets. The oversampling factor locates the zero-crossinginstant to within a quantization error of about 1% of a symbolperiod.

Correlation with a noiseless signal of periodcorresponds,in the frequency domain, to bandpass filtering around thefrequency Thus, the four correlators are bandpass fil-ters centered, respectively, at and(Fig. 8). Their 3-dB passband is inversely proportional to thecorrelation interval, here one symbol period. The bandpass

Fig. 8. Measured frequency response of correlating detector at outputsof integrate-and-dump blocks sensing+80 kHz and+160 kHz. Identicalresponses are obtained at�80 kHz and�160 kHz outputs.

response also has sidelobes, but the largest lies 10 dB belowthe main lobe, and as far as noise is concerned, the side-lobes may be ignored. However, these sidelobes have a moreserious effect on signals. Consider, for example, the case ofa conventionally modulated 4-FSK applied to this detector.The frequency offsets in this case are atand chosen in this way because they are all equallyspaced apart on the frequency axis and symmetrical around thecarrier frequency. However, after limiting, the fifth harmonicof, say, will lie in the largest sidelobe of the correlatorcentered at This will induce a spurious response in the

correlator, when in fact only the correlator shouldrespond. This degrades the decision SNR at the output. Theoffsets of and in our system werechosen to avoid this problem, because now at the frequencywhere the response of one correlator is at a peak, the sidelobesof all the others are at a null. This minimizes the undesirableinteraction.

A standalone prototype of the correlating detector was firstimplemented. The circuit includes digital phase-locked loopsto track symbol timing and frequency hopping. The operationof this digital baseband subsystem is described elsewhere [10].The total power dissipation of the digital blocks at 3 V is4 mW. This circuit takes as its input a 1-b estimate of thereceived signal from the two limiting amplifier outputs, and itconstructs 8-b correlation coefficients over each symbol whichare used for all the other functions. No A/D converter isrequired. However, because of the 1-b approximation, thereis an “implementation loss” in detection sensitivity of 1.5dB from ideal [10]. This implementation loss degrades thesensitivity curve of thedetector, specified as bit-error rateversus SNR. It does not affect the noise figure of the receiver,which specifies all the blocks up to, but excluding, the detector.

In summary, there are three sets of progressively narrowerfilters in this receiver (Fig. 9). The digital correlating detectorimplements, in effect, the narrowest bandpass filter, and thisdetermines the overall receiver noise bandwidth.


Fig. 9. Progressive filtering scheme in receiver.

III. I SSUES OFCASCADING AND MONOLITHIC INTEGRATION

Moving up one level higher than the receiver buildingblocks in the design hierarchy, the optimization of sensitivityand dynamic range in thecascadeof these blocks is nowconsidered. Two definitions of dynamic range (Fig. 10) applyto the radio receiver:spurious-free dynamic range(SFDR),the two-tone in-band signal level above noise which createsintermodulation products equal to the accompanying noise[11]; and theblocking dynamic range(BDR), the ratio ofthe 1-dB gain compression point to the noise [12], [13]. Itshould be pointed out that SFDR as defined in some texts[14] subtracts off the desired minimum signal-to-noise ratiofrom the above definition to take into account the demodulatorfollowing the receiver; however, this definition does not seemto be widely used in the literature, and it is not used here. BDRis a measure of resilience to a large out-of-band blocking signalwhich drives a receiver into compression, thereby desensitizingit to a small desired signal [12]. The two are related as follows(Fig. 10):

dB IIP3 dB

Noise Floor dBm/Hz NF BW

SFDR IIP3 Noise Floor

BDR dB Noise Floor (2)

where dB is the input power (referred to 50) whichcompresses the gain of a block by 1 dB, and BW is the netreceiver noise bandwidth. NF is the receiver input noise figurereferred to a 50- source resistor, which at 300 K generatesa maximum available noise power density of174 dBm/Hz.It is important to note that the first approximation in the setof equations above, relating dB to IIP3, usually holdsin a circuit with a single-point third-order nonlinearity, that is,when the dominant compressive nonlinearity arises only at onenode in an otherwise linear circuit. MOSFET’s are attractivein the RF context because they are only weakly nonlinear,but this also means that several nodes in a CMOS circuit maycontribute comparable amounts of nonlinearity. Now it is quitepossible that distortion at one node sets the (extrapolated) IP3,while clipping at another sets the dB. In this case, theapproximate 10-dB relation may not hold.

The overall receiver dynamic range derives from the cas-cade noise figure and intercept point of the individual buildingblocks. The correct calculation of the noise figure must take

Fig. 10. Definition of spurious-free dynamic range and blocking dynamicrange.

into account the greatly different impedance levels in anintegrated receiver. Most on-chip building blocks have a high,mainly capacitive, input impedance, while at the off-chipantenna interface, the nominal receiver input impedance is 50

The cascade noise figure is found by referring all circuitnoise sources to the noise voltage in a reference 50-off-chip source resistor (Fig. 11). Equivalent noise sourcesat the inputs of downstream blocks must be divided by theproper gain. The noise source directly adds to . Onthe other hand, the equivalent input noise voltageof block

following the LNA contributes a voltageto the noise figure calculation, where is the

voltage gain of block measured between its input and outputports, and the is the incident fraction of which definesthe LNA insertion gain . This method of calculation holdseven when the LNA is imperfectly matched, see footnote 1.The various noise contributions add as the root-mean square,and with reference to Fig. 11, the cascade noise figure is

NF

(3)

Cascade intercept point is calculated using well-knownformulas [15]; again with reference to Fig. 11

IIP3IIP3 IIP3 IIP3

(4)


Fig. 11. Various noise sources in cascade of integrated receiver blocks.

where IIP3 is the third-order intercept of blockreferred tothis block’s input and measured in terms of the input signalpower dissipated in a reference 50-resistor. The relationshipbetween intercept voltage in dBVrms and this power in dBmis dBVrms dBm 13 dB.

In practice, when individually designed building blocks areconnected together in an integrated receiver, the required totalperformance is seldom achieved at first. Usually the cascadedynamic range is not good enough. Then, to improve thedynamic range, either the blocks are redesigned or intermediategain stages are strategically inserted. Take, for example, the SCchannel-select filter used in this receiver. When it is precededonly by the 20-dB voltage conversion gain of the LNA andmixer, the filter’s 40 nV Hz input noise alone implies areceiver NF of 17 dB (calculated by (3) above). This is anunacceptably large receiver NF. The filter’s own noise can onlybe lowered at a disproportionate (quadratic) expense of currentdrain and chip area. A better way to lower the contributionof filter noise is to insert an intermediate baseband amplifierafter the downconversion mixer. The mixer buffer used here(Fig. 3) consists of two common-source PFET’s acting as alinear transconductor and using polysilicon resistor loads toimprove linearity and lower flicker noise.

It is prudent to allot gain sparingly in any receiver priorto channel-select filtering, otherwise amplified but unfilteredblocking signals may create large in-band intermod products.However, this gain should be large enough to enable thedesired minimum signal to overcome noise of downstreamblocks.3 These tradeoffs are illustrated in Fig. 12, which plotsthis receiver’s cascade noise figure, input intercept point, andSFDR versus buffer gain. It is assumed that the buffer’sload resistor sets the gain, and that the buffer’s input noiseand output clipping level remain the same at all gains. Withtoo much buffer gain, the receiver noise figure flattens outto a constant value set by the LNA, but the intercept pointfalls proportionally. Thus, the overall SFDR suffers. If widedynamic range is a priority, as it is in this spread-spectrumreceiver, then with a buffer gain of 14 dB, the SFDR iswithin 1 dB of the maximum, and the NF is 8 dB. Thesevalues are finally used. However, it is interesting to considerother possible tradeoffs with this flexible buffer, whose gain isadjusted simply by choosing the load resistors. For instance,by choosing a buffer gain of 22 dB, the receiver NF may belowered to 5 dB, now with an IIP3 of 16 dBm. These two

3Adding gain in active building blocks of a receiver only lowers the noisecontributed by blocks subsequent to the LNA to the cascade NF. It does notlower the equivalent input noise of the LNA itself, which is normally set bythe LNA input stage and the impedance matching network.

Fig. 12. Receiver NF, IP3, and SFDR versus mixer buffer gain. Gain usedin this receiver is highlighted.

Fig. 13. Signal-level diagram in receiver.

figures-of-merit are sufficient to meet the specifications on aGSM receiver.

A signal-level diagram (Fig. 13) best illustrates the cascadeeffect of the various blocks on the entire receiver. Note thatas the signal advances up the cascade, it can tolerate blockswith higher input noise, but up to and including the channel-select filter each block must also be capable of handling aprogressively larger signal before the onset of clipping. Toenable comparison with data reported in other publications onbuilding blocks, this level diagram specifies the input noisevoltage of the blocks, as measured on standalone prototypes,as the power spectral density that voltage would dissipate ina hypothetical 50- reference resistor. The input interceptpoint is specified in dBm under similar conditions. If needbe, these numbers may be converted into rms volts by usingthe equivalence: dBVrms dBm 13 dB.

A direct-conversion receiver must represent the downcon-verted signal in vector format, to distinguish between thepositive and negative frequencies in the selected channelspectrum, which is centered on zero-IF [2]. Following RFamplification in the LNA, the downconverted signal bifurcatesinto two quadrature channels (Fig. 1). The noise of the twomixers and subsequent pairs of blocks in the two basebandchannels is uncorrelated, and each channel’s noise adds to therespectivequadraturecomponent of the downconverted signalpassing through that channel. Now, if the output voltages at thetwo channels add at the detector, then the rmsnoisecontributedby the mixers and subsequent blocks is 3 dB larger than the


noise in one channel alone. However, the quadrature (vector)components of thesignalalso sum to a 3-dB larger value thanthe signal in one channel. Thus, the combined SNR is the sameat the detector input as it is at the output of only one channel.For the purposes of calculating cascade noise figure, therefore,the noise contribution of each building block is accounted foronly once. The noise of the entire receiver, as referred to a50- source resistor, may be predicted by using the individualnumbers for noise and gain given in Fig. 13, translating themto noise voltage, and then using the formula in (3)

nV Hz

where the first term arises from the input-referred LNA noisevoltage, the second from the mixer and buffer, and the thirdfrom the filter. Finally, this induces a DSB noise figure of 8.6dB in 50 As expected, it is the active filter noise, the thirdterm in the sum above, which dominates: its noise is equal tothe combined contribution of the LNA and mixer.

Similarly, the cascade IIP3 is calculated for the entirereceiver using measured intercept points for the individualblocks and (5). It is found that the mixer with its buffer limitsthe receiver’s cascade third-order intercept point to8.5 dBm.

Second-order distortion in the baseband circuits of a direct-conversion receiver, where the signal is largest, detects theenvelope of out-of-band amplitude-modulated interferers tocreate spurious tones in the filter passband [2]. This is specifiedby the extrapolated second-order intercept point, IIP2. Ideally,the IIP2 is infinite in a fully balanced receiver, but becauseof element mismatches it is finite in practice. Systematicmismatches arise from asymmetries in layout, and randommismatches from statistical fluctuations in FET’s and passivecomponents. Cumulative dc offsets in circuits with a balancedtopology imbalance the differential signal handling. Thesevarious effects cannot be easily predicted. The IIP2 is foundby measurements on the finished receiver.

All calculations of receiver SFDR use a noise bandwidthof 80 kHz, set by the one bandpass lobe in the correlatingdetector’s frequency response (Fig. 8). The cascade SFDRis about 76 dB, limited by the 73 dB SFDR of the filter(Fig. 13). This is representative of a good receiver. It is 18dB lower than the LNA SFDR and 13 dB lower than theSFDR of the standalone front-end, comprising the LNA andmixer [3]. This large difference in dynamic range between thefront-end building blocks and the complete receiver cautionsagainst simple extrapolation of the latter’s performance frommeasurements on the former. It also warns the newcomer towireless receiver design that the apparently mundane basebandbuilding blocks must be designed with great care if they arenot to seriously limit the total receiver dynamic range.

IV. EXPERIMENTAL RESULTS

The predictions of the total receiver performance are nowexperimentally verified. Strictly speaking, the total perfor-mance of any receiver includes all the blocks up to, but

excluding, the data detector. Whereas specifications such asnoise figure and intercept point are a property of the receivercircuits only, and are independent of channel bandwidth orthe modulation scheme, the detector or demodulator is specificto both. Accordingly, this receiver is characterized up to thelimiting amplifier output. The limiter is not a detector, merely abroadband nonlinear amplifier which replaces the AGC whichwould be found in a linear receiver.

Noise figure and intercept points cannot be directly mea-sured from the nonlinear output of the limiting amplifier, butmust be deduced. This is because with multiple input signals,the limiting amplifier limits on the largest, the well-known“capture effect” in FM. The consequences are somewhatunfamiliar. For instance, suppose the input to the limiter isa large signal and small noise. The limiter captures on thesignal, which drives its output to the fixed clipping level, andnoise randomly modulates the zero crossings of the signal.When the limiter input SNR is 0 dB or less, the output SNRas measured on a spectrum analyzer is the same as at the input[16].4 This means that as the signal amplitude is pegged onthe output spectrum—at 9 dBm in this circuit—the noisefloor adjusts itself to the correct SNR. If the input signal levelrises but the accompanying input noise remains constant, theopposite trend is seen at the limiter output, that is, the signalremains pegged but the noise floor drops to reproduce the inputSNR. The same behavior would be seen in an automatic gaincontrol (AGC) system, which automatically adjusts its gain tokeep the output signal always at a fixed prescribed level.

The receiver noise figure is deduced from the limiter outputspectrum by applying a small, known RF input signal. Inresponse to a 1.2-V rms RF input to the receiver offset by 80kHz from the fixed LO. Fig. 14 shows the measured limiteroutput spectrum. Also shown superimposed on this plot is themeasured frequency response of the 80-kHz bandpass lobe ofthe correlating detector which follows the limiting amplifier.The limiter output captures on the input signal, downconvertedto 80 kHz. In this case, the rms input noise to the limitingamplifier over its 10-MHz bandwidth is almost equal to theinput signal; that is, the limiter input SNR dB. Thus, asmentioned above, the limiter input and output SNR are equal,and as the receiver is linear prior to the limiting amplifier, thismust also be the net SNR referred to the receiver input.

The limiter output noise is almost flat at a level of51dBm/Hz across the detector passband centered at 80 kHz, or

60 dBc/Hz relative to the limited signal tone of9 dBm.Referred to the receiver input where the signal level is105.4dBm (1.2 V), this corresponds to a noise spectral density of

165.4 dBm/Hz. Therefore, the receiver noise figure at theRF input frequency, relative to the incident noise density of

174 dBm/Hz from 50 is 8.6 dB.The noise spectrum at the limiter output clearly follows

the low-pass characteristic of the channel-select filter. Thenoticeable peak in the noise spectrum at 230 kHz, slightly pastthe filter’s passband edge, can only be explained if it originatesin the filter’s high- biquad [5], and this independently verifiesthat the filter is indeed the dominant source of receiver noise.

4When the input SNR� 1; the aforementioned capture effect improvesthe limiter output SNR by 3 dB [16].


(a)

(b)

Fig. 14. Limiting amplifier output spectrum measured with (a) single-toneRF input and (b) zero input. The noise spectral density is in dBm/Hz. The80-kHz bandpass response of the following correlating detector is shownsuperimposed in both cases. The receiver responds only to the signal andnoise lying in the detector passband.

Below 30 kHz, the receiver noise rises because of flicker noisein the baseband circuits. However, the flicker noise corner liesbelow the lower cutoff of the correlating detector and will berejected.

The dc nulling loop very effectively suppressesstatic offsetsin the receiver. However, it cannot easily suppressdynamicoffsetswhich appear in every direct-conversion receiver andare of practical concern [2]. Due to various parasitic reso-nances, the offset produced by self-downconversion of theLO inevitably changes with the LO frequency [3]. As theLO frequency hops through a pseudonoise (PN) code in thisreceiver, the offset also cycles through a sequence of randomvalues creating a fixed-pattern noise at the mixer output.If the frequency spectrum of this pattern noise lies in thereceiver passband, it will raise the noise floor and degradesensitivity. Measurements show just this effect: with the LOhopping, the low frequency spectrum of the noise floor rises(Fig. 14). Fortunately, when the LO hops through a 54-longPN sequence at 20 kHz, the noise spectrum due to the fixed-pattern only risesbelow the lower cutoff of the correlatingdetector’s bandpass response, and this is again rejected inthe detector. Therefore, we conclude thatneither flicker noisein the baseband sectionnor dynamic offsetsdegrade thesensitivity of this direct-conversion receiver. A curve of SNversus noise at the limiter output measured across 80 dB ofRF input level (Fig. 15) summarizes the overall sensitivity anddynamic range.

Fig. 15. Measured S+ N versus noise at the limiter output, across 80 dBof input level.

Three factors set the minimum detectable signal (MDS):the receiver noise figure, the overall system noise bandwidth,and the signal-to-noise ratio (SNR ) required at the detectorinput for an acceptable bit-error rate, usually 10for avoiceband system. So far, only the noise figure has beendiscussed. One bandpass lobe of the detector determines thenoise bandwidth of the entire receiver, and this is roughlyabout 80 kHz wide (the noise bandwidth is somewhat largerthan the 3-dB bandwidth shown in Fig. 8). Regarding theminimum SNR, first recall that each detected symbol in 4-FSKcarries two data bits. Therefore, the signal energy must behalved or the noise power doubled for the per-bit signal-to-noise, referred to in textbooks as the ratio. In eithercase, this adds 3 dB to the MDS. Theoretically, for 10BERusing 4-FSK, the ratio is about 9.5 dB [9]. Thus, takinginto account the referred-input noise floor of the receiver, the3-dB adjustment for 4-FSK, the noise bandwidth, the minimumSNR, and the 1.5-dB implementation loss of the detector, wearrive at

MDS dBm/Hz dB Hz

dB dB dBm.

This corresponds to a receiver input voltage of 1.7V rmsfrom a 50- source. One additional source of improvementremains. Convolutional coding of data improves the receiversensitivity conservatively, say, by 3 dB, and then the MDSdrops to 1.2 V rms.

The third-order and second-order intercept points for thelinear portion of the receiver, that is, up to and includingthe channel-select filter, are deduced at the limiter outputwith a three-tonetest. A reference RF tone of a fixed smallamplitude is applied so that it downconverts to a frequency

in the passbandof the channel-select filter. Two otherRF tones, simulating near-channel interferers, are also appliedso that they downconvert into the filterstopband, but theirfrequency difference is such that they create intermodulation ata frequency in the passband. The latter RF inputs areswept together in amplitude. The limiting amplifier captureson the larger of the two baseband signals appearing atand . The relative levels of these frequencies at the limiter


(a)

(b)

Fig. 16. Third-order intermodulation measurement. (a) Three input tone testconditions and (b) components of the limiter output spectrum versus interfererlevel.

output are measured on a spectrum analyzer and plotted versusthe swept input amplitude. As expected, when the limiter iscapturing on the fixed signal at , the output at grows withthe third power of amplitude when it is due to third-orderintermodulation, and with the second power when second-order distortion is responsible (Figs. 16 and 17).

The crossover point where the limiter outputs at andare equal (Figs. 16 and 17) contains valuable information.

Here, the input levels of the interferers and reference tone,respectively, define abscissas with equal ordinates on the twolines comprising the respective intermodulation plot (Fig. 18).Straight lines of the appropriate slope are passed through thesecoordinates and extrapolated to find the intercept point. Thus,a total receiver IIP3 of 8.3 dBm and an IIP2 of 24 dBmare deduced.

As independent verification, the receiver IIP3 is directlymeasured at a test pad brought out at the filter input (Fig. 18).This IIP3 of 6 dBm, when cascaded using (4) with the30dBm IIP3 of the filter, gives the same total receiver IIP3.Similarly, the IIP2 of the standalone active filter was measuredto be 60 dBm [5]. When divided by the 34 dB gain precedingthis in the receiver, an IIP2 of 26 dBm is expected, whichis almost exactly equal to the measured value.

Spurious tones in the receiver LO are measured by syn-thesizing a constant frequency in the direct-digital frequencysynthesizer (DDFS) [1], finding the RF input level at theLO frequency which produces a certain SNR at the limiter,and then for various frequency offsets, finding the input level

(a)

(b)

Fig. 17. Second-order intermodulation measurement. (a) Three input tonetest conditions and (b) components of the limiter output spectrum versusinterferer level.

which produces the same SNR. If there are no spurs in theLO (and zero phase noise), the receiver will respond to an RFinput only at the LO frequency but to no other RF input. Theplot in Fig. 19 shows the relative RF input signals required atvarious offset frequencies from the LO which induce the sameSNR as an input at the LO frequency assigned a referencelevel of 0 dB. No RF filter is used in this measurement.The receiver can stand off very large levels everywhere,except those frequencies where the agile frequency synthesizerproduces significant spurious tones. Owing to inadequate gainin the frequency synthesizer, the DAC after the DDFS had tobe driven at 2 V full-scale, twice the designed value, to fullyswitch the receiver mixers. As a result, the spurious levels arealmost 20 dB higher than at the designed value of 1 V. Thisproblem is discussed at some length in the companion paper[1]. Nevertheless, in theworst case, which is at an offset of10 MHz, this receiver can stand off an interferer 43 dB largerthan the desired signal. At most other frequencies, we havetested standoff of greater than 80 dB. Again, in a redesign wewould expect the worst-case standoff level to improve by 20dB. There are other mitigating conditions here. Although in anarrowband receiver this might be considered a low immunityto the interferer 10 MHz away, the situation is different ina spread-spectrum system. First, it is generally difficult toachieve the low levels of phase noise and spurious tones in anagile frequency synthesizer that are typical in the stationaryLO of a narrowband receiver. Second, averaging in a spread-spectrum system improves the immunity to interferers. For


(a)

(b)

(c)

Fig. 18. Deducing (a) third- and (b) second-order intercept points from thelimiter outputs. (c) Measured IP3 at filter input, as independent verificationof receiver IP3.

example, if a large LO spur on a certain hop downconvertsa strong narrowband signal 10 MHz away, located, say, justoutside the ISM band, then at other hops this signal will nolonger lie on the same large LO spur. A receiver which de-interleaves blocks of data across many hops in effect averagesout the deleterious effect of one bad “hit” across all thehops.

The accumulated offset in the direct-coupled baseband sec-tions of the receiver up to the limiter is deduced from the dcvoltage which develops in the off-chip feedback loop. Thisoffset is about 80 mV. DC feedback in the limiter respondsto this by creating a 4% imbalance in the output duty cycle,with a negligible loss in detector SNR.

Fig. 19. Spurious tones at receiver LO, measured by sensitivity to down-conversion. The arrows indicates the relative height of a signal at any givenfrequency offset, which induces an output SNR equal to the tuned channel atthe LO frequency, with reference level of 0 dB.

Fig. 20. Die photo, with building blocks annotated. Note the special RFinput and output pads inside the ring of conventional pads.

V. PHYSICAL ASSEMBLY OF TRANSCEIVER IC

Several graduate student circuit designers produced thetransceiver building blocks and their respective chip layouts.These were assembled onto a common substrate (Fig. 20)without much effort at overall compaction. The transmitterblocks occupy two-thirds of the horizontal chip dimension, thereceiver blocks the remaining one-third. Twelve square spiralinductors, either 30 or 50 nH in value, are seen on the chip,surrounded by the via holes through which the etchant attacksthe fabricated wafer. The circuit is implemented in a double-metal, single-poly 1-m N-well epi-CMOS process offered byMOSIS (CMOS34/AMOSI).

The active chip area of 10.5 7.3 mm is distributedamong the various blocks in the following order (Fig. 21).The four largest blocks are the channel-select filter (used onlyfor receive), power amplifier buffer (transmit/receive), twodigital/analog converters (DAC’s) (transmit/receive), and LO(transmit/receive). The DAC’s consume a large area becauseeach DAC cell is liberally spaced from its neighbor to lowerthe fringing capacitance between cells to a few femtofarads


(a) (b)

Fig. 21. Distribution of (a) active area and (b) current consumption amongthe various building blocks.

(see [1] for details of the DAC design). In all other blocks,the passive components take up the greatest area. In fact, the12 inductors consume 40% of the total active area, and the 400pF capacitors in the two channels of balanced filters consume15%. In total, the passives consume more than half the chiparea.

The total current distribution is also broken out among thevarious blocks (Fig. 21). The PA at maximum output consumesthe largest current (20 mA), and the digital circuits comprisingthe DDFS, when clocked at 100 MHz, drain almost the samedynamic current (18 mA). All other blocks take roughly 10mA each. The baseband buffers after the DAC’s take 20 mA,and the RF buffers after the frequency synthesizer drain 25mA in transmit mode, 20 mA in receive mode. This meansthat the buffer currents account for nearly 45% of the totalcurrent in transmit mode and 35% during receive mode. TheDAC buffers are designed to deliver a large sinusoidal voltage(0.7 V ptp diff) with very low distortion to a heavy load,consisting of the upconversion mixers, the polyphase filters,and the input capacitance of the RF buffers. In turn, theseRF buffers must drive 1.7-V ptp voltages at 900 MHz intothe PA input and into the receive mixers. This shows that amonolithic transceiver is not (readily) exempt from the largepower consumption which is associated with buffers drivingdiscrete components in a board-level transceiver.

Cavities are etched under the inductors on the fabricateddie (Fig. 22) with a post-process etch in our lab. The siliconsurface of each smoothly etched hemisphere is a miniatureconcave mirror, which reflects light passing through the trans-parent oxy-nitride dielectric to give the optical illusion ofa shiny ball lying on top of the inductor. The cluster ofindividual cavities under each inductor coalesce into a largepit roughly as deep as half the inductor size. Eight of thesepits in the middle of the chip form a sort of trench. Thistrench may possibly help to isolate the noise generated inthe static CMOS digital DDFS circuits on the upper leftof the transceiver from contaminating the microvolt-sensitivecircuits in the receiver on the lower right. Unfortunately, thishypothesis cannot be verified by measurement because withoutetching, the large capacitance under the inductors disables allcircuits tuned to 900 MHz. The isolation, whether it is due tothese trenches, the balanced circuits, or the highly conductivep -substrate under the thin p-type epi is good enough thatthere is no evidence in the receive spectrum (Fig. 14) of clockfeedthrough from the DDFS, which is clocking at full speed

(a)

(b)

Fig. 22. (a) Die photo after etching of cavities under inductors and (b)detailed view of pits under inductor and under long RF interconnects.

during all measurements, nor of the SC filter clocks. Neither,in the presence of more than 122 dB of voltage gain in thereceiver baseband circuits, is there any tendency to instability.

These pits are useful in another way: they lower the sub-strate capacitance under long interconnects carrying 900-MHzsignals. A case in point is the set of four lines, each 3mm long, which connect the balanced quadrature frequency-hopped signals from the RF buffer in the transmitter sectionto the downconversion mixer in the receiver. If they are ofminimum width, distributed RC effects result in a low cutofffrequency. If they are widened to lower the resistance, theincreased capacitance to substrate heavily loads the RF buffer.The solution is to place the same via holes between pairs ofthese lines as those surrounding the inductors. Thus, when pitsare etched under the inductors, they also appear between thelines (Fig. 22). Similarly, long ac metal runs when runningalongside an inductor are routed on the area close to theinductor edge, so after etching they are suspended above anouter pit. With the substrate capacitance now gone, the linesare widened to lower the series resistance that otherwise dampsthe tuned loads of the 900-MHz RF buffers (see [1]).

The LNA input port is nominally matched to 50 byabsorbing the capacitance of the RF input pad and the package


Fig. 23. LNA input matching network and measured versus simulated inputreturn loss.

pins into the matching network (Fig. 23). Actually, the LNAinput resistance is deliberately chosen greater than 50tofurther lower the input noise figure, as a result raising theinput return loss . This is a well-known tradeoff betweenimpedance matching against noise figure. The goal is toachieve a return loss of 10 dB. This is good enough in mostcases to obtain a satisfactory response from the external RFprefilter and baluns, each of which is designed to be terminatedby 50 . The wideband match obtained from 400–1400 MHz(Fig. 23) is better than the sharply parabolic curve ofversus frequency seen often [3].

The packaged transceiver chip is mounted on a four-layerprinted circuit board for testing (Fig. 24). Each pair of RFinput and output lines from the chip is carefully matchedin length to preserve signal balance up to the power split-ting/combining baluns. Two chip inductors mounted close tothe RF input pins match the LNA input impedance. Thereare another two chip inductors at the RF output and twochokes for biasing. One large off-chip filter capacitor isconnected across the balanced lines in the dc feedback loopof each limiting amplifier. No other critical high-frequencycomponents are required, nor is any shielding called for.Compared to the multicomponent transceivers found in manyof today’s wireless devices, this highly integrated transceiverclearly simplifies assembly and testing.

VI. DISCUSSION AND CONCLUSIONS

This set of papers describes a 900-MHz ISM band spread-spectrum wireless communication system, a new transceiverarchitecture, and numerous CMOS circuit building blockswhich are combined on one chip to implement a highlyintegrated CMOS radio. The design has evolved from tradeoffsat all levels in this hierarchy.

The receiver building blocks illustrate a comprehensive all-CMOS approach. The LNA and mixer at the front-end showhow to obtain low noise and high linearity in balanced open-loop circuits. The SC CMOS channel-select filter handlesinterferers very well and uses a multirate architecture toobtain a very wide stopband. A limiting amplifier is designedto absorb large dc offset without compromising dynamicrange, and it also provides RSSI. The digital correlationdetector is nearly optimal for 4-FSK, and at negligible power

Fig. 24. Packaged transceiver mounted on a printed circuit board. Only afew support components are required.

TABLE ITRANSMITTER CHARACTERISTICS

dissipation, it implements a valuable bandpass response as wellas synchronization from a 1-b limiter output.

Building blocks must be inserted with care into the receiverto meet stringent specifications on noise and dynamic range.Unlike baseband analog circuits, downstream blocks in thereceiver chain significantly affect overall performance. Cas-cade effects must be carefully calculated, and the individualdynamic range of the various building blocks must also beadjusted to optimize overall performance.

As in the transmitter, all circuits are balanced from the an-tenna onwards, and wherever possible signals are resolved intoquadrature components. The low parasitic coupling betweenblocks and weak pulling effects, both very desirable attributesin a practical transceiver, are mainly thought to result fromthe rigorous use of a balanced signal path. On the whole,the high level of integration is found to improve, rather thancompromise, receiver performance. Tables I and II summarizethe key performance features of the transmitter and receiver.

It is felt at the conclusion of this work that with a compre-hensive and disciplined approach rooted in the CMOS designart, RF-CMOS is now viable to implement, beyond building


TABLE IIRECEIVER CHARACTERISTICS

blocks, entirely monolithic, mixed analog-digital radios withcompetitive performance.

REFERENCES

[1] A. Rofougaran, G. Chang, J. J. Rael, J. Y.-C. Chang, M. Rofougaran, P.J. Chang, M. Djafari, M. K. Ku, E. Roth, A. A. Abidi, and H. Samueli,“A single-chip 900 MHz spread-spectrum wireless transceiver in 1-�mCMOS—Part I: Architecture and transmitter design),” this issue, pp.515–534.

[2] A. A. Abidi, “Direct-conversion radio transceivers for digital communi-cation,” IEEE J. of Solid-State Circuits, vol. 30, no. 12, pp. 1399–1410,1995.

[3] A. Rofougaran, J. Y.-C. Chang, M. Rofougaran, and A. A. Abidi, “A 1GHz CMOS RF front-end IC for a direct-conversion wireless receiver,”IEEE J. of Solid-State Circuits, vol. 31, no. 7, pp. 880–889, 1996.

[4] R. E. Lehmann and D. D. Heston, “X-band monolithic series feedbackLNA,” IEEE Trans. on Microwave Theory & Techniques, vol. MTT-33,no. 12, pp. 1560–1566, 1985.

[5] P. J. Chang, A. Rofougaran, and A. A. Abidi, “A CMOS channel-selectfilter for a direct-conversion wireless receiver,”IEEE J. of Solid-StateCircuits, vol. 32, no. 5, pp. 722–729, 1997.

[6] S. Khorram, A. Rofougaran, and A. A. Abidi, “A CMOS limitingamplifier and signal-strength indicator,” inSymp. on VLSI Circuits,Kyoto, 1995, pp. 95-96.

[7] K. Kimura, “A CMOS logarithmic amplifier with unbalanced source-coupled pairs,”IEEE J. of Solid State Circuits, vol. 28, no. 1, pp. 78–83,1993.

[8] R. S. Hughes,Logarithmic Amplification with Application to Radar andEW. Dedham, MA: Artech House, 1986.

[9] J. G. Proakis,Digital Communications. New York: McGraw-Hill,1989.

[10] H.-C. Liu, J. Min, and H. Samueli, “A low-power baseband receiverIC for frequency-hopped spread spectrum applications,”IEEE J. ofSolid-State Circuits, vol. 31, no. 3, pp. 384–394, 1996.

[11] U. L. Rohde, J. C. Whitaker, and T. T. N. Bucher,CommunicationsReceivers: Principles & Design, 2nd ed. New York: McGraw-Hill,1997.

[12] R. G. Meyer and A. K. Wong, “Blocking and desensitization in RFamplifiers,” IEEE J. of Solid State Circuits, vol. 30, no. 8, pp. 944–946,1995.

[13] W. B. Kuhn, F. W. Stephenson, and A. Elshabini-Riad, “A 200 MHzCMOSQ-enhanced LC bandpass filter,”IEEE J. of Solid-State Circuits,vol. 31, no. 8, pp. 1112–1122, 1996.

[14] J. Smith,Modern Communication Circuits. New York: McGraw-Hill,1986.

[15] W. H. Hayward,Introduction to Radio Frequency Design. EnglewoodCliffs, NJ: Prentice-Hall, 1982.

[16] W. B. Davenport, Jr., “Signal-to-noise ratios in band-pass limiters,”J.of Applied Physics, vol. 24, no. 6, pp. 720–727, 1953.

Ahmadreza Rofougaran, for a photograph and biography, see this issue, p.533.

Glenn Chang (S’92), for a photograph and biography, see this issue, p. 533.

Jacob J. Rael(S’93), for a photograph and biography, see this issue, p. 533.

James Y.-C. Chang, for a photograph and biography, see this issue, p. 534.

Maryam Rofougaran (M’93), for a photograph and biography, see this issue,p. 534.

Paul J. Chang, for a photograph and biography, see this issue, p. 534.

Masoud Djafari , for a photograph and biography, see this issue, p. 534.

Jonathan S. Min received the B.S. and M.S. de-grees in electrical engineering and computer sciencefrom the University of California, Berkeley in 1987and 1989 respectively, and the Ph.D. degree in elec-trical engineering from the University of California,Los Angeles, in 1995.

From 1989 to 1991, he was with Rockwell Inter-national, Anaheim, CA, where he was involved inthe development of space electronic systems such asa multichannel GPS receiver and satellite transceiv-ers. Currently, he is with Broadcom Corporation,

Irvine, CA, working on the design and development of high-speed cablemodems. His research interests are in the areas of the wireless/wirelinecommunications systems design, spread spectrum transceivers, digital signalprocessing, and VLSI architectures for realizing advanced digital communi-cations systems.

Edward W. Roth, for a photograph and biography, see this issue, p. 534.

Asad A. Abidi (F’96), for a photograph and biography, see this issue, p. 534.

Henry Samueli (S’75–M’79), for a photograph and biography, see p. 377 ofthe March 1998 issue of this JOURNAL.

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A Single-Chip 900-MHz Spread-Spectrum Wireless Transceiver ...homepages.cae.wisc.edu/~ece734/references/00663558.pdf · Fig. 6. Measured log conformity at RSSI output over 80-dB input