IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 8, NO. 5, SEPTEMBER 2009 611

A Simple Method for Measuring Si-Fin SidewallRoughness by AFM

Xiaohui Tang, Vincent Bayot, Nicolas Reckinger, Denis Flandre, Senior Member, IEEE,Jean-Pierre Raskin, Senior Member, IEEE, Emmanuel Dubois, and Bernard Nysten

Abstract—The gate oxide reliability and the electrical behaviorof FinFETs are directly related to the surface characteristics of thefin vertical sidewalls. The surface roughness of the fin sidewalls isone of the most important structural parameters to be monitoredin order to optimize the fin patterning and postetch treatments. Be-cause of the nanometer-scale dimensions of the fins and the verticalorientation of the sidewall surface, their roughness measurementis a serious challenge. In this paper, we describe a simple and ef-fective method for measuring the sidewall morphology of siliconfins by conventional atomic force microscopy. The present method-ology has been employed to analyze fins as etched by reactive ionetching and fins repaired by sacrificial oxidation. The results showthat sacrificial oxidation not only reduces the roughness of the side-walls, but also rounds the top corners of silicon fins. The presentmethod can also be applied to characterize sidewall roughness ofother nanostructures and materials such as the polysilicon gate oftransistors or nanoelectromechanical beams.

Index Terms—Atomic force microscopy (AFM), FinFET, rough-ness of silicon fin sidewall, sacrificial oxidation.

I. INTRODUCTION

F INFET [1], a nonplanar double-gate transistor usually builton a silicon-on-insulator (SOI) substrate, is a promising

candidate for CMOS scaling down to the 10-nm regime. In previ-ous years, several electrical characterizations of FinFET [2] havedemonstrated its effective control of short-channel effects [3],higher current drive, and scalability [4]. The CMOS compati-bility of its fabrication process flow explains the growing in-terest of the microelectronics industry for the advanced MOSarchitecture.

Manuscript received June 23, 2008. First published April 21, 2009; currentversion published September 4, 2009. This work was supported by the Euro-pean Commission through the Metallic Source/Drain Architecture for AdvancedMOS Technology (METAMOS) Project under Contract IST-FP6-016677. Thereview of this paper was arranged by Associate Editor E. T. Yu.

X. Tang, V. Bayot, N. Rechinger, and D. Frandre are with the Laboratoire deDispositifs Integres et Circuits Electroniques (DICE), Universite Catholiquede Louvain, B-1348 Louvain-la-Neuve, Belgium (e-mail: xiaohui.tang@uclouvain.be; vincent.bayot@uclouvain.be; reckinger@dice.ucl.ac.be; denis.flandre@uclouvain.be).

J. P. Raskin is with the Laboratoire d’Hyperfrequences (EMIC), Univer-site Catholique de Louvain, B-1348 Louvain-la-Neuve, Belgium (e-mail: jean-pierre.raskin@uclouvain.be).

E. Dubois is with the Institut d’Electronique de Microelectronique et de Nan-otechnologies (IEMN), Centre National de la Recherche Scientifique (CNRS),59652 Villeneuve d’ascq, France (e-mail: emmanuel.dubois@isen.iemn.univ-lille1.fr).

B. Nysten is with the Unite de Chimie et de Physique des Hauts Polymeres(POLY) and Belgian Fund for Scientific Research, Universite Catholiquede Louvain, B-1348 Louvain-la-Neuve, Belgium (e-mail: bernard.nysten@uclouvain.be).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TNANO.2009.2021064

Fig. 1. (a) 3-D scheme of a FinFET showing the fin sidewall and current drivedirection. (b) 3-D scheme of Si fins showing a standing fin and released fin afteretching away the BOX.

In a FinFET, the drive current flows along the vertical side-walls of Si-fin [see arrow direction in Fig. 1(a)]. The surfacequality of the sidewalls, thus, strongly influences the gate in-sulator reliability and the device electrical performance. Roughsidewalls result in carrier mobility and lifetime reduction [5],current drive decrease, subthreshold swing deterioration, leak-age current, and low-frequency noise increase [6], [7]. It isworth noting that the Si-fin sidewall roughness impacts n-typeFinFETs more severely than p-type FinFETs. Indeed, the in-version charge centroid of electrons is closer to the surfaces ofthe fin sidewalls than that of holes [8]. Hence, electron mobilityis more affected than hole mobility through surface scatteringphenomenon. It is, therefore, of foremost importance to quan-titatively characterize the Si-fin sidewall roughness and effec-tively improve the as-etched Si-fin sidewall quality for buildinghigh-performance FinFETs. Besides the specificity of the Fin-FET architecture, the control of the line-edge roughness (LER)of the gate becomes a major issue as the size of the CMOSdevices further shrinks. A gate length less than 10 nm with largeLER causes fluctuations of the device characteristics. The Inter-national Technology Roadmap for Semiconductors (ITRS) [9]specifies a requirement of 2.8 nm for the LER for the year 2009and smaller values for subsequent years. Similar concerns existfor the fabrication of reliable nanoelectromechanical systems(NEMSs) featuring sub-100 nm dimensions [10], [11].

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612 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 8, NO. 5, SEPTEMBER 2009

Up to now, only few works evaluating the Si-fin sidewalland LER have been reported. This is because rare instrumentsare suited for such measurements. Although atomic force mi-croscopy (AFM) with its high resolution has proven to be apowerful tool to study, image, and manipulate the surface ofnanoscale systems [12], [13], it still has certain limitations forprofiling vertical sidewalls. For instance, Marrinello et al. [14]tilted the measured sample by an angle for the point-shaped tipto close untouchable regions at sidewall’s bottom, and Martinand Wickramasinghe [15] used a modified tip (a boot-shapedtip) to obtain a high lateral resolution. However, these methodsare not really suitable for scanning the sidewall of a Si-fin alongthe channel direction [current flow direction, see Fig. 1(a)], evenusing assembled cantilever probes, as recently reported by Daiet al. [16], [17]. In the other hand, Gondran et al. [18] proposedto cleave the sample along the length of the fin (channel di-rection) and polish the sample edge using focused ion beam toapproach the fin’s sidewall. This method is rather complicatedsince it requires sophisticated equipment to prepare the sample,without mentioning the difficulty to cleave the sample perfectlyparallel to Si-fin sidewall to be measured.

In this paper, we present a simple and effective method todeeply analyze the sidewall morphology of Si-fins using con-ventional AFM. Contrary to the methods mentioned previously,the present technique requires neither special tips nor cleavingof the sample. The main idea is to release the fins to presentthe sidewall surface to be measured [see Fig. 1(b)]. The re-lease of the Si-fins can be obtained by simply etching away theburied oxide (BOX) on which the Si-fins stand on. After that re-lease step in a hydrofluoric acid (HF) based solution, the Si-finspresent one of their sidewall surfaces parallel to the substrate,thus being exposed to AFM tip for the analysis. This simpleprocedure is quite powerful to quickly analyze, and then op-timize the etch conditions and the postetch treatments for thefabrication of high-quality Si-fins. The sidewall roughness ofas-etched and repaired Si-fins has been measured by using thepresent method.

II. SAMPLE PREPARATION

A p-type SOI wafer with a BOX thickness of 400 nm, whichis a common substrate for building n-type FinFETs, is used asstarting material. The 200-nm-thick Si film is thinned down to80 ± 1 nm by a wet etching in a solution (NH4OH:H2O2:H2O1:8:64 mixture) [19]. Then, a 30-nm-thick oxide is depositedon top of the film by low-pressure chemical vapor deposition toserve as a hard mask. Fins with a width of 30 nm are patternedusing electron-beam lithography. The longitudinal direction ofthe fins is chosen parallel to the [1 1 0] wafer direction, so thatthe fin sidewall surface is in the (1 1 0) plane. The hard maskis etched by CHF3 with a gas flow rate of 500 sccm and apower of 50 W. The Si-fins are etched by reactive ion etch(RIE), which is performed under a pressure of 25 mTorr witha SiCl4 gas flow rate of 20 sccm and a power of 40 W. Inthis step, the Si etch rate is 43 nm/min, and the selectivity forSi to SiO2 is about 15:1. Sacrificial oxidation [20] is carriedout at 950 ◦C for 5 min to smooth and repair the sidewalls

Fig. 2. SEM cross sections of repaired Si-fins. The fins have a width of 30 nmand a height of 80 nm.

damaged by RIE. Fig. 2 shows a scanning electron microscope(SEM) image of the repaired fins (sample A): the fin has awidth of 30 nm, a height of 80 nm, a length of 848 µm, and apitch of 400 nm. It can be seen that the fin sidewalls are quitesteep, which permits the fin to be flat when it is released afterremoving the BOX. In order to compare the sidewall roughnessbefore and after sacrificial oxidation, as-etched fins (sample B)are also characterized using the same technique. Finally, the finsare released for the characterization of the sidewall surface. Forthis purpose, both samples are immersed in buffered HF (BHF)for 20 s at room temperature to remove the BOX of the SOIwafer and rinsed in deionized water to clean the residual BHF.The BHF is composed of 40% NH4F and 49% HF (85.5:12.5),and the etch rate of the BOX in BHF is about 60 nm/min.The 30-nm-wide fins are completely released after an etch timeof less than 20 s since the etching is carried out from twosidewalls. In this step, not only the BOX is removed, but alsothe residual hard mask is removed in 20 s. As a result, the Si-fins are floating, either broken or intact, and lay on the siliconsubstrate, as shown in Fig. 3 (a) and (b), and Fig. 4 (a) and (b). Itis worth noting that the thermal oxide (grown during sacrificialoxidation) surrounding the Si-fins of sample A is also removedduring their release from the BOX.

III. ROUGHNESS MEASUREMENT OF SI-FIN SIDEWALLS

AFM analysis is performed under ambient condition on amultimode Nanoscope IV (Veeco Instruments) operating inamplitude-modulated mode. The used cantilever (Super SharpSilicon SPM-sensor from Nanosensors) [21] has a resonance fre-quency around 70 kHz and a typical spring constant of 5 Nm−1 .On this type of sensors, the tip has an aspect ratio better than4:1 and the apex radius of curvature is less than 5 nm. The freeand set-point amplitudes are set to 15 and 10 nm, respectively.Image processing and analyses are performed using home-madeprocedures developed under Igor Pro software (Wavemetrics).Images are flattened with a plane fit procedure (subtraction of anaverage plane), and are analyzed without any further treatment.

For each sample, images of several released Si-fins are ac-quired to perform a statistical analysis of the sidewall roughness.

TANG et al.: SIMPLE METHOD FOR MEASURING SI-FIN SIDEWALL ROUGHNESS BY AFM 613

Fig. 3. AFM images of repaired Si-fins (sample A). (a) General view ofreleased and standing up fins. (b) Zoom on four released fins. (c) Details of leftfin visible in (b). (d) Zoom on the sidewall of the fin presented in (c). The whitecurve in (c) is the cross section profile of the fin measured along the horizontalline.

Fig. 4. AFM images of as-etched Si-fins (sample B). (a) General view ofreleased fins. (b) Zoom on two released fins. (c) Details of left fin visible in (b).(d) Zoom on the sidewall of the fin presented in (c). The white curve in (c) isthe cross section profile of the fin measured along the horizontal line.

Images of the repaired and as-etched Si-fins are shown in Figs. 3and 4, respectively. Figs. 3(c) and 4(c) present cross section pro-files of the released Si-fins. The measured height (correspondingto the fin width) ranges between 25 and 35 nm, which are consis-tent with the targeted value of 30 nm. The sidewall width (cor-responding to the fin height) is measured around 100 nm, i.e., avalue slightly larger than the actual height of the fins (80 nm).This larger value may be explained by image widening (or dila-tion) effects [22], namely, the finite tip size produces a wideningof the lateral size of the surface features. In the present case, themaximum widening D can be estimated based on the relation

D = 2R + h/Ar , where R is the tip apex radius of curvature, Ar

is the tip aspect ratio factor, and h is the sidewall height. WithR ≤ 5 nm, Ar = 4, and h = 30 nm, the widening is estimatedto be equal or less than 17.5 nm leading to an expected apparentwidth ≤97.5 nm, consistent with the measured values.

From the large-scale images (typically 1 µm × 1 µm), thelarge-scale LER of the Si-fins was estimated as follows. 5-pixel-wide and 1-µm-long line profiles were measured along releasedfins. The LER was estimated by calculating the rms roughnessof the line profiles and by averaging the values measured ondifferent profiles measured on various fins. The obtained valuesare equal to 2.0 ± 1.3 nm for the as-etched fins and 1.1 ± 0.3 nmfor the repaired fins.

Small-scale images [60 nm × 60 nm, see Figs. 3(d) and 4(d)]are also acquired on several Si-fins. The rms roughness of thefin sidewall is calculated from those images. The average valuesare 0.25 ± 0.05 and 0.55 ± 0.10 nm for the repaired and as-etched fin sidewalls, respectively. The roughness of the sidewallsurface is approximately reduced by a factor of 2 after repairing.

To further illustrate this, the circular average power spectraldensity (PSD) of the 60 nm × 60 nm images is then calculated.The PSD curves extracted from several images are merged toobtain an average PSD curve, which statistically represents thefin sidewall surfaces. Based on the average PSD curves, thevariation of the rms roughness (σ) as a function of the lengthscale (r) is calculated using the following relation:

σ(r) =[2π

∫ sm a x

1/r

PSD(s)sds

]1/2

where s is the spatial frequency and smax is the maximum spatialfrequency or Nyquist frequency, smax = N/(2L), with N and Lbeing the image lateral pixel number and size, respectively.

The length-scale dependence of σ is presented in Fig. 5. Itshows that the repaired and as-etched Si-fins have comparablesidewall roughness at length scales lower than 2 nm. It is worthnoting that, when the length scale is much smaller than thecurvature radius of the tip (i.e., less than 5 nm in the presentcase), roughness determined by AFM may not reflect the actualroughness anymore. When the length scale is higher than 3 nm,the rms roughness is significantly improved after sacrificialoxidation.

In addition, it is found that the sidewall surface is rougher thanthe wafer surface after RIE (red lines in Figs. 5 and 6). This canbe explained by the followings. The roughness of the wafer sur-face is mainly introduced by ion bombardment damage in RIE,while the roughness of the sidewalls is caused not only by ionbombardment damage, but also by the imperfectness of the hardmask in electron-beam lithography. The repair (at 950 ◦C for5 min) used here is efficient to restore the wafer surface rough-ness to the original value of the Unibond SOI wafer (0.2 nm), butit is incomplete for the sidewall surface with a higher roughness.To further smooth the sidewall surface, a longer oxidation timeis needed. In the beginning of the thermal oxidation, the oxidantis sufficiently supplied, the rate-limiting process is the interfacereaction where the oxide thickness is proportional to oxidationtime. When the oxidation is further carried out, the rate-limiting

614 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 8, NO. 5, SEPTEMBER 2009

Fig. 5. RMS roughness as a function of length scale calculated from mergedcircular-averaged PSD’s of the small-scale images of the Si-fin sidewalls. Errorbars correspond to +/− the standard deviation on the data.

Fig. 6. RMS roughness as a function of length scale calculated from thecircular-averaged PSD’s of the image of the Si wafer surfaces. Error bars corre-spond to +/− the standard deviation on the data.

process becomes oxidant-supplying process, where the oxidethickness is proportional to square root of oxidation time. Thesurface smoothing happens during the oxidant-supplying period,because the oxidation supply rate at convex parts is higher thanat concave parts of the oxidized Si surface [23]. Therefore, theoxidation time should be long enough to pass the rate-limitingperiod, thereby flatting the rougher sidewall. This is crucial forselecting postetch treatments and designing high-performanceFinFET devices. In addition to sacrificial oxidation, the side-wall roughness of the Si-fins also can be improved by the othermethods, such as hydrogen annealing [24] and chemical dryetching [25].

IV. CORNER TRANSFORMATION OF SI-FIN

The top corner shape of the Si-fins significantly affects theperformance of FinFET device, i.e., sharp corners result inlarger subthreshold sweep and higher off-state current [26], [27].Hence, the measurement and control of the curvature radius for

Fig. 7. (a) SEM cross sections of as-etched Si-fins by RIE. (b) SEM crosssections of repaired Si-fins by sacrificial oxidation, showing that sacrificialoxidation increases radii of curvature of the top corners.

the top corners of the fin are an important technological issue.Fig. 7(a) and 7(b) shows SEM images of cross-sectional profilesfor four fins before and after the repair by sacrificial oxidation,respectively. It is clear that, after the repair, the top corners ofthe fins become rounded. According to the images, the radii ofcurvature of the top corners are estimated. For a fin with a crosssection of 80 nm × 80 nm, the radius of curvature is increasedfrom 15 to 28 nm after the repair. This implies that the cornereffect can be eliminated and suppressed by sacrificial oxidation.The rounding of the top corners is attributed to higher oxidationrate in the regions of the top corners because oxygen atoms pen-etrate these regions from the sidewall as well as from the uppersurface.

V. CONCLUSION

In this paper, we present a simple and effective method torelease Si-fins for measuring their sidewall roughness by AFM.Like in a “lift-off” process, the BOX of the SOI wafer on whichthe Si-fins are placed is removed away, and the fins are liftedoff. Some of them lay down with the sidewall exposed so thatAFM measurements can be easily performed. This method isused to analyze Si-fins etched by RIE and Si-fins repaired bysacrificial oxidation. The results reveal that sacrificial oxidationhas not only improved the rms roughness of the sidewalls, butalso rounded the top corners of the Si-fins.

TANG et al.: SIMPLE METHOD FOR MEASURING SI-FIN SIDEWALL ROUGHNESS BY AFM 615

ACKNOWLEDGMENT

The authors would like to acknowledge A. Crahay, D. Spote,B. Katschmarskyj, C. Renaux, and M. Zitout for their help.

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Xiaohui Tang received the B.S. degree in physicsand the M.S. degree in electrooptical technology fromYunnan University, Yunnan, China, in 1982 and 1987,respectively, and the Ph.D. degree in applied sci-ences from the Universite Catholique de Louvain,Louvain-la-Neuve, Belgium, in 2001.

From 1983 to 1984, she was an Assistant atKunming University of Technology, China. From1988 to 1994, she joined Kunming Institute ofPhysics, China, where she was engaged in the re-search on II–VI compound semiconductor materials

and devices. During 1995, she was a Free Researcher at Interuniversity Micro-electronics Center (IMEC), Leuven, Belgium. She is currently at the Microelec-tronics Laboratory (DICE) and the Research Center in Micro and NanoscopicMaterials and Electronic Devices (CERMIN), Universite Catholique deLouvain. She has authored or coauthored more than 60 publications in in-ternational journals and conferences. Her current research interests includefabrication, characterization, and simulation of silicon-on-insulator (SOI) low-dimensional devices as well as electrical sensors with a high sensitivity.

Vincent Bayot was born in Belgium, in 1963. Hereceived the Engineering degree in applied physicsand the Ph.D. degree from the Universite catholiquede Louvain (UCL), Louvain-la-Neuve, Belgium, in1986 and 1991, respectively.

Until 1992, he was a Postdoctoral Fellow atPrinceton University. Until 1998, he was with FondsNational de la Recherche Scientifique (FNRS),Belgium. He is currently a Professor at UCL, wherehe is also the President of the multidisciplinary “Re-search Center in Micro- and Nanoscopic Materials

and Electronic Devices” (CERMIN). He has been engaged in low-dimensionalelectronic systems and mesoscopic physics, mostly in III–V compounds (quan-tum Hall effect and ballistic transport), and also in carbon nanotubes, semimet-als, nanomagnetic materials, nanofabrication techniques, silicon-on-insulator(SOI) quantum devices, and nanoelectronics. He has authored or coauthoredmore than 160 publications in international journals and conferences.

616 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 8, NO. 5, SEPTEMBER 2009

Nicolas Reckinger received two M.S. degrees inelectrical engineering and physics in 2000 and2002, respectively, from the Universite catholique deLouvain (UCL), Louvain-la-Neuve, Belgium, wherehe is currently working toward the Ph.D. degree inapplied sciences.

His current research interests include the fabrica-tion and the characterization (physical and electrical)of Si-based nanodevices, especially nanoflash mem-ories and Schottky barrier MOSFETs.

Denis Flandre (S’86–M’91–SM’03) was born inCharleroi, Belgium, in 1964. He received the Elec-trical Engineer, Ph.D., and Postdoctoral Thesis de-grees from the Universite Catholique de Louvain(UCL), Louvain-la-Neuve, Belgium, in 1986, 1990,and 1999, respectively.

In 1985, he was a Trainee at NTT Headquaters,Tokyo, Japan. From 1990 to 1991, he was withthe Centro Nacional de Microelectronica (CNM),Barcelona, Spain. He was a Senior Research Asso-ciate of the National Fund for Scientific Research

(FNRS) with the Microelectronics Laboratory (DICE), UCL, where he has beena full-time Professor since 2001 and the Head of the UCL MicroelectronicsLaboratory since 2003. He is a Co-founder of CISSOID, a start-up company,which spun-off of UCL in 2000, where he is involved in silicon-on-insulator(SOI) circuit design services. He is engaged in the research and development ofSOI MOS devices, digital and analog circuits, as well as sensors and microelec-tromechanical system (MEMS) for special applications, more specifically, high-speed, low-voltage low-power, microwave, and rad-hard and high-temperatureelectronics and microsystems. He has authored or coauthored more than 450technical papers or conference contributions and holds eight patents.

Prof. Flandre has been a recipient of several awards. He participated, orga-nized, or lectured in many short courses on SOI technology, devices and circuits,in universities, industries, and conferences. He has been a member of the Boardsof the European (EU) Networks of Excellence for High-Temperature Electron-ics (HITEN), Silicon Nanodevices (SINANO/NANOSIL), and SOI technology(EUROSOI). He is a member of the SOI Consortium. In UCL, he is a mem-ber of the Research Center in Micro- and Nanoscale Materials and ElectronicsDevices (CERMIN), of the Director Board of the Cyclotron Research Center(CRC), Louvain-la-Neuve, and the Chairs the direction committee of the UCLMicro-/Nanotechnology Facility (Winfab).

Jean-Pierre Raskin (M’97–SM’06) was born inAye, Belgium, in 1971. He received the IndustrialEngineer degree from the Institut Superieur Indus-triel d’Arlon, Arlon, Belgium, in 1993, and the M.S.and Ph.D. degrees in applied sciences from the Uni-versite catholique de Louvain (UCL), Louvain-la-Neuve, Belgium, in 1994 and 1997, respectively.

From 1994 to 1997, he was a Research Engineerat the Microwave Laboratory, UCL. He was engagedin the modeling, characterization, and realization ofmonolithic microwave-integrated circuits (MMICs)

in silicon-on-insulator (SOI) technology for low-power, low-voltage applica-tions. In 1998, he joined the Department of Electrical Engineering and Com-puter Science (EECS), The University of Michigan, Ann Arbor. During 2000,he was an Associate Professor in the Microwave Laboratory, UCL, where hasbeen a Full Professor and the Head of the Microwave Laboratory since 2007.He has been involved in the development and characterization of microma-chining fabrication techniques for microwave and millimeter-wave circuits, andmicroelectromechanical transducers/amplifiers working in harsh environments.He has authored or coauthored more than 350 scientific papers. His current re-search interests include modeling, wideband characterization, and fabrication ofadvanced silicon-on-insulator (SOI) MOSFETs as well as micro- and nanofabri-cation of microelectromechanical system (MEMS)/nanoelectromechanical sys-tem (NEMS) sensors and actuators.

Dr. Raskin is an European Management Assistants (EuMA) Associate Mem-ber and a Member of the Research Center in Micro- and Nanoscopic Materialsand Electronic Devices, UCL.

Emmanuel Dubois received the Ingenieur degreefrom the Institut Superieur d’Electronique et duNumerique (ISEN), Lille, France, in 1985, and thePh.D. degree from the University of Lille, Lille, in1990.

During 1992, he was a Visiting Scientist at IBMT.J. Watson Research Centre, Yorktown Heights,where he was engaged in characterization andsimulation of submicrometer silicon-on-insulator(SOI) MOSFETs. In 1993, he joined the Institutd’Electronique de Microelectronique et de Nanotech-

nologie (IEMN/ISEN), Centre National de la Recherche Scientifique (CNRS),Villeneuve d’ascq, France, where he is currently the Director of Research atthe Centre National de la Recherche Scientifique and the Head of the SiliconMicroelectronics Group since 1999, and is involved in device physics, devicemodeling, and fabrication of ultimate nonconventional MOSFETs.

Dr. Dubois was the Coordinator of FP4-IST-QUEST (1997–1999), FP5-IST-SODAMOS (2001–2003), FP6-IST-METAMOS (2005–2008) EuropeanProjects, and was a Task Leader in the SiNANO Network of Excellence (2005–2007). He is currently a Task Leader of the Silicon-Based Nanostructures AndNanodevices For Long-Term Microelectronics Applications (NANOSIL) Euro-pean (EU) Network of Excellence (2008–2010) and a member of the TechnicalAdvisory Committee of the Integrated Systems Technology (IST) IntegratedProject PULLNANO.

Bernard Nysten was born in Namur, Belgium, in1962. He received the Engineering degree in ap-plied physics and the Ph.D. degree from the Uni-versite catholique de Louvain (UCL), Louvain-la-Neuve, Belgium, in 1984 and 1991, respectively.

For one year, he was a Postdoctoral Fellow at theCentre de Recherche Paul Pascal, Centre Nationalde la Recherche Scientifique (CNRS), Bordeaux,France. He joined the Polymer Science Laboratory,UCL, as a postdoctoral researcherwhere he was also aResearch Associate of the National Funds for Scien-

tific Research of Belgium (FNRS) and is currently a Senior Research Associateof the FNRS and a part-time Professor at the UCL. He has been engaged indeveloping broad expertise in the development of scanning probe microscopies[scanning tunneling microscope (STM) and atomic force microscope (AFM)]and their application to the study of organic and inorganic materials with specialemphasis on nanomechanics, nanochemistry, nanomagnetism, soft-matter self-organization, organic electronics, and surface nanopatterning. He has authoredor coauthored more than 90 publications in international journals and 180 com-munications to conferences.

Prof. Nysten is the President of the Belgian Society of Microscopy (BVM-SBM) and the Wallonia Network for Nanotechnologies (NanoWal).