1246 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 39, NO. 5, MAY 1992

Solving (7) for yp results in dicted by (14), the maximum field is not too sensitive to vanations of the gate voltage in the subthreshold region. By contrast, the field in the above-threshold region as given by (15) is sensitive to gate voltage due to the Vdsa, dependence on the gate voltage.

1 I V d + + &)I2 - = cosh-’ 1 + YP

I 6 , v; 4 N J 2

E , REFERENCES

[ I ] K . Mayaram, J . Lee, and C. Hu, “A model for the electric field in lightly doped drain structures,” IEEE Trans. Electron Devices, vol. ED-34, pp. 1509-1518. July 1987.

[2] J . S. T. Huang, “An analytical model for LDD drain structures,” IEEE Trans. E/ectron Devices, vol. 35, pp. 1158-1 159, July 1988.

(31 Y. Hu, R. Booth, and M. White, “An analytical model for the lateral channel electric field in LDD stmctures,” IEEE Trans. Electron De- vices, “01. 37 , pp. 2254-2264, Oct. 1990.

[4] T. Chan, P. KO, and C. Hu, “Dependence of channel electric field on device scaling,” IEEE EIecrron Device Letr., vol. EDL-6, pp. 551- 553, Oct. 1985.

(lo)

r . (cosh? - I)]] - y .

If Y , > L,, then EdL,) is finite. All y,’s i n (7) and (8) should be replaced by L, resulting in ( 7 ) and (8) being the equations to solve for Yp and E2(Ln). Equation ( IO) still gives the value Ofyp but with yn replaced by L,. E,@,) can then be calculated from (8).

The maximum electric field is given by either (4) or (6) with y = o

The influence of the gate voltage on the field is explicit in (11 ) . For devices in which Nd >> N , and y,! << yp, and 1 , the second term on the right side of ( 7 ) can be ignored and (7) becomes

vd + (@$ - V ; ) = (@$ - V ; ) cosh (?). (12)

Multiplying (1 1) by 1 and then squaring, we have

E:&’ = (% - V;)* sinh’ (+) . Squaring (12) and subtract the result from (13), we obtain the max- imum electric field as

An approximate expression for the maximum field when the device is operating in the saturation region was derived in [4] as

where Vdsat is the drain saturation voltage at the source end of the pinch-off region. It is of interest to note that (14) follows directly from (15) in the subthreshold regime for which

For an n-channel LDD MOSFET in which Nd = 10’’ cm-3, Nu = 5 X 10’‘ C I T - ~ , xo = 2 X cm, x, = 3 X I O - ’ cm, and L, = 0.1 pm, the electric field distributions for V i = 0, 0.3, and 0.6 V and at Vd = 5 V are calculated and plotted in Fig. 1. Also plotted in Fig. 1 for comparison is the field profile of a conven- tional p-n junction in the absence of a gate, as can be obtained from one-dimensional Poisson’s equations. The usual doping concentra- tion of the LDD region is such that the depletion layer in the ab- sence of mobile carriers does not reach the N - - N + junction prior to breakdown. It is shown in Fig. 1 that the maximum electric field is increased by the presence of the gate resulting in a decrease of the breakdown voltage. As can be seen from Fig. 1 and also pre-

+ 0.

A Semi-Empirical Model of the MOSFET’s Small- Signal Drain Conductance in Saturation for

Analog Circuit Design

F. S . Shoucair

Abstract-A semi-empirical model is presented for the incremental drain conductance g,, of the long-channel MOSFET in saturation which is useful for hand analysis of MOS amplifiers. The model’s accuracy is higher than that of current commercial simulators and comparable to the parameter spread observed in current VLSI processes. Important modeling errors in the standard SPICE model for g, are pointed out.

I . INTRODUCTION

An accurate model of the small-signal drain conductance gd in saturation is critical to the prediction of gain, distortion, and other related performance parameters in analog MOS VLSI. In simula- tion programs such as SPICE, gd models are optimized with respect to computational efficiency at the expense of some accuracy and physical insight [I]. These programs typically “predict” g d , and therefore the gain of amplifiers, to within a factor of two of exper- imental measurements, but can be in error by up to two orders of magnitude as will be shown. We propose a simple model for gd whose accuracy in pinchoff is better than that of current commer- cial simulators, and is comparable to the data spread observed in state-of-the-art VLSI processes. The latter feature justifies the use- fulness of the model in the design of modem integrated circuit am- plifiers such as those found in switched capacitor filters, high-lin- eanty O T A ’ s , neural networks, and general telecommunication IC’s [21, [31.

11. ANALYTICAL RESULTS

Consider an n-channel MOSFET in saturation with a long, strongly inverted and pinched off channel. A simple and widely

Manuscript received September 12, 1991. The review of this brief was arranged by Associate Editor M. D. Feuer.

The author is with the Department of Electrical Engineering, Brown Uni- versity, Providence, RI 02912.

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used expression for the drain current of this device is

(1)

where we have used standard terminology. The channel length L = LDRAWN - 2LD - X, , X , is the drain junction’s depletion region width, and LD is the lateral diffusion distance under the gate oxide. For VDs 2 V D S A T , I D depends on VDs implicitly through the param- eter X , . In order to obtain an explicit expression for the incremental conductance g , in terms of X , , I D , and VDs, we write (1) in the altemate form

ID -!LE- ’ zL (VCS - VTH)2

where Le, = LDRAWN - 2L,, X models the widening of X , with increasing VDs, and ( 2 ) is used in most standard treatments [ 2 , p. 731 with X assumed constant at fixed Leff. In the following analysis, we do not assume a priori X to be constant, but instead examine its functional dependence on channel length and drain bias. Equat- ing (1) and (2) yields

(3)

In a one-dimensional physical model of the pinchoff region for an abrupt drain-body junction (i.e., the “standard” SPICE model), X , varies as ( V D s - V D S A T ) ” ’ , where VDsAT is derived from the accurate “ 3 / 2 power law” I , expression for a MOSFET [4, p. 4421. We have determined after careful examination of experimen- tal data over a wide range of gate, body, and drain voltages, that X , does not vary as ( V D s - V D s A T ) ” ’ . Towards this end, we show analytically (6) that the ratio ( & / I D ) is proportional to x,, and experimentally that ( & / I D ) does not vary as ( V D S - V D S A T ) ” * (Fig. 1). We have found instead that the best agreement with experi- mental observations is obtained with an expression for X , of the form

(4)

where &, is an empirically determined constant whose optimal value for our devices is approximately 0.7 V. From a CMOS circuit designer’s standpoint, the quantity ( & / I D ) is particularly useful because it readily yields the small-signal voltage gain of a stage at a given bias current I D . Since the latter quantity is usually chosen first by the designer, and since gd is strongly affected by I D , any useful model of gd must provide for the specification of the corre- sponding I D . We therefore derive the following expression for ( g d / I D ) using ( 2 ) :

Using (3) and ( 4 ) in (5) now yields

(6)

where the right-hand side approximation holds under long-channel conditions (X,, << L e f f ) . Our experimental results for the variations of ( & / I D ) with terminal voltages and with LeR are presented in Section 111.

2J €Si

Leff 2qNwb(vDS + 4x4)

0. I

0.01 - 5 h

I . n

en v

0.001

VDSAT (v)

0.35 0.69 1.04 1.41 1.78

Na - 2 ~ 1 0 ’ ~ cur3

1.5 2 2.5 3 3.5

VGS (v) Fig. 1. Experimental data for (g,,/Z,,) for n-channel MOSFET’s as a func- tion of gate and drain saturation voltage VDSAT. Notice the weak depen- dence on VDSAT.

111. EXPERIMENTAL RESULTS

We have examined n- and p-channel MOSFET’s fabricated by MOSIS, whose drawn channel lengths ranged between 3 and 100 pm. Fig. 1 shows the variations of ( & / I D ) with Vcs and VDSAT at fixed drain and body (Vse) potentials. These data are qualitatively inconsistent with an X , dependence on ( V D s - VDSAT)”’ as mod- eled in SPICE. Fig. 2 shows that Vss has a negligible influence on ( g d / I D ) for VDs 2 2.5 V approximately, while SPICE again dis- plays the incorrect dependence on ( V D s - V D S A T ) ” 2 and system- atically miscalculates ( & / I D ) . Fig. 3 shows that our model is con- sistently closer to measurements than is SPICE, and that hole avalanche injection becomes increasingly pronounced with increas- ing Leff for VDs > 3 V. We found the effect to be about an order of magnitude weaker for p-channel MOSFET’s at comparable fields (as expected from the relative ionization coefficients of holes and electrons [ 4 , p. 471) by monitoring the substrate currents of our devices. While our model does not account for carrier injection effects, this phenomenon is likewise absent in SPICE. Its conse- quences for analog IC’s include gain, distortion, and dynamic range degradations, which have not been properly accounted for to date. A standard two-stage CMOS OPAMP and a balanced version thereof [3] were fabricated with the MOSIS process whose data are presented in Figs. 1-3, in which device Leff’s ranged between 2 .6 and 64.4 pm. The open-loop voltage gain measurements exceeded our model’s predictions by 20% on average, and those of SPICE and PSPICE by 80% on average.

IV. CAD MODELING ERRORS

While SPICE typically overestimates ( & / I D ) by a factor of 2 through most of the pinchoff region (Figs. 2 , 3), it underestimates this ratio by 1 to 3 orders of magnitude (Fig. 3, L = 100 pm) near the onset of saturation! Experimental data show a smooth, gradual, transition for ( & / I D ) from high to low as the lateral electric field near the drain builds to form the pinchoff region. This transition extends to approximately 1 V above VDsAT for our devices and rep- resents a substantial dynamic range reduction (30 to 50%) which

1248 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 39. NO. 5. MAY 1992

I

0. I h - t h

I . n

M - 0.01

I X VDSAT - 1 1

V. CONCLUSION

We have presented a simple model for the incremental drain con- ductance gd of the long-channel MOSFET in saturation, whose ac- curacy is higher than that of current commercial simulators (SPICE) and is comparable to the data spread observed in modem VLSI processes. We have reported important discrepancies between ex- perimental observations and the corresponding SPICE models for the pinchoff characteristics of MOSFET’s, which include qualita- tively incorrect models through the saturation voltage, optimistic dynamic range predictions, and systematic quantitative errors throughout the pinchoff region.

REFERENCES

[ I ] S. Liu and L. W. Nagel, “Small-signal MOSFET models for analog circuit design,” IEEE J . Solid-State Circuits, vol. SC-17, no. 6, pp. 983-998, Dec. 1982.

[2] Gregorian and Temes, Analog MOS Integrated Circuirs for Signal Pro- cessing. New York: Wiley, 1986.

erational amplifiers with accurate output balancing,” IEEE J . Solid- State Circuits, vol. 23, no. 6, pp. 1410-1414, Dec. 1988.

New York: Wiley, 1981,

0 1 2 3 4 5 [3] M. Banu, J . M. Khoury, and Y. P. Tsividis, “Fully differential op- 0.001

VDS (V) [4] S. M. Sze, Physics of Semiconductor Devices.

Fig. 2. Comparison of experimental data and SPICE predictions for ( & / I D ) versus VDS for n-channel MOSFET’s with source-body voltage Vss as a parameter.

h - t h

I . s v

1

0.1

0.01

U : + o MOSFETs Na - 2x1016 cm-3 1 1 I

0.001

0 1 2 3 4 5

VDS (v) Fig. 3. Comparison of theory, SPICE, and experimental data for n-chan- ne1 MOSFET’s of the MOSIS 2-pm p-well CMOS process. Note the re- versal of the decreasing trend of (g,,/ID) for v,, > 3 V caused by ava- lanche injection of holes into the substrate. All values of L represent drawn channel length dimensions.

Determination of Junction Temperature in AIGaAs/ GaAs Heterojunction Bipolar Transistors by

Electrical Measurement

J . R. Waldrop, K . C. Wang, and P. M. Asbeck

Abstruct-A method to measure the junction temperature, and as- sociated thermal resistance, of heterojunction bipolar transistors by using the temperature dependence of the de gain is described.

Heterojunction bipolar transistor (HBT) technology is being ac- tively developed for high-speed digital and high-frequency micro- wave applications [ 11. For optimal performance high current den- sities and small device dimensions are often employed. Reasonably accurate knowledge of device temperature rise during operation, which may be appreciable under typical power dissipation condi- tions, is desirable from circuit design, modeling, and reliability standpoints.

Measuring the junction region temperature of a small device is generally troublesome. Optical IR thermometry has limited spatial resolution and liquid crystal methods can be somewhat tedious; both approaches also must relate an observed surface temperature to the internal junction temperature. In this brief we demonstrate a

Manuscript received March 5 , 1991; revised October 2, 1991. This work by Wright Laboratory under Contract F33615-88-C-1737.

J . R. Waldrop and K. C. Wang are with Rockwell International Science

P. M . Asbeck was with Rockwell International Science Center, Thou-

is not accounted for by SPICE. Moreover, in SPICE, continuity of the g d function through the saturation voltage-which is essential for numerical computations-is ensured by artificially “matching” the pinchoff and triode models near VDsAr, Consequently, SPICE

the g d function is not differentiable through the saturation voltage (see Fig. 3 at VDs = 0.7 V).

was The review of this brief was arranged by Associate Editor M. Shur.

Center, Thousand Oaks, CA 91360.

predicts non physical^ changes for ( g d / ’ D ) near ‘DSAT since sand Oaks, CA 91360. He is ,,ow with the University of California, San ~ i ~ ~ ~ , cA 92093.

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