A Self-Testing Platform with a Foreground DigitalCalibration Technique for SAR ADCs
Yi-Hsiang Juan 1, Hong-Yi Huang 2, Shuenn-Yuh Lee 1, Shin-Chi Lai 3, Wen-Ho Juang 1and Ching-Hsing Luo 1,*
1 The Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan;email@example.com (Y.-H.J.); firstname.lastname@example.org (S.-Y.L.); email@example.com (W.-H.J.)
2 The Department of Electrical Engineering, National Taipei University, Taipei, 23741, Taiwan;firstname.lastname@example.org
3 The Department of Computer Science and Information Engineering, Nanhua University, Chiayi 62249,Taiwan; email@example.com
* Correspondence: firstname.lastname@example.org; Tel.: +886-6-2757575-62375; Fax: +886-6-234-548
Academic Editor: Teen-Hang MeenReceived: 29 May 2016; Accepted: 26 July 2016; Published: 29 July 2016
Abstract: This study presents a self-testing platform with a foreground digital calibration techniquefor successive approximation register (SAR) analog-to-digital converters (ADCs). A high-accuracydigital-to-analog converter (DAC) with digital control is used for the proposed self-testing platformto generate the sinusoidal test signal. This signal is then implemented using an Arduino board, andthe clock signal is generated to test the ADCs. In addition, fast Fourier transform and recursivediscrete Fourier transform (RDFT) processors are adopted for dynamic performance evaluationand calibration of the ADCs. The third harmonic distortion caused by the non-linearity of thetrack-and-hold circuit, the mismatch of the DAC capacitor array, and the direct current (DC)offset of the comparator can be calculated using the processors to improve the ADC performance.The advantages of the proposed platform include its low cost, high integration, and no need for anextra analogy compensation circuit to deal with calibration. In this work a 12 bit SAR ADC and anRDFT processor are used in the Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) 0.18 mstandard complementary metaloxidesemiconductor (CMOS) process with a sampling rate of 18.75kS/s to validate the proposed method. The measurement results show that the signal-to-noise anddistortion ratio is 55.07 dB before calibration and 61.35 dB after calibration.
Keywords: analog-to-digital converters (ADCs); digital calibration method; self-testing; successiveapproximation register ADC (SAR)
An analog-to-digital converter (ADC) is an important component in various areas, such ascommunication and biomedical systems, among others. The performance limitations of the ADCsare mainly dominated by the static and dynamic non-linearity effects, which cause the harmonicdistortion in the output power spectrum. These non-linearities slightly deteriorate the overall systemperformance, and also increase the sensitivity to the process variation and system interface noisebecause of the technology scaling into the nano-scale region. A calibration method is thus essential toensure system quality [1,2]. The successive approximation register (SAR) analog-to-digital converter(ADC) has the advantages of medium speed conversion and medium to high resolution. It is thereforevery suitable for biomedical and communication systems. With regard to the implementation of mostSAR ADCs, the performance should be maintained by the internal circuits, including the track-and-hold(T/H) circuit, the DAC capacitor array, and the comparator circuit. However, the non-linearity of
Appl. Sci. 2016, 6, 217; doi:10.3390/app6080217 www.mdpi.com/journal/applsci
Appl. Sci. 2016, 6, 217 2 of 13
the internal circuits always limits the performance of the ADCs. This is the reason why a calibrationmethod is required to overcome this problem. In this paper we focus on the digital calibration method.For example, the lookup table or the state-space technique is a common calibration method for ADCerror correction . The correction in this approach is based on a table that uses pre-calculated valuesor the slope of the input signal. However, the drawback of this method is the requirement of a largememory size, thus consuming more areas. An equalization-based digitally calibrated method isproposed in Reference . The advantage of this is the reduction of both the ADC testing time and theconvergence time. In addition, this paper utilizes the least mean squares (LMS) algorithm to correctand calibrate the ADC error, similar to that in Reference .
An internal redundancy dithering (IRD) technique is reported in Reference . The IRD methodbased on bit-weight calibration employs a pseudorandom bit sequence to determine the thresholdvalues. The method utilizes the LMS algorithm to calibrate the SAR ADC error. However, the maindrawback of the approaches in References [5,6] is that a high resolution ADC is required, which isimpractical in actual implementation. A fast-Fourier transform (FFT)-based calibration method forpipelined ADC is reported to calibrate the capacitor mismatch and non-linearity error of the operationalamplifier (OPAMP) . However, the shortcoming of the FFT process is the consumption of morepower because all frequency bins should be computed during the operation mode. Juan et al. proposedan RDFT-based calibration algorithm to overcome this problem , because the RDFT processor hasthe advantages of variable transform length, lower complexity, and less hardware cost.
In this paper, we present a self-testing platform based on previous works [7,8] to measure theADC performance using the proposed testing stimulus and compensate for the error using a simplifieddigital calibration algorithm. A 12 bit SAR ADC and an RDFT processor are implemented in theTSMC 0.18 m to verify the proposed platform. The output is analyzed using MATLAB (version126.96.36.1994 (R2008a), The MathWorks, Natick, MA, USA, 2008), including the performance calculationand ADC calibration.
2. Proposed Self-Test Platform
2.1. Conventional SAR ADC Architecture
The basic block of the traditional SAR ADC includes a track-and-hold circuit (T/H), an N-bitDAC capacitor array, a comparator circuit, and a SAR controller (Figure 1). The SAR ADC generallyuses a binary-weighted method to implement the circuit . According to the results for the switchingcapacitor array, the digital output signal can be obtained as Logical High (1) or Logical Low (0). Inaddition, some biomedical applications require an adaptive resolution using a multi-switch operatedin 8 bit or 12 bit mode . However, the non-linearity of the multi-switch in the T/H circuit will limitthe SAR ADC performance. The proposed calibration method also has the capability of eliminatingthe non-linearity and enhancing the performance of the multi-mode SAR ADC. Figure 2 depicts themulti-mode SAR ADC structure. In this, switch S2 is applied to control the two operation modes,namely the 8 bit and 12 bit modes. The bootstrapped switch is also adopted to provide a smallon-resistance with a constant value and better linearity.
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comparator circuit. However, the nonlinearity of the internal circuits always limits theperformanceoftheADCs.Thisisthereasonwhyacalibrationmethodisrequiredtoovercomethisproblem.Inthispaperwefocusonthedigitalcalibrationmethod.Forexample,thelookuptableorthe statespace technique is a common calibration method for ADC error correction . Thecorrection in thisapproach isbasedona table thatusesprecalculatedvaluesor theslopeof theinputsignal.However,thedrawbackofthismethodistherequirementofalargememorysize,thusconsumingmoreareas.AnequalizationbaseddigitallycalibratedmethodisproposedinReference.TheadvantageofthisisthereductionofboththeADCtestingtimeandtheconvergencetime.Inaddition,thispaperutilizestheleastmeansquares(LMS)algorithmtocorrectandcalibratetheADCerror,similartothatinReference.
An internal redundancy dithering (IRD) technique is reported in Reference . The IRDmethodbasedonbitweight calibration employsapseudorandombit sequence todetermine thethresholdvalues.ThemethodutilizestheLMSalgorithmtocalibratetheSARADCerror.However,themaindrawbackoftheapproachesinReferences[5,6]isthatahighresolutionADCisrequired,which is impractical in actual implementation. A fastFourier transform (FFT)based calibrationmethodforpipelinedADCisreportedtocalibratethecapacitormismatchandnonlinearityerrorofthe operational amplifier (OPAMP) . However, the shortcoming of the FFT process is theconsumptionofmorepowerbecauseallfrequencybinsshouldbecomputedduringtheoperationmode. Juan et al. proposed anRDFTbased calibration algorithm to overcome this problem ,because theRDFTprocessorhas the advantagesofvariable transform length, lower complexity,andlesshardwarecost.
Inthispaper,wepresentaselftestingplatformbasedonpreviousworks[7,8]tomeasuretheADC performance using the proposed testing stimulus and compensate for the error using asimplified digital calibration algorithm. A 12 bit SAR ADC and an RDFT processor areimplementedintheTSMC0.18mtoverifytheproposedplatform.TheoutputisanalyzedusingMATLAB (version 188.8.131.524 (R2008a), TheMathWorks, Natick,MA, USA, 2008), including theperformancecalculationandADCcalibration.
Thebasicblockof the traditionalSARADC includesa trackandholdcircuit(T/H),anNbitDACcapacitorarray,acomparatorcircuit,andaSARcontroller(Figure1).TheSARADCgenerallyuses a binaryweightedmethod to implement the circuit . According to the results for theswitchingcapacitorarray,thedigitaloutputsignalcanbeobtainedasLogicalHigh(1)orLogicalLow (0). In addition, some biomedical applications require an adaptive resolution using amultiswitchoperatedin8bitor12bitmod