A

REQUEST FOR PROPOSAL (RFP)

FOR

GaN MMIC FOUNDRY SERVICE

FOR POWER MMIC DEVELOPMENT

SPACE APPLICATIONS CENTRE

INDIAN SPACE RESEARCH ORGANISATION

GOVERNMENT OF INDIA

AHMEDABAD - 380 015

INDIA

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INTRODUCTION Space Applications Centre (SAC) is one of the major centres of the Indian Space Research Organisation (ISRO) located in Ahmedabad, Gujarat. SAC focuses on the design of space-borne instruments for ISRO missions having applications in communication, broadcasting, navigation, etc.

The GSAT/INSAT is a domestic multipurpose system, using satellites in geo‐stationary orbit, for long distance telecommunications, radio and TV program distribution, meteorological earth‐observation, data relay, search and rescue.

For fabrication of these INSAT/GSAT series Spacecrafts, the Department of Space (DOS) of the Government of India, through its SPACE APPLICATIONS CENTRE (SAC) of Indian Space Research Organization (ISRO), is planning to purchase certain spacecraft components, sub‐systems and related services. We are requesting, proposals from you for similar products and services for the INSAT/GSAT satellites for developing prototypes. It is proposed to develop the Prototype MMICs up to Ku band Amplifiers with high efficiency to be used in Communication Payloads. After the successful completion of prototype development as per this RFP, a separate requirement for FM dies through the same process may be subsequently taken up.

SAC would like to have a contract with the company to develop MMICs in order to reduce size, weight & DC power requirements of the payload, while improving the repeatability and reliability.

Space Applications Centre (SAC) of the Indian Space Research Organization (ISRO) requests your company to submit quotation for GaN MMIC on Silicon Carbide (SiC) Process(es).

This RFP is divided in Six Exhibits

Exhibit-A: Scope of work

Exhibit-B: Guidelines to Vendor

Exhibit-C: Reliability & Quality Assurance requirements

Exhibit-D: Technical Information

Exhibit-E: Quantity, Schedule and Warranty

Exhibit-F: Proprietary rights, Training and design reviews.

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EXHIBIT-A

SCOPE OF WORK

A request for proposal (RFP) for the development of Gallium Nitride (GaN) on Silicon Carbide (SiC) based power MMICS up to Ku band is invited.

Now onward in this RFP MMIC shall be considered as GaN MMIC on Silicon Carbide (SiC) process.

1. The development of MMICs through established GaN MMIC process(es) as detailed in EXHIBIT-B to EXHIBIT-F.

2. The Proprietary Rights of developed and supplied MMICs under contract will be with SAC. Vendor is required to support for 2-5 years to meet requirements of SAC. These MMICs will be used in the Prototype development of subsystems required for the Communication/Broadcast Satellite Service Payloads of INSAT/GSAT series of satellites in future.

----------END OF EXHIBIT-A-----------

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EXHIBIT-B

GUIDELINES TO VENDORS

1. GENERAL GUIDELINES:

a. The Vendor must propose an MMIC process(es) capable of meeting the feasibility of proto‐type design & development with specifications in Table D.1 of Exhibit‐D, following the work distribution arrangement as shown in Table D.2 of Exhibit‐D. Same process (es) should be able to comply the requirement of Exhibit‐C for future FM chips fabrication with similar specifications.

b. The vendors are requested to examine the RFP thoroughly and offer compliance / non-compliance point by point. In case of non‐compliance, the deviation from the specified parameter shall be furnished and for complied parameters the vendor specification (better or same) shall be provided. Vendors are also advised to give their comments with proper justification if some parameter details are to be highlighted by the vendor.

c. It is necessary for the vendor to furnish complete information as required in various exhibits of this RFP for proper evaluation and assessment of the proposal.

d. The vendor can attach additional information, if any, which may provide more information on these products.

e. The vendor may seek clarifications, if any, in advance before submitting the quotations. However, any clarification thus sent to the vendor will also be sent to all other vendors.

2. GUIDELINES FOR GaN MMIC DEVELOPMENT: 2.1 Introduction

Vendor is required to provide complete details on possibility of achieving specifications with the proposed process. This should be supported along with the details of so far developed MMICs or subsystems built around the developed MMICs by the vendor. The term development of MMICs includes providing the foundry process design kit, training to SAC, Mask making, Wafer fabrication, RF & DC on‐wafer testing, Chips visual inspection, dicing and delivery of dice .

2.2 Vendor is required to submit proposal along with following.

a. Foundry has to provide training to SAC on design of MMICs using component library, based on

its foundry and technology at Vendor site. SAC has design & development experience in discrete

devices, MIC and MMICs using softwares like ADS.

b. SAC will design all MMICs proposed in the RFP. These designs are required to be reviewed

and approved jointly by the foundry and SAC.

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c. Foundry is then responsible for fabrication, testing, dicing and shipment of all MMICs, in

this Prototype phase.

 2.3 Design Verification & Prototype Mask, Wafer Fabrication along with on Wafer

Tests:

a. After the award of contract, the vendor will develop the proposed MMICs designed by SAC.

The Design Review shall be held soon after the completion of design. RF analysis & Yield

analysis along with variations expected due to temperature and process drift should be clearly

brought out. The effect of off‐chip component (if any) on the RF performance of individual

MMIC has to be emphasized.

b. After completion of PDR (Preliminary Design Review) the MMIC designs from SAC (arranged

in reticule(s)) will be sent to foundry. Wafer will be fabricated using Mask. On‐wafer test

results (table - B.3) should be made available to SAC for the pre study from the integration

point of view.

c. After the satisfactory completion of On-wafer testing and visual inspection (VI), each

type of MMIC (as shown in Table D.1) need to be diced and delivered in two different

waffle packs (classified as Known Good Dies (KGD) and remaining dies separately).

KGD definition is mentioned in Exhibit C, paragraph 6. 

 3. GUIDELINES FOR PREPARING TECHNICAL DETAILS: a. Vendor is required to quote for fabrication of MMICs and subsequent characterization and

testing of all the electrical parameters, as given in EXHIBIT C & EXHIBIT B.

b. Yield estimation including process (es) yield should be indicated. Details may be provided during design review.

Vendor is also required to include in proposal; training to SAC engineers on design, development, fabrication process (es) and testing of MMIC at SAC, along with details mentioned in EXHIBIT F. Other relevant topics may also be included.

c. Vendor shall include details of the process (es) used, previous data of similar developmental activities undertaken by the foundry and list of users to whom they have supplied similar products.

d. Two/Three SAC personnel will visit the foundry for on wafer testing and Critical Design Review (CDR)

e. Maximum tile size is to be provided.

f. Test Parameter Matrix for all MMICs as detailed in Table B.3

g. It is necessary for the vendor to furnish compliance for all the Exhibits along with all supporting documents.

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h. The vendor can attach additional information, if any, which may provide more information on these products.

4. GUIDELINES FOR PREPARING QUOTATIONS: 4.1 The quotation shall include in addition to unit cost all the prices towards

screening. The cost break up should have format as shown below in Table B.1.

Table B.1: Prototype Phase

Table B.1-A

PROTOTYPE PHASE - Pizza wafer runs, of 4" wafer Sr. No. Item Qty/Duration Cost

1. Training at Vendor Site (2 to 4 Persons) Four Days

2.

Design Consultancy including assistance to issues related to design, simulation, device models, DRC etc through email/ Telephone/ video lecture.

50 hours

3. PDR (Preliminary Design Review) Per quarter wafer 4. Mask making of Pizza wafer of quarter size per quarter wafer 5. Mask making of 1/8 Pizza wafer per 1/8 pizza wafer 6. Pizza wafer Fabrication of quarter size per quarter wafer 7. Pizza wafer Fabrication of 1/8 size per 1/8 pizza wafer

8. Pizza wafer of quarter or 1/8 wafer size , DC & RF testing at ambient conditions (Refer Table B.3)

Typical two types of circuits

9. SAC participation in pizza wafer testing and Critical Design Review (CDR)

Per participation

10. Pizza wafer inspection, dicing, packaging and supply

Per quarter Pizza wafer /

Total Prototype MMICs development cost -1

Table B.1-B

PROTOTYPE PHASE - Full wafer (4") runs Sr. No. Item Qty/Duration Cost

1.

Design Consultancy including assistance to issues related to design, simulation, device models, DRC etc through email/ Telephone/ video lecture.

50 hours

2. PDR (Preliminary Design Review) Per wafer 3. Mask making of full wafer Per wafer 4. Full Wafer Fabrication Per wafer

5. Cost of customized test Probe (deliverable if ordered)

In slabs of 1-2 3-10

6. On wafer DC & RF testing of full wafer at ambient conditions. (Refer Table B.3)

Typical eight types of Circuits

7. On wafer testing at +85⁰C (Refer Table B.3) (OPTIONAL)

Typical eight types of Circuits

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8. SAC participation in wafer testing and Critical Design Review (CDR)

Per participation

9. SEM test (Refer TABLE-C.3) (OPTIONAL) Per die

10. Wafer inspection, dicing, packaging, documentation and supply

Per wafer

Total Prototype MMICs development cost-2 Note : -

i. Pizza Wafers and full wafer fabrication shall be loaded sequentially. ii. SAC reserves the right to include / exclude the items in final order.

iii. Quotations for one/ two or three pizza of 1/8wafer, quarter wafer and one or two full wafer may be fabricated.

iv. Each items in table B.1-A & B shall be quoted independently. 4.2 The quotation shall consist of two parts: a. PART‐1: “Detailed Technical Proposal” giving all details as required in Exhibit – B to Exhibit

-F and payment terms without Disclosing the Cost. b. PART‐2: “Cost & Management Proposal” giving cost, payment terms and other financial

details. Note: Part‐2 shall be submitted in a separate sealed envelope. THIS REQUIREMENT SHALL BE STRICTLY ADHERED. However both parts shall be submitted together in a sealed envelope. 5. DESIGN GUIDELINES TO FOUNDRY 5.1 Choice of Foundry

It will be based on the following considerations

a. The foundry shall offer the latest and established GaN wafer fabrication process (es) for the realization of MMICs. Foundry shall have an MMIC technology (with operating frequency ≥ 18 GHz) designed specifically for high efficiency power applications and processes necessary for the realization of high power amplifiers in CW mode of operation. Foundry shall refer & comply with Table B.2 before suggesting a suitable MMIC process (es).

Table B.2: Process Parameter@25DegC

S.No. Process Parameter Specifications @

25° C

1. Operational frequency ≥ 18 GHz

2. Trans‐conductance,Gm @ 12 GHz ≥ 300 mS/mm

3. Saturation Current, Idss ≥ 800 mA/mm

4. RF output at 12 GHz at 3‐dBcompression point

≥ 4 W/mm

5. PAE at 12 GHz at 3‐dB ≥ 50 %

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compression point

6. Drain-Source break down voltage

(VBDS), > 3 times Vds (Operating)

7. i. Precision low TCR Resistor ii. High Sheet Resistivity Resistors

iii. Spiral Inductors iv. MIM Caps

Vendor to specify Vendor to specify Vendor to specify Vendor to specify

8. Metal layer interconnects ≥2

9. i. Via-holes ii. Air bridges

Required Required

10. i. Wafer diameter ii. Maximum tile size

Vendor to specify Vendor to specify

11. i. Linear & Non Linear scalable models for active devices,

ii. Scalable models for passives components,

iii. Auto‐Layout generation capability from Schematic & vice‐versa,

iv. Data for statistical analysis, v. RF/DC Pads, dicing streets, text tools, vi. Substrate definition for EM

simulation, vii. DRC compatible with ADS

viii. Electro- Thermal model/data(if available)

Required

b. The software libraries being used should be compatible with ADS-2012 (or above) and these

shall be made available to SAC with layout of library components. c. Following standard library components should be available: Resistors, Capacitors, Inductors,

Transistors, via holes, Air bridges, Transmission lines, bonding wires, RF & DC pads, dicing streets, text tools, etc.]

d. Small signal and large signal (at various bias points) models of all active components (e.g.

transistors) based on measurement results should be provided. e. The model should include noise, temperature, power, electro-thermal model (preferable)

& process variation data. The models should be valid from DC to fT. f. Thermal data to estimate the channel temperature should be provided. g. The technological details for air bridges or via holes for grounding is to be clearly brought out

by the vendor if they are used in wafer fabrication process.

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5.2 Design Variations / test structure

It is proposed that at least two design variations, for all MMIC circuit architectures, may be submitted for manufacturing. Additionally, test structures of the most sensitive/critical passive and active circuit elements and/or sub‐parts shall be inserted in the tile to increase diagnostic possibilities after the first design iteration.

a. EM‐Simulation Data :

The foundry shall provide the complete substrates parameters required for EM‐Simulation. These parameters should be compatible to ADS-2012 (or above) for complete EM‐simulation.

b. Extracted Circuit :

The vendor should provide the extracted circuit of the final layout. Its format should be compatible with standard design software like ADS-2012(or above).

c. Temperature/Process variation/Supply voltages dependence:

The dependence on temperature, process variation and supply voltages of the main parameters shall be simulated using foundry data or measured data from tests components. SPC (Statistical Process Control) data of the foundry should be made available in the PDK.

d. Design reviews :

Design and layout review shall be held between the Foundry and the SAC, when appropriate. Foundry should suggest any precaution or special requirements to be taken while simulating the designs using PDK/models in order to prevent any deviations from simulation to measurement results. However, Foundry & SAC jointly will come up with a report comparing the simulated & measured results with insight into the deviations (if any).

 e. Thermal analysis:

The maximum channel (or junction) temperature shall be computed for the maximum base‐plate temperature (operating temperature range). Method of calculating channel temperature and Rth is to be provided. For suggested MMICs, characteristics of the MMICs (e.g. power dissipation) shall be analyzed. The foundry shall suggest a suitable procedure for chip attachment to ensure best thermal performance.

 

 

 

 

 

 

 

 

 

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5.3 On-wafer testing

Table B.3: On Wafer Test Parameters (FCENTER = CENTER FRENQUENCY)

Sr No.

Type of MMICs

Nature of Tests to be done

Test Conditions

On 100% Circuits/

Wafer @ 25⁰C

Optional Separate price shall

be quoted On 5% (on min. 1)

Circuits/Wafer +85 ⁰C

1. All type of

MMICs

DC i. IDS, IGS Y Y

RF

ii. Gain, I/P & O/P Return Loss over Frequency band

Y Y iii. Gain Flatness over

band Y Y iv. Pulsed (duty cycle to

be adjusted according the DC power dissipation) Y Y

a. Type of MMICs are defined in Exhibit-D, Table D.1.

----------END OF EXHIBIT-B----------

 

 

 

 

 

 

 

 

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EXHIBIT-C

QUALITY ASSURANCE REQUIREMENTS FOR PROTOTYPE DEVELOPMENT

1. INTRODUCTION  

The fabrication processes play a crucial role in the reliability of any MMICs. As the technology for the fabrication of GaN MMICs is relatively new, it is essential that the participating manufacturer’s capabilities in terms of fabrication &testing need to be clearly identified and the reliability of all the fabrication processes as well as the MMICs thereof is established.

This document details the QA requirements, which shall be implemented for Fabrication, testing & delivery of prototype GaN MMICs.

2. QUALITY REQUIREMENTS

a. Process proposed by the vendor for the fabrication of MMIC dies as per RFP requirements, should have been evaluated/under evaluation for space/aerospace/military/Hi-rel applications thru Hi-rel testing. Supporting details are required to be supplied along with the quote.

b. It is required that MMICs are being developed continuously on proposed process and supplied to other applications like wireless communication, RADAR, military, scientific space missions etc.

Supporting details are required to be supplied along with the quote.

c. PART-A of this R & QA requirement addresses the quality requirements for prototype MMIC die. Manufacturer’s capability to meet the requirements of Fabrication, testing & delivery is required to be evaluated for the present design/prototype phase. Only after successful completion of design phase, implementation of FM production phase may be considered. As realisation of prototype and FM phases are sequential events, it is desirable that all the quality aspects required for Space grade (Flight Model) GaN MMIC die shall be properly incorporated from the prototype phase itself.

d. PART-B of this R & QA requirement addresses the quality requirements for FM MMIC die. Vendor has to provide compliance to all the requirements mentioned in PART-B in their response to this RFP. However, execution is not required for the present design phase and no commercial details are required in reference to PART-B. Execution of PART-B is required only when SAC enters into FM MMIC die production phase. Testing requirement as mentioned in part-B may be modified during FM phase.

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PART-A

RELIABILITY &QUALITY REQUIREMENTS FOR PROTOTYPE MMIC DIE

3. FOUNDRY PRE-REQUISITES  

As a pre-requisite to fabrication and testing activity of prototype MMIC, manufacturer should have adequate capability to fabricate GaN MMICs. Details as required in 3.1 & 3.2 will be required to evaluate the proposed foundry, semiconductor technology, manufacturer’s capability and heritage for the proposed dies.

Manufacturer shall give the following details of the foundry process to be used for supply of proposed MMIC die.

3.1 PROCESS CAPABILITY REQUIREMENT:  

a. GaN MMICs process shall be capable to fabricate MMIC die with the following environmental conditions:

Table-C.1

1. Storage Temperature -55°C to +150°C 2. Operating Temperature (base plate temperature) -20°C to +85°C

3. Radiation tolerance TID 150 KRads (Si)

b. LIFE & RELIABILITY:

i. Process shall be capable to fabricate the MMICs which will meet all the specification requirements over the above defined environmental specifications for minimum operating life of 18 years.

ii. For this, manufacturer shall provide test data of actual life completed/ undergoing of the proposed MMICs. The summary report/analysis shall accompany the quote.

iii. Maximum channel temperature that can be achieved through proposed process shall be supplied along with the quote.

3.2 FOUNDRY DETAILS Following details along with necessary documents/data/reports are required to be supplied along with the quote. In the absence of the details, offer is liable to be rejected.

Table–C.2 Requirement of details for the evaluation of proposed MMIC process

S.No. Description Details required 1. Foundry related i. Name of the foundry 2. Proposed

semiconductor process related

i. Proposed Semiconductor process technology details including Name of process (HEMT, PHEMT, etc.) along with main features of the process like output

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power capability / gate length and cut-off frequency 3. Foundry process

capability related i. Structures

ii. Maximum absolute ratings

4. Foundry process controls related

i. Stages at which PCMs (Process Control Monitor) are monitored

ii. PCM structure details 5. Foundry process

consistency related

i. Details about the process consistency over the multiple fabrication batches. PCM details yield & field data shall be supplied in support of this. ii. Typical annual production of GaN MMICs

6. Circuit details related

i. GaN circuits developed in general by foundry ii. Details of any other GaN circuits developed in terms of a) Complexity b) RF output power c) Gain d) (Minimum & maximum) die size with power

rating

7. Heritage details related

i. Details of the MMICs developed on proposed process and supplied to other applications like wireless communication, RADAR, military, scientific space missions etc. Generic process monitor details at foundry

8. Testing details i. Details for the Hi-rel testing done at the foundry to evaluate the proposed semiconductor process technology in terms of nature of tests and testing levels ii.. Details of life tests conducted test duration, outcome iii. Details of any typical failure mechanism

After review of the details supplied, SAC will decide suitability of the proposed part for required application as well as suitability of the manufacturer for the fabrication of GaN MMICs.

3.3 PROCESS CONTROL  

The MMICs shall be fabricated and assembled on a production line that is having well defined, controlled and repeatable processes, with adequate checks and controls to monitor and assure the quality of the fabricated units. Critical process parameters shall be identified, the data for the critical parameters shall be logged and produced, whenever necessary.

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3.4 TRACEABILITY INFORMATION  

Manufacturer shall follow an effective traceability procedure right from purchase history of parts and materials till the end-product. Traceability from wafer lot to final MMICs and vice-versa shall be maintained.

4. WAFER FABRICATION AND TEST REQUIREMENT FOR PROTOTYPE MMICs

 

Die shall be fabricated, tested and delivered as per the steps laid down in Fig.1.

Figure-1: Steps for Delivery of prototype MMIC die

5. WAFER FABRICATION CONTROL CONFORMANCE  

a. Following tests are required to be carried out on each fabricated prototype wafer as a part of wafer fabrication control conformance. Test results should be supplied to SAC for review.

TABLE-C.3: WAFER FABRICATION CONTROL

Sr. No TEST MIL-STD 883 METHOD No.

SAMPLE SIZE (failure allowed)

1. Process Control Monitor (PCM)

manufacturer’s spec manufacturer’s spec

2. SEM Inspection 2018 4 die/ wafer (0) 3. Die Thickness 5007 2 die/ wafer (0) 4. Glassivation Thickness 5007 2 die/ wafer (0) 5. Metallization Thickness 5007 2 die/ wafer (0)

Note: If Sr. no. 3, 4 & 5 of Table-C.3 is covered during SEM (Sr. no.-2 of Table-C.3) then this is not required to be repeated.

b. SEM report & photographs is a mandatory requirement however vendor may quote for the SEM inspection charges per wafer separately if required.

                  Fabrication of Prototype MMIC 

Wafer screening as per Table‐C.4 

                  Delivery of Prototype MMIC 

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c. Vendor shall specify the details regarding glassivation / passivation layer.

6. WAFER SCREENING & KGD IDENTIFICATION:  

All the fabricated wafers shall be on-wafer tested& visually inspected as per table-C.4 below. Electrical parameters shall be referred from Table-B.3:

TABLE–C.4: WAFER SCREENING

S.No. Test Test condition Sample size

(failure allowed)

1. On-wafer DC & RF probing

@ 25 degC Refer Table- B.3 of this document

for on-wafer measurement

1. On-wafer DC & RF probing(Optional)

+85 degC Refer Table- B.3 of this document

for on-wafer measurement

2. Post dicing visual inspection &

identification of KGD

MIL-STD-883, method 2010

100%(0); Note-1& Note-2

Note 1: As per the visual acceptance criteria defined in applicable test methods/standards shall be followed. Note 2: KNOWN GOOD DIE (KGD): MMIC die selected from wafers which have successfully completed wafer fabrication control conformance as per Table-C.3 as above and are meeting the requirements of visual inspection and DC & RF probing as per Table-C.4 above will form KGD.

7. MARKING AND IDENTIFICATION  

Each die shall be identified by assigning unique serial number on the exterior surface by a suitable process. Marking shall not degrade the performance of the die. The permanency of marking shall be sufficient to withstand the specified environmental conditions.

 

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PART-B

RELIABILITY &QUALITY REQUIREMENTS FOR FM MMIC DIE

Following is the requirement for FM, manufacturer’s response is required.

8. REQUIREMENT FOR FM MMIC DIE This section addresses the quality requirements for FM MMIC die. Vendor shall provide compliance to all the requirements mentioned below in their response to this RFP. However, execution is not required for the present design/prototype phase and no commercial details are required in reference to this section.

9. WAFER FABRICATION & WAFER TESTING (only compliance to be stated)

Following flow chart shows the steps to be followed during FM MMIC die serialization & testing.

Figure-2 : Steps for realization & testing of flight model MMIC die

Testing requirements for Table-C.3 & Table-C.4 to be referred from above.

10. TESTING REQUIREMENTS FOR FM MMIC DIE (only compliance to be

stated 10.1 WAFER ACCEPTANCE TESTING (WAT):

Wafer Acceptance Testing: on 10 samples per wafer after successful completion of wafer screening.

Wafer fabrication

Table-C.3

Wafer Fabrication Control

Table-C.4 Wafer Screening

Table- C.5

Wafer Acceptance Testing

Deliver Flight die and WAT samples

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TABLE-C.5: WAT REQUIREMENT

Sr. No TEST METHOD Subgroup-

1 1. Die assembly into fixtures As per manufacturer’s standard

process for hi-Rel devices 2. Initial Visual Inspection MIL 883; method 2009 3. Initial electrical tests @ 25 degC As per agreed specifications 4. Electrical tests @ maximum

operating temperatureAs per agreed specifications

5. Pre burn-in Electrical tests @ 25 degC

As per agreed specifications

6. Burn-in MIL 883; Method 1015; for 240 hours @TCH = TBD deg C

7. Post Burn-in Electrical tests @ 25 degC*

As per agreed specifications

8. Post burn-in Visual Inspection MIL 883; Method 2009

9. Drift Calculation As per agreed specifications 10. Pre- life test As per agreed specifications 11. Steady state life for 2000 hours @ TCH = TBD

deg C12. Intermediate electrical test @ 25

degC

Intermediate Visual Inspection

250 hours, 500 hours & 750 hours, 100 hours, 1500 hours As per agreed specifications MIL 883; Method 2009

13. Post life-electrical test @ 25 degC

As per agreed specifications

14. Post life Visual Inspection MIL 883; Method 2009

Sub-group 2

1. Wire bond evaluation MIL 883; 2011 2. Die shear MIL 883; 2019

----------END OF EXHIBIT-C-----------

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EXHIBIT – D

TECHNICAL INFORMATION

1. GENERAL DESCRIPTION

GaN MMIC’s are envisaged to be used in SSPAs at different frequency bands. Based on their frequency of operation, these MMICs are categorized as below:

Table D.1: Types of MMICs PART-I (PIZZA Wafer)

PART-II (Full Wafer)

S.No. Types Band Freq (GHz) Power (W)

1. MMIC-1A L 1.1-1.3 30

2 MMIC-1B 1.4-1.6 30

3. Test Structure

As per SAC requirement

S.No. Types Band Freq (GHz) Power (W)

1. MMIC-1A L 1.1-1.3 30

2 MMIC-1B 1.4-1.6 30

3. MMIC-2A S 2.1-2.3 25

4. MMIC-2B 2.4-2.6 25

5. MMIC-3A

C

3.6-3.9 20

6. MMIC-3B 3.9-4.2 20

7. MMIC-3C 4.5-4.8 20

8. MMIC-4A

Ku

10.7-11.3 4

9. MMIC-4B 11.3-11.9 4

10. MMIC-4C 11.9-12.5 4

11. Test Structure

As per SAC requirement

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Table D.2 Shows the responsibilities of SAC and the foundry.

S.No. SAC FOUNDRY

1. i. Training. ii. Supply of MMIC design library compatible to ADS2012 including statistical and temperature dependant model data. iii. Supply of DRC tools in ADS-2012. iv. The electrical models should also be valid for a range of gate and drain voltages.

2. Design of MMICs and Layout

i. DRC, ii. Electrical Rule Check with Circuit Extraction

3. Design consultancy & PDR

4. i. Simulation of Extracted circuit and final layout in GDSII. ii. On Wafer test parameter,

i. Fabrication of Mask ii. Fabrication of Wafer iii.Test method and test document. iv. On Wafer Measurement v. Thermal measurement

5. Critical Design Review

6. i. Selection of KGD ii. Delivery of Diced chips

----------END OF EXHIBIT-D-----------

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EXHIBIT-E

QUANTITY, SCHEDULE & WARRANTY

1.0 QUANTITIES

The RFP is for minimum of two wafers and an optional third wafer.

2.0. DELIVERY SCHEDULES The Time Schedule shall be as follows:

TABLE –E.1: Delivery schedule

Sr. No.

Wafer type Activity Activity

Carried by Time

Schedule Remarks

1. i. Training within 30 days from PO placement.

Foundry TA 4 Days

2. i. Design phase, MMIC design. ii. Review, DRC & acceptance

of layout SAC

TB = TA + 18 weeks

3. 

Wafer / PIZZA Wafer Fabrication 

i. Authorisation by SAC to start fabrication.  

SAC + Foundry  

T0* 

 

Per Order 

ii. Mask making   Foundry   T1 = T0+ 32 Weeks  

iii. Wafer Processing   Foundry  

iv. On wafer test & CDR  Foundry  

v. Wafer dicing, Visual inspection,  transfer to waffle trays and shipment  

Foundry  T2= T1 + 4 Weeks 

   T0* – Milestone for Liquidity Damage (LD) calculation per order   3.0 WARRANTY a. The vendor shall provide Warranty as given below: "The units supplied here upon shall be free

from any defects in material or workmanship and in accordance with the applicable specifications and drawings".

b. Vendor has to meet the standard fabrication yield for the fabricated Pizza wafers/ full wafer .

In case of any non-compliance in meeting the standard fabrication yield, wafer is to be replaced with new pizza wafer/ wafer . If there is a process failure, new wafer shall be fabricated free of cost by the vendor. LD clause shall not be applicable for new pizza wafer/ full wafer fabrication if fabricated due to process failure or in case of not meeting standard fabrication yield.

4.0 DELIVRABLES a. Delivery of diced MMIC chips, classified into KGD and remaining dies in two different waffle

packs for each type of MMICs.

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b. Test Probe (if ordered)

c. On wafer test results as per Exhibit-B, Table B.3.

5.0 LIST OF DOCUMENTS TO BE SUPPLIED ALONG WITH THE PROPOSAL

Point by point compliance to all sections of this QA requirement, with all support documents, test data etc. For any partial compliance/non-compliance/deviation from the (electrical specifications / R & QA) requirements, detailed technical justification shall be provided. Sections of RFP not specifically referred to or for which all supporting documents are not supplied shall be treated as “non-compliance”.

6.0 LIST OF DOCUMENTS TO BE SUPPLIED ALONG WITH THE DELIVERABLES

The following detailed documents, as applicable shall be made available as per the milestones mentioned below:

a. PCM data, b. Wafer fabrication control data, c. SEM Report, d. Wafer screening electrical & visual test results

7.0 PACKAGING, STORAGE & TRANSPORTATION

The following packing instructions shall apply to the deliverable MMICs: The dice shall be packaged in waffle pack, to ensure that they are isolated from electrical, mechanical and environmental damage. The dice for the MMICs shall be purged with nitrogen or evacuated, so that the MMICs are not exposed to external environment. The individual packages and the intermediate packages shall be fixed within the shipping package, which shall be resistant to mechanical shocks, humidity and dust. In addition to other mandatory shipping marking, the following additional marking shall appear on the shipping package in bold letters:

HANDLE WITH CARE ESD SENSITIVE

TO BE OPENED UNDER CLEAN ENVIRONMENT WITH ESD PROTECTION ONLY STORE IN A COOL AND DRY PLACE

----------END OF EXHIBIT-E-----------

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EXHIBIT – F  

PROPRIETARY RIGHTS & TRAINING

1.0 PROPRIETARY RIGHTS

The Developed Mask and MMICs chips will be the property of SAC and without permission of SAC it shall not be provided to third party.

2.0 TRAINING

Vendor is required to provide extensive training covering minimum following topics on ADS-2012.

a. Circuit Design, Simulation & Optimization  

Microwave circuit design techniques for MMIC based circuits, including simulation & optimization using foundry supplied library elements.

b. Device Modelling  

The training should cover detailed aspects of modelling of various active & passive devices. All transistor models should have minimum three terminals (Drain, Gate, Source pins).

c. Mask Design :  

i. CAD Layout Design ii. Design Rule Check (DRC) iii Mask Design with incorporation of PCM and general reticule design iv. Criteria of Acceptance.

 

d. Fabrication Processes Including:  

i. GaN processing technology ii. Wafer Processing

v. Wafer Probing vi. Acceptance & Rejection Criteria

v. Yield Estimation.

 

e. Testing Wafer Level as well as Dice Level:  

i. Process Control Monitor and their Measurements ii. DC Testing iii. RF Probe Station: Principle and Capability

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iv. RF on Wafer testing v. RF testing on packaged MMIC vi. Wafer fracturing.

f. Packaging:  

The training should include package considerations such as use of models for interconnections, modification of models due to close proximity of cover, simulation for coupling effects due to proximity of enclosure to circuit layout and bond wires, chip assembly, mounting and hermetic sealing of MMICs chip and packaging of various MMICs.

During the training period, sufficient time should be given for “Hands‐on” use of simulators to apply the above to real situations from the concept to design to layout to DRC checking of the some sample circuits.

 ----------END OF EXHIBIT-F-----------

 

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