A pseudo-differential current-reuse structure for opamp-sharing pipelined analog-to-digital converters

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONSInt. J. Circ. Theor. Appl. (2014)Published online in Wiley Online Library (wileyonlinelibrary.com). DOI: 10.1002/cta.1983

A pseudo-differential current-reuse structure for opamp-sharingpipelined analog-to-digital converters

Tohid Moosazadeh and Mohammad Yavari*,†

Integrated Circuits Design Laboratory, Department of Electrical Engineering, Amirkabir University of Technology,Tehran, Iran

SUMMARY

In this paper, a power efficient pseudo-differential (PD) current-reuse structure is presented to alleviate thememory effects of opamp-sharing in pipelined analog-to-digital converters. To implement the PD current-reuse structure, a switched-capacitor circuit is introduced for multiplying digital-to-analog converter, whichhas a slight modification compared with the conventional switching scheme with no power penalty. In theproposed multiplying digital-to-analog converter circuit, the common-mode offset amplification of the PDstructures is eliminated. Moreover, a PD current-reuse amplifier is developed from the telescopic structurewith an inverter-based gain-boosting circuit. The effectiveness of the proposed structure is evaluated incomparison with existing current-reuse techniques. Copyright © 2014 John Wiley & Sons, Ltd.

Received 17 July 2013; Revised 31 January 2014; Accepted 1 February 2014

KEY WORDS: current-reuse opamp-sharing structure; pseudo-differential pipelined ADCs; low-powerlow-voltage switched-capacitor circuits

1. INTRODUCTION

The pipelined analog-to-digital converter (ADC) is the most popular architecture in complementarymetal-oxide-semiconductor (CMOS) technology for high-speed and medium to high resolutionapplications [1]. Among the key building blocks in pipelined, ADCs, residue amplifiers, which areused in the multiplying digital-to-analog converter (MDAC), are the most power hungry parts [2].Therefore, various methods have been proposed to reduce the power consumption in residueamplifiers. Opamp-switching [3–5] and opamp-sharing [6,7] between two subsequent stages are themost popular techniques to reduce the power dissipation. But the former suffers from the turn ondelay and the latter from the memory effects.

The memory effects in the opamp-sharing technique come from the non-resetting amplifier summingnodes. To reduce these effects, partial opamp-sharing [8] and dual-input amplifier [9] techniques areemployed to reset the summing nodes at the cost of increased power and/or circuit complexity.Furthermore, opamp current-reuse technique [10], which uses a dual-input amplifier withcomplementary structure, can be employed to solve these effects. In this method, both amplifier inputpairs are reset to the appropriate common-mode (CM) voltage alternatively, and the memory effectsare eliminated without any additional clock phase. But the main drawback of this technique is thereduced signal swing, which decreases the opamp-sharing benefits. This problem is resolved by usinga pseudo-differential (PD) amplifier in [11]. However, the scheme used for MDAC with PD amplifierin [11] cannot overcome large input CM offset and will affect the performance of the ADC.

*Correspondence to: Mohammad Yavari, Integrated Circuits Design Laboratory, Department of Electrical Engineering,Amirkabir University of Technology, Tehran, Iran.†E-mail: [email protected]

Copyright © 2014 John Wiley & Sons, Ltd.

T. MOOSAZADEH AND M. YAVARI

The current-reuse opamp-sharing technique introduced in [10] is less power efficient than theconventional opamp-sharing structure because the opamps are shared in nonconsecutive stages. Toreduce this inefficiency, a switched bias power reduction technique is introduced in [12] at the costof increased complexity in the amplifier design.

The dual-input fully differential folded cascode amplifier in [13] uses a switching circuit to share theamplifiers between the consecutive MDAC stages with no memory effects. However, the switchingbetween the input pairs can affect the opamp transient behavior. Generally, the main drawbacks ofusing a switching part in the amplifiers of opamp-sharing technique are the turn on delay andswitches charge injection.

In this paper, a PD current-reuse structure is proposed for opamp-sharing pipelined ADCs. Aswitching scheme is presented for the MDAC to prevent the input CM offset amplification reportedin [11]. Moreover, a dual-input current-reuse PD amplifier is introduced to achieve a power efficientopamp-sharing architecture, which employs an inverter-based gain-boosting technique. A prototypepipelined ADC is designed and simulated to demonstrate the feasibility of the proposed structure.

The paper is organized as follows. In Section 2, the memory effects in opamp-sharing pipelinedADCs are described. The proposed PD current-reuse structure is explained in Section 3, andSection 4 introduces the proposed gain-boosting amplifier used in the MDAC circuit. Simulationresults for a transistor-level prototype are provided in Section 5, and finally, conclusions aregiven in Section 6.

2. MEMORY EFFECTS IN OPAMP-SHARING PIPELINED ANALOG-TO-DIGITALCONVERTERS

High-speed pipelined ADCs usually use the minimum resolution per stage to achieve the requiredspecification [14]. Minimizing the stage resolution improves the conversion rate and reduces the diearea and power dissipation in pipelined ADCs [15]. Furthermore, opamp-sharing is more effectiveon the power reduction of the ADC with low resolution stages [13]. So, a 10-bit 1.5-bit/stageopamp-sharing pipelined ADC is used as the prototype in simulations. The front-end sample-and-hold of this ADC is eliminated by using matched sampling networks in the signal paths of the firststage to reduce the power consumption. The core pipeline structure consists of eight 1.5-bit stagesfollowed by a 2-bit back-end flash ADC. Each two successive stages shares an amplifier toimplement the MDAC operation.

The single-ended implementation of the conventional opamp-sharing for capacitor flip-around(CFA) MDAC is shown in Figure 1. The CFA MDAC is selected because of its large feedbackfactor, which results in fast settling to be employed in high-speed applications [16]. During Ф2

phase, the opamp generates the output of first MDAC, Vout =Vo1, while driving the input of thesecond MDAC. In the next phase, Ф1, the opamp generates the output of the second MDAC,

Figure 1. Conventional opamp-sharing technique in 1.5-bit multiplying digital-to-analog converters.

Copyright © 2014 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2014)DOI: 10.1002/cta

A NEW MDAC AND AMPLIFIER FOR OPAMP-SHARING PIPELINED ADCS

Vout =Vo2, and drives the input of the subsequent stage. Additional switches, S1 and S2, provideswitching of the negative opamp input (the summing node) between two MDACs.

The residual charge in parasitic capacitance CP of summing node causes the memory effect becauseof the limited opamp Direct current (DC) gain, A, and hence results in nonlinearity [17]. According toFigure 1, during Ф2 (t1 interval), the opamp output is Vout=Vo1. Then, the opamp is switched fromMDAC 1 to MDAC 2 to generate Vout=Vo2 during Ф1 (t2 interval), and CP injects a charge of(�CPVo1/A) at the summing node of MDAC 2. The transfer function of MDAC 2 can be calculated as

Vo2 n½ � ¼ 1

1þ 1ACS2þCF2þCP

CF2

� CS2 þ CF2 þ CP=A

CF2Vo1 n½ � � CS2

CF2VDAC2 n½ �

� �(1)

Although VDAC2 and Vo1 are generated at different times, any signal referring to the conversion ofthe same input sample is considered with the same time index (n) for simplicity. According to therelation (1), Vo2 depends only on the current sample of Vo1 and DAC voltage, VDAC2, without anymemory effect, and the charge injected from CP causes a gain error in the transfer function [17].

Now, consider MDAC 1 when the opamp is switched from generating Vout=Vo2 duringФ1 (t2 interval)toVout=Vo1 duringФ2 (t3 interval). In this case,CP injects a charge of (�CPVo2/A) at the summing node ofMDAC 1. Then, the transfer function of MDAC 1 can be calculated as

Vo1 n½ � ¼ 1

1þ 1ACS1þCF1þCP

CF1

� CS1 þ CF1

CF1Vin n½ � � CS1

CF1VDAC1 n½ �

� �

þ︷

CP

1þ Að ÞCF1 þ CS1 þ CP

λ

Vo2 n� 1½ �

(2)

Because the Vo1 output of MDAC 1 depends on the previous sample of Vo2, a memory effect isproduced that can result in nonlinearity [17].

According to relation (2), λ≈CP/(ACF1) and so, two basic methods to reduce the memory effects areincreasing the DC gain, A, and decreasing the input parasitic capacitance, CP. However, realizing ahigh DC gain amplifier needs more power and adds in design complexity. To reduce CP, the size ofamplifier’s input transistors should be chosen small resulting in lower bandwidth and higher inputoffset voltage.

Another method to eliminate the memory effects is the resetting of the amplifier inputs resulting inλ= 0 in relation (2). An additional clock phase can be used to reset CP at the cost of a decreasedconversion rate and increased clocking complexity. The current-reuse structure is an efficientmethod to reset the amplifier inputs without any extra clock phase. In the next two sections, theproposed current-reuse scheme is presented.

3. PROPOSED PSEUDO-DIFFERENTIAL CURRENT-REUSE STRUCTURE

3.1. Current-reuse structure

Using a dual-input amplifier in the MDAC circuit is an appropriate solution to reset the summing nodeof a shared opamp with no additional clock phase [9,12,13]. Figure 2 shows an opamp-sharingstructure, which uses a dual-input amplifier in a 1.5-bit CFA MDAC for two successive stages.Capacitors CS1 and CF1 in combination with the first input pair of the amplifier, Vi1+ and Vi1� formthe first MDAC while the second MDAC comprises of capacitors CS2 and CF2 and the second inputpair, Vi2+ and Vi2�.

During Ф1, the first MDAC is in the sampling phase and the inputs Vi1+ and Vi1� are reset to Vcmi1,while the second MDAC is in the holding phase using the active inputs of Vi2+ and Vi2�. During Ф2,the situation is vice versa and the first inputs, Vi1+ and Vi1�, are the active inputs of the first MDAC in


Figure 2. Opamp-sharing with a dual-input pair amplifier.


holding phase while Vi2+ and Vi2� are reset to Vcmi2. In this phase, the second stage samples the firstMDAC output. Because with a dual-input architecture, both input pairs are reset in each clock cycle,memory effects of the opamp-sharing are eliminated (λ will be zero in (2)).

Two different implementations of a dual-input amplifier for opamp-sharing are shown in Figure 3(a)and (b). In Figure 3(a), active inputs of the amplifier are selected by switches, which are in series withinput transistors [9]. In Figure 3(b), during Ф2, the switch S1 is open, and M1,2 are the opamp activeinput pair with M3,4 as the cascode transistors. During the next phase, Ф1, this switch is closed toshort the drains of M1,2 as the cascode transistors to the tail current source. In this phase, M3,4 workas the opamp active input. It should be noted that the main drawback of both amplifiers described inFigure 3(a) and (b) is their turn on delay.

A power and area efficient dual-input amplifier with no additional turn on delay was implemented in[10] named as a current-reuse amplifier. Conceptual scheme of this current-reuse amplifier is shown inFigure 3(c), which uses complementary input pairs. Connecting the inactive input pair of this amplifierto the bias voltage in the corresponding clock phase makes them as the active load of the next input

(a) (b) (c)

Figure 3. (a) and (b) simplified scheme of dual-input amplifier used in [9] and [13], respectively, and (c) theconceptual scheme of a current-reuse amplifier.



pair. The main drawback of this current-reuse amplifier is the reduced output swing due to theadditional tail current source. To achieve a large output voltage swing with the current-reusestructure, a PD amplifier was introduced in [11]. The PD amplifier similar to the differential oneneeds a common-mode feedback (CMFB) circuit. Otherwise, any input CM offset will be amplifiedlike the input signal. It is worth mentioning that the CMFB circuit makes the CM voltage of thehigh impedance nodes to be fixed and hence suppresses the CM components of the input signal[18]. But it often degrades the frequency response of the differential path, increases the designcomplexity, and results in more power consumption. In [11], the CMFB circuit is eliminated and theinput signal CM gain is reduced to one for a 1.5-bit CFA MDAC. The MDAC proposed in [11],which has the same concept as [16], is shown in Figure 4(a). During the sampling phase, Ф1, of thisfigure, a floating interconnection is used for capacitor CS and its differential counterpart, where CF isused the same as the conventional 1.5-bit MDAC, which results in a CM gain of one. In thisstructure, a small input CM offset will not saturate the MDAC output, but it is not a reliablestructure for large CM offsets. In the next subsection, a PD MDAC is proposed to solve this problem.

3.2. Proposed 1.5-bit pseudo-differential multiplying digital-to-analog converter

To prevent the amplification of the input CM offset in a conventional 1.5-bit MDAC without using anyCMFB circuit, a structure is developed as shown in Figure 4(b). In this figure, the MDAC switched-capacitor circuit is shown without the opamp-sharing for simplicity. This structure eliminates theinput signal CM components while the MDAC output CM level is adjusted by the DAC signal,VDAC. The input signal sampling in this circuit is approximately the same as the conventionalbottom-plate sampling technique to eliminate the signal dependent charge injection. In each side ofthis differential MDAC, when Vin+ is applied to the bottom-plate of CS, Vin� is applied to the top-plate of CF and vice versa. Suppose an amplifier with an open-loop gain of A and input parasiticcapacitance of CP, then the single-ended stored charge (top side of MDAC in Figure 4(b)) in thecapacitors, Q1, at the end of Ф1 is as follows:

Q1 ¼ CPVcmi þ CS Vcmi � vinþ � Vcm � ΔVcmð Þ þ CF vin� þ Vcm þ ΔVcm � Vcmið Þ (3)

where Vcm and ΔVcm are the input signal CM level and its offset, respectively. During the amplificationphase, the capacitors CF are flipped and configured as the feedback capacitors, and DAC signals areapplied through capacitors CS. At the end of Ф2, capacitors charges, Q2, are as follows:

Q2 ¼ CS Vcmi � Voutþ=A� vdacþ � Vcmð Þ þ CF Vcmi � Voutþ=A� Voutþð ÞþCP Vcmi � Voutþ=Að Þ

(4)

(a) (b)

Figure 4. (a) The multiplying digital-to-analog converter (MDAC) circuit presented in [11] and (b) the pro-posed MDAC.



where the same CM voltage, Vcm, is assumed in DAC and input signals. By using the chargeconservation rule for Q1 and Q2 and considering vin+ =�vin�, and CS = (1 + ε)CF, we have

Voutþ ¼︷

1

1þ 1A

2þεð ÞCFþCP

CF

α

� 2þ εð Þvinþ � 1þ εð Þvdacþ � ε� ΔVcm þ 2Vcmi � Vcmf g (5)

where ε is the capacitors mismatch. By choosing Vcmi = Vcm, the proper output voltage will be as

Voutþ ¼ α 2þ εð Þvinþ � 1þ εð Þvdacþ � ε� ΔVcm þ Vcmf g (6)

For example, if ε =0.1% (10-bit resolution) and ΔVcm=50%�Vcm, (as a worse-case condition), theoutput CM offset (ε�ΔVcm) will be 0.05%�Vcm. As a result, ΔVcm is significantly attenuated at theMDAC output, and hence, it cannot change the output CM voltage where it is determined by the DACsignal CM voltage. With an ideal amplifier and matched capacitors, the relation (6) is simplified as

Voutþ ¼ 2vinþ � vdacþ þ Vcm (7)

Thus, the input signal has a gain of two while the DAC signal gain is one similar to the conventionalCFA MDAC. The feedback factor and the total capacitor used in the proposed MDAC are equal to theconventional structure. As a conclusion, the proposed structure works similar to the conventional onein terms of speed and power, but it does not need any CMFB circuit. It should be noted that in theproposed MDAC, the input and output CM voltages of the amplifier must be equal.

Generally, the amplifier offset and signal-independent charge injection in the pipelined ADCs can becorrected by redundancy and digital correction without any performance degradation [19]. In theproposed structure, the input-referred offset voltage of the amplifier is transferred to the MDACoutput similar to the conventional one. So, like the conventional MDAC, the proposed MDACshould be laid out carefully to minimize the offset voltage of the amplifier. In the proposedMDAC, not only there is no signal dependent charge injection from the sampling switches but alsosignal-independent charge injection from switches controlled by Ф1a appears as the CM voltage, andhence, they are attenuated in Ф2 clock phase.

3.3. Extension to multi-bit pseudo-differential multiplying digital-to-analog converter

The proposed switching scheme can also be extended to multi-bit MDACs. For example, a 2.5-bitMDAC with this technique is shown in Figure 5 along with its conventional counterpart. For

(a) (b)

Figure 5. A 2.5-bit multiplying digital-to-analog converters: (a) conventional and (b) implementationwith proposed switching technique (half circuit shown for simplicity and VDAC1,2,3=VDAC1+,2+,3+

�VDAC1�,2�,3�= {�1,0,1}Vref).



simplicity, Figure 5 shows the positive side of the differential structures with one differential-inputamplifier. In conventional MDAC (Figure 5(a)), all capacitors sample Vin+ during Ф1 while in theproposed MDAC (Figure 5(b)), capacitors CS1 and CS2 sample Vin+, and capacitors CS3 and CF

sample Vin� at the same clock phase. In the next phase, Ф2, in both MDACs, CF is flipped aroundand configured as the feedback capacitor and CS1, CS2, and CS3 are switched to the appropriate DACvoltage based on the stage sub-ADC digital output.

By repeating the same procedure as 1.5-bit MDAC and assuming equal CM voltage for the inputsignal and amplifier’s input, it can be shown that the proposed 2.5-bit MDAC has an output, Vout+,as follows:

Voutþ ¼ 1

1þ 1A

X3i¼1

CSiþCFþCP

CF

� 1þX3i¼1

CS;i

CF

!vinþ �

X3i¼1

CS;i

CFvDACiþ þ ε1 þ ε2 � ε3ð Þ � ΔVcm þ Vcm

( )

(8)

where CSi= (1 + εi)CF for i ∈ {1,2,3} and εi is the mismatch between the capacitors CSi and CF. So, theinput signal CM offset is appeared with a very small coefficient at the MDAC output, and for matchedcapacitors, it will be completely canceled. Although always the capacitor mismatch exist, but its smallvalue will guaranty the attenuation of the CM voltage offset at the MDAC output.

Generally, for an n-bit single-ended MDAC implemented with the proposed technique, 2n equalsized capacitors are needed. In this circuit, half of the capacitors sample Vin+ in the sampling phaseand the rest will sample Vin�. Then in the amplifying phase, one of the capacitors makes the opampfeedback, and the others switched to the appropriate DAC voltages.

4. PROPOSED CURRENT-REUSE AMPLIFIER

4.1. Conceptual schematic

Figure 6 shows the conceptual schematic of the proposed pseudo-differential current-reuse amplifier. Itcomprises of a telescopic structure, M1 to M4, and a new inverter-based gain-boosting scheme A1 andA2. Input level shifters, VLS1 and VLS2, are used to satisfy the needed condition for the proposedMDAC. In other words, with level shifters, the amplifier’s input and output CM voltages will be equal.

During Ф2, transistors M1a and M1b are the amplifier active inputs, and the gate of transistors M2a

and M2b is connected to the bias voltage, VB2. In the next phase, Ф1, their role is changed. The DCgains for Vin1 and Vin2 inputs named as Av1 and Av2, respectively, are given by

Figure 6. Conceptual schematic of the proposed pseudo-differential current-reuse amplifier.



Av;j ¼ Gm;jRout;Gm;j ¼ gm;j; j ∈ 1; 2f gRout ≈ gm3ro3ro1A1ð Þjj gm4ro4ro2A2ð Þ (9)

where A1 and A2 are the voltage gain of the boosting amplifiers and gmi and roi denote thetransconductance and output resistance of the ith transistor, respectively.

4.2. Complete circuit of the proposed amplifier

Figure 7 shows the complete circuit of the proposed current-reuse amplifier. The inverter-based gain-boosting is implemented by transistors M5 to M8. The small-signal variations at nodes X and Y are atthe same direction. So, transistors M5 with M7 and M6 with M8 form simple inverters where theirgates are level shifted with VXY voltage. The DC gain of the boosting amplifiers, A1 and A2, are asfollows:

A1 ¼ gm5 þ kgm7ð Þ ro5ð jjro7Þ;A2 ¼ kgm6 þ gm8ð Þ ro6ð jjro8Þ

k ¼ vXvY

¼ gm4ro4 þ gm6 ro6jjro8ð Þ gm4 � gm3ð Þgm3ro3 þ gm5 ro5jjro7ð Þ gm3 � gm4ð Þ

(10)

Satisfying the saturation condition for all transistors, the single-ended output voltage range in theproposed amplifier is given by

Veff 3 þ Veff 5;8 þ VTH5;8≤Vout≤VDD � Veff 4 þ Veff 6;7 þ VTH6;7

�� (11)

where Veff = (VGS�VTH), VGS, and VTH are the overdrive voltage, gate-source voltage, and thresholdvoltage, respectively. The output voltage range of the proposed amplifier is reduced by the thresholdvoltage of the regulating transistors, M5 to M8, in comparison with the PD telescopic structure.

By increasing the transistor channel length from the minimum size, the threshold voltage is firstlyincreased, and then it is decreased because of the short channel effects in nano-meter CMOStechnologies [20]. So, to prevent the output swing reduction and preserving the saturation conditionfor boosting transistors, their channel length are chosen long enough to have a low threshold voltagein the standard technology. As will be shown later, by selecting a proper channel length for boostingtransistors, 1-V peak-to-peak differential output swing is achieved in 1-V power supply with asufficient linearity.

The total input-referred thermal noise of the proposed amplifier for each active input can beapproximately calculated as

Figure 7. Proposed pseudo-differential current-reuse amplifier (M1,3 : 94.5/0.09 μm, M2,4 : 135/0.09 μm,M5,8 :30/0.54μm, M6,7 :90/0.54μm).



V2nj ≈ 8kTγ gm1 þ gm2ð Þ=g2mj; j ∈ 1; 2f g (12)

where γ is the excess noise factor in short channel transistors. So, similar to the telescopic amplifier, theactive input transistors are the dominant noise sources, and the contribution of other transistors isnegligible.

Capacitive level shifters are used at the inputs of the proposed amplifier to achieve the proper inputCM voltage and make Vcmi and Vcm equal in the proposed MDAC. During, the sampling phase of eachMDAC, the level shifter capacitors, CLS1 and CLS2, are charged to the difference of Vcm and the biasvoltage of the respective amplifier input pair (VB1 or VB2). In the amplifying phase, the gate of inputtransistors are level shifted from the input signal CM voltage. In this condition, the equivalent Gm ofthe amplifier for each input is

Gm;j ¼ gm;jCLS;j= CLS;j þ CP;j

� �; j∈ 1; 2f g (13)

where CP,j is the parasitic capacitance at the gate terminal of the input transistors. The equivalent Gm isdecreased because of the charge-sharing of the level shifter capacitors with the gate capacitance of theinput transistors. So, CLS,j >>CP,j is considered here to prevent from any gain reduction.

5. CIRCUIT-LEVEL VERIFICATION

To realize the proposed current-reuse structure, the schematic description of a 10-bit 1.5-bit/stage 100-MS/spipelined ADC is designed and simulated in a 90-nm CMOS technology with 1-V power supply.

In order to reduce the ADC power consumption further, the front-end sample-and-hold is removed.Figures 4(b) and 7 show the MDAC and amplifier architectures, respectively. By using the digitalcorrection, the offset of comparators is relaxed, and hence, capacitively coupled comparators with asimple dynamic latch [21] are employed to realize 1.5-bit sub-ADCs and 2-bit back-end flash ADC.The sampling capacitors of the first stage are chosen 0.8 pF while they are scaled down with a factorof 2 for the next four stages according to the thermal noise considerations and the matchingrequirements for 10-bit resolution. The rest stages use a 0.1 pF sampling capacitor.

The simulated DC gain and unity gain frequency of the proposed amplifier with an n-type metal-oxide-semiconductor (nMOS) input pair are 68.6 dB and 1274MHz, respectively, where they are66.9 dB and 835MHz for the p-type metal-oxide-semiconductor (pMOS) input pair. Figure 8(a)shows the open-loop frequency response of the PD opamp for each input pair.

With 1-V power supply, 1-V peak-to-peak differential output swing is considered for MDAC insimulations. The settling time with 0.1% accuracy (10-bit resolution) of the simulated MDAC foreach input pair is less than about 3.1 ns, which satisfies the ADC speed requirements. Figure 8(b)

-50

-30

-10

100

30

50

7080

Gai

n (

dB

)

Frequency (Hz)

Ph

ase

(deg

ree)

NMOS inputPMOS input

Phase

Gain

(a)

-1 0 1 2 3 4 5 6

Time (ns)

Ou

tpu

t (V

)

NMOS inputPMOS input

1 2 3 40.49

0.495

0.5

(b)

-0.1

0

0.1

0.2

0.3

0.4

0.5

102 104 106 108

-140

-120

-100

-80

-60

-40

-20

0

Figure 8. (a) Frequency response of the proposed amplifier and (b) step response of the proposed multiplyingdigital-to-analog converter in multiply-by-two mode.



shows the transient response of the MDAC when it is configured in the multiply-by-two scheme. TheMDAC total harmonic distortion with a full swing input signal is less than �64 dB at 50MS/s.

As expected, for opamp shared stages, it is better to use the nMOS input pair in the front-end stageand the pMOS input pair in the back-end stage because the accuracy requirements of the back-endstage is less than that of the front-end stage by the number of bits resolved in the front-end stage.

The ADC output power spectral density is plotted in Figure 9 for 1-V peak-to-peak and48.73046875MHz differential sinusoidal input signal. The achieved signal-to-noise and distortionratio (SNDR) and spurious free dynamic range (SFDR) are 57.05 and 65.56 dB, respectively, whilethe analog power dissipation of the ADC is 4.85mW. The achieved figure of merit (FoM) definedas FoM=Power/(fS� 2ENOB) is 83.3 fJ/conversion-step where fS is the sampling frequency andENOB= [(SNDR� 1.76)/6.02]. Figure 10(a) plots the simulated SNDR/SFDR versus the inputsignal frequency, which shows approximately the same dynamic performance for the whole inputsignal frequencies.

The simulated ADC’s SNDR and SFDR versus the input signal CM offset are also provided.Moreover, to prove the drawback of the pseudo-differential ADC in [11], another prototype 10-bit1.5-bit/stage ADC is designed and simulated. Figure 10(b) shows that the performance of the ADCin [11] is degraded for large CM offsets while the proposed structure works as well.

Table I compares several current-reuse architectures. In [9,12,13], the shared opamp uses twonMOS input pairs while the proposed structures in this study and in [10,11] use one nMOS and one

0 10 20 30 40 50-140

-120

-100

-80

-60

-40

-20

0

SNDR = 57.05dB

SFDR = 65.56dB

Input signal frequency (MHz)

PS

D (d

B)

Figure 9. Output spectrum of the simulated analog-to-digital converter.

0 10 20 30 40 50

56

58

60

62

64

66

68

Input signal frequency (MHz)

SN

DR

& S

FD

R (

dB

)

SNDRSFDR

(a)

-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.510

20

30

40

50

60

70

SN

DR

& S

FD

R (

dB

)

SNDR [11]

SFDR [11]

SNDR [this work]

SFDR [this work]

(b)

Figure 10. Dynamic performance versus (a) analog-to-digital converter input signal frequency and (b) theinput common-mode offset of this work and [11].


Table I. Comparison of current-reuse architectures.

Architecture This work [9] [10] [11]* [12] [13]

Opamp structure Telescopic Telescopic Telescopic Telescopic Foldedcascode

Foldedcascode

Consecutive stage sharing Yes Yes No Yes No YesSwitching delay No Yes No No Yes YesOutput swing loss No Yes Yes No No NoSensitivity to CM offset withoutany CMFB circuit

No Yes Yes Yes Yes Yes

Opamp circuit complexity No No No No Yes No

CM= common-mode. CMFB= common-mode feedback.*PD structure in [11] is considered here.


pMOS input pair. The dual-input amplifier in [9] has a switching delay owing to the series switches inthe amplifier architecture. In [10], the amplifier transistors are always on. But the output swing isreduced because of the additional tail current source, and it is not enough power efficient because itdoes not share the consecutive MDACs. In [11], the output swing reduction of [10] is solved. But itsuffers from the CM offset amplification. In [13], by using a switched bias circuit, the powerefficiency of [10] is increased at the cost of needing a complicated amplifier facing the switchingdelay problem. The current-reuse structure in [12] shares the consecutive MDACs, but it has theswitching delay, and also, the amplifier input swing is reduced in one of phases because of thecascode tail. The proposed structure shares the consecutive MDACs without any switching delayand output swing reduction. It achieves all advantages of [11] and also does not have the CM offsetamplification problem.

6. CONCLUSIONS

In this paper, a PD current-reuse structure is proposed to implement an efficient opamp-sharing techniquein pipelined ADCs without any memory effect. The current-reuse scheme is realized by using a PD dual-input pair amplifier with a new gain-boosting technique and a new switched-capacitor MDAC. Theproposed MDAC cancels the offset of the input signal CM voltage without needing any explicit CMFBcircuit in the amplifier. The circuit level simulation results of a prototype ADC verify the efficiency ofthe proposed PD current-reuse structure for low-power applications.

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Documents

A pseudo-differential current-reuse structure for opamp-sharing pipelined analog-to-digital converters