A physical model for random telegraph signal currents in semiconductor devicesK. Kandiah, M. O. Deighton, and F. B. Whiting

Citation: Journal of Applied Physics 66, 937 (1989); doi: 10.1063/1.343523 View online: http://dx.doi.org/10.1063/1.343523 View Table of Contents: http://scitation.aip.org/content/aip/journal/jap/66/2?ver=pdfcov Published by the AIP Publishing Articles you may be interested in Examination of the application of multiphonon models to the random telegraph signal noise in metal-oxide-semiconductor structures J. Appl. Phys. 113, 144503 (2013); 10.1063/1.4800528 A percolation model for random telegraph signals in metal-oxide-silicon field effect transistor drain current Appl. Phys. Lett. 93, 043517 (2008); 10.1063/1.2966157 Modeling random telegraph signals in the gate current of metal–oxide–semiconductor field effect transistors afteroxide breakdown J. Appl. Phys. 94, 703 (2003); 10.1063/1.1579134 Observation and modeling of random telegraph signals in the gate and drain currents of tunnelingmetal–oxide–semiconductor field-effect transistors Appl. Phys. Lett. 78, 2790 (2001); 10.1063/1.1360779 GRT model for random telegraph signals in MOSFETS AIP Conf. Proc. 466, 96 (1999); 10.1063/1.58294

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A physical model for random telegraph signal currents in semiconductor devices

K. Kandiah Rutherford Appleton Laboratory, Chilton, Oxon OXIl OQX, United Kingdom

M. O. Deighton United Kingdom Atomic Energy Research Establishment (AERE), Harwell. Oxon OXil ORA, United Kingdom

F. B. Whiting Link Analytical Ltd" High Wycombe, Bucks HPl2 38E, United Kingdom

(Received 6 February 1989; accepted for publication 24 March 1989)

The model proposed by McWhorter for low-frequency noise in metal-oxIde-semiconductor field-effect transistors (MOSFETs) assumed that the lI/spectrum was due to the sum of the Lorentzian spectra produced by modulation of the channel current by charge state transitions at traps in the adjacent oxide. Considerable evidence for the presence of such current modulation has been accumulated recently. From extensive studies of random telegraph signal (RTS) current waveform in many types of devices we present new results on the dependence of the amplitUdes and characteristic times on device geometry, bias, and temperature. Based on these results we propose a comprehensive model for the generation of R TS waveforms in semiconductor devices. The amplitUde modulation of a steady current in a device due to the trapping of a carrier at a fixed site is derived by applying an extension of Ramo's theorem. The characteristic times of the R TS are derived from the properties of the trap, the carrier concentrations, and temperature. The model is applied to the analysis ofRTS waveforms in bipolar junction transistors, junction field-effect transistors, and MOSFETs. Experimental results on the dependence of the RTS characteristics on bias and temperature provide validation of the model. It is shown that the intrinsic carrier concentration plays a dominant part in determining the characteristic times in a MOSFET in weak inversion. The problems associated with the application of standard formulas for capture when there is no spherical symmetry around the trap are discussed.

I. INTRODUCTION

Bistable current waveforms resembling a random tele­graph signal (RTS) were reported over 30 years ago.! Since then there have been numerous publications2

.-7 on such ef­

fects, usually caned burst noise, in forward and reverse bi­ased diodes, bipolar junction transistors (BJTs), and optical isolators. R TS-type waveforms have also been observed in the drain current of junction field-effect transistors (JFETs)8 and insulated gate field-effect transistors (MOS­FETs).9-11

The origin of RTS currents has been attributed to var­ious physical mechanisms. The studies of avalanche diodes suggested that they are caused by microplasmas 12 associated with dislocations in the crystal. RTS waveforms in bipolar transistors were attributed to dislocations or crystallograph­ic defects,4 generation-recombination (G-R) centers in as­sociation with metallic precipitates,13 or extensive defects near to the surface of the junction. I> It has been estabJi~hed8 that R TS drain currents in JFETs are caused by single point defects in the silicon. RTS currents in MOSFETs are attrib­uted to charge state transitions at traps in the oxide9

-11 very

close to the Si interface. The increasing interest in these phenomena stems from

recent evidence that RTS currents are the main components of low-frequency noise in IFETss and MOSFETs. 10. 14

McWhorterl5 proposed that iow-frequency noise in a MOS-

FET can be derived by summing the R TS currents caused by individual traps at the oxide interface. An understanding of the physical mechanisms responsible for R TS current modu­lations is essential for the formulation and interpretation of noise in these devices using McWhorter's model. Studies of RTS currents also provide a unique opportunity to obtain a detailed understanding of the behavior of individual electri­cally active point defects (traps).

There are many common features in the experimental data reported in the literature. We summarize these and our extensive studies in BITs, MOSFETs, and JFETs in Sec. II where the general characteristics of R TS currents and their dependence on the bias conditions and temperature are de­scribed. These results lead to the conclusion that RTS cur­rents in most Si devices are generated by traps in the 5i or near the Si-Si02 interface.

The elements ofa physical model for RTS current gen­eration in semiconductor devices are outlined in Sec. III. In Sec. IV we discuss the nature of bulk defects in silicon and of interface states and traps within the oxide. We consider the parameters which determine the mean times between charge state transitions at these defects.

The model for RTS currents is expanded in Sec. V and amplitudes are derived by using Ramo's theorem 16 and ex­tensions. 17-19 The dependence of the characteristics of RTS waveforms on the location and properties of the trap and on the device parameters including temperature are discussed.

937 J. Appl. Phys. 66 (2). i 5 July 1989 0021-8979/89/140937-12$02.40 (c) 1989 American Institute of PhysiCS 937

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Although it is not possible to ascertain the exact location and characteristics of an individual trap, it is shown that detailed studies of RTS currents and low-frequency noise as a func­tion of an parameters, especially temperature, can yield some of the properties of the trap and indicate its approxi­mate location at least in one dimension.

In Sec. VI we discuss the model with reference to the experimental data in Sec. n and present detailed results of our recent studies which validate the basis oftne model. The verification of some aspects of the model is only possible by establishing the limiting values of certain RTS characierls­tics as a function of parameters and not the specific charac­teristics due to a particular trap. Correlation phenomena and anomalies arc discussed in Sec. vn.

II. GENERAL CHARACTERISTICS OF RTS CURRENTS

A. Discovery rate

Almost all published data indicate that RTS currents are mostly seen in devices of small dimensions9

.!O.20 when they are operated at low mean currents. Although larger devices also exhibit the phenomena, the levels of thermal noise and superposition of many RTS waveforms with a wide range of amplitUdes and characteristic times make it difficult to observe them. Among large-area devices R TS waveforms are seen more often in JFETs and BJTs which have little residual low-frequency noise. They are observed more frequently in the base current of BJTs with a high h fl. than in forward biased diodes at similar junction currents. We find that more devices of a specified type, as identified by a type number, are seen to exhibit the phenomena if the ob­servations are extended over a wide range of temperature, bias, and characteristic times. A short inspection at a fixed set of conditions might yield a discovery rate of 1 % or less but a wider ranging study may well increase this to 10% or more. RTS drain currents are seen in virtu.ally every MOS­FET with a gate width of about 1 pm or less. Repeated cy­cling of temperature and other parameters does not normal­ly result in a change in the R TS characteristics but we have seen two notable instances over the past 7 years when a per­manent change of characteristic occurred during a cycled multiparameter run.

B. Amplitudes

Individual RTS waveforms show a stable amplitUde un­der fixed conditions. In junction devices the amplitUde often increases monotonically with bias current over a limited range. In forward biased junctions, particularly base cur­rents in BJTs, the amplitude is often proportional to the mean current, and therefore exponentially related to the bias voltage. The dependence of the amplitude on temperature occurs indirectly through the dependence of the bi.as current on the temperature. At or near room temperature we have seen amplitudes ranging from 0.5 fA to 100 pA in reverse biased diodes and gates of JFETs and up to a saturation value of about 200 nA in base currents of BJTs.

The amplitude ofR TS drain current in a JFET is almost independent of gate bias but increases with drain voltage up to pinchoif. 8 We have seen a wide range of amplitUdes up to

938 J. Appl. Phys., Vol. 66, No.2, 15July 1989

about 10 nA in JFETs with a nominal gate length of 4 /lm. The maximum observed amplitude is independent of gate width up to a few 100 f.Lm beyond which the RTS is not discernable above thermal noise. It may be noted that these devices have a much larger gate area than MOSFETs,9-1l point contact diodes,l tunnel devices,2!l and BJTs in which R TS currents have been observed.

In the studies of MOSFETs !!l.ll at low drain voltage and current it has been observed that the amplitude is a fixed fraction of the mean current as the bias and temperature are varied. This has also been observed in small tunnel junc­tions. 20

C. Characteristic times

For a fixed operating condition there is a random distri­bution of the dwell times in each of the two states. Experi­mental limitations favor the detection ofRTS modulation in which the two characteristic times th and t l , the mean dwell times at the higher and lower current levels, respectively, are nearly equal. We have carried out measurements ofth and t{ as a function of device parameters and operating conditions in which the ratio between the two times is as large as a few 100.

The characteristic times observed in the drain current of JFETs range from some hundreds of microseconds to about 1 s. The observable limits are set by experimental difficulties arising from other fluctuations in the drain current. The shortest times can be studied more easily ifthe device is oper­ated at a low current when the drain current noise is small.

We have seen characteristic times in the base current of BJTs, gate current of JFETs, and drain current of MOS­FETs from milliseconds to many hours. In BJTs and MOS­FETs there is a strong dependence of the characteristic times on bias and temperature. Because of the dependence of the effective bias on the temperature it requires very detailed multiparameter studies to separate the temperature effects which are independent of the bias.

Do Experimental techniques

In most of our work we have used a sampling waveform recording equipment with a sampling period variable from 1/10 s up to values limited solely by the available experimen­tal time. The shortest characteristic time in our studies is therefore about 1 s. Although noise measurements show that characteristic times down to microseconds do exist it will be shown in Sec. VI that these cannot be observed above ther­mal noise in most situations. We have studied characteristic times up to many hundreds of seconds as a function of many parameters in support of our model. In a few experiments we have observed characteristic times of about 20 h.

The device current is averaged for a time up to the sam­pling period in order to minimize noise. The bias conditions and sample temperature can be automatically cycled with high precision and the importance of these facilities will be evident from the data presented later. Amplifiers and their power supplies were thoroughly checked to ensure that they did not generate significant RTS wavefonns. The amplifiers have a fiat response from de to a few kHz. Automatic adjust-

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ment of de offset and amplifier gain are carried out prior to recording the waveform for each set of parameters since the mean current and the R TS amplitude can vary over many decades during a cycled multiparameter experiment. The amplitude resolution of the sample is 1 in 105 and RTS wave~ forms with an amplitude as small as 1/500 of the mean cur~ rent can be recorded,

Unattended runs lasting many days were necessary to obtain quantitative data on the dependence of the character~ istic times on the various parameters. Even with these long runs the standard deviations of our measurements of mean transition times ranged from 10% to 25%. Owing to the strong dependence of the R TS characteristics on the tem­perature and bias the choice of conditions which give clear single RTS waveforms for quantitative studies requires many exploratory runs.

The need to carry out exploratory recordings before committing the system to obtain quantitative data can be appreciated by studying the recording in Fig. 1 of the drain current waveform of a small MOSFET. This recording was preceded by a few minutes of visual observation in order to select parameters which gave detectable R TS modulation. It is seen that there is a superposition of two different R TS waveforms with similar amplitudes. One of them has nearly equal t hand t f of a few seconds while the other has unequal times of hundreds of seconds. Since the two R TS currents will vary independently with bias there are numerous possi­bilities for misleading results when computing the mean transition times. Our computations presented in Sec. VI and most ofthe illustrations were obtained from selected record­ings which have a single dominant R TS current.

E. Some results

Figure 2 shows the gate leakage current waveforms in a small JFET, with the source and drain connected together, at two bias voltages at a fixed temperature, This strong de~ pendence of the two characteristic times on a bias voltage is found only in a few cases of reverse biased diodes.

Figure 3 shows the recordings of the drain current of a MOSFET with a gate width of 1.5 !tm at a fixed temperature and drain voltage and at three gate voltages, The increase in drain current with gate voltage is as expected for these sub­threshold conditions. The values of th and tl are seen to change with gate voltage in opposite directions. This behav­ior is seen in most of our recordings on MOSFETs,

5

FIG. 1. Drain current waveform in a MOSFET (INJ5) with 1.5 flm gate width after preliminary optimization of bias and temperature showing su­perposition oftwo uncorrelated RTS.

939 J. App!. Phys., Vo!. 66, No.2, i 5 July 1989

, :~~~j '~. "~I '"" ,.",.oj' "'1" UO.5 W~~;tI_~ ~M'_

o - .....o....-_~_ ......... ~._~ ___ .~ --L-___ ...r--_~_->. __ _ ......... "~_>J

o 5 W Time (1000.)

FIG. 2. RTS current waveform in a JFET gate (reverse biased) showing dependence of characteristic times on bias. The amplitudes are unusually large.

Figure 4 shows the effect of source voltage with fixed gate bias and temperature in the same MOSFET. Again there is a change in the values of til and t, similar to that due to changes in gate voltage. This type of behavior is also com~ monly seen.

The effect of temperature on the R TS waveform in the same MOSFET, with the bias voltages fixed at values which make th and tl nearly equal at a temperature of 280 K, is shown in Fig, 5. It is seen that th and t, change in the same direction with temperature, This is found to be true in aU recordings even when th and t[ are widely different.

.. c

1.5

~ O.S L ,

U

Gate O. ?2V ~ Id··' .. '.3nA

TI me (1005)

FrG. 3. Effects of gate voltage on amplitUde and characteristic times in MOSFET INJ5 with fixed temperature and drain voltage.

Kandiah, Deighton, and Whiting 939

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:[ V.~-'20mV. rd~110pA FIXED Vg-O.6V, Temp.-260.BK

i:m\iir~r oL_~_~~.~ . .L-_~_.~_.~ .. '_~._;

I :~J~ij~U1f1Jlf~~ oL--b. __ ~~_~ __ .~~_.A-.. __ -'---' I ,--.l

VSE5-S0mV, Id ... 3.1nR

;r 8 0.

2 6

~-----,----~~ __ ~_~ __ ._~_~_->.--.J .5 I

Tl me (10000$)

FIG. 4. Effects of source voltage on amplitude and characteristic times in MOSFET INJ5 with fixed temperature and gate voltage.

III. THE PHYSICAL MODEL

Ramo's theorem16 states that the current induced into an electrode by an electron moving in its electric field is given by

(1)

where q is the electronic charge, E is the incremental electric field per volt due to that electrode at the point occupied by the charge, and u is the component of the velocity of the electron in the direction of the field. This is valid for any number of electrodes and irrespective of whether there is charge neutrality or space charge l

7-lQ at the point under con­sideration.

Two simple geometries give an interesting result. The first is an FET with a long channel at low drain voltage where, using the gradual channel approximation. we obtain

dl=quIL, (2)

FIG. 5. Effect of temperature on amplitude and characteristic times in MOSFET INJ5 with fixed bias voltages.

940 J. Appl. Phys., Vol. 66, No.2, 15 July 1989

where L is the channel length. A similar result is obtained17

for a lightly doped reverse biased planar diode where L is now the width of the depletion region.

The essence of the physical model for RTS current mod­ulation due to charge state transitions at a trap is that the mean charge density is unaltered, over distances greater than the screening length, when the charge is trapped. However, the current to the biasing electrode changes in the dielectric relaxation time by the magnitude given by Eq. (1) where u is taken to be the drift velocity. The current is restored to its original value when the charge is released. The lower-cur­rent state corresponds to the more negative charge state of the trap in an n-channel FET and to the more positive charge state in ap-channel FET. The dwell times t/ and th are deter­mined by the characteristics of the trap, the local charge environment, and temperature as discussed in the following section.

IV. TRANSITIONS OF CHARGE STATE AT TRAPS

The traps can be grouped into three categories accord­ing to the different physical processes involved in the capture and release of charge. They are (a) traps in the silicon, (b) traps at the oxide interface, usually caned interface states, and (c) traps within the oxide.

A. Traps in silicon

Each trap in silicon has a discrete energy level and there are about a score of types of traps which are relevant. The change of charge state can take place due to capture or emis­sion of either type of carrier. The characteristic time for emission of an electron or a hole is

te = exp (E,lkn INvc, (3)

where E t is the energy level of the trap in relation to the conduction- or valence-band edge, respectively, N is the den­sity of states in that band, Ii is the thermal velocity, and cis the capture cross section. The mean capture time for elec­trons or holes is

tc = 1!nvc, (4)

where n is the concentration of electrons or holes, respective­ly, in the vicinity of the trap.

Since the capture of an electron or the emission of a hole produce the same change of charge state, the characteristic time t for this change is given by

1/t = 1/tl + l/t2 , (5)

where I j is the characteristic time for capture of an electron and t2 is the characteristic time for emission of a hole. In many situations one of these processes will dominate except at or dose to a junction or the edge of a channel of an FET where very large changes in free-carrier densities, and there­fore in the capture times, can be achieved by changes of bias of tens of m V. A similar argument applies to the change of charge state in the opposite direction.

B. Traps In the oxide and at the interface

According to the conventional model the traps at the interface have a continuum of energy levels from one band

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edge to the other. An individual interface trap behaves in a manner identical to a trap in the silicon with emission times appropriate to its energy level and capture times determined by the electron and hole densities in the adjacent silicon.

The use ofEq. (4) when spherical symmetry around the trap cannot be assumed needs further study. In the case of an MOS interface n varies by many orders of magnitude within a distance of a few Debye lengths Ld from the interface. Similarly the component of v normal to the interface, which is an equally important parameter determining the success rate of attempts to reach the trap, varies from nearly zero to the thermal velocity in a similar distance. Since It and u ap­pear as a product in Eq. (4) we shall simply assume that the thermal velocity is used for !J but an average value over a depth of a multiple of Ld is used for n. The choice of this multiple of Ld is crucial since the average of the majority­and minority-carrier concentrations have vastly different sensitivities to this factor. The large differences between the classical solution and the self-consistent quantum mechani­cal calculations2

! for the spatial distribution of these param­eters over distances of a few nm from the interface can then bei.gnored.

We now consider those oxide traps which are accessible to carriers from an adjacent silicon region by tunneling. The characteristic time for electron tunneling is

t, = exp(2Ky)/4nvc, (6)

where y is the distance from the trap to the Si interface,

K = (2mEo) 1/2/h, (7)

m is the electron mass, Eo is the height of the oxide potential barrier, and h is the reduced Planck's constant, We shaH again assume that n is the average over a depth Ld into the Si. A similar expression applies to tunneling of holes.

It is seen that the characteristic time decreases rapidly with y. It reaches the value given by Eq. (4) for y = Yo = In( 4 )/2K, which is somewhat less than the lattice dimen­

sion. Interface traps can be defined as those oxide traps lying at a depth less than Yo which therefore also possess emission characteristics given by Eq. (3). We shall use Eq. (6) for capture times at all oxide traps including interface states.

v. CURRENT MODULATION DUE TO CHARGE STATE TRANSITIONS AT A TRAP

A. Field~effect transistors

Let us first consider the effect of the location of a trap in the Si in the direction normal to the channel on the ampli­tude ofRTS. As an extension to the use of Ramo's theorem for calculating R TS amplitudes in field-effect transistors we propose that Eq. (2) is modified for traps in the depletion or Debye (transition) region to the general form

dl=Mqu/L, (8)

where M is the ratio of the image charge in the channel to that in all other conducting regions combined due to the fixed charge at the trap and u is the average drift velocity of carriers in the region of the image charge in the channel. Clearly M = 1 when the trap is within a highly conducting channel and very nearly equal to 1 when it is in the Dcbye

941 J. Appl. Phys~, Vol. 66, No.2, 15 July i 989

region adjacent to the channel. When the trap is in the deple­tion region M will be reduced as the distance to the channel increases and will become zero when the trap is in close prox­imity to the gate or substrate.

The amplitude will also depend on the location of the trap in the source-drain direction, increasing smoothly as the trap location moves from source to drain, owing to the variation in u. As the drain voltage is increased from very small values the amplitUde for every trap location will in­crease until carrier velocity saturation takes place near the drain. The maximum amplitude in this case, due to a trap located in the pinched-down region of the channel, will be approximately qv/L where v is the thermal velocity,

At norma! temperatures the characteristic times for changes of charge state at traps in the channel wiU be domi­nated by capture of the majority carriers alternating with thermal emission of that type of carrier. The traps that will be most active at any temperature will have an appropriate energy level in the conduction half of the band in n-ehannel JFETs. It isreadily seen from Eqs~ (3) and (4) that the other two possible routes for change of charge state will be less significant for defects of any energy level.

The mean capture time of a majority carrier at a trap in the channel according to Eq, (4), assuming n = lO!I\/cm\ v = 107 em/s, and c = 10-- 14 cm2

, will be of the order of nanoseconds, The R TS current will consist of extremely short pulses occurring at a mean rate determined by the emission time given by Eq. (3). These pulses will therefore be impossi.ble to detect above thermal noise.

Traps located in the fully depleted region between the gate and the channel will undergo changes of charge state only by alternate emission of electrons and holes since the capture processes will be insignificant owing to the dearth of free carriers. R TS currents due to such traps can have neady equal values ofth and ti' for the most favorable conditions of observation, only when the energy level is very dose to mid­band and the temperatures are near or above room tempera­ture, The traps must also occupy positions close to the chan­nel at the drain end in order to maximize dI as given by Eq. ( 8). Owing to these restrictions RTS due to such traps are rarely detected.

The most important trap sites which generate observ­able RTS currents at the lower temperatures are those locat­ed in the Debye region at the boundary of the channel. lfthe local free-carrier density is of such a value that the capture time is comparable to the emission time the RTS waveform will be within normal observation times. The carrier densi­ties of interest range from 107/cm3 to lOll/em' which will give capture times ranging from 1 s to 100 ?Is. For normal doping levels this corresponds to a distance of about 2Ld in a direction normal to the channel boundary, where Ld is the Debye length. A change of gate voltage of about 0.5 V will be required to move the edge of the conducting channel by this amount in a typical JFET.

Figure 6 shows the effect of gate bias at a fixed tempera­ture on RTS drain current in a small JFET. The waveforms show the presence of two active traps at the higher bias but only one at the lower bias. The characteristic time th in the hi.gher-current state is shorter at the lower bias since the

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T:: 166K

2

XS01

VD ::: 2V

FIG. 6. Drain current RTS in an n-channel IFET. The slight forward bias on the gate for RTS at any drain current indicates that the traps are on the gate side of the channel.

ULJJLLLL o

o 10

VG "'. O.34V I

20

TIME (msecs)

carrier density is higher at the trap. The characteristic time tl is independent of bias since it is detennined by the emission characteristics ofthe trap. Such results and associated noise measurements on small-area JFETs confirmed a complete model for LF noise in JFETs8 based on RTS drain current modulations.

B. MOSFETs

Coordinate axes for MOSFETs will use x for the direc­tion of current flow, y for the direction normal to the interfa­cial plane, and z for the channel width direction. The origin will be at a point where the metallurgical source substrate junction meets the oxide interface, positive x in the direction of the substrate, and positive y into the oxide.

The amplitude ofthe RTS drain current in a MOSFET in strong inversion will be identical to that in a JFET of the same gate length for the same position ofthe trap relative to the channel. Traps in the oxide or at the interface wiH give an amplitude which is also given by Eq. (8) where

(9)

tox is the oxide thickness andy is the distance of the trap from the silicon interface. From Eq. (6) the maximum value of y will be less than 2 nrn for the longest characteristic time of interest. M is therefore very close to unity for oxide thick­nesses much greater than 2 nm.

In weak inversion the channel is not opaque to fields between the substrate and gate. Then the image of a charge trapped in or near the channel resides partly on one Of both of these electrodes. A special case is that of a trap situated at a point where the absolute magnitudes of x and yare very small. A MOSFET in weak inversion can be described as an emitter situated close to the line x = y = 0 with a width equal to the gate width Wand an average depth less than a screening length L, in the negative y direction. We use the symbol L, to emphasize the difference between this local screening length and the extrinsic or intrinsic Debye lengths

942 J. Appl. Phys., Vol. 66, No.2, 15 July 1989

30 40

La and L i • respectively. Ls has directional properties at points close to x = Y = O. Electric fields and carrier drift velocities at this junction are much greater than elsewhere. Consequently the RTS currents generated by traps in this region will have amplitudes much larger than those due to traps only one L, away in the x direction. In this percolation mode of current flow a fixed charge at a trap in the junction region will block or enhance the current flow for a width approximately equal to Ls in the z direction. The amplitude of the RTS modulation will therefore be

dI=L,IIW, ( 10)

where I is the mean drain current. The linear increase in amplitude with mean current will be maintained until the onset of strong inversion.

At very low source-drain voltages the high fields are still concentrated around the junctions even in strong inversion owing to the built-in field. Consequently the most important region for RTS is also within a distance of about L, of a junction. We shall assume that the amplitude is given by Eq. (10) with increasing current until it saturates at the value given by Eq. (l) or (2).

c. Junction devices

In forward biased devices, traps in transition regions of the junction are most important for the same reasons as de­scribed above for MOSFETs. Extending those arguments it is proposed that the amplitude of the RTS current due to traps in these regions of a planar junction with uniform CUf­

rent density over its area is

dI=L/I lA, (11 )

where A is the junction area. Clearl.y this is a small fraction of I for most junctions.

An interesting case is that of a forward biased junction with a boundary at the surface of the Si in which doping profiles are such that virtually all the current flows at the

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surface at low bias. This junction is identical to the MOS­PET source in weak inversion and the amplitude for a trap in the transition region at the surface is given by Eq. (10) where W is now the peripheral length of the junction at the surface. This will clearly give more favorable conditions for detecting the R TS modulation for any size of device for a fixed trap density. The bipolar transistor under "nonideal" low-current conditions is an important example. The modu­lation of the emitter current will be given by Eq. (10) but it would be difficult to estimate the effective h fe for the region around the trap and hence the amplitude of the RTS base current.

Junctions with large reverse bias are different from those with forward bias or small reverse bias in one impor­tant respect. With ideal structures, the electron and hole densities are never of similar magnitudes in any part of the device except in fully depleted regions where they are zero. Owing to the poor understanding of the mechanisms for cur­rent generation and the spatial nonuniformities in the cur­rent flow, we shaH not attempt to formulate the behavior of these devices. Under favorable conditions RTS amplitudes given by Eq. (10) may be expected.

VI. VALIDATION OF THE PHYSICAL MODEL

OUf RTS data has been acquired over a total recording time in excess of 8000 h during the last 7 years. Approxi­mately equal amounts of data on JFETs and MOSFETs have been accumulated. As explained in Sec. n only a very small fraction of the data is suitable for checking the quantitative predictions ofthe model. In this section we shall review some of the results presented in Sec. II and recent experiments to validate the physical model. The emphasis will be on the dependence of R TS characteristics on parameters such as device type and size and operating conditions such as bias and temperature.

A. Limits of detection

The lower limit of detection of R TS waveforms can be estimated from the background noise and the required band­width dictated by the expected characteristic times, We shall assume that we require a minimum bandwidth of about 101 t where t is the shorter of the two characteristic times. Al­though this bandwidth may be adequate to detect the pres­ence of anR TS waveform by correlation techniques it would be grossly inadequate to study the distribution of t. The smallest detectable R TS amplitude dlo in the presence of a noise current In (rms) per unit bandwidth will be about five times the rms noise, giving

(12)

The background noise will have three important compo­nents. There will be a noise current Id due to the device. Two further noise sources are introduced by the resistor R used to convert the R TS current to a voltage signal. Firstly there is the thermal noise of the resistor which is equivalent to a noise current I, given by

I r =(4kTIR)I/2. (13)

There wiH also be a noise current Ii due to the flow of the

943 J. Appl. Phys .• Vol. 66, No.2. i5 Ju.ly 1989

.; ......•.•.•.•.•. "' •.•.•. ~.y ... -0:' "," ·.·;·.~.~.·.·.v.·.·.·.·.-.; . .';·.·.<;".·.·.<;'.~.:~.;.; •••••••••••••• ~.:.:.:.:.:-:.: •• -. ••••••• >.~.~.~ ........ ;' .................... -.-... -.... ; ...... ~ ... ~ ....... -.-.. ,.} .................... ' ..... z.;.;.; ... ,: .•.•.•.•. •.·.· .. · .. -.. ;.;., ......•.•. •.·.· .... -

mean device current I through the high value resistor which will have a power spectrum proportionai to the current and to 1//

Let us use approximate expressions for the thermal or shot noise of the device as a function of operating conditions. We can then assume that the noise current in a dinde, BIT, or a MOSFET in weak inversion is given by

Jd =(2qI)liz. (4)

The thermal noise of the resistor will be negligible compared to the device noise if IR >- 2kT I q. This condition corre­sponds to the de voltage developed across the resistor by the mean device current being much greater than 50 m Vat room temperature. Extremely large values of R are not used for two reasons. The values of R to satisfy this condition for mean currents of a few fA are not readily available and the noise in these resistors due to the mean current flowing through them may become dominant. In our experiments we usually restrict JR to values between about 2 and 20 times kT I q in order to avoid these problems. In the foHowing dis­cussions we shall neglect the noise components due to the resistor.

For a diode, BlT, or a MOSFET in weak inversion we then have

(15)

This explains why RTS waveforms are in general more easily observed at low currents and long characteristic times. From Eqs. (10) and (14) we find that the ratio ofRTS amplitUde to current noise increases with current. From Eqs. (10) and (15) we derive the minimum mean current [min at which RTS can be observed:

(16)

Ls in Eqs. (10) and (16) is the value appropriate to the trap position very dose to the junction. If the junction has a sman forward or reverse bias the value of Ls will be only slightly higher than the extrinsic Debye length L d • For a junction with a large reverse bias the appropriate value of L,v could be orders of magnitude greater. This is confirmed by the nu­merous dean RTS waveforms which have been observed at mean currents much less than those expected trom using Ld corresponding to the lightly doped side of the junction in Eq. ( 16). An example of a very small amplitUde R TS is found in Fig. 2 which shows the waveform in the gate current of a JFET with a gate width of 100 p.m. Other causes of unex­pectedly large amplitUdes such a'> uncertainties in the effec­tive width Wand device processing anomalies are beyond the scope of this paper.

The thermal noise in the drain current of a JFET is ap­proximately given by

ld = (4kTg)I!Z, (17)

where g is the transconductance. The thermal noise of the load resistor R will be negligible in this case if gR >- 1. Assum­ing this condition we have from Eqs. (12) and (17)

dlo = (1000kTglt) liZ. (18)

Figure 7 is the R TS drain current in a JFET with character­istic times ofabont 1 mS using a recording bandwidth of 104

Hzo The RTS signal-to-noise ratio in this record is dose to

Kandiah, Deighton, and Whiting 943

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T = 166K

2

~ I

o

XS01

Vo::: 2V

I ~ , I r I

~~\ FIG. 7. Drain current RTS in a JFET with short characteristic times close to the limits (If detection.

Vss= -l30V

o 2 4 5

T'ME ( m.~cs)

the prediction from Eq. (18) for the measured device trans­conductance of 5 X 10-- 5 mho.

B. Discovery rate

Let us first consider drain current R TS in JFETs. Ac­cording to our model the volume of the silicon in which traps will produce large amplitude RTS is a region with a thick­ness Ls adjacent to the pinched down region ofthe channel. This has a volume WLsLx where Lx, the length of the pinched-down region, will depend on the drain voltage. If we assume that Ls = 40 nm, Lx = 500 nm, the effective volume for a JFETwith a gate width of 0.1 mm is 2 X 109 nrn3

• Defin­ing the threshold trap density Nt as that giving an average of one active trap in a device for a fixed operating condition we obtain N, = 5 X 101Icm -3 for this JFET. This defect density is below the limits of detectability of diagnostic techniques such as DLTS assuming that the channel doping density has the typical value of 1016 cm-- 3

• Measurements of low-fre­quency (LF) noise peaks as a function of gate bias12 and the present RTS studies indicate that the trap density is about 1011 em - 3 in many low-noise JFETs. We have found that R TS and noise measurements provide a good method for obtaining defect characteristics at such low densities. The energy levels of some commonly occurring defects derived from studies of LF noise in JFETs with gate widths up to 0.5 mm have been reported. 23

Traps in the oxide are the dominant sources of R TS in most enhancement mode MOSFETs. RTS currents due to bulk traps in the Si are only seen in MOSFETs when anneal­ing of implantation damage in the Si is incomplete. If the MOSFET is biased to strong inversion with a drain voltage > k T I q, the oxide traps below the whole of the gate area will experience such high carrier densities in the adjacent Si that there will be a continuum of characteristic times from nano­seconds to seconds. The number of these pulses win be so large even in small-area devices that separating the effects of individual traps from the continuum will be impossible.

944 J. Appl. Phys., Vol. 66. No.2, 15 July 1989

6 8

These conditions give a 1/fnoise spectrum. At very low drain voltage the effective volume for active

traps is reduced to the region around the junctions. These regions, in the oxide or Si, will cover an area Ls W in the interfacial plane and the threshold area trap density is then lILs W. Let us assume that all traps in the oxide have an areal density of 1010 cm-- 2 and that Ls is 40 nm. The model predicts that there will be only a single active trap, on the

average, in a MOSFET with a gate width of2S0 nm. This is in agreement with most observations. It may be noted that a JFET with a gate width nearly 1000 times as great will yield a similar discovery rate due to traps in the Si. The above assumptions will be discussed in detail under characteristic times.

The R TS discovery rate in diodes, BJTs, and gate cur­rents in JFETs varies widely and is not in line with predic­tions from the simple modeL

c. Amplitudes

In the case of JFETs the amplitude is given by Eg. (2). Since it is impossible to identify the exact location ofindivid­uaI traps in the source-drain direction it is impossible to pre­dict the pertinent value of u and hence the expected RTS amplitude for each trap. However, the maximum possible amplitude for any trap is qv/L which is dependent only on channel length and temperature for any bias condition. We have observed a wide range of amplitudes at any fixed tem­perature but none greater than this value. Values of about 0.8 qulL have been measured at 90 K. At 160 K the maximum recorded amplitude for devices with an estimated channel length of 51tm was 2.5 nA, which compares with a value of 3.5 nA derived from the above expression. In our studies of JFETs with gate widths ranging from 100 to 800 pm the maximum amplitudes were independent of gate width and bias at sufficiently high drain voltage.

We have found a wide range of R TS amplitudes in junc-

Kandiah, Deighton, and Whiting 944

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tion devices and confirmation of the model is found in the foHowing respects:

(a) With constant bias the ratio dI /1 is often found to be almost independent of temperature over the range 230 K-280 K for forward or reverse bias.

(b) At a fixed temperature dI/ lis independent of bias over a wide range. In forward bias it remained constant over many decades of mean current as reported also by other ob­servers.4,13

(c) The maximum amplitUde never exceeded that ex­pected from Eq. (2) using simple depletion width approxi­mations. For a depletion width of 100 nm in a forward biased junction and a carrier drift velocity of 107 cmls we calculate a dIof 160 nA whereas the maximum observed value is 100 nA.

The most reliable and detailed confirmation of the pre­dictions of amplitUde were obtained with MOSFETs in weak inversion. It may be noted that aU the waveforms in Figs. 3-5, for the same device, show a constant dI /1 in spite of the widely varying conditions. Figure 8 shows a typical histo­gram of the density distribution of dl I I at a temperature of 241 K with a drain voltage of20 m V for various gate voltages in a MOSFET with a nominal gate width of 1.5 {lm. The drain current varied by about 1 decade in these measure­ments of dI II. The peak at dI II = 0.014 would indicate an L, calculated from Eq. (10) of 21 nm. In a series of such measurements at different temperatures it was found that the peak value of dI II decreased from 0.016 at 236 K to 0.013 at 246 K. This effect of temperature on dl II confirms that the screening length is more closely related to the intrin­sic Debye length Li since L; decreases but the extrinsic Lcl increases with increasing temperature.

The decrease of dI I I at high currents predicted in Sec. V has also been observed by Uren, Day, and Kirton. 1O The measured peaks of dI /1 in devices with gate widths in the

<II c .2 ~ c

!f '0 t

.C! E ::J Z

120

30

40

dl -I~

J

FIG. 8. Density distribution ofRTSamplitude ratio dI I lin MOSFET INJ5 at a temperature of 241 K for various bias conditions.

945 J. Appl. Phys., Vol. 66, No.2, 15 July 1989

range 0.7-3 !tm agree with the value expected from Eq. ( 10). We have also found that, as in JFETs, the saturation value of dI is in good agreement with Eq. (2) for channel lengths up to 5 p,m.

D. Characteristic times

Most of this subsection will be devoted to an analysis of characteristic times in MOSFETs. It has been reported'>·24 that the dependence of th and tl on temperature in MOS­PETs indicates a thermally activated process with di.fferent activation energies for til and fl' The energies and capture cross sections were found to be in a wide range and, in many instances, a function of gate bias. Those papers do not report on the effect of source or drain voltage on the characteristic times. As expected from the model we find that these vol­tages play equally important parts as the gate voltage as seen in Figs. 3 and 4. For each situation it is necessary to ascertain which physical processes discussed in Sec. IV determine characteristic times.

Let us first examine the role of emission assuming the validity of Eq. (3). Using the conventional model, those in­terface states which are at midband will have the largest nearly equal values of t, and til' The emission times will be about 9 ms at 300 K rising to 0.7 sat 250 K assuming capture cross sections of 10- 15 cm- 2. We conclude that the charac­teristic times from 1s to many hundreds of seconds found by most observers cannot be determined by emission unless we assume very small capture cross sections. The shorter char­acteristic times due to emission can be observed by using appropriate bandwidths but they will have a poor RTS sig­nal-to-noise ratio.

A compelling reason for assuming that only capture processes are important is the observed dependence of t I and th on gate and source-drain bias. For low source-drain vol­tages in weak inversion, t/ and th will be nearly equal if the oxide trap is close to the metallurgical junction (x slightly positive), neglecting the differences in capture cross sections and effective masses of electrons and holes, since the average hole and electron concentrations as defined in Sec. IV will be equal. If the value of x at the trap is more negative, tl will decrease at the expense of t h, whereas for more positive val­ues of x, t/ will increase and til will decrease. Most of our experiments show that th and tl change in opposite direc­tions as a function of gate or source-drain voltage as in Figs. 3 and 4. Ralls et aC observed similar effects as a function of gate voltage. We conclude that the changes of charge state in these situations have characteristic times determined by Eq. ( 6).

Let us consider the effect of variations in y. From Eq . ( 6) we find that the characteristic time increases by a factor of 14 000 when the depth of the trap increases by 0.5 nm. The range of characteristic times studied by aU observers is about this magnitude indicating that the traps of interest lie within an oxide thickness of about 0.5 nm. It has been reported that analysis of noise measurements using McWhorter's model yielded14 a volumetric trap density of about 1017 cm-- 3 in the oxide for a range of MOSFETs. The equivalent areal density of the traps in 0.5 nm is then 5 Xl 09 cm - 2 which is nearly equal to the areal density of conventionally defined interface

Kandiah, Deighton, and Whiting 945

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states over the whole of the band gap, From Eq. (6) we have

(19)

where C is a constant;;.. 1 for a fixed trap location, nil and np are the averaged concentrations, Ve and Vh are the thermal velocities, and Ce and Ch are the capture cross sections ofthe trap for electrons and holes, respectively. We shall assume that Ce and Ch do not change with bia'i or temperature. Therefore, we expect the product (P) on the right-hand side of Eq. (19) to be independent of bias and temperature.

If the drain voltage is small we can use the thermal equi­librium value n; for the product n" np ' giving

(20)

Sincen;, ve ' and Viz will be independent of bias, we expect tht[

to remain constant for all bias conditions at a fixed tempera­ture. Figure 9 shows th , t/> and their product as a function of the source voltage at a fixed temperature, for a trap estimat­ed to have a slightly positive value of x, in good agreement with the above analysis. Systematically lower values of the product th t[ at the higher source voltages as seen here have been observed in many of our experiments. We interpret this as a failure of the assumption of thermal equilibrium since we expect nnnp to be higher than n; at a forward biased junction. Measurements of th and tl as a function of gate voltage have also confirmed that th t/ remains constant at a fixed temperature.

The intrinsic carrier concentration is given by25

ni = 3.1 (1016) T 3

/2 exp( - O.603/kT). (21)

If tht{ is measured as a function of temperature with low drain voltage it is possible to calculate the product P from Eqs. (20) and (21). Figure 10 shows plots of (th t;) 112 and p 1/2 as a function of temperature. Since there is little vari­ation in the value of P with temperature we conclude that the activation energy of Un t[) li2 is that of ni which is 0.6 eV. If we assume that C = 1 and Ce = Ch , we obtain capture cross sections of 4 X 10- 14

, which is close to accepted median val~ ues.

1000

-0.02 -0.04 -0.06 -0.08 -0.1

Vs{V)

G Ii 1$)

+ ttl (5)

I!! \ I \ h (51)

FIG. 9. Characteristic times th , t, and the product t"tl as a function of drain­source voltage in MOSFET INJ5 at 261K and gate voltage of 0.6 V.

946 J. Appl. Phys., Vol. 66, No.2, 15 July 1989

100

~ JTifh (s)

(;) IP" 10'3(cm~2) El

'1 El

-l

t (') (') 0 G (;) 1 (:) (:) 0

(:) 0

1 11 I I I 3.5 3.6 3.1 3.8

1000iT

FIG. 10. Measured values of (thtl) 1/2 and deduced values of pl/2 as func­tions of lOGO/T.

The good agreement with the model and a possible error at high source-drain voltage noted above suggested an exper­iment using forward bias between the substrate and the source and drain. The drain-source voltage of this n~channel MOSFET was kept at + 20 mV but the substrate-source voltage was slowly increased from 0 to + 0.45 V while the gate bias was reduced to maintain similar drain currents. The R TS was kept under constant observation in order to be certain that it was due to the same trap. At this forward bias voltage there is no significant current to the substrate. The characteristic times of the R TS were studied for gate voltage from + 0.4 to + 0.5 V corresponding to drain currents in the range O. 5-9 nA, with the temperature also as a variable in the range 236-256 K It will be noted that the surface poten~ tial under the gate is much lower than that at the onset of weak inversion. The activation energy of (t h t/ ) 112 was again found to be that of n;. However, the values tht/ were nearly two orders of magnitude less than those with 0 V on the substrate for the same temperature. We ascribe this to the higher value of n n n p at the increased forward bias. The low value of the product cannot be ascribed to a reduced value of C for this trap since C can only have values greater than 1.

VII. ANOMALIES

We have found satisfactory explanations of most of the observed R TS characteristics based on the physical models presented in this paper. There are some anomalous phenom­ena described in this section which are not fully understood,

The discovery rate and amplitudes ofRTS in gate cur­rents of JFETs is one example. There is good evidence that both of these are strong functions of the device geometry and the detailed layout. Large variations in these characteristics between nominally similar devices from different manufac­turers have been observed. Particularly significant are the wide range of values of dIll from less than 0.0001, which is

Kandiah, Deighton, and Whiting 946

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permitted in our model, to almost I as in Fig. 2, which is not possible from the simple interpretation ofthe model. An ex­planation is the roughness in the edges which define the sepa­ration between the gate and the source or drain at the surface leading to current crowding.

Unusual RTS waveforms with a correlation between the occupancies of charge states at different traps were first re­ported by KnottS in bipolar transistors, by Rogers, Farmer, and Buhrman2u in tunnel junctions using amorphous Nb2 Os and by Dren, Kirton, and Collins26 in MOSFETs, There are various explanations for complex behavior of traps from the Anderson negative-U effect27 to simple coulombic shielding. An example of very complex correlated RTS in the base cur­rent of a BIT is shown in Fig, 11 (a). This device also showed extremely long memory effects with very large changes in the R TS characteristics after cycling of bias and! or tempera­ture. The characteristics changed from that in Fig. 11 (a) in October 1984 to those in Figs. !l(b) and liCc) in July 1988. A large permanent change in bias for the same emitter cur­rent was also observed at the same time as the change in R TS characteristics. In the interim period there were other major changes. We have not been able to determine the reasons for the ageing effect. The most important aspect of the wave­forms in Fig. 11 is that the amplitude differences between the various levels are not identical.

The amplitudes ofRTS due to two traps in a MOSFET will. be identical if they lie in precisely the same x coordinate even though widely separated along the width of the chan­nel. Correlation will be found if the traps are well within a screening length in the direction of the width of the channel. It is necessary to distinguish between the two situations (a) when one trap is acceptor type and the other is donor type and (b) when both are of the same type.

(0 )

FIG. 11. Anomalous RTS waveforms in the base current of a bipolar tran­sistor.

947 J. AppL Phys., Vol. S6, No.2, 15 July 1989

In situation (b) coulombic effects will result in only two charge states for the pair of traps with a charged state of + or - one electronic charge of one or the other of the traps and a neutral state for the larger part of the observations. The resulting R TS waveform will have the characteristics of only two current states but alternating between two pairs of characteristic times as in Fig, 1 of Ref, 26. The large differ­ence between the characteristic times of the two traps can be ascribed to differences in the values of y of no more than a fraction of a urn. The proportion of detected R TS recordings which will show such correlation due to traps in the oxide will be L ;Na where NQ is the areal density of all traps in the interface plane.

AssumingLs = 20nmandNa = 1O lO cm- 2 wefindthat there will be correlation in 4% of R TS records. This is in reasonable agreement with the discovery rate of such events found in onr experiments and in Ref. 26.

The RTS waveforms of Fig. 3 in Ref. 26 and our Fig. 11 are probably examples of situation (a). The variations in capture times of electrons and hOles in the two pairs of states are to be expected in this case. We have also found correlated RTS waveforms in MOSFETs with a much smaller discov­ery rate oftype (a) than those of type (b) as reported in Ref. 26. The assumption that both types of correlated RTS are due to the proximity of two traps is also supported by the high rate of such events in amorphous Nb2 0 5 junctions20

which may be expected to have a high density of traps. The main anomaly in Figs. 11 (b) and 11 (c) is the large differ­ence in amplitudes between the two types ofRTS. We should note that from Ramo's theorem the amplitudes of correlated R TS may be different due to different values of x at the two traps resulting in different fields even though the separation is less than L,. The possibility of an extended defect like a dislocation at the surface of the Si causing these anomalous waveforms cannot be ignored.

VII!. CONCLUSIONS

The physical model describes the mechanisms for gener~ ation ofRTS currents and predicts the discovery rates, am­plitudes, and characteristic times as a function of device type, geometry, and operating conditions. All published work and our studies, particularly relating to MOSFETs, confirm the model in detail. We have not found experimental evidence in conflict with any major aspect of the model. The explanations of a few anomalous results require more de­tailed investigation,

The localization of active traps in MOSFETs in weak inversion to a small region close to the source or drainjunc­tion has been funy established. It has been proved that the observed temperature dependence of characteristic times in excess of about 1 s at about room temperature is entirely due to the effect of the intrinsic carrier density on the capture times at traps insi.de the oxide. The activation energy agrees with the predictions.

A full calculation of noise in MOSFETs, both depletion and enhancement mode and over a wide range of operating conditions, based on the McWhorter model using the phys­ical model proved in this paper is now feasible.

Although the experimental results are solely concerned

Kandiah, Deighton, and Whiting 947

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with Si devices the model can be applied with little change to a wide range of semiconductor devices. Emitters incorporat­ing tunneling junctions and quantum well devices are likely to provide some interesting data relevant to some of the pro­posals in this paper. The concepts of screening length and effective carrier density for capture processes where spheri­cal symmetry does not apply require further study.

ACKNOWLEDGMENTS

We would like to thank C. Carter of Plessey Optoelec­tronics for drawing our attention to spurious gate currents in JFETs and for the supply of the first samples. The MOS­FETs which provided the bulk of the data confirming our model were supplied by S. Partridge of GEe, Hirst. Stimu­lating discussions with E. Gatti, M. Kirton, M, J. Pepper, and M. J. Uren are gratefully acknowledged. The work was carried out at the Harwell laboratories of the UKAEA be­fore April 1988 and is now continuing at the Rutherford Appleton Laboratory of SERe.

ID. A. Bell. Electrical Noise (Van Nostrand. Princeton, NJ, 1960), p. 258. lW. H. Card and P. K, Chaudari, Proe. IEEE 53, 652 (1965). 'G. Giralt, J. C. Martin. and F. X. Mateu-Perez, Electron. Lett. 2, 228 (1966).

4G. Blasquez. Ph.D. thesis No. 532. Dnlv. Toulouse, 1973. 'K. F. Knott, Solid-State Electron. 21,1039 (1978). OK. F. Knott, Solid-State Electron. 23, 727 (1980). 7K. B. Cook, W. Yeh, and V. W. Ruwe, Solid-State Electron. 23, 811 (1980).

948 J. Appl. Phys., Vol. 66, No.2, 15 Ju!y 1989

"K. Kandiah, M. O. Deighton, and F. B. Whiting, in Proceedings of the 6th International Conference on Noise in Physical Systems, NBS Publication 614 (U.S. Department of Commerce, Washington, DC, 1981), p. 75.

9K. S. Ralls, W. J. Skocpol. L. D. Jackel, R. E. Howard, L. A. Fetter, R. W. Epworth, and D. M. Tennant, Phys. Rev. Lett. 52. 228 (1984).

10M. J. Uren, D. J. Day, and M. J. Kirton, App\. l'hys. Lett. 47, 1195 ( 1985).

"M. Bolin and F. Koch, in Proceedings of the Conference on Insulating Films on Semiconductors, Leuven, 1987.

12W. Schockley, Solid-State Electron. 2, 35 (1961). I3S. T. Hsu, R. J. Whitter, and C. A. Mead, Solid-State Electron. 13, 1055

(1970). 14K. Kandiah, Noise in Physical Systems and 1 If Noise 1985 (North-Hoi­

land, Amsterdam, 1986), p. 19. I5A. L. McWhorter, Semiconductor Surface Physics, edited by R. H. Kings­

ton, (University of Pennsylvania Press, PA, 1956), p. 219. HIS. Ramo, Proc. IRE 24,934 (1939). I7G. Cavalleri, E. Gatti, G. Fabbri, and V. Svelto, Nue!. Instrum. Methods

92, 137 (1971). IKB. Pellegrini, Phys. Rev. B 34,5921 (1986). \9B. Pellegrini, Alta Freqnenza LVI, 157 (1987). 20C. T. Rogers, K. R. Farmer, and R. A. Buhrman, Noise if! Physical Sys­

tems, edited by C. M. Van Vliet (World Scientific, Singapore, 1987), p. 293.

21F. Stem and W. E. Howard, Phys. Rev. 163, 816 (1967). 22e. E. Cox and K. Kandiah, ill Proceedings of the 6th International Confer­

ence on Noise in PhYSical Systems, NBS Publication 614 (U.S. Depart­mentofCommerce, Washington, DC, 1981), p. 71.

13K. Kandiah, Noise in Physical Systems and 1 /fNoise, edited by M. Savel\i, G. Lecoy, and J. P. Nougier (Elsevier, Amsterdam, ]983), p. 287.

24M. J. Kirton and M. J. Uren, App!. Phys. Lett. 48, 1270 (1986). 25E. H. Putley and W. H. Mitchell, Proc. Phys. Soc. London Sect. A 72, 193

( 1958). 26M. J. Uren, M. J. Kirton. and S. Collins, Phys. Rev. B 37,8346 (1988). 27p. W. Anderson, Phys. Rev. Lett. 34. 953 (1975).

Kandiah, Deighton, and Whiting 948

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