1
Readout circuit gain measurement Transfer function is obtained sweeping VRST voltage and measuring the output DC voltage. ܣ= ( ) () ୗୀଵ. ܣratio: ி ி = 1.08 IN AVDD VBP OUT AVSS VBN M1 M2 M3 M4 M5 FB1 FB2 C d C f C gd VRST C p IN AVDD VBP OUT AVSS VBN M1 M2 M3 M4 M5 FB1 FB2 C d C p C f C gd VRST IN AVDD VBP OUT AVSS VBN M1 M2 M3 M4 M5 FB1 FB2 VRST ¾ DC voltage Gain (bulk connected to source): ܣ= ଵା ¾ Transistor M1: source follows the gate potential: ܥ is not charged, ܥ = ܥ+ ܥ + ܥDecreasing ܥ with increasing ܥ ο ܥ =0 Æ ENC Ļ ᬆο ܥ ൎο ܥ Æ ENC Ļ ᬇο ܥ بο ܥ Æ ENC Ĺ e.g. shielding the input routing metal. Ceff [fF] C L = 6 fF: Standard source follower (SF) AVSS C f AVDD VBP OUT C gd IN M2 M1 AVSS AVSS C d C p VRST C L Sensing node signal measurement, capacitance & ENC calculation Source follower vs back bias voltage (VBB) Source follower vs source-drain follower at -6 V VBB Source-drain follower with/without shielding at -6 V VBB VBB from -1 V to -6 V: Signal amplitude increases with increasing VBB. Cluster signal is a little wider than single signal. Larger density moves to the lower cluster multiplicity. ܥ is reduced by ~ 38%. ENC decreases by ~ 22% . ¾ Measurement results with 5.9 keV X-ray from 55 Fe source˖ ~ 1640 electron/hole pairs generated in silicon. ¾ VRST = 1.3 V. ¾ Sensing node signal is calculated after gain calibration. ¾ Terms definition: Cluster: group of contiguous pixels where > ௧௦ௗ Cluster multiplicity: number of pixels in a cluster (n) Cluster signal: ௨௦௧ = σ ୀଵ Seed signal: ௦ௗ = max[ ] Single signal: = ௨௦௧ with n=1 SF and SDF: Signal amplitude is larger for the SDF circuit. Cluster signal is a little wider than single signal. The effect on the cluster multiplicity is neglect. ܥ decreases by ~ 9% for the SDF circuit. ENC decreases by ~ 25% for the SDF circuit. SDF with shielding: Signal amplitude is larger. Cluster signal is a little wider than single signal. The effect on the cluster multiplicity is neglect. ܥ decreases by ~18%. ENC increases by ~ 34%. A Novel Source-Drain Follower for Monolithic Active Pixel Sensors C. Gao b , G. Aglieri a , H. Hillemanns a , A. Junique a , M. Keil a , D. Kim c , M. Kofarago a , T. Kugathasan a , M. Mager a , C.A. Marin Tobon a , P. Martinengo a , H. Mugnier d , L. Musa a , S. Lee c , F. Reidt a , P. Riedler a , J. Rousset d , K.M. Sielewicz a , W. Snoeys a , J. W. van Hoorne a , P. Yang b a CERN, Geneva, Switzerland b Central China Normal University, Wuhan, China c Dongguk and Yonsei University, Seoul, Korea d Mind, Archamps, France [email protected] Introduction Monolithic Active Pixel Sensors (MAPS) [1] for the ALICE Inner Tracking System (ITS) upgrade [2]: ¾ MAPS advantages: lower production cost, easier assembly, good power - S/N ratio performance. ¾ Charge conversion gain (1/ ܥ ) for low power and low material budget: ן( ܥ /) for constant S/N ratio [3]. [: power consumption, ܥ : effective input capacitance, Q: input charge, S/N: signal-to-noise. ] ¾ Technology: TowerJazz 180 nm CMOS image sensor process. High resistive epitaxial layer ( ߩ>1 ߗή ). Deep pwell layer allows full CMOS circuitry in the pixel ¾ Installation during the LS2 in 2019. A novel source-drain follower: ¾ provides better charge conversion gain and power - S/N ratio performance. ¾ provides a way to estimate the capacitance of the sensor itself. ¾ Three types of readout circuits from the sensing node to the output PAD: SF with buffer: (a) SDF with buffer: M0 in (a) circuit is substituted by (b) circuit. with/without shielding the input routing metal. ¾ Deep nwell separates the periphery circuit ground from substrate. It allows the substrate back bias. Test Chip VRST SUB AVDD AVSS Pixel PixSel PixSel AVDD ColSel OUT Periphery I 0 I 1 I 3 I 2 M0 M2 M3 M4 IN D S AVSS AVSS AVSS CED spacing Pitch 8 x 8 mini matrix surrounded by dummy pixels. AVSS VBN IN D M5 M6 M7 M8 S (b) (a) Pixel layout: Collection Electrode Diameter (CED): 3 um. Spacing: 3 um. Pitch: 20 um ݒ = ݒ + ௦ଵ = ݒி+ ௦ଷ = ௦ଷ + ௦ସ + ݒி= ௦ସ + ிIN + g m1 v sg1 r o1 r o2 OUT v OUT - v sg1 g m4 v sg4 g mb4 v sb4 FB1 r o4 g m3 v sg3 FB2 r o5 r o3 + - v sg3 + - v sg4 a b c + - v i + - + - v FB2 + - v FB1 Novel source-drain follower (SDF) ݒ௦ଵ + ݒ ݒி ݎ+ ݒி ݎ+ ݒ ݎ=0 ݒ௦ଷ + ݒி ݎ+ ݒி ݒ ݎ=0 ݒ௦ସ + ݒ௦ସ ݒ௦ଵ + ݒி ݒ ݎ+ ݒி ݎ=0 ݒ ݒ = ݎ(1 + ܭ) 1+ ݎ(1 + ܭ) ݒி ݒ = ݎ ܭ1+ ݎ(1 + ܭ) ݒி ݒ = ݎ( ݎ+ ܭ) 1+ ݎ(1 + ܭ) ܭ=( + ) ݎ+ ݎή ݎTransistor M1: source and drain follow the gate potential. DC voltage Gain˖ ܥ and ܥ are not charged: ܥ = ܥ+ ܥ Shielding the input routing metal: ܥ , ܥ and ܥ are not charged, ܥ = ܥ. KVL & KCL: Source-drain follower: DC voltage gain is closer to unity Lower ܥ Lower bandwidth. Lower ENC Larger area. VBB [V] -1 -6 C eff [fF] 4.94 3.04 ENC [e - ] 65 51 Table 3. source follower vs VBB VBB = -6 V SF SDF C eff [fF] 3.04 2.76 ENC [e - ] 51 38 Table 4. SF and SDF at -6 V VBB VBB = -6 V /W /O C eff [fF] 2.27 2.76 ENC [e - ] 51 38 Table 5. SDF with and without shielding at -6 V VBB -3 dB bandwidth [MHz] SF SDF 208 125 Table 1. SF and SDF: bandwidth from simulation Conclusions ¾ MAPS achieves very low sensor capacitance. Charge conversion gain ( ) is critical for ENC and power consumption. ¾ The novel source-drain follower circuit reduces the ܥ hence increases voltage swing of sensing node, reduces ENC. ¾ The DC voltage gain of the source-drain follower is closer to unity than the one of the standard source follower. ¾ The bandwidth of the source–drain follower is smaller than the one of the standard source follower. ¾ Measurement results with 55 Fe radiation source: Standard source follower ܥ decreases by 38% and ENC decreases by 22% changing VBB from -1 V to -6 V. Source-drain follower reduces ܥ by 9% and ENC by 25% compared to the standard source follower at VBB = -6 V. Source-drain follower with shielding achieves 18% reduction of ܥ , however ENC increases by 34% at VBB = -6 V. 10th International "Hiroshima" Symposium on the Development and Application of Semiconductor Tracking Detectors, Xi'an, China References [1] H. Hillemanns et al., Radiation hardness and detector performance of new 180 nm CMOS MAPS prototype test structures developed for the upgrade of the ALICE Inner racking System, Nuclear Science Symposium and Medical Imaging Conference, Oct.27–Nov.2, 2013 Seoul. [2] ALICE Collaboration, The ALICE experiment at the CERN LHC, 2008 JINST 3 S08002. [3] W. Snoeys, ”Monolithic pixel detectors for high energy physics ”, Nucl. Instr. and Meth. A, 731 (2013), p. 125, doi:10.1016/j.nima.2013.05.073. Equivalent Noise Charge (ENC): ENC = ή ܣmean rms SF * Buffer 0.722 0.019 SDF * Buffer 0.778 0.014 Table 2. voltage gain for 8 x 8 pixels https://indico.cern.ch/event/340417/contribution/94 / e.g. a cluster of 4 pixels pwell Deep Pwell Collection electrode Deep Pwell pwell pwell pwell Deep Pwell Nwell Collection electrode Epitaxial Layer p-- P-Substrate ƽ ĸ ķ ƽ ƽ Ĺ ƽ ENC: ܥ Ļ Æ ENC Ļ ܥ ܮĹ Æ ENC Ļ

A Novel Source-Drain Follower for Monolithic Active Pixel ...€¦ · ¾MAPS achieves very low sensor capacitance. Charge conversion gain ( 5 ¼ Ð Ñ Ñ) is critical for ENC and

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Page 1: A Novel Source-Drain Follower for Monolithic Active Pixel ...€¦ · ¾MAPS achieves very low sensor capacitance. Charge conversion gain ( 5 ¼ Ð Ñ Ñ) is critical for ENC and

Readout circuit gain measurement

Transfer function is obtainedsweeping VRST voltage andmeasuring the output DCvoltage.

= ( )( ) . ratio: = 1.08

IN

AVDD

VBP

OUT

AVSS

VBN

M1

M2

M3

M4M5

FB1

FB2

Cd

Cf

Cgd

VRST

Cp

IN

AVDD

VBP

OUT

AVSS

VBN

M1

M2

M3

M4M5

FB1

FB2

CdCp

Cf

Cgd

VRST

IN

AVDD

VBP

OUT

AVSS

VBN

M1

M2

M3

M4

M5

FB1

FB2

VRST

DC voltage Gain (bulk connected to source): =

Transistor M1: source follows the gate potential:is not charged, = + +

Decreasing with increasing = 0 ENC

ENC ENCe.g. shielding the input routing metal.

Ceff [fF]

CL = 6 fF:

Standard source follower (SF)

AVSS

Cf

AVDD

VBP

OUT

Cgd

IN

M2

M1

AVSSAVSS

Cd Cp

VRST

CL

Sensing node signal measurement, capacitance & ENC calculation

Source follower vs back bias voltage (VBB)

Source follower vs source-drain follower at -6 V VBB

Source-drain follower with/without shielding at -6 V VBB

VBB from -1 V to -6 V:• Signal amplitude increases

with increasing VBB.• Cluster signal is a little

wider than single signal.• Larger density moves to the

lower cluster multiplicity.• is reduced by ~ 38%.• ENC decreases by ~ 22%.

Measurement results with 5.9 keV X-ray from 55Fe source ~ 1640 electron/hole pairs generated in silicon.VRST = 1.3 V. Sensing node signal is calculated after gain calibration.Terms definition:• Cluster: group of contiguous pixels where >• Cluster multiplicity: number of pixels in a cluster (n)• Cluster signal: =• Seed signal: = max [ ] • Single signal: = with n=1

SF and SDF:• Signal amplitude is larger

for the SDF circuit.• Cluster signal is a little

wider than single signal.• The effect on the cluster

multiplicity is neglect.• decreases by ~ 9% for

the SDF circuit.• ENC decreases by ~ 25%

for the SDF circuit.

SDF with shielding:• Signal amplitude is larger.• Cluster signal is a little

wider than single signal.• The effect on the cluster

multiplicity is neglect.• decreases by ~18%.• ENC increases by ~ 34%.

A Novel Source-Drain Follower for MonolithicActive Pixel SensorsC. Gaob, G. Aglieria, H. Hillemannsa, A. Juniquea, M. Keila, D. Kimc , M. Kofaragoa, T. Kugathasana, M. Magera, C.A. Marin Tobona,P. Martinengoa, H. Mugnierd, L. Musaa, S. Leec, F. Reidta, P. Riedlera, J. Roussetd, K.M. Sielewicza, W. Snoeysa, J. W. van Hoornea, P. Yangba CERN, Geneva, Switzerland b Central China Normal University, Wuhan, China c Dongguk and Yonsei University, Seoul, Korea d Mind, Archamps, [email protected]

IntroductionMonolithic Active Pixel Sensors (MAPS) [1] for the ALICE Inner Tracking System (ITS)

upgrade [2]:MAPS advantages: lower production cost, easier assembly, good power - S/N ratio performance.Charge conversion gain (1/ ) for low power and low material budget:

( / ) for constant S/N ratio [3].[ : power consumption, : effective input capacitance, Q: input charge, S/N: signal-to-noise. ]Technology: TowerJazz 180 nm CMOS image sensor process.

• High resistive epitaxial layer ( > 1 ).• Deep pwell layer allows full CMOS circuitry in the pixel

Installation during the LS2 in 2019.A novel source-drain follower:

provides better charge conversion gain and power - S/N ratio performance.provides a way to estimate the capacitance of the sensor itself.

Three types of readout circuits from the sensing node to the output PAD: • SF with buffer: (a)• SDF with buffer: M0 in (a) circuit is substituted by (b) circuit.

with/without shielding the input routing metal.Deep nwell separates the periphery circuit ground from substrate. It allows the substrate back bias.

Test Chip VRST

SUB

AVDD

AVSS

Pixel

PixSel

PixSel

AVDD

ColSel

OUT

PeripheryI0

I1I3

I2

M0M2

M3

M4IN

D

S

AVSS AVSS AVSS

CED spacing

Pitch

8 x 8 mini matrix surrounded by dummy pixels. AVSS

VBN

IN

D

M5

M6

M7

M8

S(b)

(a)

Pixel layout:Collection Electrode Diameter (CED): 3 um.Spacing: 3 um.Pitch: 20 um

= + = + = + + = +

IN

+gm1 vsg1 ro1

ro2

OUT

vOUT-vsg1

gm4 vsg4 gmb4vsb4

FB1

ro4

gm3 vsg3

FB2

ro5

ro3

+

-vsg3

+ -vsg4

a b c

+

-vi

+

-

+

-vFB2

+

-

vFB1

Novel source-drain follower (SDF)

+ + + = 0 + + = 0 + + + = 0

= (1 + )1 + (1 + )= 1 + (1 + )

= ( + )1 + (1 + ) = ( + ) +

Transistor M1: source and drain follow the gate potential.

DC voltage Gain

and arenot charged:= +

Shielding the input routing metal:

, and are not charged, = .

KVL & KCL:

Source-drain follower:• DC voltage gain is closer to unity• Lower • Lower bandwidth.• Lower ENC• Larger area.

VBB [V] -1 -6 Ceff [fF] 4.94 3.04 ENC [e-] 65 51

Table 3. source follower vs VBB

VBB = -6 V SF SDF Ceff [fF] 3.04 2.76 ENC [e-] 51 38

Table 4. SF and SDF at -6 V VBB

VBB = -6 V /W /O Ceff [fF] 2.27 2.76 ENC [e-] 51 38

Table 5. SDF with and without shielding at -6 V VBB

-3 dB bandwidth [MHz]

SF SDF 208 125

Table 1. SF and SDF: bandwidth from simulation

ConclusionsMAPS achieves very low sensor capacitance. Charge conversion gain ( ) is critical for ENC and power consumption.

The novel source-drain follower circuit reduces the hence increases voltage swing of sensing node, reduces ENC.The DC voltage gain of the source-drain follower is closer to unity than the one of the standard source follower.The bandwidth of the source–drain follower is smaller than the one of the standard source follower.Measurement results with 55Fe radiation source:Standard source follower decreases by 38% and ENC decreases by 22% changing VBB from -1 V to -6 V.Source-drain follower reduces by 9% and ENC by 25% compared to the standard source follower at VBB = -6 V.Source-drain follower with shielding achieves 18% reduction of , however ENC increases by 34% at VBB = -6 V.

10th International "Hiroshima" Symposium on the Development and Application of Semiconductor Tracking Detectors, Xi'an, China

References[1] H. Hillemanns et al., Radiation hardness and detector performance of new 180 nm CMOS MAPS prototype test structures developed for the upgrade of the ALICE Inner racking System, Nuclear Science Symposium and Medical Imaging Conference, Oct.27–Nov.2, 2013 Seoul.[2] ALICE Collaboration, The ALICE experiment at the CERN LHC, 2008 JINST 3 S08002.[3] W. Snoeys, ”Monolithic pixel detectors for high energy physics ”, Nucl. Instr. and Meth. A, 731 (2013), p. 125, doi:10.1016/j.nima.2013.05.073.

Equivalent Noise Charge (ENC):

ENC =

mean rms

SF * Buffer 0.722 0.019 SDF * Buffer 0.778 0.014

Table 2. voltage gain for 8 x 8 pixels

https://indico.cern.ch/event/340417/contribution/94 /

e.g. a cluster of 4 pixels

pwellDeep Pwell

Collection electrode

Deep Pwellpwell pwell pwell

Deep PwellNwell

Collection electrode

Epitaxial Layer p--

P-Substrate

ENC:• ENC • ENC