A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA)

Ratna Chakrabarty Member of IEEE,

Department of Electronics and Communication Engineering Institute of Engineering and Management,

West Bengal, India

N. K. Mandal University of Engineering and Management,

West Bengal, India

Dipak Kumar Mahato Abhisekh Banerjee

Sayantani Choudhuri Moumita Dey

Student member of IEEE, Institute of Engineering and Management,

West Bengal, India

Abstract-As the device dimension is shrinking day by day the conventional transistor based CMOS technology encounters serious hindrances due to the physical barriers of the technology such as ultra-thin gate oxides, short channel effects, leakage currents & excessive power dissipation at nano scale regimes. Quantum Dot Cellular Automata is an alternate challenging quantum phenomenon that provides a completely different computational platform to design digital logic circuits using quantum dots confined in the potential well to effectively process and transfer information at nano level as a competitor of traditional CMOS based technology. This paper has demonstrated the implementation of circuits like D, T and JK flip flops using a derived expression from SR flip-flop. The kink energy and energy dissipations has been calculated to determine the robustness of the designed flip-flops. The simulation results have been verified using QCA Designer simulation tool.

Keywords- Flip-flop; Majority gate; Quantum Dot; Kink energy; Energy Dissipation.

I. INTRODUCTION

Due to the rapid development of technology, the scenario of digital industry has changed in the past few years. Intel co-founder Gordon Moore in 1960 predicted that the number of transistors on a single chip will double in every eighteen months. According to his prediction, the conventional CMOS based devices advanced from micron to submicron, submicron to deep submicron and to nanometer regime over last five decades. But the scaling of CMOS devices at nano scale affects the performance of several factors like heat dissipation and leakage currents. The heat generated can no longer dissipate and results in damage of the chip as more and more devices are packed into the same area. So many novel technologies and materials have been extensively researched and developed at

nano scale to replace conventional transistor based VLSI technology. Among several other alternatives, Quantum Dot Cellular Automata (QCA) is a revolutionary promising transistor less quantum paradigm that performs computation and routing information at nano domain. The unique feature of QCA is that logic states are represented by a cell. A cell is a nano scale device capable of transferring data by two state electron configurations. The advantages of QCA over conventional CMOS technology include lesser delay, high density circuits and low power consumption which permits us to perform quantum computing in near future.

II. REVIEW OF QCA

The basic logic unit of Quantum Dot Cellular Automata is based on QCA cells which contain four quantum dots arranged in a square pattern. Each cell contains two mobile electrons which can tunnel quantum mechanically between dots [1-3]. Due to the mutual columbic repulsion, the electrons in quantum dots confined in the potential well will always try to occupy the two possible diametrically opposite positions of a square shaped cell[1-2][4-7]. Unlike conventional transistor logic, QCA connects the state of one cell to the state of its immediate cells by columbic interaction. The state of a cell is called its polarization defined by P [1]. Therefore, two distinct cell states exist. Figure-1 shows two possible minimum energy states of a quantum dot cell [1-2]. It is assumed that logic ‘0’ as cell

polarization P =-1 and logic ‘1’as cell polarization P=+1

Figure1: Schematic of QCA cell

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A polarization P in a cell is defined by:

P=( ) ( )

There are mainly two types of quantum cell orientations namely 45˚ and 90˚ as shown in the Figure 2.

In order to transfer information from one cell to another cell QCA wire is used [1-2][5] which is shown in Figure 3.

Logic ‘0’ Logic ‘1’

Figure 2:45 degree QCA cell

Figure 3:90 degree QCA wire

Clock is used to overcome the tunneling barriers between the adjacent quantum dots confined in the potential well within a cell for transfer of information from one clock to next clock sequentially. There are mainly two types of clocking zone clocking and continuous clocking. We performed zone clocking scheme as it is supported by QCA Designer tool [8-9]. In zone clocking, each QCA cell is clocked using a four-phase clocking scheme. The four phases correspond to switch, hold, release and relax [10][12-15] is shown in Figure 4 and Figure 5.

Figure 4:Transfer of Information through Clocking

Figure 5: Four phases of clocking

III. THE BASICS OF MAJORITY GATE

The fundamental structure of majority gate contains minimum five QCA cells to represent it [3] [12]. Four of them are in four

different directions making themselves at the angle of 90° with the nearest neighboring cells on the substrate and there is one cell which is in the middle of them, is shown in the Figure6. The Boolean expression which is suitable to represent the majority gate is –

M(A, B, P) =A.B. + A.P + B.P

Figure 6: Majority Gate in QCA

Where the first two terms A and B represent the inputs from the majority gate and P is the fixed polarization. This polarization P will vary according to the gate we want to use. For the case of AND gate P = “0”& OR gate P= “1” [3] are shown in the Figure 7.

(a) (b)

Figure 7: The fundamental structure of QCA majority gate - (a) 2- input AND gate, (b) 2- input OR gate

IV. IMPEMENTATION OF FLIP-FLOP DESIGN Flip-flops are sequential circuits whose output depends both on the present input as well as the past ouput[12].It is a one bit binary storage device capable of storing binary information ‘1’ or ‘0’.In this paper,most commonly used three types flip-flops namely D,T & JK flipflop are designed from the derived equations of SR flip-flop.

• Proposed Expression to Design All Flip-flops

Using the derived expression in equation 1 and equation 2 from the Figure 8, we can simply construct any flip-flop in a much easier way just by modifying the inputs. All the flip-flopshave been designed in this paper using the circuit as shown in the figure.The simulation results are verified by the truth table which is shown in the Table 1.

409

Figure 8: Flip flop design using NAND gate

Equation 1 and 2 are derived from figure 8 are used for the design of the other flip flops. The design of SR, D, T, JK flip flops are realized using QCA designer simulation tool in this paper.

Qb = . . = B . CLK + ……………..….(1) (Where, Qb is the inverse of Q) and Q = . . = A.CLK + = A.CLK + . . Q ….(2)

TABLE 1 : TRUTH TABLE

INPUT OUTPUT

CLK A B Q Qb 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 1 0 1 1 1 1 0

(a)

(b)

Figure 9: (a) Block with layout design of the flip-flop, (b) Simulation result

A. SR Flip-Flop

The S-R flip-flop has two inputs namely, SET(S) and RESET(R), and two outputs Q and Qbar which are complement to each other. The clock pulse input acts as an enable input to the other two inputs S and R. We have simply replaced A by S and B by R from our proposed equation to generate SR flip-flop.

(a)

(b)

(c)

Figure 10: (a) Block diagram of SR flip-flop from the proposed design, (b) Layout of SR Flip-Flop, (c) Simulation result of SR Flip-Flop

B. D Flip-Flop

The D flip-flop is called Delay (D) flip-flop as it introduces a delay between input and output. We have easily constructed D flip-flop from our proposed logic just by replacing A by D and B by which is shown in the Figure 11.

410

(a)

(b)

(c)

Figure 11: (a) Block diagram of D flip-flop from the proposed design, (b)

Layout of D flip-flop, (c) Simulation result of D flip-flop

C. JK Flip-Flop

The limitation of SR flip-flop is overcome in JK flip-flop. The inputs J and K behave as inputs S and R to set and reset the flip-flop respectively. When J=K=1, the flip-flop output toggles i.e. switches to its complement state. A JK flip-flop has been obtained from our proposed expression by adding two additional AND gates, is shown in the Figure 12.

(a)

(b)

(c)

Figure 12: (a) Block diagram of JK flip-flop from the proposed design, (b)

Layout of JK flip-flop, (c) Simulation result of JK flip-flop

D. T Flip-Flop

Another basic flip-flop, called T or trigger or toggle flip-flop has only a single data (T) input, a clock input and two outputs Q and Qb[14]. The T-type flip-flop is designed from a J-K flip-flop by connecting its J-K inputs together. The term T comes from the ability to ‘toggle’ or complement its state and are also called single input JK flip-flop. Here we have assumed inputs J and K both as T and they are tied together. Table 2 shows the brief calculation of complexity for the designed flip flops.

411

(a)

(b)

(c)Figure 13: (a) Block diagram of T flip-flop from the proposed design, (b) Layout of T flip-flop, (c) Simulation result of T flip-flop

V. COMPLEXITY OF THE PROPOSED FLIPFLOPS

TABLE 2: CALCULATIONS OF CELL COUNT, AUF, O-COST & LATENCY OF THE DESIGNED FLIP-FLOPS

QCA Structure

Length Covered

(nm)

Width Covered

(nm)

Cell Count (cells)

Operation Cost(O-Cost)

Net Area, (nm2)

Total Area, (L×W) (nm2)

Area Utilization Factor(AUF =

Net Area/ Total Area )

Latency

SR flip-flop

258

158

38

38

12,312

40,764

0.302

1.50

D flip- flop

238

178

43

43

13,932

42,364

0.328

1.25

T flip- flop

258

258

81

81

26,244

66,564

0.394

1.50

JK flip-flop

278

258

78

78

25,272

71,724

0.352

1.50

VI. EXPRESSION OF KINK ENERGY

The Kink energy is defined as the energy difference between two adjacent or neighboring cells of same or opposite polarization. We can calculate the kink energy using formula depicted in [16]

U=

Where U is the Kink energy, K is a constant given by K=1/4πε0εr=9 x 109 andQ1 & Q2 are the electronic charges and r is the distance between them. Therefore,

U= . ×

J

The variation of kink energy for the two possible combinations in the output cell for SR, D, T, JK flip-flop is plotted in the 3 dimensional graphs which are shown in Table 3.

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VI. CALCULATIONS OF KINK ENERGY

TABLE 3: CALCULATIONS OF KINK ENERGY OF THE OUTPUT CELLS OF SR, D, T, &JK FLIP-FLOPS RESPECTIVELY

Flip-flops Kink energy of Output cell 3-D plot of Total Kink energy (Total kink energy for electron x = , Total kink energy for electron x = )

SR flip-flop

For Output = ‘1’

For Output = ‘0’

D Flip-flop

For Output = ‘1’

For Output = ‘0’

T Flip-flop

For Output = ‘1’

For Output = ‘0’

JK Flip-flop

For Output = ‘1’

For Output = ‘0’

VII. ENERGY DISSIPATION

The energy dissipation [7, 11] due to change in polarization can easily be computed from the equation 3.

≤ − +( − ) … (3)

Figure 14 : Energy Dissipation of 0→0, 0→1, 1→0 &1→1 transitions

Figure 14 shows four different combinations of polarizations from 0→0, 0→1, 1→0 &1→1. From the four different transition of polarization we have found out corresponding the energy dissipations. Energy dissipation of 0→0 &1→1 transition will be same but not same for the transition of 0→1 &1→0. Similarly, energy dissipation of 0→ 1&1→0 transition will be same but not same for the transition of 0→0 &1→1. If we plot

the energy dissipation graph ( vs ), then we have

found out a increasing graph of energy dissipation which is parallel to each others. Here, we considered that the clock energy during switching event & are same and then we

plot varying from 0.5Ek to 2Ek.

413

Figure 14: Energy Dissipation for the transition of 0→0, 0→1, 1→0 &1→1

If the condition is that the clock energy during switching event & are different then will be slightly less than but

more than the kink energy, which comes from the calculation as shown in equation 4. − …………. (4)

The minimum energy requirement to dissipate the energy between the two neighboring cells is kink energy and is less than from the equation 3 because if more energy is given at the input cell, then there will be more tunneling of quantum dots from one potential well to another potential well then there is a possibility of extra energy to dissipate due to the rotational tunneling and remains same polarization as before. This rotational tunneling may not happen in the previous cells because these cells are already adjusted accordingly and it is difficult to modify them again within the QCA design. We cannot predict the electron tunneling as well as we cannot distinguish that the same electron will remain same position. Ina cell of two electrons, they may exchange their position and it will happen when the applied dissipated energy is more than the required. In that case to stabilize the energy within the cell, the electrons may rotate their position.

Therefore, the energy dissipation may vary even if the state of a cell does not change (Transition from 1 → 1, 0 → 0)

VIII. CONCLUSION

In this paper we have developed a standard equation from SR flip flop and using that equation other flip flops like D, T and JK flip-flops are subsequently designed. This is a new approach of designing flip-flops with less hardware complexity in nanotechnology. Any memory storage device can be built using the flip-flops designed in the above mentioned approach. The layout has been generated and simulation results are verified using QCA Designer simulation tool. The stability of the circuit

has been clearly determined by the 3-D plots of kink energy of the two possible combinations of the output cell. In future there is a scope for design other sequential circuits like registers, counters, memory blocks and other flip flops using this generalized block.

IX. REFERENCES

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