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A NEW STATIC SYNCHRONOUS SERIES COMPENSATOR FOR REAL POWER
CONTROL ON AC TRANSMISSION LINES
Cristina 1. Terek Graduate Program in Engineering Science
Department of Electricai & Cornputer Engineering
Submitted in partial filfilment of the requirements fot the degree of
Master of Engineering Science
Facuity of Graduate Studies The University of Western Ontario
London, Ontario May 1999
@ Cristina 1. Terek 1999
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Abstract and Keywords In this thesis a new Static Synchronous Series Compensator (SSSC) for the control of active power flow on a transmission line is proposed and its effectiveness is inves- tigated. The new SSSC is based on injecting a voltage in a givea line to counter or augment the voltage &op produced by the inductive reactance of the he. The result ing compensator , t herefore, emulates the controL of transmission line reac tance and thus, it assists in controbg the power transmission capacity. The voltage to be
injected in a iine is produced by a Binary Voltage Source Inverter (BVSI). -4 BVSI is an attractive recently proposed Voltage Source Inverter. Its output contains very
little hamonics and it utilizes very few dc sources unlike conventional multi-level VSIs. The %phase output of the BVSI is synchronized to the line fiequency and its phase is arranged to be in or out of phase with the Line reactance drop.
The proposed BVSI-SSSC is realized by using three binary proportioned dc sources, which may be appropriately dimensioned capacitors. The resulting output of a BVSI- SSSC is a 15-step ac voltage waveform. The BVSESSSC has a sophisticated set of coordinated controllen which ensure: BVSI frequency is in synchronism with the system frequency, firing pulses are regulated for inverter valves to ensure minimum harmonic content, the selection of Modulation Index and arrangement regulates an
appropriate phase relationship to create the desired change in the power flow, and
adjustment of firing angles to ensure that the capacitors creating dc binary propor-
tioned sources maintain desired charge on them. Aumliary controls may be added to
create positive system damping through active power control, and voltage dependent
controllers rnay be added to ümit over and under voltage (charging) of capacitors
during fault conditions. The proposed BVSI-SSSC is a device in the family of Flexible .AC Transmission
Systerns (FACTS) devices which are becoming vital in emerging open access transmis- sion networks. The proposeci BVSI-SSSC is digitally simdated using PSCAD/E&ITDC (commercial) software to validate its working and testing its effect iveness to dynam- ically control active power changes in a Iine. The BVSI-SSSC is finally =amined for its operation and recovery when the line on which it is connected is subjected to
serious üne to ground faults of vanbus kinds.
Keywords Series compensation of transmission hes Voltage source inverters Binary voltage source inverter Static Synchronous Series Compensator
Co-Aut horship
The fdowing thesis contains material korn a mimuscript subrnitted for publication
CO-authored by Cristina 1. Terek, R.M. Mathur and K.V. Patil.
AU the research, developmentd, and simulation work presented in this thesis was
performed by Cristina 1. Terek. The original manuscript, a version of which appears
in this thesis, was written by Cristina 1. Terek.
"FACTS ARE BETTER THAN DREAMS"
Winston Churchill
Dedicated to my dear parents
Acknowledgement s
In the endlessness that 1 feaced being a full-time mothes and student, in accomplishing my mission and the writing of this thesis, 1 had many wonderful people around me to whom 1 am truly indebted.
I would üke to offer my sincere gratitude to m y advisor and dean, Dr. Mohan Mathur, for allowïng me to enrich my knowledge h m his unlimiteci experience, and for his valuable guidance and kind understanding without which 1 could not have completed my Master's thesis. To Krishnat, &end, coiieague and experienced engineer, 1 wish to thank for his
availability and patience, support and advice, always and whenever it was most needed.
I have also had support fmm professor Tom Bonnema, to whom 1 have often confessed numemus womes and kom whom 1 have received only good appreciation regarding m y duties.
Throughout my studies I felt the encouragement from m y fnends and farni'v, especially from my husband, Bogdan, and m y daughter to mhom 1 dedicate my time
spent in the Universi@, Julia's i ~ o c e n t everyday smile has granted me a tremendous amount of constant happiness which energized me day by day. God bless her!
Lastly, 1 am thankful to my dear parents for letting me freely choose my future and for ali the efforts they have put into m y life to gratify me.
Contents
Certikate of Examination
Abstract and Keywords
Co-Aut horship
Epigraph
Dedication
Acknowledgements
Table of Contents
List of Tables
List of Figures
List of Appendices
ii
iii
V
vi
vii
viii
ix
xîii
xiv
xvi
Chapter 1
INTRODUCTION 1
1.1 REAL POWER FLOW MANAGEMENT 1 . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 1.1.1 Classicd devices 3
. . . . . . . . . . . . . . . . . . . . . . . . . 1.1.2 Advanced devices 4
. . . . . . . . 1.2 STATIC SYNCHRONOUS SERIES COMPENSATOR 5
. . . . . . . . . . 1-2.1 Inductive and Capacitive modes of operation 7
. . . . . . . 1.2.2 Immunity to classical subsynchronous resonances 8
. . . . . . . . . . . . . 1.2.3 Capabüify to exchange active power . .- 8
. . . . . . . . . . . . . . . . . . . . . . . . . 1.3 THESIS OBJECTIVES 9
1.4 O U T L ~ O F T ~ T H E S I S . . . . . . . . . . . . . . . . . . . . . . 9
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 2
VOLTAGE SOURCE INVERTERS 12
2.1 IMPLEMENTATION OF SYNCHRONOUS VOLTAGE SOURCES . 13
. . . . . . . . . . . . . 2.2 VOLTAGE SOURCE BRIDGE INVER3ER.S 13
. . . . . . . . . . . . . . . 2.3 VOLTAGE AND HARMOMC CONTROL 18
. . . . . . . . . . . . . . . . . . . . . 2.4 VARIOUS VSI TOPOLOGIES 23
. . . . . . . . . . . . . . 2.5 BINARY VOLTAGE SOURCE INVERTER 24
. . . . . . . . . . . . . . . . . . . 2.5.1 Configuration and Topology 25
. . . . . . . . . . . . . . . . . . . . . . . . 2 .5.2 Harmonic Analysis 28
2 .5.3 Selective Harmonic Elimination Modulation Technique . . . . 30
. . . . . . . . . . . 2.6 USE OF BVSI FOR REAL POWER CONTROL 31
. . . . . . . . . . . . . . . . . . . . . . . . . 2.7 CHAPTER SUMMARY 3'2
Chapter 3
BVSI BASED SSSC 34
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 INTRODUCTION 134
. . . . . . . . . . . . . . 3.2 UNIFIED POWER FLOW CONTROLLER 34
. . . . . . . . . . . . . . . . . . . . . . 3.2.2 Basic control functions 37
. . . . . . . . . . . . . 3.2.3 Generalized power control perspectives 38
. . . . . . . . 3.3 STATIC SYNCHRONOUS SERIES COMPENSATOR 39
. . . . . . . . . . . . . . . . . . 3.3.1 Configuration of a new SSSC 39
. . . . . . . . . . . . . . 3.3.2 Phasor and analytical representation 41
. . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 Main Controller 43
3.3.4 Capacitor Voltage Controller . . . . . . . . . . . . . . . . . . . 44
3.3.5 Conti01 of power flow . . . . . . . . . . . . . . . . . . . . . . . 48
3.4 TESTOFTHENEWSSSC . . . . . . . . . . . . . . . . . . . . . . . 48
3.4.1 Test case with line represented by an inductor . . . . . . . . . 49 3.4.2 Discussion of the results . . . . . . . . . . . . . . . . . . . . . 50
3.4.3 Sunulateci Test . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.5 CHAPTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . 53
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Chapter 4
DEVELOPmNT OF A TEST SYSTEM FOR SSSC 55
4.1 SIMULAmON PROGRAM . . . . . . . . . . . . . . . . . . . . . . . 55
4.2 TWSMISSION LINE CHARACTERISTICS . . . . . . . . . . . . 57
4.3 TRANSMISSION LINE WTTH INFINITE BUSES . . . . . . . . . . 60
4.4 POWERORDERCHANGES . . . . . . . . . . . . . . . . . . . . . . 62
4.5 LZNE WITH SYNCHRONOUS GENERATOR . . . . . . . . . . . . 63
4.6 LOAD CHANGES . . . . . . . . . O . . . . . . . . . . . . . . . . - . 63
4.7 FAULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.8 CHUTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . 65
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Chapter 5
SIMULATION RESULTS 67
. . . . . . . . . . . . . . . . . . . 5.1 DISCUSSION OF THE RESULTS 67
. . . . . . . . . . . . . . 5.1.1 Switchingfromonemodetoanother 67
. . . . . . . . . . . . . . . . . . . . . . 5.1.2 Different power orders 69
. . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 Load changes 69
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.4 Faults 70
2 TMNSIENT SIMULATIONS - . . - - - . - . . . . - . . - . . - - . 72
5.3 CEfAPTERSUMMARY * , , - . - - - . - - - - - . . . . , . . - . - 82
Bibliography . . . . . . . . . . . . . . . . . - - . . . . . . . . - - - . - - . 83
Chapter 6
DISCUSSIONS AND CONCLUSIONS 84
6.1 GENERAL DISCUSSIONS . . . . . - . . . . - . - - . . . . . . . . . 84
6.2 CONCLUSIONS . . . . . . . . . . . . . - - - . . - . - - - - - - - - - 85 -
6.3 SUGGESTED FUTURE STUDIES . . . . . . . . . . . . . - . - . . 86
Bibliogaphy . . . . - . . . . - - . - - . . - - - - - . . - - - - . - - . - - 88
Appendix A
CIRCUIT D I A G W S
Appendu B
GATE PULSE GENEUTION
Appendix C
IEEE COPYRIGHT TRANSFER
Vita
xii
List of Tables
. . . . . . . . . . . . . . . . . . . 2.1 Switching patterns for 3-level BVSI 32
. . . . . . . . . . . . . . . . . . . . . . . 4.1 BVSI's output voltage limits 62
. . . . . . . . . . . . . . . . . . 5.1 THD for single-phase to ground fadt 79
. . . . . . . . . . . . . . . . . 5.2 THD for double-phase to ground fault 80
. . . . . . . . . . . . . . . . . . 5.3 THD for three-phase to ground fault 81
. . . . . . . . . . . . . . . B.1 Gate pulses output fiom switch firing logic 94
List of Figures
. . . . . . . . . . . . . . . . 1.1 Elementary Power Tkansmission System 2
1.2 SSSC in inductive and capacitive modes and the related phasor diagrarns 6
2.1 One-phase full bridge inverter . . . . . . . . . . . . . . . . . . . . . . 14
2.2 Three-phase bridge inverter . . . . . . . . . . . . . . . . . . . . . . . 16
2.3 Waveforms of Sphase bridge inverter with 180' conduction . . . . . . 17
. . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Single pulse modulation 19
. . . . . . . . . . . . . . . . . 2 -5 Selective harmonic elimination method 21
. . . . . . . . . . . . . 2.6 Three-phase star connected blevel binary VSI 25
. . . . . . . . . . . . . . . . . . 2.7 Typical voltages of 3-level binary VSI 27
3.1 The family of synchronous voltage source based power flow controllers
. . . . . . . . . . . . . . . . . . . . . . 3.2 Basic UPFC control functions
. . . . . . . . . . . . 3.3 Series comection of BVSI in a transmission line
. . . . . . . . . . 3.4 Phasor diagram of the compensated system voltages
. . . . . . . . . . . . . . . . . 3.5 Inverter voltage phase angle controller
. . . . . . . . . . . . . . . . 3.6 Control diagram of the capacitor voltages
. . . . . . . . . . 3.7 Polar representation of the trigonometric functions
3.8 Steady-state operation of the SSSC for capacitive (a) and inductive (b)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . compensation
. . . . . . . . . . . . . 3.9 SSSC in capacitive and inductive mode . . . :
. . . . . . 4.1 Lumped-element representation of a long transmission Line 57
. . . . . . . . . . . . . . . . 4.2 Phasor diagram of a naturally Ioaded Iine 59
5.1 SSSC switching fkom capacitive to inductive mode . . . . . . . . . . . 72
5.2 SSSC switching from inductive to capacitive mode . . . . . . . . . . . 73
5.3 Power flow and Modulation Index variation . . . . . . . . . . . . . . . 74
5.4 Adding more load without SSSC connecteci . . . . . . . . . . . . . . . 75
5.5 Adding more load with SSSC c o ~ e e t e d . . . . . . . . . . . . . . . . 76
5.6 Reducing the load without SSSC connected . . . . . . . . . . . . . . 7'7
5.7 Reducing the Ioad with SSSC connected . . . . . . . . . . . . . . . . 78
5.8 Single-phase to ground fadt o c c h g in the capacitive mode . . . . 79
. . . . . . 5.9 Tw~phasetogroundfaultoccurringintheinductîvemode 80
. . . . 5.10 Three-phase to ground f d t occumng in the capacitive mode 81
A.1 Main system for test case with two infinite buses at the ends . . . . . 90
. . . . . . . . . . . . .4.2 Subsystem representing the real power controller 91
. . . . . . . . A.3 Subsystemrepresentingthecapacitorvoltagecontrolier 92
A.4 Main system for test case with synchronous machine and resistive load 33
List of Appendices
. . . . . . . . . . . . . . . . . . . . . . . . . . A CLRCUITDIAGRAMS 89
. . . . . . . . . . . . . . . . . . . . . B GATE PULSE GENERATION 94
. . . . . . . . . . . . . . . . . . . . C IEEE COPYRIGHT TRANSFER 97
Chapter 1 INTRODUCTION
REAL POWER FLOW MANAGEMENT
Electrical energy transmission and utilization is under two dinerent sets of challenges.
The developing countries are experiencing an unprecedented rapid growth, whereas
the developed countries, notably in Western Europe and North America, are expe-
riencing demand leveling. However, the monopolized structures of deetrical power
utilities in these developed countries are crumbling, giving rise to cornpetition among
new generating companies through an open access to power transmission structures.
Although the two scenarios are radicaliy different , the resulting pressure on the t rans-
mission networks is similar. In each case the requirement is to stably transfer as mrrch
power as possible on each existing IÏne, delay the installation of new lines and/or con-
trollably transfer power on selected lines to reIease capacity as well as cut down ttic
circulating power, fkeeing up lines for added export out of the region. For new lines,
in addition to the cost, environmental considerations and the public concerns delay
securing new nght-of-ways. Attempts should be made to transmit only active power
as far as possible over the high voltage transmission lines and the required reactive
power should be generated locally by various means. Extracthg the highest possible
power transmission capacity on any given line is a high priority for any transmis-
sion Company. Aiso, higher power loads are made possible by deploying new control
devices and smart controis.
1.1. REAL POWER FLOW MANAGEMENT 2
To develop an appreciation of the pmblem and its solution a simple system is
considered. A schematic diagram of a simple power transmission line, represented
by its inductive reactance, connecting a sending-end voltage source and a receiving-
end voltage source is depicted in Figure 1.1. To conform to a realistic situation, the
voltage magnitudes at the two ends are chosen to be nearly equal and the phase
difference between the two ends is defined as the load angle. The active and reactive
power flow on a line between two ends (which can be in either direction) is a hinction
of the magnitudes of the voltage at both ends, the Line impedance and the load angle:
where V, and Vr are the magnitudes of the voltage at the two ends IV, 1 = 1 Vr[ = 1 VI,
XL is the line impedance (assumed purely inductive) and 6 = (6, - 6,) is the load
angle. Generdly, the transmitted power can be controlled by varying the voltages,
impedance and load angle. When the power transfer requirernent for a given length of
line increases, higher transmission voltages (V,, V,) must be selected. However, since
Figure 1.1: Elementary Power Transmission System
1.1, REAL POWER FLOW MANAGEMENT 3
power networks operate as voltage sources, it is desirable to hold the node voltages
at near rated dues. Therefoce, the active power can be iduenced mainly by phase
shifters (acting oniy upon 6) or by line compensation as the means of changing the
line impedance.
This thesis is not intended to provide a comprehensive analysis of transmission
lines but only some aspects wbich enhance the understanding of the dependence
between electrical parameters of a line and the resulting real power flow.
1.1.1 CIassicd devices
It is a well established practice to use reactive power compensation in order to increase
the transferable power in an ac power system or to control the voltage at a particular
bus-bar. In the past, fixeci or mechanically-switched capacitors and reaetors have
long been employed to increase the steady-state power transmission by controlling
the voltage dong the lines. As a means for real power control, phase angle regulators
( P m ) provide the phase-shifting by controllable quadrature voltage injection with
respect to the terminal voltage, with the objective of angle regdation. Since the
phase relationship between the injected voltage and the line current is arbitrary, the
phase shifter in general has both real and reactive power exchange with the ac power
system.
Since the late 19609, thyristor controlled series capacitors (TCSC) have been used
to Vary the effective series compensating capacitance (a typical scheme using a thyris-
tor controlled reactor in parallel with a capacitm), being only able to affect the mag-
nitude of the current flowing through the transmission line. Similar to conventional
phase shifters are the thyristor controlied phase angle regulators which are able to
continuously vary the phase angle between the voltages at the two ends of an insertion
transformer without changing the magnitude of the phase-shifted voltage from that
of the original line voltage.
1-1. REAL POWER FLOW MANAGEMENT 4
Among various power electmnic devices, the inverter which converts a dc voltage into
an ac voltage of a desireci amplitude and kequency seems to be by far the most useful
to be employed in power systerns, in order to make them more reliable, more efficient
and more flexible. Recent technological advancements have made manufacttlfig of
semiconductors with thermal and surge current handüng capability appropriate to
voltage and current ratings of hi& power transmission iines possible.
The development of high-power semiconductor devices with self commutating
capabilities like gate tum-off thyristors (GTO), insulateci gate bipolar transistors
(IGBT) or insuiated gate controiied thyristors (IGCT) opens up new perspectives in
the range of the relatively new Flexible AC Transmission System (FACTS) equip
ment [l]. The very concept of FACTS includes the use of high power electronics
and appropriate control technologies. Two main objectives of FACTS devices are: to
increase the transmission capability of the lines and to control the power flow over
designated transmission routes. In the future, what is aimed to be realized through
their solid-state implementation is a teal-the control of any of the parameters char-
acterizing a üne: transmission voltage, line impedance and phase angle.
The universal and most effeetive device is expected to be the Unified Power F l w
Controller (UPFC) which is able to control aJi three of the above parameters indepen-
dently and concurrently, and to internally generate controllable reactive power. thus
operating as a static syuchronous cornpensator, static synchronous series compensator
and phase angle regulator ail together. A major project is undertaken for the instal-
lation of the first large scale prototype of UPFC for Amencan Electric Power [2, 31.
The Static Synchronous Compensator (SSC or STATCOM) is a voitage source
inverter connected in shunt with the power system, capable of controllhg the trans-
mission line voltage by hternaily generating reactive power (both inductive and ca-
pacitive). The practicd efficiency of this equipment has been recently validateci by
2 STA'ïIC SYNCFIEtONOUS SERIES COMPENSATOR n -
the I I 0 0 MVAR STATCOM installation [4] for the Tennessee Valley Authority, the
first of its kind in the orrorld.
The Static Synchronous Series Compensator (SSSC) is a series comected voltage
source inverter which can modify the effective line impedance. Various studies [5, 61
have been carried out with Merent software models to demonstrate the practicability
and the effkctiveness of such technology. In this thesis, a new SSSC application in
power systems is investigated through digital simulations for various test systems.
STATIC SYNCHRONOUS SERIES COMPENSATOR
Static Synchronous Senes Compensation represents a novel approach, and an alterna-
tive to series line compensation, in which a synchronous voltage source, implemented
by a thyristor based voltage source inverter (VSI), is used to provide controllable se-
ries compensation. This compensator is, in generai, a solid-state switching converter
which is able to exchange active and reactive power at its output tenninals with an
ac power system, when operated with an appropriate dc power supply at its input
terminals. When coupled to an energy storage capacitot, an SSSC can only gener-
ate or absorb reactive power to and from the system. The SSSC considered in this
thesis is a llevel binary VSI connected in series with a three phase transmission line
t hrough a coupling transformer.
The power flow on a line can be increased by inserting an additional capaci-
t ive reactance in series wit h the transmission line, t hus decreasing the effective line
impedance. The power flow can also be decreased by inserting an additional in-
ductive reactance, thereby increasing the effective reactance. The SSSC is a static,
synchronous generator operated as a series compensator without an extemal electric
energy source, whose output voltage is controllable and is in quadrature with the Iine
current. It is employed for increasing or decreasing the overall reactive voltage drap
across the line, thus modeling an inductive or a capacitive reactance in series with
1.2. STATIC SY5fCHRONOUS SEFUES COMPENSATOR 6
the transmission Line. This variable reactance iduences the electric power flow in
the transmission Iine. A small component of the voltage which is in phase with the
Lne current provides for the losses in the inverter.
The transmitted red power therefore becornes a parametric function of the injected
voltage (V,) and can be expressed as foilows:
Normal mode Inductive mode Capacitive mode
of operation of opration of operation
Figure 1.2: SSSC in inductive and capacitive modes and the related phasor diagrams
1-2- STATIC S ~ C H R O N O U S SERlES COMPENSATOR 7
The compensating reactance (Xq) iIIustrated in Figure 1.2 is defined to be negative
when the SSSC is operated in an inductive mode; the compensating reactance has a
positive value when the SSSC is operating in the capacitive mode.
1.2.1 Inductive and Capacitive modes of operation
Figure 1.2 shows an example of a simple power transmission system with an SSSC
operating both in inductive and capacitive modes, and the related phasor diagrams.
The transmission b e with the inductive reactance Xc delivering power fiom the
sending-end voltage source to the receiving-end voltage source, having no compensa-
tion of any kind, is said to be in a steady-state. The voltage impressed by the effective
reactance is the same with the voltage drop across the uncompensated line because
the degree of series compensation is zero.
The line reactance is constant and by adding variable series (capacitive/inductive)
reactance, the amount of compensation can be controlled. The degree of series com-
pensation in this case is dehed as:
Xq x 100 % compensation = - XL
where XL is the line inductive reactance and X, is the emulated series reactance.
In the inductive mode of operation, the line current decreases as the inductive
reactance compensation Ievel increases from 0% to 100%. In the capacitive mode of
operation the line current increases with the capacitive reactance compensation level
from 0% to 33%. It is worthy to note fiom the diagrams that the SSSC not only can
increase the transferable power but it c m ais0 decrease it, simply by reversing the
polarity of the injected voltage. The reversed voltage is added directly to the line
voltage drop as if the Line impedance was increased.
The effects of the compensating reactance on the normdized power Bow in the
transmission Iine are as foliows: when the emulated reactance is inductive, the real
and reactive power flow decrease and the effective reactance increases as the reactance
1.2- STATIC SYNCHRONOUS SERIES COMPENSATOR 8
compensation increases in the negative direction, and when the emulated reactance
is capacitive the real and reaictive power flow increase and the effective reactance
decreases as the reactance compensation incteases in the positive direction.
1.2.2 lmm-ty to c h s i c d subspcbronous resonances
The subsynchronous resonance is known as an electric power system condition where
the electric network exchanges energy with a turbine generator at one or more of the
natural frequencies of the combined system below the synchronous frequency of the
system.
An SSSC is an ac voltage source operating o d y at the fundamental output fie-
quency and its output impedance at any other frequency should be zero. In practice
though, the SSSC may have a very smaii inductive impedance provided by the leakage
inductance of the series insertion transformer. The voltage &op across this impedance
is cornpensated at the fundamentai frequency when the SSSC provides capacitive line
compensation (in the capacitive mode). Consequently, the SSSC is unable to form a
series resmant circuit wit h the inductive line impedance to initiate subsynchronous
system oscillations,
1.2.3 Capabiüty to exchange active power
The SSSC when operated with an appropriate dc power supply (an energy source
and/or sink, or a suitable energy storage) can inject a component of voltage in anti-
phase with the voltage developed across the line resistance, to counteract the effect
of the resistive voltage drop on the power transmission. The capabiiity of the SSSC
to exchange both active and reactive power makes it possible to compensate for
both the reactive and resistive voltage drops, maintainhg a high effective X/R ratio
independently of the degree of series compensation.
1-3. THESIS OBJECTIVES 9
1.3 THESIS OBJECTIVES
The scope of this thesis is to examine the use of a Static Synchronous Senes Corn-
pensator (SSSC) in an electrical power transmission line for real power control under
various operating conditions.
The application of a new mdtilevel BVSI to reaüze a new SSSC for reai power
control is investigated. A real power controiler is developed and a capacitor voltage
controiler is adapted for the SSSC.
Initidy, the performance of the BVSI based SSSC is evaluated for providing
series compensation in a power system comprising a long transmiîsion line fed by two
infinite buses at the ends-
Then, BVSI-SSSC operation is examinecl for sudden load changes in a power
system configuration comprising synchronous machine, long transmission Line and
resistive load.
0 The robustness of the BVSI-SSSC is hally tested by applying he-to-ground
faults on a line where it is connected.
1.4 OUTLINE OF THE THESIS
Chapter 2 provides a general and basic background of voltage source inverters. Tlic
newly proposed binary voltage source inverter (BVSI) is introduced with its configii-
ration and operating principle and its application for a new SSSC to be used for real
power control Ïs proposed.
The theoretical aspects of the dynamic control of active and reactive power flow are
discussed within the concept of the Unified Power Flow Controuer in a simple system
in Chapter 3. Rirther, the principle of operation, configuration and the controllers
employed for the S tatic Synchronous Series Compensator are presented.
Chapter 4 introduces the software tool used for the transient simulations. It offers
some of the theoretical aspects of long transmission lines and how they are modeled. A
1.4. OUTLINE OF THE THESIS 10
few test systems are explicitly elaborated for the verincation of the SSSC performance
in various cases.
A comprehensive digital simulation study using a 3- level, lssteps BVSI based
SSSC as a real power compensator in a 230 kV transmission line is performed in
Chapter 5. Several r d t s are presented and discussed.
Lastly, Chapter 6 presents the h a l discussions, conclusions and some future te-
search directions-
Bibliography
[I] N.G. Hingorani, ''Flexible ac transmission," IEEE Spectrum, pp. 40-45, April
1993.
[2] M.E. Rahman, M. Ahmed, and etal., WE'C application on the AEP system - planning consideratiolis," IEEE Tmnsactzons on Power Systems, vol. 12, no. 4,
pp. 1695-1701, November 1997.
[3] C. Schauder, E. Stacey, and et-al., "AEP UPFC project: Installation, commis-
sioning and operation of the *160 MVA STATCOM," IEEE PES Winter Meeting,
December 1998.
[4] C.D. Schauder and et. al., "Development of a k100 MVAR static condenser for
voltage control of transmission lines," IEEE Tmmactions on Pow er Delivery, vol.
10, no. 3, pp. 1085-1097, Jdy 1995.
[5] L. Gyugyi, C.D. Schauder, and K.K. Sen, "Static synchronous series compensator:
A solid-state approach to the series compensation of transmission hes ," IEEE
TransactZons on Power Delàuery, vol. 12, no. 1, pp. 406-417, January 1997.
[6] K.K. Sen, "SSSC-static synchronous series compensator: Theory, modeling and
applications," IEEE l'kansactions on Power Delivery, vol. 13, no. 1, pp. 241-246.
January 1998.
Chapter 2
VOLTAGE SOURCE INVERTERS
The overd situation regardhg the traditional power transmission and control aspects
needed to be reviewed and what the FACTS development is bringing into attention to-
day is a totally novel series compensation theory and practice: the power fiow control
by solid-state, synchronous voltage sources (SVS) (11. The general concept of an SVS
can be understood through an analogy to an ideal synchronous machine generating a
set of three sinusoidal voltages at the fundamentai frequency, with controllable mag-
nitude and phase angle. The machine connected to the system can interndy generate
reactive power (capacitive and inductive) and its response is almost instantaneous,
not affecting the existing system impedance.
The goal is to allow full utilization of the exïsting power generation and trans-
mission facilities and this has to be done without altering the system avaiiability and
security. When employed for series compensation, an SVS has to be connected in
series with the transmission line, norrndy through a coupling transformer. The real
and the reactive power that can be exchanged with the ac system are dictated by the
phase displacement of the injecteci voltage with respect to the line current. When
these two variables are in phase, oniy real power is exchanged while for a quadra-
ture phase relationship between the two variables, only reactive power is transferred
to/fkom the system.
2.1. EMPLEMENTATION OF SYNCHRONOUS VOLTAGE SOURCES 13
2.1 IMPLEMENTATION OF SYNCHRONOUS VOLTAGE SOURCES
A solid-state SVS can be implemented by voltage-source inverters (VSI). The VSE
based devices employ inverters using forced turn-off switches and dc energy storage
capacitors to generate synchronous voltage. In order to simulate the effects of series
compensation, the voltage inserted by a VSI must be in phase quadrature with the
line current a t the point ofconnection. For normal capacitive series compensation, the
output voltage of the inverter must hg the Luie current by 90°, in order to compensate
for the inductive voltage &op taking place in the line reactance. EIowever, if the
inverter voltage leads the line current by 90°, it will be in phase with the inductive
line voltage drop and therefore will create such an effect as if the inductance of the
line is increased, resdting in reduction of the power transmitted over the line.
2.2 VOLTAGE SOURCE BRIDGE INVERTERS
Inverters are power electronic devices used to convert dc power into ac power at some
specific desired output voltage magnitude and frequency. This particular switching
power converter when fed by a dc source with a very smail or negligible interna1
impedance is called a voltage source inverter. When using forced turn-off switches in
appropriate multi-pulse circuit configurations, this type of inverter is most practicd
for power utility applications [2].
The voltage source inverters are also classified as forced commutated inverters be-
cause of their commutation process. Each switch is conducting for a period indicated
by its gate pulse and is commutated once the puise is removed.
The switches empioyed in a bridge inverter are comected in a bridge configuration.
There are certainly different bridge inverter circuits that can be built. Among them,
the basic bridge inverter circuit is the simplest one from the control strategy point
of view and the output voltage waveforms are sMply rectangular/square waveforms
2.2- VOLTAGE SOURCE BRIDGE INVERTERS 14
with one positive and negative cycle over one period of time. The two possible
configurations for a 1-phase bridge inverter are the haIf bridge inverter and the fidl
bridge inverter and the Iater one is drawn in Figure 2.1-(a). The reasons for using
either of these configurations depend on the type of appücation. The number of
components (thyristors and diodes) used in a half bridge inverter is haif that of a fidi
bridge inverter but the disadvantage is that the dc source required in a half bridge
inverter has to be a three wire dc source, or two similar sources with the d u e half
of that in a full bridge inverter are necessary
Figure 2.1: One-phase full bridge inverter
2.2. VOLTAGE SOURCE BRIDGE INVERTERS 15
The gate pulses and the output voltage waveforms are shown in Figure 2.1-(b).
During the period O t 5 Tl2 thyristors Tl and T2 conduct and the voltage V is
applied to the load. At the moment t = T/2, thyristors Tl and T2 are commutated
off and T3 and T4 are then gated on. During the second half of the interval thyristors
T3 and T4 conduct and the load is subjected to a vokage -Y. Thus, the inverter
output voltage which is the load voltage is an alternating tectangular waveform with
the frequency ( l /T) . By controllhg the duration of period T, the frequency of the
output voltage can be varieci.
Normallx in a circuit with a pure resistive Ioad, the thyristors would be enough
to convert the dc voltage into an ac signal. But the majority of loads are inductive
or capacitive and even a resistive load would have some inductance or capacitance.
Therefore, for these cases the current io flowing through the load cannot reverse its
polarity at the same instant with the load voltage &. The main role of the feedback
diodes connected in antiparallel with each thyristor is to permit load current to flow
continuously and more than that, to ensure that the two thyristors in the same branch
(Tl and T4, or T3 and T2) do not conduct simultaneously to allow a shortcircuit to
take place across the dc source. Of cowse, the magnitude of the output voltage in
the fidl bridge inverter is twice that of the half bridge inverter at the cost of doubling
the number of thyristors and diodes in the circuit.
The bridge inverter can be built in a three phase configuration as well and the
load, which can be connected in star or delta across the terminals A, B and C,
is subjected to an output voltage with a higher number of steps in the rectangu-
lar voltage waveform. In Figure 2.2 the thyristors are fired in the fouowing order:
Tl, Tz, T3, T4, Ts, Ts, Ti, ... and so on. Considering the period T divided into 2a
radians, each thyristor is fired in sequence after an interval of r / 3 .
In the Sphase bridge inverter, there are two dinerent modes in which the thyriston
can be gated and commutated: each thyristor can conduct for a period of r or
2-2- VOLTAGE SOURCE BRIDGE INVERTERS 16
Figure 2.2: Three-phase bridge inverter
for a duration 2 ~ 1 3 . The gate pulses for the first type of conduction are depicted
in Figure 2.3 and they indicate the duration for which the respective thyristor is
conducting. Again a thyristor is turned on with the application of a gate pulse and
as soon as the pulse is removed, commutation takes place in that specific thyristor.
From the waveforms in Figure 2.3, it can be seen that 6 commutations are required
in a cycle and each gate signal Iasts for 180" in order to obtain the expected waveform
at the output terminals. The inverter operation foilows the next pattern: gate signals
are given at an interval of lr/3 to three thyristors at a tirne. Therefore, they conduct
in this order: 156, 126, 123, 234, 345 and 456. In this commutating pattern thrce
thyristors conduct a t a time and by identimng them one can easily draw the h i e
voltage waveform, for example UAB, and the other two simüar waveforms v s c and
UCA will be displaced by 120' in time.
With the help of the Fourier series [2], the output voltages can be expressed as:
2.2- VOLTAGE SOWCE BRIDGE INVERTERS 17
Figure 2.3: Waveforms of %phase bridge inverter with 180° conduction
These equations show that the üne voltages have values defined by the intervals
of conduction and they do not depend on the type of load. Therefore, any linear,
balanced or unbalanceci load, or even any combination of resistance, inductance and
capacitance is possible to be connected at the output tenninals [2]. Also, the equa-
tions (2.1) to (2.3) show that the triple harmonies are not present in the line voltages.
The phase voltage UN has been drawn for a resistive load connected in a star config-
uration at the output terminais. Thus, for the first three intervals, the phase voltage
2.3- VOLTAGE AND HARMOPJIC CONTROL 18
VAN equals in sequence V/3, 2V/3 and again V/3, following the same shape in the
negative semi-cycle as weii (-V/3, -2V/3, -V/3).
The second mode of operation consists in gating and commutating the thyristors
such that each one wiU conduct for a period of 21r/3. Like in the previous case, in
this pattern six commutations per cycle are slso required, but ody two thyristors
conduct a t a time in each of the six intervais in which they are fired. Having only two
thyristors conducting simultaneously, two of the load terminais are always connected
to the dc supply and the third phase periodicalIy remains in a floating state during
the six intervals.
DifEerent a d a r y components lîke thyristors, diodes, capacitors, inductors or
resistors can be introduced in any configuration of a bridge inverter to modify the
design of the commutation circuit. Thus, dinerent commutation methods can be
utilized in gating and commutating the thyristors to obtain better efficiency from
this category of switching power converters. For example, the circuit tum-off time
should be greater than the thyristors turn-on t h e in order to minimize the energy
lost in the commutating circuit, condition that corresponds to a minimum supply
voltage and maximum load curent. The modified McMurray half and fidl bridge
inverters (1-phase and 3-phase), the modified McMurray Bedford half bridge inverter
and the three-phase bridge inverter with dc side commutation are just a few circuits
that use different methods of commutation in this scope.
2.3 VOLTAGE AND HARMONIC CONTROL
When using inverters in different applications the control of the output voltage is one
of the most important issues that are of concern. Sometimes a constant ac voltage is
required and, most of the times, control of circuit voltage is necessary dong with the
fiequency (in motor control applications). In this sense, a few methods have been
developed that fall in three dinerent categories:
2-3. VOLTAGE AND EURMONIC CONTROC 19
- control of the dc voltage supplied to the invert-
- control of the voltage delivered by the inverter to the Ioad;
- control of the voltage within the inverter using time ratio control techniques.
Out of the three categorïes, the 1 s t one is of more interest to power systems
applications and it involves tirne ratio control employing suitable modulation schemes.
The inverters that use this type of control are c d e d pulse width modulated inverters.
In these schemes, the total number of power circuit components is not significantly
increased. Another advantage of great use for power systems is that in parailel with
voltage control, it is ais0 possible to reduce or at least eliminate lower order harmonic
fkequencies. High order harrnonics can be eliminated by the inductive part of the
load, so filter circuits do not necessarily need to be employed to reduce the harmonics
in the load curent.
The pulse-width moduiation technique can be applied through single pulse modu-
lation (SM), symmetrical multiple pulse modulation (SMM) , multiple pulse modula-
tion with selective reduction of harmonics (MMSR) and sinusoidd pulse modulation
(Sin M).
(a) Wavefonn without modulation
. (b) Modulated waveform
Figure 2.4: Single pulse modulation
2-3. VOLTAGE AND HARMONIC CONTROL 20
Figure 2.4 shows the output voltage waveform of a single-phase full bridge inverter
without modulation and the shape that the waveform takes &ter modulation- The
difference consists in the duration of the pulse; instead of 180' duration for an un-
modulated wavefom, a pulse with duration of 2d is generated symmetricdy around
90". By m g the pulse width 2d, control of the output voltage is achieved. The
following Fourier series describes vo:
where n = 1,3,5, ...
and
By replacing the Fourier coefncients in the original formula of the output voltage, ZQ
becomes the next function:
O0 4v vo = C (, sin nd) sin nwt
n=L,3,5
From the equation-(2.7), for n=l, it can be seen that the maximum value the funda-
mental component c m take occurs for a puise width d = 7r/2 and is a square waveform
with the magnitude given by:
Therefore, the maximum rms value of the fundamental represents 90.4% of the dc
supply voltage. Still, for low values of the output voltage the amount of harmonic
content introduced is very substantial. In order to elhinate it , a symmetrical multi-
pulse modulation (SMM) can be achieved simply by using several equidistant pulses
2.3- VOLTAGE AND EUEMONIC CONTROL 91
per half cycle. With this method the harmonie content at low output voltages can be
reduced.
A better method to permit harmonic content reduction wodd be a selective elimi-
nation of harmonics which can be implemented with the help of Multiple pulse modu-
lation with selective reduction of harmonics (MMSR). Figure 2.5 illustrates the pulse
positions per quarter cycle. By selecting suitable M pulse positions, any M harmon-
ics c m be elMinateci and the output voltage can be varied by controliing the pulse
duration 2d symmetncally around the pulse position. In a quarter of a cycle, the
puise positions are indicated by BI to BM.
As in the previous cases, the waveform is symmetrical in each quarter cycle so the
B,, coefficient in equation (2.4) is again zero. Correspondingly, the n-th harmonic
amplitude is now:
8V M
(vo ) nm = - sin nd sin n BK nr
K=l
where n represents the harmonie numbers to be eliminated and M corresponds to
the total number of harmonics selected to be eliminated. By making equation ( 2 -9)
equd zero, M non-linear algebraic equations need to be solved to find out B I , B2.
B . Considering the elimination of only the third, @th and seventh harmonics.
Figure 2.5: Select ive harmonic elimination method
2-3. VOLTAGE AND HARMONXC CONTROL 22
for example, the next equation has to be solved fot BI, B2 and B3:
8V (qJnm = - sin &(sin nBr + sin nB2 + sin n Ba)
nr
By replacing n = 3, 5 and 7 in the above equation, a systern of three non-ünear
equations solvable with the Newton-Raphson numerical technique yields the solutions:
Using the angles Bi, Bz and B3 as h g puises in a quarter cycle and symmetri-
ca.liy for the rest of the interval, one can have harmonics 3rd, 5th and 7th not exactly
zero but with the amplitudes alrnost negligible. The advantage of using selective har-
monic elimination instead of SMM is that some low order hannoaics are eliminated
rather than just minimized, but in the case of 3rd, 5th and 7th harmonics elimina-
tion the fundamental component reaches only 67% of that of an unmodulated square
wave.
Sinusoidal puise modulation (Sin M) is another method which permits a reduction
în the harmonic content. The only difference between Sin M and the two previous
methods is that the pulse width in this case is a sinusoidal fûnction of the anguiac
position of the pulse in the cycle. A comparative study of sinusoidal pulse modulation
(Sin M) with selective reduction of harmonics (MMSR) given in [3] shows that in the
case of a few pulses per half cycle MMSR is superior to Sin M which is essentiaily a
harmonic reduction method.
Voltage control of the output voltage of a bridge inverter can be achieved thsough
different methods together with harmonic reduction or elimination of certain low
order harmonics. However, there are applications where it is more important that
the harmonic component of the load curent be l e s than 5% of the fundamental
regardless of the amplitude obtained in the output voltage. Therefore, a harmonic
elimination and reduction by Pulse Width Modulation (PWM) is possible which
cannot be used for voltage control. This modulation method employs four additionai
2.4- VAFUOUS VSI TOPOLOGIES 23
commutations per cycle instead of one uecessary for the unmodulateci squarewave.
This method presents the disadvantage of high switchuig Iosses due to the four extra
commutations. This drawback of large number of commutations taking place in the
inverter constitutes an important limitation when dealing with a configuration of
many full bridge inverters co~mected together because the energy l o s would increase
in a direct proportion with the number of inverters used.
2.4 VARIOUS VSI TOPOLOGIES
-4s it was described in section 2.2, the output voltage waveform of a simple &pulse
inverter contains ail harmonic components of odd frequencies except for the tnpk
harmonics. The harmonic content frequencies can be expresseci as [6k I l] f, where
f is the fundamental output fiequency and k = l , 2 , 3 .... It is evident that the high
harmonic content of such an elementary inverter makes its utilization impractical for
power utility applications. However, if harmonic neutralization met hods are used, the
input and output of n basic &pulse inverters can be combined to obtain a P = 6n
multi-pulse stmcture. The bequencies of the harmonics present in the output voltage
of such an inverter configuration with P p&es are [Pk k l] f . It is obvious that
the harmonic spectnun improves rapidly with increasing pulse number. Asa, the
amplitude of these harmonics is inversely related to the pulse number (for example,
the magnitude of the k-th hatmonic is proportional to l / [ P k f II).
Multi-pulse harmonic neutralized inverters can be implemented by a selection of
different circuit arrangements. Even though the implementations may be different,
the output voltage waveforms obtained wiU be essentiaily the same. Among the
vanous VSI topologies, the muiti-phase and multi-Ievel configurations have become
popular for power systems application& In these configurations the switching fre-
quency can be kept low in order to minimize device stresses, switching losses and the
harmonic distortion.
2.5. BINARY VOLTAGE SOURCE I N V E m R 24
A three-level VSI topology has been constructeci and tested for a laboratory mode1
of an Advanced Static VAR Compeasator (ASVC) [4]. In this particdat configuration
the number of levels refers to the positive voltage levels including zero which appear
in the ASVC output iine voltage. For transmission lïne applications, a puIse number
of 24 or higher is required in order to achieve adequate waveform quality without
passive 6lters.
A &pulse inverter was used for the development of a new static compensator
(STATCOM) whose output voltage is a 21-step staircare waveform apprmtimating
very closely the sinusoidai line voltage. This arrangement contains a number of
8 elementary &pulse inverters with their outputs combined electrwnagneticdy to
produce a nearly sinusoidal resultant waveform [5]. Another inverter structure exem-
plified in [l] can use any n &pulse inverter modules, connected in parallel to the same
Vdc source. A 12-pulse static synchronous compensator using a 3-level GTO inverter
was also proposed in [6].
In a high power inverter ushg a sufnciently high pulse number the output voltage
distortion can be reduced theoretically to any degree and so the capacitors ripple cur-
rent. Thus, a perfect inverter shodd generate sinusoidal output voltage and draw pure
dc current without htroducing any harmonies into the system to which is connected.
Different multilevel VSI schemes have been studied and tested so far, included
among them are diode-clamp, flying-capacitor and cascaded separate dc source in-
verters [7]. The next section introduces a new contiguration for a VSI scheme which
does not requite any transformers, clarnping diodes or flying capaciton.
2.5 BINARY VOLTAGE SOURCE INVERTER
A new binary voltage source inverter (BVSI) with three separate dc sources was
proposed in [8]. In general, this n-level BVSI produces a (2"+' - 1) step ac voltage
output against (272 + 1) step output correspondhg to the conventional n-level VSI
2.5- BNARY VOLTAGE SOURCE INVERTER 23
configuration. By appropriate switching topology, aIi the important harmonies can be
either minirnized or compIetely eiiminated and a 15-step ac voltage output is produced
over one cycle, using only three dc sources of binary proportion.
2.5.1 Codguration and Topology
In this configuration, in order to increase the voltage rating, a number of three single
phase full bridge inverters (FBI) have been connected in series on each phase, as
shown in Figure 2.6.
The three-phase star-connected arrangement of the proposeci inverter contains
three separate dc sources. Three single-phase FBk are connected in series and each
FSI has its own dc source. The magnitude of each dc source is in binary proportion
of Vdci 2Vd, and 4Vk, where Vk was chosen to get the desired fundamental ac voltage
L 1 1 1 1
Figure 2.6: Three-phase star comected Blevel binary VSI
2.5. BINARY VOLTAGE SOURCE INVE-R 26
output for normalized one per unit modulation index, defined later in this section.
In this scheme, the switches (GTOs) are turned -on and -off to generate the 15step
ac voltage output over one fundamental cycle. The ac voltage output of each level
(ulit v12, v13) coincides with a conduction period of each capacitor and the resulting ac
phase voltage (va) is given by:
The voltages of the three Ievels take diffetent values consecutiveiy, depending on
which thyristor is fued and when (Table BI-Appendix B).
By appropriate switching of various thyristors and their combination, the output
of each N1 bridge inverter level is varieci, resulting in the phase voltage given in (2.12).
The switching frequency of a device decreases as its voltage rating increases as can
be seen fiom Figure 2.7. Highest voltage rating devices (VC3) are switched -on and
-off just once per half cycle. Figure 2.7 presents the ac output voltage for each level
(va,) and the fundamentai output voltage of the inverter (v,), as weil as the current
(icJ flowing through the capacitors. Also, the firing angles el to 07 which determine
the conduction period of each capacitor are indicated.
The advantages of using such a configuration have been explained and demon-
strated in [8] and also, the use of a selective hannonic elimination modulation tech-
nique to either completely eliminate or minirnize the low order harmonics was stud-
ied. Finally, the selective harmonic elimination modulation (SHEM) technique was
employed for the elimination or minimization of the 5", p, 1 13'", l p , 19"
harmonics .
2-5. BINXRY VOLTAGE SOURCE INVERTER 27
1; m i r
91 02 94 96 $ ?r 35
Figure 2.7: Typical voltages of 3-level binary VSI
2.5. BINARY VOLTAGE SOURCE INVERTER 28
From Figure 2.7, the staircase output waveform of the binary voltage source inverter
can be defined for the positive haIf cycle as foiIows:
The Fourier analysis gives the fiequency components of this wave as below:
This waveform is a symmetric, odd huiction (f (t) = - f (-t) ) , and beause f (t) =
- f (t + n) it contains only odd harmonies, so:
a0 = O, ah = O (2.16)
2.5. BINARY VOLTAGE SOURCE INVERTER 29
resulting in the next expression for u,:
Considering bh = ûa-l for k = 1,2,3,4, -.. equation (2.17) becomes:
The waveform having quarter-wave symmetry, Û Z k 4 is being determined as below:
Replacing again h as 2k - 1 in the above equation, Û2k-L can be written as:
Now generaking for a n-level binary voltage source inverter:
where N = 2" - 1. Combining equation (2.18) and equation (2.21) together yields:
The fundamental rms and the harmonic ms phase voltages can be extracted from
the above equation:
va =
%k-1 =
Equation (2.23) can be rewritten for the three-level BVSI: ..
2.5. BINXRY VOLTAGE SOURCE INVERTER 30
Therefore, the maximum fundamental phase voltage is given by:
Having defined the harmonic rms for the inverter output voltage, the total harmonic
distortion (THD) can be de- as:
where,
Vh = magnitude of individual harmonic components (rms volts)
h = harmonic ordet
V, = nominal system voltage (rms volts)
2.5.3 Selective Harmonic Elimina tion Modulation Technique
The harmonic analysis performed on the waveform (v,) from Figure 2.7 shows very
clearly that the harmonic content of the inverter output voltage can be improved
significantly if a proper technique is used. Two switching strategies are considered in
a cornparison study in [4]: a Selective Harmonic Elimination Modulation technique
(SHEM) together with a fundamental frequency modulation (FFM) and the benefits
of using SHEM are highlighted. In the case of the three-level binary VSI, the mod-
ulation angles (Bi) in the equation (2.20) can be varied to rninimize the harmonic
distortion and also to control the magnitude of the fundamental output voltage. In
general, for a n-level BVSI, (2" - 1) steps pet haif cycle in the inverter output volt-
age provide control of the fundamental and elimination or minimization of (2" - 2)
harmonics. So, for a three-level binary VSI, seven steps introduced by the seven
modulation angles (Ol to &) help eliminate any six harmonics.
It has been explaineci that due to the quarter symmetry of the switching pat-
tern only odd haxmonics are present in the output voltage, so six harmonics of order
2.6- USE OF BVSI FOR REAL POWER CONTROL 31
5th, p, l l t h , 1 3 ' ~ ~ 17Lh, lgUL are chosen for elimination or minimization. The triple
harmonics are filtered by the circulation through the delta configuration of the tram-
former primary through which the inverter is coupled to the system.
In order to solve the equations that yîeld the solutions of the seven modulation
angles, another variable must be dehed to introduce the last equation to complete
a system of six non-linear equations that reflect the harmonics voltage magnitudes.
The Modulation Index (MI), also known as amplitude modulation ratio, is defined
fiom equations (2.25) and (2.26): -
The voltage magnitudes of the six harmonies c m be deriveci fkom equation (2.20) and
by equalizing their expressions with zero, the next system is obtained:
The set of seven non-linear equations given above were solved using the Newton-
Raphson numerical technique and only the solutions for a Modulation hdex varying
between 0.51 and 0.886 fall inside the first quarter-cycle (O < < n/2). Thesefore,
these solutions are the only ones acceptable for firing pulses. Table 2.1 exemplifies a
few of these solutions which were obtained off-line for a Modulation Index of 0.51 to
0.886 in steps of 0.001 and used as firing angles during nui-time simulations.
2.6 USE OF BVSI FOR REAL POWER CONTROL
In this thesis, the new Binary Voltage Source Inverter (BVSI) is employed as a Static
Synchronous Series Compensator (SSSC) for real power compensation in a transmis-
sion line. The 15-step, ac output voltage produced by the inverter is injected in the
system through a couphg transformer, in phase quadrature with the line current.
The magnitude of the voltage is dictated by the level of the compensation required
and is not dependent on the current amplitude. This BVSI based SSSC provides
2.7. CHAPTER SUMMARY 32
Table 2.1: Swïtching patterns for 3-level BVSI
Modulation Angles in degrees
91 l 02 i 03 1 04 1 85 1 86 1 07
capacitive and inductive compensation at the transmission Ievel with minimum har-
monic distortion introduced into the system. F'urther, this compensator is tested
for various operating conditions including severe faults through transient simulations
studies using PSCAD/EMTDC software package.
2.7 CHAPTER SUMMARY
This chapter aims to provide basic background about voltage source inverters and
how the output voltage of this type of power converters is influenced by computing
the gating pulses. The harmonic reduction and voltage output control in the inverters
is discussed and a few general methods for harmonic content reduction are brought
into attention. Various VSI topologies introduced in the literature are exemplified.
A new configuration for a multilevel VSI, as welI as a new method employed for
the elimination or minimization of the harmonie content (SHEM) is presented. The
application of this binary voltage source inverter as a novel series compensator is
pointed out at the end of the chapter.
-
Bibliography
[II L. Gyugyi, "Dynamic compensation of ac transmission lines by solid-state syn-
chronous voltage sources," IEEE ~ n s a c t i o w on Power Delivery, vol. 9, no. 2,
pp. 904-911, April1994.
[2] A. Joshi G.K. Dubey, S.R. Doralda and R.M.K. Sinha, Thyr i s toeed Power
Controllers, John Wdey & Sons, 1986.
[3] K.A. Krishnamurthy, "Selective reduction of harmonies in inverters," Interna-
tional Journal of Eleetronies, vol. 46, pp. 321-330, 1979.
[4] J.B. Ekanayake and N. Jenkins, "A three-level advanceci static var compensator,"
IEEE Trmactions on Power Delàuery, vol. 11, no. 1, pp. 54G545, January 1996.
[5] C. Schauder, M. Gernhardt, E. Stacey, T. Lemak, and L. Gyugyi, "Development
of a MO0 MVAR static condenser for voltage control of transmission lines," IEEE
Transactions on Power Deliuery, vol. 10, no. 3, pp. 1085-1097, July 1995.
[6] C. J. Hatziadoniu and F.E. Chalkiadakis, "A 12-pulse static synchronous com-
pensator for the distribution system employing the 34evel GTO-inwrter," IEEE
Transactions on Power Delivery, vol. 12, no. 4, pp. 1830-1835, October 1997.
[7] Jin-Sheng Lai and Fang Zheng Peng, "Multilevel converter - a new breed of
power converters," IEEE Transactions on Indwtry Applications, vol. 32, no. 3,
pp. 509-517, May 1996.
[8] K.V. Patil, R.M. Mathur, J. Jiang, and S.H. Hosseini, "Distribution system com-
pensat ion using a new binary multilevel voltage source inverter," IEEE Transac-
tions on Power Delivery, vol. 14, no. 2, pp. 459-464, April 1999.
Chapter 3
BVSI BASED S S S C
INTRODUCTION
This chapter describes a novel series cornpensator based on the Binary Voltage Source
Inverter (BVSI) for a transmission line. The series connected VSI is called Static
Synchronous Senes Compensator (SSSC). Its operating principle has been described
in [l, 2, 31 and the theory of its operation has been summarized in Chapter 1.
This FACTS device is capable of injecting an aimost sinusoidal voltage in quadra-
ture with the line cunent, thus modeling an equivalent inductive or capacitive reac-
tance in series with the transmission line. In order to fuaher understand the purpose
and the theoretical assumptions regarding the operation of the SSSC in any power
system, a good approach is to extend the dynamic control of active and reactive power
flow to the general concept of the Unilied Power Flow Controuer (UPFC) [4].
3.2 UNIFIED POWER FLOW CONTROLLER
The control of ac transmission systems which empioys the voltage source inverters as
synchronous voltage sources (SVS) for reactive shunt compensation, reactive series
compensation, and transmission angle adjustment was proposed in [5]. Then came
the concept of the UPFC (61 which was later generalized for dynamic active and
reactive power control [4].
3.2, UNIFIED POWER FLOW CONTROLLER 33
Compensator (SSSC)
f I
- Unificd Powet Flow Controiicr - (UPFC)
Figure 3.1: The family of synchronous voltage source based power flow controllers
The use of a SVS for transmission line compensation and control can be generalIy
visualized in Figure 3.1. Considering an elementary single transmission luie inter-
connecting two systems in a simple arrangement, the control of the power flow P
transmitted through the line is given by:
3.2. UNIFIED POWER FLOW CONTROUER 36
where h, I; are the magnitudes and &, b2 are the angles of the voItages of the two
systems and & is the impedance of the Iine.
As illustrateci in Figure 3.1, the transmission line voltage can be controued by the
Static Synchronous Compensator (STATCOM) ah* is shunt-connected, the Iine
impedance can be effectively controlied by the series-connecteci Static Synchronous
Series Compensator (SSSC) and al1 of these variables (voltage, impedance and power
angle) are controlled by the most effkctive Unified Power Flow Controller [WFC),
selectively or concurrentiy.
The basic operating principle of the UPFC is to inject a voltage vector in senes
with the transmission line and force current through it, so as to obtain the desired
power transmission. The power source based on VSI providing this voltage vector
exchanges real and reactive power with the ac system, as the magnitude and angle
of the injected voltage is varieci. The inverter executing series voltage injection is
able to generate internaliy the reactive power exchanged. The reai power exchanged
appears at the dc terminal as a real power demand. The shunt-connected inverter is
used to provide the real power demanded by the senes inverter, which is dranm frorn
the ac system. The UPFC makes it possible to handie al1 power flow controI aiid
transmission iine compensation problems using solid-state VSI instead of switched
capacitors and reactors.
The two inverters in the UPFC are back-teback connected with a common dc
source to accommodate bidirectional reai power transfer between the ac input (shunt)
and output (series) terminais. If a specific application requires only controilable shunt
or series reactive compensation, the two inverters can be separateci, each with its own
dc source. Each becomes a VAR source, controllhg the voltage of its own capacitor
by exchanging real power with the ac system.
3.2. UNIFIED POWER FLOW CONTROLLER 37
The paraiiel branch can supply reactive power for shunt compensation and repre-
sents an advanced static VAR compensator (ASVC). The series branch can provide
controllable series compensation and acts as a series condenser (a controllable voltage
source whose magnitude can be controiled independently of the üne current). These
two main parts of the UPFC, when used independently as an advanceci static VAR
compensator (ASVC) and as an advanced controilable series compensator (ACSC),
individudy display characteristics superior
devices.
to those of the conventional equivalent
The basic UPFC power flow control functions can be better iiiustrated using phasor
representations. Figure 3.2 presents the effects of the UPFC reguiating the terminal
voltage, providing series compensation (acting on the line impedance), regulating the
transmission angle (phase angle) and, in a multi-function power flow control, where it
is able to simultaneously regulate terminal voltage, line impedance and phase angle.
In all four cases power flow control is achieved by adding a voltage phasor V,, to
the terminal voltage phasor V, (Figure 3.1). The ac voltage injected in series with
the line via a coupling transformer is supposed to have a controllable magnitude V,,
between O and a dehed maJcimum value &,-, and any angular position between O"
and 360" with respect to the terminal voltage. Since this voltage source is assumed
to have no restrictions, the end-point of its phasor can be situated on the edge of a
circle with the center at the end of the reference phasor V, and the radius of hP,. Terminal voltage regdation is obtained simply by making the angle of Qq equal
zero and its magnitude V, = *AVo, so the injected voltage is in phase or in anti-phase
with the terminal voltage, and is affecting only the magnitude of L$ (Figure 3.2-a). A
series line compensation is shown in Figure 3.2-b, where V, = V, and the phasor V, is
perpendicular to the line current phasor I . The voltage V, increases or decreases the
total voltage &op across the Iine impedance aecording to whether Vc lags or leads the
3.2. UNll?IED POWER FLOW CONTROLLER 38
Voltage Series Phase angle Mdti-function regdation compctlsation regdation power fiow contml
Figure 3.2: Basic UPFC control functions
line current respectively. A phase angle regulation can be achieved when Vw = V, is
injected with an angular relationship with respect to V,, and so the resultant terminal
voltage phasor VJ at the end of the line has the same magnitude as V. but its phase
angle is shifted with the desireci c (the phase shift can be advanced or retarded) as
iilustrated in Figure 3.2s. Practicdy, the phase sh i f t is achieved without any change
in the magnitude of the terminal voltage.
In the multi-function power flow control, the Unified Power Flow Controller can
achieve combined terminal voltage regulation, series l h e compensation and phase
angle regulation at the same time. This is obtained by synthesizing the injected
voltage phasor £rom the three phasors controlled individually AV., Vc, and Vq. so
that the phasor V, = AV, + V, + V, (Figure 3.2-d).
3.2.3 Generalized power control perspectives
The basic power transmission concepts can therefore be expanded with the help of
this generalized Unified Power Flow Controller (UPFC). This approach permits corn-
bined shunt reactive compensation with controllable series compensation and phase
angle regulation. At the same time, the transition from one selected compensation
3-3- STATIC SYNCHRONOUS SERIES COMPENSATOR 39
mode to another in real tirne is fast and thus dinerent system contingencies can be
handled more effectively. As an inneasing naber of FACTS devices WU start to be
used in relatively large interconnecteci power systems, the control compatibility and
coordination wi l l have to be maintaineci regardless of any equipment f ' u r e or sys
tem changes. A b , the approach of a UPFC provides more operating flexibility by its
inherent adaptability to power systems changes or expansions without any alteration
in the hardware.
3.3 STATIC SYNCHRONOUS SERIES COMPENSATOR
This section provides a very thorough description of the Binary Voltage Source In-
verter (BVSI) based Static Synchronous Series Compensator (SSSC) , with ali the
controllers employed. Once again, its functioning and principle of operation are ïilus-
trated through explicit diagrams and detailed representations.
3.3.1 Configuration of a new SSSC
For active or reactive power compensation, injection of a controfled, synchronized volt-
age in a transmission line is a better alternative to adding circuit devices (capacitors or
inductoa) and controlling the current through them. This approach is recommended
for power flow control by soiid-state, synchronous voltage sources (SVS). It has been
shown in Chapter 2 that a solid-çtate, Synchronous Voltage Source implemented by
Voltage Source Inverters is able to produce a synckronous voltage similar to the one
generated by a synchronous machine at the fundamental frequency, by using only dc
energy sources and gate-turn-off devices.
For series compensation of a transmission line, the SVS must be connected in
series with the line through an insertion transformer. The real and the reactive
power of the compensatecl line is govemed by the phase angle and magnitude of the
injected voltage wïth respect to the line curent. When the injected voltage is in
phase quadrature with the line current, only the real power is influencecl. On the
3.3- STATXC SYNCHRONOUS SERIES COMPENSATOR 40
other hand, when the injected voltage is in phase with the voltage at the point of
common coupling (PCC), the ceactive power is rnainly influenced.
The new series compensator based on the BVSI is presented in Figure 3.3. The
SSSC is connected in series with a simple three-phase transmisson line modeled
through an impedance (assumed pure inductive).
The transmission line, which can be part of a more complex power system, is
connecting two systems considered infinite buses: a sendingsnd voltage source Vs
and a receiving-end voltage source VR. The buses considered are 230 kV, 60 Hz and
the voltage and bequency are assumed to remah constant during the operation. The
load angle between the two bus voltages is considered to be b degrees. The series
CAPACïïOR SWIII'CH ,- SWITCHING MI L
FlRING PAITERNS Km+ - VOLTAGE s Tpi CONTROL LOGE ** TABLE
Power Controller
Figure 3.3: Series connection of BVSL in a transmission line
3.3. STATIC SYNCHRONOUS SERIES COMPENSATOR 41
connection of the SSSC is realized through an insertion transformer. The windings of
the BVSI transformer side are delta-connected for the circulation of triple harmonies.
The SSSC consists of the lbstep, harmonie neutralized BVSI, three single-phase
coupling tramformers and the controllers represented in block diagram in Figure 3.3.
The controller gains are given in Appendix A.
Considering the diagram in Figure 3.4 representîng the phasors £rom the mode1 in
Figure 3.3 and, for simplicity, the voltages of the two systems to be equal, the power
in equation 3.1 can be also written as:
P = vr cos 4 (3-2)
Normdy, for equality between the magnitudes of the voltages at the two ends of the
transmismon line the current phasor is located at approximately the same angle with
respect to the two voltage phasors, so # = b/2. Then, equation 3.2 becomes:
The voltage injected by a multi-pulse inverter can be mathematically expressed as:
v Figure 3.4: Phasor diagram of the compensated system voltages
3.3. STATIC SYNCHRONOUS SERIES COMPENSATOR 42
where Vc is the injected compensating voltage, 1 is the Iuie eurrent, Xc is the reactive
line impedance, Xc is the capacitive reactance of the series compensation and k
defines the degree of the series compensation. Aftet the injection of the compensating
voltage Vc, the remaining voltage drop between the two systems can be defineci as:
b IXc - Vc = 2V sin -
2
or the h e current can be deducted as below:
By replacing the current in the equation 3.3:
V 6 6 P = -(2V sin - + Vc) cos -
XL 2 2
Thus, the tramferable power for two systems connected through a short transmission
line incorporating the effect of this compensation is given as a function of Vc:
In fact, the same compensated power can be written for an equivalent k pu compen-
sation as:
P = v
sin S X d l - k)
An interesting case arises for 6 = O0 when Vc = IXt is injected in the line. Then,
the effect of the compensating voltage is exactly the same as that of a phase-shifter,
introducing a phase Merence between each system voltage and the voltage at the
point of insertion, which should remain constant in magnitude. Theoreticdy, the
transmitted power would depend on the angle introduced by the compensating voltage
with respect to the terminai voltages.
3.3. STATIC SYNCHRONOUS SERIES COMPENSATOR 43
3.3.3 Main Controller
As can be seen fiom the bfock diagram in Figure 3.3, the main function of the power
controller is to respond to any change in the power demand and to adjust the z t u d
power trammitteci through the line such as to make these two variables qua1 at any
moment in t h e -
In order to do this, a compensating voltage Vc of certain amplitude and in quadra-
ture with the line current needs to be injected by the SSSC at the point of coanection.
The magnitude of the Vc is controlIed by the power contro1Ier in closed-loop until
the power request is met. The angle of the BVSI voltage wîth respect to the line
current is estabIished by a phase angle controller (-90' or 90') based on whether the
compensation required is capacitive or inductive.
The power flowing in the line at the point of the BVSI connection is measured
continuously and per-unitized by dividing the measured value to the rated power. The
rated power of the Iine is chosen to represent 1 pu. Thus, every t h e there is a new
power demand in the line above or below 1 pu, the controller responds by calculating
an error signal based on the new power demand and the power flowing through the
h e at that moment. This error is passed through a proportional plus integral (PI)
controller with fdback signal denved from the power measured in the line and the
new demand. The output of this PI controller is the modulation index (MI) and
depending upon its value, the modulation angles (Bi...&) to fire various switches are
selected from the precornputed switching patterns table (Table 2.1 in Chapter 2).
The sequence of d u e s for the firing angles (Bi...&) coming out kom the switch firing
logic are gate signal vectors (sa, sb, s,) for the inverters in the configuration of the
3-level binary VSI.
Figure 3.5 illustrates the phase angle controller used for generating a voltage signal
in quadrature with the line current for one phase. SlmiIar schemes are employed for
the other two phases, with the corresponding phase shiRs of f 120". The controlIer
3.3. STAmC SYNCHRONOUS SERIES COMPENSATOR 44
Phase due ta
I nansformer configuratim Fquenc y
*@d Magnitude
Figure 3.5: Inverter voltage phase angle controller
calculates the line current angle (4) with respect to the receiving-end voltage (VR)
considered as the reference phasor (6 = 0'). The phase angle of the generated signai
is either q5 - 90' when the inverter is operated in the capadive mode, or q5 + 90" for
the inductive mode of operation.
Also, the phase-shift fiom the delta configuration in the primary of the coupling
transformer to the star comection in the secondary is taken into account, and the
angle f& obtained fiom the capacitor voltage controller is added/subtracted fiom the
calculated voltage phase angle ( ~ ) depending on whether the capacitor voltages are
above or below the normalized levels. The fiequency of the voltage signal is held con-
stant at 60 Hz and synchronized to the supply. The magnitude of the output voltage
is controlled by the modulation index (MI) through the PI controller depending upon
the desired level of compensation.
3.3.4 Capacitor Voltage Con trouer
At the beginning of the BVSI operation, the capacitor voltage levels are set at
V&, 2Vd, and 4Vk, where the value of Vat was establisheà at 2 kV. As soon as
the batteries are removed leaving in place the capacitors to provide a constant dc
voltage and during the operation of the inverter, these voltages may drift from their
set levels due to the power losses in the inverter and an unbaianced operation of the
three phase system.
Basicdy, the charge and therefore the voltage across each capacitor is maintained
by prolonging or shortening the duration of the current flowing through it. This can
be achieved by shifting the switching patterns.
More charging of the capacitor can raise its falhg voltage when the inverter is
producing leading vars or absorbing laggîng vars. Also, a discharge of the capacitors is
necessary when the dc source voltages are jumping up while trying to support a VAR
request (hi case of a fa& occurring in the line during the capacitive compensation
mode). This can be done by deviating ftom the phase quadrature of the compen-
sating voltage with respect to the line current with a small angle; a few degrees can
cause a small real power exchange between the SSSC and the system for charging or
discharging the de side capacitors.
Figure 3.6 illustrates the dc source voltage controller employed on each phase,
which is the same controuer originally conceived for the capacitor voltage controller
in STATCOM [7]. In order to maintain the capacitor voltages constant and in b i n q
proportion, the phase angle of the generated voltage signal with respect to the line
current (1C, in Figure 3.5) is calculated to be a few degrees less than 90".
This deviation fiom 90' (Bd) is calculated nom the outputs of four PI controllers.
One error signal passing through the first controller is the ciifFerence between the
average of the dc voltages normalized for each level and a V&,rcj of 1 pu. The output
of the other three controliers is proportional to the difference between the average dc
voltage in pu on all the dc sources, and each individual capacitor voltage measured
and normalized to its reference value, producing some s m d angles A&. These AB1,
A& and A& are time intervals during which the conduction ofeach capacitor is either
shortened or prolonged depending on whether the capacitor voltage level is above or
below the reference value.
3.3. STATIC SYNCHRONOUS SElUES COMPENSATOR 46
Figure 3.6: Control diagram of the capacitor voltages
For the capacitive mode of operation, the delay @,.J (negative in si*) is subtracted
from the -90" phase quadrature of the voltage signal, resulting in a lagging angle for
the compensating voltage smaiier than -90". During the inductive operation of the
inverter, the (negative) deviation Or is added to the +90° phase quadrature of the
voltage signal such that +90° is decreased to a smaller leading angle of the inverter
voltage. The power exchanged at the t e d a l s of the SSSC is given by:
3.3. S?'ATIC SYNCHRONOUS SERIES COMPENSATOR 47
Figure 3.7: Polar representation of the tngonometric hinctions
where Vc is the compensating voltage, 1 is the h e current at the point of common-
coupling and Bd ïs the deviation calculateci in the capacitor voltage controiler.
As can be seen fiom the diagram in Figure 3.7, whenever the inverter voltage angle
is found in the positive semi-circle of the cosine function, the power exchange will be
positive causing a circulation of some real power fiom the system into the inverter
to keep the capacitors charged. However, for an angle exceeding f90°, the cosine
function wilI be negative and therefore the power exchange wilI have a negative sign
supplying a certain amount of watts to the system, thus reducing the overcharging.
In principle, the resulting angle gd causes the inverter to draw sufficient amount
of active power from the system to keep the capacitors charged, or to pump the
same amount of active power into the system to discharge the capacitors, in order
for their voltages to be kept to binary constant levels. In essence, it adjusts the net
active power flow intolout of the inverter, while the angles AB1, A& and A& are
used to prolong or shorten the conduction period of the capacitors Cl, C2 and Cs,
respectively. The net active power exchange with the system equalizes the switching
and the capacitor losses.
3.4. TEST OF THE NEW SSSC 48
3.3.5 Control of power flow
The operation of the SSSC is baseci on the injection of an almost sinusoidd voltage
in series with a transmission üne, having a variable magnitude and a phase angle
lagging or leading the iine current by 90". The amplitude of the injected voltage
is independent of the Iuie current magnitude. The load angle between the voltage
phasors at the two buses is supposed to remain unchangeci.
By injecting this compensatirtg voltage in anti-phase with the voltage drop across -
the line, the total voltage drop between the point of injection and the receiving-
end bus is increased as if the line impedance was increased. In fact, the effective line
impedance remain constant while more current and accordingly, more power is allowed
to flow through the line (Figure 3.8-a). On the contrary, when the compensating
voltage is inserted in phase with the iine voltage &op, the effect on the total voltage
drop is reversed, the load angle between the intermediate bus and the receiving-end
bus is decreased (fkom 6 to Y), and also the amount of current and power transferred
through the line (Figure 3.8-b).
From the phasor diagrams in Figure 3.8 the power transfer characteristic of a iine
compensated with SSSC is:
The fundamental V, of the injected voltage is controlled to lag or to lead the line
ciirrent by 90°, and the compensating reactance is defineci to be positive for capac-
itive compensation and negative for inductive compensation, t hereby increasing or
decreasing the current and the power in the line, respectively.
3.4 TEST OF THE NEW SSSC
The operation of the new Static Syndironous Series Compensator and the validity
of the power controlier are evduated through transient simulations using PSCAD
3.4. TEST OF THE NEW SSSC 49
Figure 3.8: Steady-state operation of the SSSC for capacitive (a) and inductive (b) compensation
software package. For simplicity, a test case is considerd where two infinite buses
are connected through a line represented by an inductance.
3.4.1 Test case with fine represented byan inductor
This case considers two inhi te buses, a sending-end voltage source and a receiving-
end voltage source, with the rated line voltage of 230 kV, at a constant synchronous
kequency of 60 Hz and the system base hf VA value (3-phase) is 100. In the model,
the source impedance type is resistive and no zero sequence of the impedance is
included. The load angle assumed is 30". The three phase line impedance is rnodeled
by an inductance, assuming no resistance. The value of the inductor is chosen such
as, according to the parameten of the system, a rated reai power flow of 100 MW is
transferred through the line. That gives an inductance of 701.6 mH in each phase.
The configuration of the BVSI, together with the power controller functions, are
rnodeled very precisely and the sd tch firing logic to generate firing pulses is called to
trigger the pulses during the run-time simulation. For simplicity, the voltages across
each dc source in the BVSI configuration are set to the binary ievels by batteries.
Thereiore, they are kept constant to the binary levels during the simulation. The
capacitor voltage controller will be employed later on, once the effeetiveness of the
new SSSC is tested.
3.4. TEST OF THE NEW SSSC .?O
The transformer used to conneet the BVSI to the line is modeled through three
single-phase transformers rated at 10 W A each. A small l ehge reactance of 0.1
pu is modeled inside the transfomers and no losses are considered so the transformer
model is lossless. The ta? changer windinq fkom primary to secondary have the
ratings 1:l but the magnitude of the voltage injected by the secondary is higher
than the magnitude in the pcimary because of the delta-star configuration of the
transformer.
3.4.2 Discussion of the results
The simulation results for the case described above are presenteâ in Figure 3.9. It is
to be noted that dinerent graphs use difEerent scales in order to highlight the requited
part of the characteristic.
In the beginning the SSSC is disconnected from the system and the 0ow of red
and reactive power is initialized to reach a steady-state in the k t 0.3 seconds, with
100 MW & 25 MVAR power transfer, which represents the line operating at full
capacity (1 pu). As long as no compensation is needed, the SSSC can remain discon-
nected fkom the h e .
At 0.5 seconds, the reference power is increased from 1 pu to 1.25 pu (Figure 3.9-
a) and the breakers co~ect ing the inverter to the line are closed. To increase the
power transferred, capacitive compensation is necessary in order to decrease the line
impedance. The voltage that the BVSI injects into the system is lagging the line
current by 90' (Figure 3.9-d) and the power controller calculates the correspondhg
Modulation Index (MI) (Figure 3.9-c). The value of the MI is initialized in the PI
controiler a t 0.631, increases abruptly when the error is considerably large because
of the new demand, and then settles to a certain value which produces the specific
required voltage to compensate for the power demand. Soon after the connection
of the BVSI, the required real power flow is transferred through the line. With the
3-4- TEST OF THE NEW SSSC
increase in the reai power Bow, a change in the amount of the reactive power flow is
also observed (Figure 3.9-b) which is due to the leakage reactance of the traosformer.
At 1 second, the power demand is decreased to 0.75 pu. The new demand imposes
the inverter to mit& the operating mode fion capacitive to inductive compensation.
The controiier adjusts the angle of the injected voltage such as to Iead the line current
which decreases in magnitude and therefore, the active power flow is reduced. A rapid
phase adjustment in the inverter output takes place within one cycle of power change
order.
It is to be noted that the SSSC is able to successfully switch from capacitive
operation to inductive operation in a few millisecon&. The fast response of the
inverter enhances the transient overall stability of the system to the changes that
take place in the power demand.
3.4. TEST OF TEE NEtK SSSC -5 2
3.4.3 Simulateci Test
tirne, sec
O Red power O Reactive power (b)
- - -
- . . tirne, sec
Modulation Index
t h e , sec
v , o r
time, sec
Figure 3.9: SSSC in capacitive and inductive mode
3.5. CHAPTER SUMMARY 53
3.5 CHAPTER SIAMMARY
A new Static Synchronous Series Compensator for real power control in a transmis-
sion line is presented in this chapter. First, the dynamic control of active and reactive
power flow is extendeci to the general concept of Unifieci Power Flow Controiier. O p
erating principle as well as phasor representation are given in order to understand
its control functions. The configuration of the new BVSI based SSSC is elaborated
and explaineci together with the controliers ernployed by this compensator. Again,
prïnciple of operation and brief analytical formulation are provided in expiicit dia-
grains and representations. Finally, the two modes of operation are tested in a simple
case with the transmission line represented by an inductor. The preliminary results
provide a sound basis for the following chapter in which more complex systems are
developed.
Bibiiography
[Il L. Gyugyi, CD. Schauder, and K.K. Sen, "Static synehronous series compensator:
A soüd-state approach to the series compensation of transmission Lines," IEEE
Transactions on Power Delivery, vol. 12, no. 1, pp. 406417, January 1997.
[2] K.K. Sen, ''SSSGstatic synchronous series compensator: Theo y* modeiing and
applications," IEEE ~ n s a c t z o n s on Power Deliveq, vol. 13, no. 1, pp. 241-246,
January 1998.
[3] C. J. Hatziadoniu and A.T. Funk, "Development of a control scheme for a series-
connected solid-state SVS," IEEE ~ n s a c t z o n s on Power Delivery, vol. 11, no.2,
pp. 1138-1144, April1996.
[4] L. Gyugyi, C.D. Schauder, and S.L. Williams, "The irnified power flow controuer:
A new approach to power transmission control," IEEE Transactions o n Power
Delivery, vol. 10, no. 2, pp. 1085-1093, April 1995.
[5] L. Gyugyi, "Dynamic compensation of ac transmission lines by solid-state syn-
chronous voltage sources," IEEE Transactions on Power Delàuery, vol. 9, no. 2.
pp. 904-911, April 1994.
[6] L. Gyugyi, "Unined power-flow control concept for flexible ac transmission sys-
tems," IEE Proceedings-C, vol. 139, no. 4, pp. 323-331, July 1992.
[7] K.V. Patil, R.M. Mathur, J. Jiang, and S.H. Hosseini, "Distribution system corn-
pensation using a new binary muitilevel voltage source inverter," IEEE Transac-
tions on Power Delàwery, vol. 14, no. 2, pp. 459-464, April 1999.
Chapter 4
DEVELOPMENT OF A TEST SYSTEM FOR S S S C
In this chapter a complete test system is developed progressively, starting ftom the
mode1 of two infinite- buses connected t hrough a transmission line, then replacing one
end with a synchronous generator and the other end with a resistive load. Different
load changes and power order changes are simulated and tested to prove the vaIidity of
the SSSC operation under various operat ing conditions and system changes. FinaiIy,
a few faults are simulated fiom single-phase to ground fault to most severe conditions
Iike a three-phase to ground fault o c c d g for five cycles. Each case is presented
separateiy and simuiated with the help of the PSCAD/EMTDC software program [II which is described briefly in the following section.
4.1 SIMULATION PROGRAM
PSCAD (Power System Computer Aided Design) is a collection of programs created
to provide a very flexible interface to electromagnetic transients simulation software.
EMTDC is a library of various power system models, components and procedures
which, t oget her with the collection of programs, constitutes the simulation software
provided with PSCAD. These two software packages are known and referred to as
" PSCAD/EMTDC . In other words, PSCAD is a famiiy of cornputer tools designed
to help simuiate power systems.
4.1. SIMULATION PROGRAM 56
The EMTDC program has been developed since 1976- It tas been used to solve
systems far larger and address problems far bigger than origindy conceived. One
advantage to the uset is the FORTRAN coding which must be used to develop modeis
such that the user can create his/her own unique system.
EMTDC can model:
resistor, inductor and capacitor circuit elements;
mutuaiiy coupled windings;
distributeci, fkequency dependent transmission lines and cables;
sources;
swit ches, thyristors, diodes and gate- turn-O ff devices;
analogue and digital control hct ions;
AC machines and static compensators;
meters and measuring functions;
generic DC and AC machine controis.
EMTDC is used for studies such as:
1 - Control system studies with non-linear eiements, for optimizing performance
of DC transmission, static compensation, AC machines, switched systems.
2. Subharmonic problems of an AC system such as transient torque analysis a d
subsynchronous resonance including response and effects on DC transmission, static
compensation and AC machines.
3. Methods of forced commutation of DC systems.
4. Impact of weak AC systems on DC converters and methods of improving system
performance.
5. Series or parallel DC transmission systems.
6. The effects of AC and DC circuits on the same tower.
7. Flexible AC transmission systems (FACTS).
8. The impact of electromagnetic pulse on transfomen.
9. Operation of self excited induction generators for use in smali hydro and wind
turbine systems,
In this thesis, the EMTDC program was used to build a system model of a new
FACTS device to provide series compensation for a transmission iine connectbg two
buses. The new series compensator is a Binary Voltage Source Inverter (BVSI) based
Static Synchronous Series Compensator (SSSC). The BVSI model was created by a
FORTRAN mitten user program [21.
4.2 TRANSMISSION LINE CHARACTERISTICS
Out of the four distributed electrical circuit parameters of a transmission h e (se-
ries resistance R and inductance L, shunt conductance G and capacitance C), the
characteristic behaviour of the line is dictated by its series inductance and shunt Ca-
pacitance. The series resistance and shunt conductance are ignored when modeling
the line because their influence is insignificant. Figure 4.1 shows a lumped-parameter
equivalent circuit of one phase of a transmission line with identical synchxonous ma-
chines connecteci at both ends. This is a model of a symmetrical line 131.
RECEIVING END Line inductance
A I - l n 1
\ Line capacitance
Figure 4.1 : Lumped-element representation of a long transmission line
Since both G and R are negligible, the high voltage lines are assumed to be lossless.
Hence, the characteristic impedance Zc with losses neglected is often referred to as
the surge impedance (SI) [41. It is numerically equd to:
being a function of the line inductance and capacitance but independent of the line
length. It has the dimension of a pure resistance. For high voltage overhead-lines,
the positive sequence value Iies in the range of 2 0 0 0 Q. A convenient average value
of the surge impedance is 400 Q [5].
If losses are neglected, then the line is entirely characterized by its length and by
two other parameters, Zc and p:
where X is the wavelength and /3 is the wave number. At 60 Hz, A is 3100 miles and
p can be expressed as 0.116°/mz. Since these two parameters are roughiy equal for
al1 lines, the behaviour of a line is different according to its length, voltage and level
of power transmission.
When a resistance equal to the surge impedance of a transmission line is connected
across the receiving-end of the line, a sinusoidal voltage introduced into the sendinp
end travels along the line being completely absorbed. The voltage at the receiving-end
varies sinusoidally in tirne, has the same magnitude as the voltage at the sending-
end, and is displaced by an angle equivalent to the time required for the wave to
move from one end to the other. The phase angle between the sending-end and the
receiving-end, which is also known as the electriccil length of the h e , expressed in
radians or wavelengths, is given by:
where L is the total length of the line. For a 100-miles line a t 60 Hz, the electrical
length of the iine is 0.203 radians or 11.6'.
4.2. TRANSMISSION LINE CEfARACTERISTICS .5 9
Figure 4.2: Phasor diagram of a naturdy loaded line
If both V and I a t each end have a constant amplitude and are in phase with each
other dong the line (Figure 4.2), the line is said to have a flat voltage profile and to
be naturally loaded. The load deüvered over the line to the resistance equivalent to
the SI is caiied surge impedance lauding (SIL) or natural load and is given by:
K2 P o = - [MW] zc where iç the rated voltage of the line in volts. Based on an average value for the
SI of 400 O, the SIL can &O be written as:
SrL =2.5(kv)* [kW] (4.5)
where kV represents line-to-line kilovolts of the transmission line. For a nominal
voltage of 230 kV the SI is approximately 380 0, while the SIL is about 140 MW.
The reactive power balance is achieved at the natural loading (SIL). This is the
unique value for the transmitted power that gives a flat voltage profile of the line and
unity power factor at both ends. Po is also caiied the natural power of the line and
the reactive power is zero. It means that, at the natural load, no reactive power is
absorbed or generated at either end of the line.
4-3- TRANSMISSION LINE WITH INFINITE BUSES 60
4.3 TRANSMISSION LINE WITH INFINITE BUSES
This case presents the mode1 of a medium-length line (230 kV, 60 Hz) connecting
two infinite sources.
In modeling the test system, a 200 km (124.3 mi) length of the line is chosen
with ground resistivity of 100 ohm - m. This medium-length line is modeled as
a Bergeron, ideally-tramp& line, with the low frequency of 60 Hz and a high
fiequency of 106 Hz. The conductors type is AC conductors, 3 phases, rated at
230 kV line-teiine rms, displaceci by 120 electrical degrees. The generd conductor
data is considered by default in solving for the line constants. After the program
processes and solves the data, it is saved in a batch fde which is hurther compiled in
the draft file before running the simulation.
Two infinite sources are connected at each end of the line. Each source bas a
system impedance which is represented as RRL (R in series with paraIlel combination
of RL circuit). The system base MVA (%phase) is 100, the base fiequency is 60 Hz.
For this case, since the line losses are modeled, the magnitude of the voltage at the
sending-end is chosen to be slightly higher than the magnitude at the receiving-end.
That ensures the direction of the power flow, together with the phase displacement
between the two sources. The initial source magnitude of the sending-end is thus
selected to be 235 kV line-to-line while the voltage magnitude at the receiving-end is
only 230 kV. These values are assumed to stay constant during the operation since
they represent voltage-controlled buses.
For a line length of 200 km (124.3 mi), the phase angle between the two sources
is 14.5" according to equation (4.3). The initial phase from the receiving-end to the
sending-end is thus chosen to be 15 degrees. This value is found on the stable part
of the power-angle diagram ensuring stable operation.
In the above situation the line is able to transfer approximately 185 MW of real
power fiom the sending-end to the receiving-end, which corresponds to 1.32 pu SIL
4.4. POWER ORDER CHANGES 61
operation. While the circulation of the real power is done in one direction only, both
sources are generating a smaU amount of reactive power (approximately 5 MVAR),
which is injected in the üne symmetricaliy by both ends. That can be explained by
the fact that the line operates heavily loaded (with 1.32 pu SIL) and, therefore, a
certain amount of reactive powec is absorbed by the line, which is suppüed by the
infinite sources at the two ends.
The transformer through which the conneetion of the SSSC to the iine is realized
has the same characteristics as the one modeled in the test of the new SSSC (Chapter
3). According to different ratings of the tap changer windings, control of the real
power can be provided starting fiom the immediate viciniv of 1 pu real power floming
through the line up to 50% of compensation. The maximum power transferred during
normal operation without the SSSC comected to the line (185 MW) represents 1 pu
rated real power for this line.
When no compensation is needed, the inverter can be disconnected nom the Line.
As soon as the reference power in the power controllet changes, the breakers connect-
ing the SSSC to the system are closed and the angle of the compensating voltage
is adjusted to lag or to lead the line curent, depending upon whether capacitive or
inductive compensation is required.
4.4 POWER ORDER CHANGES
For the system modeled in Section 4.3 the rated power on the line is 185 JI1 k W .
representing 1 pu. The circuit of the mode1 is presented in Appendix A.
The transformer co~ec t i ng the SSSC to the system has delta to star configuration
£iom the inverter side to the h e , to eliminate triple harmonies produced by BVSI
entering the line. Therefore, the magnitude of the voltage injected fkorn the secondary
side will be higher than the one produced in the ptimary of the transformer, and
also there wili be a phase shift of 30° (change fkom ph& voltages to line voltages),
Table 4.1: BVSI's output voltage limits
marginally modifieci by intenial impedance voltage drops. This angle was taken in
consideration when designing the invertet voltage phase angle controller for the SSSC.
According to the selected value for Vd, of 2 kV on the capacitors side and in
b c t i o n of the Modulation Index calculated fiom the PI controller, the inverter is
able to produce a voltage of a certain magnitude between two ümits dictated by the
maximum and minimum acceptable values for the MI (Chapter 2, Section 2.5.3).
Sorne of these values are shown in Table 4.1, and the corresponding voltages are
calculated from equations (2.25) and (2.28). As can be seen from the above table,
the configuration of the BVSI aliows for a minimum of 6.4 kV and a maximum of
11.16 kV at the output terInbals of the inverter. The voltages on the transformer
secondary are 4 times the primary d u e s .
In order to provide compensation for the real power over a wide range ( h m 0%
to 50%), by selecting dinetent ratings for the tap changer windings of the transformer
more flexîbility in the magnitude of the inverter output voltage can be obtained- To
provide control in the immediate vicinity of 1 pu real power flowing through the
line, the insertion transfomers on each phase must have an appropriate rating of
the transformer windings of 41. A ratio of 2:l for the transformer windings makes
possible a compensation degree between 15%-25%. With 1:l rating of the tap changer
windings, the compensation level can be increased up to 50%.
A higher degree of compensation could be achieved if the transformer ratings are
ML 0-510
T t d o r m e r primary voltage (kV) 6.40
Transformer secondary voltage (kV) 11.09
4.5. LNE WITH SYNCHRONOUS GELIERATOR 63
further changed to 1:2, but in this test case compensation over 50% is not considered
for the study. Difterent power order changes are made possible by selecting appr*
priate ratings in the insertion transformer model, thus providing control over a wider
domain.
4.5 LINE WITH SYNCHRONOUS GENEUTOR
This case considers the above described transmission line connecting a 350 MtrA
synchronous generator with aU the dynamics enabled, with a stepup transformer at
one end, to a resistive ioad at the other end. The PSCAD circuit drawing and the
data are shown in Appendix A.
For the 350 MVA, 13.8 kV, %phase synchronous machine, the rated voltage and
current are respectively 13.8 kV l ine-tdhe and 14-64 kA. The machine is connected
to the 230 kV transmission iine through a %phase 350 MVA stepup transformer
with A-Y configuration. At the other end of the iine a resistive load of 0.5 pu is
connected to the terminal. In steady-state the machine should supply 173 MW of
power accordhg to the load flow.
4.6 LOAD CHANGES
Initiaily, the machine runs in steady state until load changes are made. Different
load changes are simulateci at the receivîng-end of the transmission line to verify the
ability of the inverter to respond to the changed operating conditions at the customer
bus.
A change in the reai load is created by adding a resistor in parailel to the Load
resistor. The total load resistance is changed to produce 1.5 pu load. However,
increased loading reduces the voltage at the load bus with a smali percent and, with
the SSSC disconnectecl from the system, the real power transiend to the load is seen
to be l e s than 1.5 pu. With the SSSC connected at the sending-end its effectiveness
is demonstrated as it creates capacitive compensation. The invertet is able to reduce
4.7. FAULTS 64
the total effective transmission h e impedance through the injectai voltage and &O
helps in improviag the voltage profile at the load bus. Therefore, the r e q d red
power is delivered to the load.
The system is tested for inductive compensation as weli. Instead of adding more
load to the system, a change is created by reducing the initial load by 50%. Thus, l e s
power should be drawn fiom the generator at the sending-end bus and the load on
the system should equd 0.5 pu. It is seen again that with the SSSC connecteci to the
system, the real power flow through the Iine is reduced exactly to 50% because the
line impedance is axtificiaiiy increased by the inverter voltage injected at the point
of comection. Inductive compensation is thus realized when l e s power is required
£rom the consumer bus. This request is translated in a reference power per unit and
rocesseci as input to the power controuer which determines the necessary value
of the Modulation Index. Hence, a certain amount of voltage is added to the line
providing the needed compensation. The voltage profile is maintained approximately
at 1 pu a t the load bus as well.
4.7 FAULTS
The operation of the SSSC is examined and tested under abnormal operating condi-
tions occurring in the transmission üne. DifFerent faults are simulated in the system
described in Section 4.3, starting with a single-phase to ground fault of 5 cycles du-
ration. Next, a two-phase to ground fault and f indy a three-phase to ground fault
with the same duration are tested. The simulation results prove the effectiveness of
the SSSC to maintain operation even when faults occur during dinesent operating
modes of the compensator. Mter clearing the fault the system restores back to its
predisturbed state.
In order to check the validity of di controllers the capacitot voltages are monitored
during the mn-time simulation and also the luie voltages. An harmonic analysis is
performed for each particular type of fault at Herent moments in time after the
fault has been cleared to verify the percent of the total harmonic distortion present
in the line voltages.
4.8 CHAPTER S-Y
In this chapter a cornplete test system for the SSSC has been developed snd simulateci
to test its functioning under dBerent operat ing conditions. Lnitiaily, the transmission
h e is fed by two W t e sources and multiple power order changes can be applied to
the system. In order to aehieve a level of capacitive/inductive compensation over a
wider range, different ratios in the transformer windings have to be changed. Then,
two infinite buses are replaced by a synchronous machine and a resistive load and
Merent load changes are applied to verify the SSSC response in a more realistic
system. Faults of changed severity are initiateci in the Line while SSSC is working to
verify its performance under abnormal operating conditions.
[l] PSCAD/EMTDC Power Systems Simulation Softwafe, user's manual, Manitoba m c Research Center, Winnipeg, Manitoba, Canada, 1996.
[2] Krishnat V. Patil, Dynornzc Compensation of Electfical Power Sys tem wing
a new BVSI STATCOM, Ph.D. thesis, Electrical and Cornputer Engineering, University of Western Ontario, March 1999.
[3] T.J.E. Miiier, Guide for Economic Evaluatàon of FACTS in Open Access Envi- ronrnents, John Wiley & Sons, 1982.
[4] Prabha Kmdur, Power System Stability and Control, McGraw-EW, Inc., 1994.
[5] Central Station Enmeers of the Westinghouse Electric Corporation, Ed., Elec- trical ~ n s m ù s z o n and Distdmtion Reference Book, Oxford &IBH Publishing Co., East Pittsburgh, Pennsylvania, 1950.
Chapter 5
SIMULATION RESULTS
In this chapter the results of significant power order/Ioad changes and recovery of
a system subsequent to various iine faults, obtained from the transient simulations
nui with PSCAD/EMTDC [l], are presented. Conclusions are drawn based on the
observations made with regard to the operation and utilization of the new SSSC for
real power control. The simulations are run for dinerent intervals of time fiom 1 to 3
seconds and some of the graphs are presented ody for a smailer duration to highlight
the important part of the curve. Also, some of the variables are plotted on magnified
scales to allow a cornparison between the shapes for curves of different order.
5.1 DISCUSSION OF THE RESULTS
The test system with two infinite sources at the ends (Figure 3.3) is considered first
for examining the effectiveness of the SSSC for real power compensation in both
capacit ive and inductive modes.
5.1.1 Switching fiom one mode to another
At the beginning of the operation, the two-bus system is tramferring a certain amount
of real power fiom one end to the other according to the parameters described in pre-
vious chapters. The cornplete system is illustrated in Figure A.1. In the normal state
5.1. DISCUSSION OF THE RESULTS 68
135 MW power is transferred on the line and this amount reprgents the iine operat-
ing at 1 pu power. The SSSC is disco~e~ted fiom the system, when no compensation
is needed.
Once the simulation stabilizes to a steady-state (0.4 s), the iine is operating at
its fidl capacity. For SSSC, the capacitors (voltages) are initiaily charged at 2, 4 and
8 kV levels by batteries. Figure 5.1 presents the r d t s showing the action of SSSC
operating in both capacitive (boost) and inductive (buck) modes.
At 0.5 seconds the reference power for the line is increased from 1 to 1.5 pu with
SSSC connected to the system to provide the requwd 50% capacitive compensation.
It is seen that the power in the line attains the reference value change in less than
0.2 seconds (Figure 5.1-a). At 0.1 seconds after the BVSI is connected to the system,
the batteries placed across the dc sources are removed and the capacitor voltages
(Figure 5.1-b) axe adjusted and maintaineci in the binary proportion by the capacitor
voltage controuer which starts operating at the same t h e with the power controller.
At 1.5 seconds the power demand is reduced abruptly to 0.5 pu requiring an induc-
tive compensation of 50% from SSSC. To accommodate the power order reduction the
phase of the injected voltage by SSSC undergoes 180° phase shift, which is achieved
within one cycle as may be observed from Figure 5-14. Notice that the phase of the
h e current remains unchanged but its magnitude is reduced conesponding to the
power level change. It should be observed that the line voltages (Figure 5.1-d) remain
almost unaffected and that the harmonic distortion due to the injection of the 15-step
BVSI-SSSC output voltage is practicdy negligible (Figure 5.1-e) .
A harmonic analysis is perfomed on the line voltages measured after the point
of common coupling and the total harmonic distortion coefficient (THD=1.5976%)
proves that a very srnall percent of harmonies is introduced into the system by the
inverter voltage.
This result is achieved by the injection of a voltage waveform (V,) approxhating
5-1. DISCUSSION OF THE RESULTS 69
a sinusoida1 (Figure 5.1-c) which compensates foc the &op across the üne between the
two buses. The phasor of this voltage being perpendicular to the curent phasor at the
point of insertion, either supplements or annihilates part of the voltage drop taking
place in the uniforrnly distributeci reactance of the transmission line. Hence, more
or l e s current is drawn from the sendineend since the power angle of the voltage at
the intermediate point is either advanceci or retarded from the original phase shift
between the two buses, which remains unaffecteci by the power changes.
Figure 5.2 presents simüar results when the power order is changed fiom 0.5 pu
to 1.5 pu, switching the SSSC from inductive to capacitive compensation. In both
situations, the transition occurs very fast wit h a rapid phase adjustment in the inverter
output within one cycle of the power order change.
5.1.2 Diiferent power orders
Compensation of the real power can be achieved at Merent power orders. Figure 5.3
illustrates a power order step change of 25% in both directions together with the
modulation index (MI) values. The modulation angle is calculateci contiouously based
on the actual power need at every instant. Therefore, the variations of the real
power flow take place according to the output of the PI controller which produces
the MI. It is to be noted that for a higher error in the power controller there is a
jump in the value of the MI and as the power in h e approaches the desired value,
the MI stabilizes to an almost constant output, thus maintainhg the level of the
compensation. Obviously, the lower the compensation level required, the smaller is
the injected voltage. And also, with a smder step in the power order change, the
capacitor voltages are subjected to a smoother variation.
5.1.3 Load changes
Different load changes are simulated in the second test system with a synchronous
machine at the sending-end and the resistive load at the receiving-end (Figure A.4).
5.1. DISCUSSION OF TEE RESULTS TO
The simulation results show the performance of the SSSC in a more realistic system.
AMer the initiaization of the machine the real power flow is 1 pu. At 0.6 seconds
another resistive load is switched in at the load bus demanding 50% more real power
from the genetator. The line is able to increase its transmission capacity but not to
the required demand (Figure 5.4-a) and this happens because the voltage at the load
bus (VR) drops below the 1 pu level due to line &op (Figure 5.4-c). This situation
requires voltage regdation at the receiving-end which was not modeled in this case.
Figure 5.5 demonstrates the efféctiveness of the SSSC under such circumstances. The
required power transfer is made possible since the voltage profile at the load bus is
dso improved (Figure 5.5-c) .
Figures 5.6 and 5.7 depict the same situation when the load is reduced by 50%.
The power in the line is reduced partly without the SSSC connected to the system
and the voltage at the load bus increases above 1 pu (Figure 5.6-c). The inductive
compensation is &O effective in providing the exact amount of power to the consumer
as weU as bringing back the voltage level at the receiving-end (Figure 5 -74 .
5.1.4 Faults
The performance of the SSSC operation under different faults was studied for the test
system in Figure A.1 and the results are presented in Figures 5.8, 5.9 and 5.10. The
resulting wavefonns for this case show the variations in the fault severity.
Figure 5.8 presents a single-phase to ground fad t while the line is transferring
1.1 pu real power being capacitively compensated. At 0.5 seconds a fault occurs in
phase A of the transmission line reducing the line voltages Kb and V, by 1/fi and
leaving Vk unchanged for 5 cycles (80 milliseconds) until the fault is cleared. It is to
be obsewed that due to high fault cments in the b e , the capacitors charging leads
to transiently high values of Vds, 2Vd, and 4Vk. A few cycles after the fadt is cleaxed
the power in the system is restored and so are the capacitor voltage levels. The
5.1. DISCUSSION OF THE RESULTS Tl
total harmonic distortion is calcuiated at different moments in time &er the fault is
eliminated. The T H D is found to be less than 2% which shouid be acceptable as is.
A two-phase to ground and thee-phase to ground fadt are simuiated next. The
results are shown in Figure 5.9 and Figure 5.10. It should be noted that the variation
in the dc capacitor voitages are dinerent in the inductive operating mode (when the
iine powor is reduced to 0.9 pu).
In case of a fauit in a reai system, a voltage dependent controller could be added
which would detect fault conditions when the Iine voItages drop beIow a threshold, and
disable the SSSC (voltage) controllers to ensure that the capacitors are not subjected
to overvoltages during the fault and its recovery period (Figures 5.8-b and 5.10-b).
Capacitor overcharging (overvoltage) is observed when the SSSC experiences fault in
its capacîtîve operatîng mode. Figure 5.9 shows undervoltage when the fault occurs
when the SSSC is operating in the inductive mode. The voltage dependent cut-off
controller wodd remedy this undervoltage as well and actually speed up recovery.
5.2, TRALVSfENT SIMULATIONS 72
5.2 TRANSIENT SIMULATIONS
time, sec
time, sec
1.45 1.47 1 -43 1-51 1.53
tirne, sec
Harmonic Spectnim (THI)=1.5976%) (4 350 - 280
210 - 140 - 70 - -
O i - - - 1 . . s . . O 5 10 1s 20 2s 30
Hanaonic Number
Figure 5.1: SSSC switching fiom capacitive to inductive mode
5.2- TRANSIENT SIMUCATIONS 73
- 0 0.5
time, sec
O 0.5
t h e , sec
1.4s 1.47 1.49 1-51 1.53
time, sec
Harmonic Spectrum (THD=l.5995%)
Harmonic Number
Figure 5.2: SSSC switching from inductive to capacitive mode
5.2. TWVSIENT SIMULATIONS 74
a Real power O Reactive power (4
I - -
time, sec Modulation hdex
0.9 - 0.8
0.7
0.6
0.5 r . O 0.5 1 1.5 2 25
time, sec
a Vdcl 0 vu vdc3 (cl
10
8 - - - 6
4 - J I
2 - - I m -
Y
O + . . s O 0.5 t 1 -5 2 2.5
time, sec r o v , id)
1 -4 1.43 1.46 1.49 1.52 1-55
time, sec
Fime 5.3: Power flow and Modulation Index variation
time, sec
Real power 270 - 22s.
. \
O 0.3 0.6 03 1 2 1.5
tirne, sec
O 0.3 0.6 0.9 12 15
time, sec
Figure 5.4: Adding more load without SSSC connected
5.2. TRXIVSlENT SIMULATIONS 76
1.6 r - - - 1 2
. . I
O 0.3 i l6 0.9 1 2 3.5
time, sec
Real power (b)
O 0 3
time, sec
0.3
tirne, sec
Figure 5.5: Adding
0.6 0.9
more load with SSSC
12
connected
5-2, TFtMVSIENT SIMULATIONS 77
0 0 3 0.6 0.9 t 2 1 3
tirne, sec
Real power
time, sec
time, sec
Figure 5.6: Reducing the load without SSSC connected
5.2. TRANSIENT S-ATIONS 78
O 0.3
time, sec
Real power (b)
. . O 0.3 0.6 O3 1 1 15
tirne, sec
a VS 0 VR (4
250.
245
- - -
O 0.3 0.6 03 1 2 1.5
tirne, sec
Figure 5.7: Reducing the load with SSSC connected
5-2. TRANSIENT SIMULATIONS 79
Phase A to ground a t 0.5 seconds for five cycles
Table 5.1: THD for single-phase to ground fault
1 THD measured at 1 THD 1
- . 0.3
tirne, sec
0.3
time, sec
zoo-
0 - -200 -
I 0.47- 0.- 0.58 0.835 0.- 0-74s 0.0
tune, sec
F i m e 5.8: Sinde-s hase to mound fault occurrinn in the capacitive mode
Phases A and B to ground at 0.5 seconds for five cycles
Table 5.2: THD for doubIe-phase to ground fauit
1 T H D measuredat 1 THD 1
t - - - 0.8 - - 0.6 - 0.4 - 0.2 -
O 4 0.3 0.6 0.0 1.2 r .S 1.8 al 2-4 27 3
time, sec
0 4 4 0.3 O 1 0.9 1 3 1.5 1.6 2 1 2.4 27 3
time, sec (4
400 ! 0.47. 0- 0.50 0.03s 0.60 0.7- O d
time, sec
Figure 5.9: Two-phase to ground fadt occurring in the inductive mode
5 -2, TRANSIENT SIMULATIONS 81
Phases A, B and C to ground at 0.5 seconds for five cycles
Table 5.3: THD for three-phase to ground fault
1 .s
- -
0.2s
O q 4 0.3 0.6 0.0 1.2 1s 1 .a ~r 24 27 3
time, sec (b)
0.47- 032s 0- 0.- 0.69 0.7- 0.8
time, sec
Figure 5.10: Three-phase to gtound fault occurring in the capacitive mode
5.3 CHAPTER S L M M M t Y
This chapter presents digital simulation results of a BVSI based SSSC working in
both capacitive and inductive modes of compensation, in steady-state and under
abnormalities such as fauits. In order to examine the effectiveness of this new corn-
pensator, various operating conditions and multiple types of fadts are simulateci. The
transient analysis results show a very good control and fault recovery performance,
accompanied by a Iow value of the total hannonic distortion for the various cases
studied. This achievement reestablishes the usefuIness of the SSSC as a real power
cornpensator with a minimum harmonic distortion, due to the increased number of
steps in the stair-case output of BVSI voltage, its modulat structure and the selected
haxmonic elimination aIgorithm used for the minimization or elimination of the ha-
monics introduced into the system [2]. The BVSI based SSSC can successfully switch
its operating mode from leading to lagging and vice-versa, withont endangering the
system steady-state performance or the harmonic content, and the transition occurs
smoothly in any direction.
Bibiiography
(11 PSCAD/EMTDC Power Systenrs SimuZution Software, user's manual, Manitoba HVDC Research Center, W i p e g , Manitoba, Canada, 1996.
[2] Krïshnat V . Patii, Dynamic Compemotion of Electn'cal Power Systerns wzng a new BVSI STATCOM, Ph.D. thesis, Electricai and Cornputer Engineering, University of Western Ontario, Merch 1999.
Chapter 6
DISCUSSIONS AND CONCLUSIONS
This last chapter presents some important discussions and conclusions extracted from
the investigation conducted in this thesis. Also, it includes a few directions for further
studies regarchg the application of the SSSC in a power line.
6.1 GENERAL DISCUSSIONS
The electrical power industry is undergohg deregdation, requiring bill control of
power transmitted on important iines. This power control is derived from using
FACTS devices. To provide reasonable control of the power flow in transmission
networks, advanced power electronic devices are proposed, some of which ernploy
new, fast and sophisticated voltage source inverters (VSI). One topology for such a
device, named binary voltage source inverter (BVSI), capable of generating an ac
voltage at its output termin& with minimum harmonic distortion was proposed by
K.V. Patil, R.M. Mathur, et al. (11. It is a multilevel binary voltage source inverter. Its
configuration, toget her wit h a selective harmonic elimination modulation technique is
Nly researched by K.V. Patil[2]. This BVSI scheme increases the number of steps in
the ac voltage resulting in an almost sinusoida ac output reducing the total harmonic
distortion within acceptable limits and therefore, eliminating the need of employing
extemal filters.
6.2. CONCLUSIONS 85
This thesis has investigated the appiication of BVSI for the control of the real
power transferred over high voltage transmission networlrs. In the FACTS fiterature
such devices are c d e d Static Synchronous Series Compensators (SSSC) [3].
In this thesis a BVSI based SSSC has been proposai and hilly investigated. In-
vestigations were conûned to off-line digital simulations with appropriately designed
BVSI-SSSC and the requîred controllers. In the proposed SSSC a BVSI is used to
inject a voltage of the line frequency such that it either compensates for the iine re-
actance &op ( j IXL) thereby creating an effect akin to series capacitor compensation
(capacitive compensation), or increasing the line reactance (inductive compensation).
The resulting compensation increases (capacitive) or decreases (inductive) the power
flow on the Lne. A BVSI-SSSC therefore acts as an active power compensator (phase-
shifter). The proposed BVSI-SSSC operates as desired. In order to test its robustness
the proposed BVSI-SSSC is tested for step changes in power order as we11 as under
fault condit ions.
A BVSI-SSSC is designed and tested for a 230 kV transmission line. Its perfor-
mance is anaiyzed through transient studies. A two-bus system is modeled together
with the SSSC connecteci to the Iine. A real power controuer and a phase angle con-
troller are developed in the simulation program, and a capacitor voltage controller is
implemented to keep the voltages of the three de sources in binary proportion. The
digital simulation results demonstrate the performance of the BVSI based SSSC as
a real power compensator under various operating conditions, in steady-state as
as under abrupt fauits.
6.2 CONCLUSIONS
1. The low total harmonie distortion proves that the proposed stmcture of the
BVSI and the selected harmonie eiimination algorithm are effective in mini-
mization or complete elimination of the harmonies introduced in the system.
6-3. SUGGESTED FUTURE STUDIES 86
2. The BVSI based SSSC can smoothly switch its operating mode from lagging
to leading injected voltage with respect to the cment phasor at the point
of common-eoupüng, effectiveIy providing both series capacitive and inductive
compensations on a transmission line.
3. The proposed BVSI-SSSC operates tobustly as its operation is unafkcted by
severe line faults. Its recovery from fauits is reliable.
4. It can be conchded that the precise and fast, flexible and controiiable BVSI
based SSSC can therefore be utilized as a reai power compensator in a trans-
mission system to improve not only the power transmission capacity but it
can be used to add active power system damping without any degradation or
deterioration in the power quality even under severe disturbances.
6.3 SUGGESTED FUTURE STUDIES
The proposed BVSI-SSSC offers an alternative to the classical series compensation of
lines. In addition it offers controlled compensation and extends the range to inductive
compensation as well. The study of the proposed BVSISSSC has been carried out
in a simple test system. It should be extended to a complex transmission utility
system. Also, the location of the SSSC could be optimized for a network through
furt her studies.
The BVSI based SSSC, a series connected device, is designeci to provide only
real power control over a transmission line without massive real power exchange
with the system. When connected in shunt, such a voltage source inverter calleci
STATCOM negotiates reactive power at the point of common coupling. The dynamic
compensation of a distribution system with BVSI STATCOM was studied in [2].
These two elements, series and shunt connected, are the two parts constituting the
most universal and effective compensator known as Unified Power Flow Controller
(UPFC) .
6.3. SUGGESTED FUTURE STUDIES 87
It would be valuable to investigate the ability of the BVSI-SSSC to provide both
real and reactive power compensation by controiling the angle of the injected voltage.
The resulting device may be more econornical and effective for realizing a new BVSI-
UPFC as compared to a UPFC which combines a STATCOM and SSSC.
B I B L I O G W H Y 88
Bibliography
[l] K.V. Patil, ELM. Mathur, J. Jiang, and S.H. Hosseini, "Distribution system com-
pensation using a new binary multilevel voItage source inverter," IEEE Tmnsac-
tions on Power Delivery. vol. 14, no. 2, pp. 45-64, April 1999.
[2] Krishnat V. Patil, Dynamic Compensation of Eleetricaf Power Systerns using
a new BVSI STATCOM, Ph-D. thesis, Electrical and Computer Engineering,
University of Western Ontario, March 1999.
[3] FACTS Applieotiow, Number 96TP 116-0. IEEE Power Engineering Society,
1996.
Appendix A
CIRCUIT DIAGRAMS
This appendix gives the draft mes and data from PSCAD/EMTDC. The first three subsystem represent the initial test system with the two W t e sources at the ends.
The transmission line and the BVSI connected are represented together with the mea- surement functions in the main system. The main controllers (power controller and
phase angle controuer) are iilustrated in the block diagrams of the second subsystem.
The third subsystem presents the capacitor voltage controiler and the outputs which are used in the main system. The last diagram presents the main system when the
sending-end is replaced by the synchronous machine and the receiving-end by the re- sistive load to which more load is added and also, some load is removed respectively,
in order to simulate the load changes at the customer bus. The Controuer gains and the Insertion T'kansformer parameters are given neut:
Capacitive compensation K, = 1 Inductive compensation Km = -1
T' (seconds) = 0.1 Capacitive compensation Kp, KpI, Kp2, Kpj = 10, 12, 10, 12 Inductive compensation K,, Kpl, Kp2, Kp3 = -10, -12, -10, -12
Tp, TP1, TpZ , Tp1 (seconds) = 0.8, 1.5, 1, 1
Iosertion transformer parameters Transformer Single Phase = 10 MVA Leakage reactance = 0.1 pu
Magnetizing current = 1%
Air core reactance = 0.2 pu
Figure A.1: Main system for test case with two infinite buses at the ends
Figure A.2: Subsystem representing the red power controller
Figure A.3: Subsystem representing the capacitor voltage controiier
Appendix B
GATE PULSE GENERATION
GATE PULSES The gate pulses for the 12 mitches in one phase are shown in the foiiowing Table.
These firing pulses have b e n used in the FORTRAN algorithm for turning -on and -off the thyristors in the BVSI configuration.
Table B.1: Gate pulses output from switch firing logic
(degrees)
Fmm 1 TO
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Gate Pulses
1 mm ITO II:
180 - el - ne, + d, 180 + el - ~ e , 180 + Or - A& Ji80 + O i -A@l +dt
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I wt (degrces) II
