A New Cell Bypass Arrangement and Control for Modular ...1073693/FULLTEXT01.pdf · the whole structure operation is alidatedv on a 3 phase MMC PSCAD model. The ... MMC modular multilevel

IN DEGREE PROJECT ELECTRICAL ENGINEERING,SECOND CYCLE, 30 CREDITS

, STOCKHOLM SWEDEN 2016

A New Cell Bypass Arrangement and Control for Modular Multilevel Converters based on Thyristor Forced Commutation Circuit

SOTERIS POYIADJIS

KTH ROYAL INSTITUTE OF TECHNOLOGYSCHOOL OF ELECTRICAL ENGINEERING

A NEW CELL BYPASS ARRANGEMENT AND CONTROL

FOR MODULAR MULTILEVEL CONVERTERS BASED ON THYRISTOR

FORCED COMMUTATION CIRCUIT

Soteris Poyiadjis

A thesis submitted in partial

fulfillment of the requirements for the

degree of

Master of Science in Electric Power Engineering

Electric Power and Energy Systems Department,

KTH Royal Institute of Technology, Sweden

November 2016

Supervisor: Alireza Nami, Research & Development Power Electronics Team Leader at ABB

Corporate Research, Västerås, Sweden

Examiner: Hans Peter-Nee, Professor in Power Electronics at KTH, Stockholm, Sweden

Soteris Poyiadjis Master thesis i

Abstract

HVDC transmission lines are a competitive and in some cases are proven to bea superior choice compared to AC transmission applications. Suitable convertershave been developed for that matter where Modulär Multilevel Converters (MMC)are highly preferred due to their low losses, no ltering requirementsand direct andfast control of AC and DC side. However, the overall eciency of the converteris higher than of a six pulse voltage source converter, it is still lower than the linecommutated converter type.

In this master thesis an attempt to decrease the conduction losses of the MMC isinvestigated. A new cell structure design used in MMC is proposed along with itsassociated control strategy. The main idea is to divert the current at steady stateoperation through thyristors, which have lower conduction resistance than IGBTsthat are used in MMC topologies, at time intervals where the capacitor is bypassedfrom the cell. This new cell commutation is tested initially in the lab and thenthe whole structure operation is validated on a 3 phase MMC PSCAD model. Theresults from the lab conrmed the commutation of the new cell and the results fromthe 3 phase model showed that the new cell structure does not disturb the normaloperation of the MMC. A rough loss comparison that have been conducted betweenthe new cell structure and a half bridge that is used in a typical MMC, showed thatthe rst one was less ecient. For that reason a generalized concept is introducedwhich promise higher eciency than of the proposed concept.

A New Cell Bypass Arrangement and Control for Modular Multilevel Converters

Soteris Poyiadjis Master thesis ii

Sammanfattning

HVDC transmission är ett fördelaktigt sätt att överföra eekt i jämförelse med ACtransmission. Omriktare har utvecklats för att passa applikationen, där ModularMultilevel Converters (MMC) har visat sig passa bra för HVDC på grund av de lågaförlusterna och dess obentliga krav på lter. Dessutom har de en direkt och snabbkontrollteori på både AC och DC sidan. Även om dess totala verkningsgrad är högreän hos six-pulse voltage source converter (VSC) men lägre än Line CommutatedConverter (LCC).

Detta exjobb innefattar att minska ledningsförlusterna i MMCn. En ny designav cell strukturen föreslås, tillsammans med en passande kontrollteori. Idén äratt, på grund av dess lägre ledningsresistans använda tyristorer snarare än IGBTervilka annars är vanliga i MMCer, detta då kondensatorn är förbikopplad.. Dennya cellstrukturen testas initialt experimentellt i laboratorium och hela systemetvalideras genom simulering av en 3-fas MMC modell i PSCAD. De experimentellaresultaten bekräftade att den nya modellen fungerar och de simulerade resultatenvisar att den föreslagna topologin inte stör funktionen hos MMCn. En jämförelsemellan den nya topologin och den konventionella halvbridge strukturen har gjorts,där den föreslagna topologin hade lägre verkningsgrad. Istället har en generelltkoncept introducerats för att utlova en högre verkningsgrad än den först föreslagnatopologin.


Soteris Poyiadjis Master thesis iii

Contents

List of Figures v

List of Tables vii

1 Introduction 1

1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 State of the art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3 Description of the project . . . . . . . . . . . . . . . . . . . . . . . 4

1.3.1 Basic operation of MMC . . . . . . . . . . . . . . . . . . . . 51.3.2 Time periods to divert the current . . . . . . . . . . . . . . 71.3.3 Choice of device . . . . . . . . . . . . . . . . . . . . . . . . . 91.3.4 New cell structure . . . . . . . . . . . . . . . . . . . . . . . . 9

1.4 Generalized Concept . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2 Thyristor forced commutation in a full bridge 16

2.1 Basic operation of Thyristor . . . . . . . . . . . . . . . . . . . . . . 162.1.1 Switching characteristics . . . . . . . . . . . . . . . . . . . . 172.1.2 Turn-o time tq . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.2 Thyristor commutation in a Full Bridge . . . . . . . . . . . . . . . . 202.2.1 Tested Setup . . . . . . . . . . . . . . . . . . . . . . . . . . 202.2.2 Single pulse test sequence . . . . . . . . . . . . . . . . . . . 232.2.3 Results and Discussion of Single pulse test . . . . . . . . . . 24

3 Control Strategy for the New Cell Arrangement 27

3.1 Description of the MMC model design . . . . . . . . . . . . . . . . 273.2 Control of the new cell arrangement . . . . . . . . . . . . . . . . . . 29

3.2.1 Thyristor and Submodule control strategy for Rectier oper-ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.2.2 Thyristor and Submodule control strategy for Inverter operation 323.2.3 Improved Thyristor and Submodule control strategy for In-

verter operation . . . . . . . . . . . . . . . . . . . . . . . . . 34

4 Simulation results 36

4.1 Rectier operation using thyristor bypass . . . . . . . . . . . . . . . 374.2 Inverter operation using thyristor bypass without compensation . . 384.3 Inverter operation using thyristor bypass with compensation . . . . 39

5 Conclusions 41

5.1 Lab experiment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415.2 Control of the new cell arrangement . . . . . . . . . . . . . . . . . . 41


Soteris Poyiadjis Master thesis iv

6 Discussion 42

6.1 Loss comparison with MMC with half bridges . . . . . . . . . . . . 426.2 Generalized concept . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7 Future Work 48

7.1 Further investigation on tq turn-o time . . . . . . . . . . . . . . . 487.2 Apply the generalized concept . . . . . . . . . . . . . . . . . . . . . 48

8 Appendix 51


Soteris Poyiadjis Master thesis v

List of Figures

1.1 Evolution of HVDC converter topologies versus power devices tech-nologies [1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Alstom topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3 Trapezoid Waveform[5] . . . . . . . . . . . . . . . . . . . . . . . . . 31.4 Two slope Trapezoid Waveform[7] . . . . . . . . . . . . . . . . . . . 41.5 Three Phase Modular Multilevel Converter . . . . . . . . . . . . . . 61.6 Arm current and voltage . . . . . . . . . . . . . . . . . . . . . . . . 81.7 Arm current and voltage . . . . . . . . . . . . . . . . . . . . . . . . 81.8 Commutate Tp thyristor in a Full Bridge . . . . . . . . . . . . . . . 101.9 Commutate Tn thyristor in a Full Bridge . . . . . . . . . . . . . . . 101.10 Single Phase MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.11 Control Strategy of Generalized Concept . . . . . . . . . . . . . . . 141.12 Single Phase MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1 Thyristor (P-N-P-N structure) . . . . . . . . . . . . . . . . . . . . . 162.2 Waveshapes illustrating thyristor turn-on time for a resistive load[10] 172.3 Waveshapes illustrating thyristor turn-o time[10] . . . . . . . . . . 182.4 Thyristor current and voltage waveforms during circuit commutated

turn-o [10] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192.5 Single pulse test setup . . . . . . . . . . . . . . . . . . . . . . . . . 212.6 Picture of single pulse test setup . . . . . . . . . . . . . . . . . . . . 222.7 Full Laboratory Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 232.8 Single Pulse Test Sequences . . . . . . . . . . . . . . . . . . . . . . 242.9 Single Pulse Test Sequences . . . . . . . . . . . . . . . . . . . . . . 25

3.1 Control Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.2 Sorting balancer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293.3 Phase Disposition PWM . . . . . . . . . . . . . . . . . . . . . . . . 293.4 Positive arm's current (top), number of inserted capacitors (middle)

and signal of the 1st submodule (bottom) with unity PF at rectifyingoperation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.5 Thyristor Tn control strategy for one Submodule . . . . . . . . . . . 313.6 Positive arm's current (top), number of inserted capacitors (middle)

and signal of the 1st submodule (bottom) with unity PF at invertingoperation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.7 IGBTs signal of 1st submodule: Top - sorting balancer output, Bot-tom - modied signal . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.8 Thyristor Tp control strategy for one Submodule . . . . . . . . . . . 343.9 Thyristor Tp control strategy with compensation for one Submodule 35


Soteris Poyiadjis Master thesis vi

4.1 Output currents (top) and voltages (bottom) of the converter . . . 364.2 Positive and negative arm currents (top) and voltages (bottom) . . 374.3 Rectier operation: Arms and thyristors Tn currents, arms voltages

and arms signals of rst submodule . . . . . . . . . . . . . . . . . . 384.4 Inverter operation without compensation: Arms and thyristors Tp

currents, arms voltages and arms signals of rst submodule . . . . . 394.5 Inverter operation with 50% compensation: Arms and thyristors Tp

currents, arms voltages and arms signals of rst submodule . . . . . 404.6 Inverter operation with full compensation: Arms and thyristors Tp

currents, arms voltages and arms signals of rst submodule . . . . . 40

6.1 Half bridge cell operating modes (a) bypass (ip > 0), (b) insert (ip >0) (c) bypass (ip < 0), (d) insert (ip < 0) . . . . . . . . . . . . . . . 42

6.2 Zero crossing of arm current . . . . . . . . . . . . . . . . . . . . . . 436.3 New cell structure operating modes (a) bypass (ip < 0), (b) insert

positive (ip > 0) (c) bypass (ip > 0), (d) insert positive (ip < 0) . . . 456.4 Thyristor conduction area . . . . . . . . . . . . . . . . . . . . . . . 46

8.1 Circulating current control . . . . . . . . . . . . . . . . . . . . . . . 518.2 Active/reactive control and 3rd order harmonic injection . . . . . . 518.3 MMC model design . . . . . . . . . . . . . . . . . . . . . . . . . . . 52


Soteris Poyiadjis Master thesis vii

List of Tables

1.1 Characteristic Values of Power Semiconductors . . . . . . . . . . . . 9

2.1 Unidirectional Thyristor TZ500N . . . . . . . . . . . . . . . . . . . 212.2 Bidirectional Thyristor 5STB 18U6500 . . . . . . . . . . . . . . . . 212.3 HiPak IGBT Module 5SNA 0500J650300 . . . . . . . . . . . . . . . 222.4 Turn-o tq time for dierent on-state currents . . . . . . . . . . . . 26

3.1 MMC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 273.2 Signals (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31


Soteris Poyiadjis Master thesis viii

Acronyms

BCT bidirectional controlled thyristor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CTB controlled transition bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

FB full bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

GTO gate turn-o thyristors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

HVDC high-voltage dc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

HB half bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

IEGT injection enhanced gate transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

IGCT integrated gate commutated thyristors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

IGBT insulated gate bipolar thyristors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

LCC line commutated converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

MMC modular multilevel converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

PCT Phase controlled thyristors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

VSC voltage source converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1


Soteris Poyiadjis Master thesis 1

1 Introduction

1.1 Background

Although ac power systems have dominated the market since the late 19th centurythe advents of high-voltage dc (HVDC) transmission are commonly acknowledged.HVDC transmission applications proved to be a competitive and in some cases asuperior choice against the ac transmission applications. Examples for HVDC appli-cations are long under water cable crossing, long distance bulk power transmission,stable ac interconnection, interties with low short-circuit levels, coupling 50/60 Hzsystems and long-distance underground cable systems[1]. HVDC technologies arenot only used for point-to-point bulk power transmission but also for the integrationof large scale renewable systems such as wind farms and photovoltaics.

The eciency of these systems are dependent on the development of suitable con-verters. The continuous advancement of high-power switching devices has had animportant impact on converters used in such systems. Figure 1.1 shows the evolutionof HVDC converter topologies versus power device technologies[1]. In 1954, Mercuryarc valves were used for the rst time in line commutated converters (LCC). Lateron, thyristors repalced these valves due to the development of bipolar technologies.The capability to turn o a thyristor was later implemented in gate turn-o thyris-tors (GTO), and some years later integrated gate commutated thyristors (IGCT)were designed. In 1970s, the focus shifted to MOS technologies. A new eld of semi-conductor switching devices with metal oxide technology emerged, such as insulatedgate bipolar thyristors (IGBT). The IGBT was used for the rst time in convertersin 1990s, with the reputation of high eciency and fast switching. This developmentwas a cornerstone for the power converters eld. The voltage source converter (VSC)was developed by ABB for HVDC systems where series connection of IGBTs enablesto reach the required high dc transmission voltage. The VSC transmission technol-ogy is now in the fourth generation using modular multilevel converter (MMC).MMCs have been proposed by Marquardt, [2], and its main features are low lossesdue to a low switching frequency and no ltering requirements due to less harmonicdistortions.



Figure 1.1: Evolution of HVDC converter topologies versus power devices technolo-gies [1]

Although the overall eciency of the converter is higher than of a six pulse VSCbridge, it is still lower than the LCC converter type [3]. A lot of research hasbeen done with to improve MMCs eciency. Even though switching losses couldbe signicantly reduced by the development of advanced modulation techniques [4],no major improvements were achieved in terms of conduction losses. However, astudy has been performed by Alstom with the purpose to reduce conduction losses.Their proposed approach is discussed in the following section.

1.2 State of the art

(a) Control Transition Bridge [5] (b) Augmented Modular Multilevel Converter[6]

Figure 1.2: Alstom topologies



Alstom has proposed an innovative converter topology, the controlled transitionbridge (CTB)[5]. It represents a system, formed by a six pulse bridge with threechainlink converters, with each ones end connected to an AC phase and the otherend on the ground, as shown in Figure 1.2a. The main idea of this topology is thathigh average current would be diverted to the series connected semiconductors for alarge portion of the period of time. A trapezoid waveform is used in this topology asshown in Figure 1.3, where at the top and bottom at periods the semiconductorswill be switched on. The chainlink will give a controlled voltage transition fromone voltage rail to the opposite voltage rail while both semiconductor switches inthe said phase are open. The benet of this is that the switches can be formed byseries connected thyristors, which have low on state resistance. Another benet isthat not only the chainlink circuit will provide commutation of thyristors but byregulating the slope of the transition the snubber components can be minimized.

Figure 1.3: Trapezoid Waveform[5]

By using a trapezoid waveform, it gives the advantage of the fundamental com-ponent of the converter voltage, to rise above the DC link voltage. Thus, the ACcurrent for a given power rating is reduced and consequently the converter losses arelower. Moreover, the remaining harmonics can be signicantly reduced by reducingthe slope angle of the transition. However, some issues arise with this topology.Some levels of low order harmonics are produced and need ltering. A second issueis that it does not allow much variation in fundamental magnitude, which makesthe converter less attractive regarding the out of balance conditions caused by singlephase faults.

A development of this converter was made by Alstom where in [6] proposed a topol-ogy shown in Figure 1.2b. The three bidirectional chainlink have been replaced bythree unidirectional chainlink. The converter follows the same operational principalas that given in [5] and it combines a six pulse VSC bridge with an MMC. Themain dierence of this converter is that it can operate with a trapezoid waveformin which the slope angle (γ) of transition can go beyond π/6, without the currentin the DC link becoming discontinuous. This feature solves the main issue that was



addressed at the initial topology in [5]. From the calculation of converter losses theresult showed that are in region of 0.6% compared to a notional 0.7% loss, typicalfor an equivalent MMC. Furthermore, the results indicate that capacitors size canbe signicantly reduced since the energy ripple associated with the chainlink circuitoperation is decreased. However, the problem addressed in this topology is thatthe process of switching between dierent channels within the bridge is leading totransient spikes appearing in the terminal waveforms. Furthermore, the THD wascalculated in the region of 1.5% which for VSC applications still requires ltering.

A further study was made to deal with problems in [7]. The proposed solution wasto produce a transition curve comprised with two slopes, which are dened by threeterms (γ1, γ2 and k) as shown in the Figure 1.4. In this study it was found thatthe fundamental could be controlled over a wider range. Nonetheless, high THD inthe region of 1% was found, which for VSC applications still requires a degree ofltering.

Figure 1.4: Two slope Trapezoid Waveform[7]

1.3 Description of the project

In this project a new cell structure will be developed to reduce conduction losses inMMC topologies. The main idea is to divert the current to a path with a lower on-state resistance, not only during the transition as Alstom topologies but also duringthe steady state operation of the converter. The advantage of the proposed methodis the modularity of the structure, which makes it possible to be applied to anymodular multilevel converters without interfering the topology and its operation.

This section has been organized as follows: Initially the basic operation of MMC isintroduced. After that, according to the converter operation, the periods of timethat is mostly preferable to divert the current are indicated. Later on a choice ofa semiconductor switch with low on-state resistance is made. Finally, the new cellstructure design is presented.



1.3.1 Basic operation of MMC

The schematic of a three phase MMC is shown in Figure 1.5. Each phase leg consistsof two chain arms, one positive arm and one negative, connected in series betweenthe DC terminals. At the midpoint of each leg the ac terminal is indicated. Eacharm has an inductor and N number of submodules connected in series. OriginallyMMC is build up by half bridge (HB) cells as the basic commutation cell. However,other types of the submodules and their functionalities for MMC have been proposedand discussed in [1].

By applying KCL and KVL and neglecting the voltage drop over arm inductor(Larm) the currents of both positive and negative arms are dened as:

ip(i) = IDC/3 + is(i)/2 (1.1)

in(i) = IDC/3− is(i)/2 (1.2)

where is(i) and IDC are converter phase and dc current, respectively. Note that iindicates the phases a, b or c and p and n indicates the positive and negative armrespectively. The converter phase current (is(i)) is obtained from (1.1) and (1.2)as:

ip(i)− in(i) = is(i) =√2Is(i)cos(ω1t− φ(i)) (1.3)

where Is(i) is the phase current rms value and φ(i) the load angle. Substituting(1.3) to (1.1) and (1.2) yields:

ip(i) =IDC3

+

√2Is(i)cos(ω1t− φ(i))

2(1.4)

in(i) =IDC3−√2Is(i)cos(ω1t− φ(i))

2(1.5)

The voltages of both positive and negative arms are dened as:

vp(i) = VDC − vs(i) = VDC −√2Vs(i) cos(ω1t) (1.6)

vn(i) = VDC + vs(i) = VDC +√2Vs(i) cos(ω1t) (1.7)

where Vs(i) is the phase voltage rms value.

In addition, the operating range of an MMC can be extended by injecting a thirdorder harmonic in the phase voltages[8]. The power transfer can be increased by15% since the modulation index can be increased by that amount.

Hence, the voltages of both positive and negative arms yield:

vp(i) = VDC − vs(i) = VDC −√2Vs(i) cos(ω1t) +

√2

6Vs(i) cos(3ω1t) (1.8)

vn(i) = VDC + vs(i) = VDC +√2Vs(i) cos(ω1t) +

√2

6Vs(i) cos(3ω1t) (1.9)



SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

VDC

VDC

up(a)

Larm

Larm Larm Larm

LarmLarm

us(a)

IDC ip(a)

is(a)

ip(b) ip(c)

in(a) in(b) in(c)

un(a)

Figure 1.5: Three Phase Modular Multilevel Converter

Assuming equal ac and dc side power, the current IDC can be represented as afunction of converter power (Pc) and dc voltage (VDC) as:

IDC =Pc

2VDC=

3Vs(i)Is(i) cos(ϕ)

2VDC(1.10)

The modulation indices are dened as:



m(i) =

√2Vs(i)

VDC=vs(i)

VDC(1.11)

Hence using vs(i) = vs(i) cos(ω1t) and equations (1.11), (1.8) and (1.9) the insertionindices of positive and negative arms respectively are dened as:

ninp (i) =vp(i)

2VDC=

1− m cos(ω1t) + m cos(3ω1t)/6

2(1.12)

ninn (i) =vn(i)

2VDC=

1 + m cos(ω1t) + m cos(3ω1t)/6

2(1.13)

Consequently, by controlling the insertion indices in the arms, desired voltages andcurrents can be produced in the ac and dc terminals of the MMC.

1.3.2 Time periods to divert the current

The conduction losses are mainly caused by the semiconductors and they are basedon the instantaneous on-state voltage v(t) and the instantaneous current i(t) passingthrough them. The on-state voltage is

v(t) = von +Roni(t) (1.14)

where von is the threshold voltage of the device and Ron is the on-state resistance.The total conduction losses of semiconductors can be expressed as:

Pcond =1

T

∫v(t)i(t)dt

=1

T

∫von +Roni(t)i(t)dt

= vonIavg +Ron(Irms)2

(1.15)

where T is the fundamental period of the converter.

To reduce conduction losses in MMC it is mostly preferable to divert the currentto a path with lower Ron, when i(t) is high. The periods of time that is feasible todivert the current is when the insertion index is low. It will be shown that someconverter operations are more preferable than others. According to equations (1.4)and (1.6) the arm currents and voltages are ploted using p.u. values and modulationindex m = 1 for dierent operations.

Figures 1.6a and 1.6b depicts inverter and rectier operation of the converter, re-spectively, at unity power factor. It is observed that in both operations at the areawhere less than 10% of capacitors are inserted (ninp 6 10%) (between the red verticallines) the current is at the highest levels.



0 π/2 π 3π/2 2π

-0.2

0

0.2

0.4

0.6

0.8

1 narm

in = 100%

narmin = 50%

narmin ≤ 10%

iarm

uarm

(a) Inverter Operation at Unity Power Factor

0 π/2 π 3π/2 2π

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1 narmin = 100%

narmin = 50%

narmin ≤ 10%

iarm

uarm

(b) Rectier Operation at Unity Power Factor

Figure 1.6: Arm current and voltage

Figures 1.7a and 1.7b depicts inverter operation of the converter with power factorcos(φ) = 0.7 and reactive transfer operation of the converter, respectively. FromFigure 1.7a it is observed that the current is not always at high levels during thewhole area of ninp 6 10% and from Figure 1.7b it is observed that the current is atvery low levels.

0 π/2 π 3π/2 2π-0.2

0

0.2

0.4

0.6

0.8

1 narm

in = 100%

narmin = 50%

narmin ≤ 10%

iarm

uarm

(a) Inverter Operation at cos(φ) = 0.7

0 π/2 π 3π/2 2π-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1 narmin = 100%

narmin = 50%

narmin ≤ 10%

iarm

uarm

(b) Reactive Transfer Operation

Figure 1.7: Arm current and voltage

Consequently, it is concluded that inverter and rectier operation at unity powerfactor are the most preferable operations of the converter to divert the current to apath with lower on-state resistance.



1.3.3 Choice of device

For the new cell design the most suitable semiconductor device has to be chosen. Thecritiria of this choice are low on-state resistance of the device, easy implentable in thesystem and not increase the complexity of the system. In [9], a loss evaluation of fourhigh power semiconductor devices has been made, arranged in a three level neutral-point-clamped back-to-back conguration. The tested devices were IGCT, moduletype IGBT, press-pack IGBT and press-pack injection enhanced gate transistor(IEGT). These devices are shown in the Table 1.1 with some of their operatingcharacteristics. Also a GTO and a bidirectional controlled thyristor (BCT) areshown in the table.

Device IGCT Module type IGBT Press-pack IGBT Press-pack IEGT GTO BCT

Manufacturer ABB ABB Westcode, IXYS Toshiba ABB ABBCode 5SHY42L6500 5SNA0750G650300 T2400GB45E ST2100GXH22A 5SGF40L4502 5STB18U6500Blocking voltage 6.5kV 6.5kV 4.5kV 6.5kV 4.5kV 6.5kVITGQM 3800A - - - 4000A -ITAV M 1290A - - - 1180A 1580AIC/ICM - 750/1500A 2400A/4800A 2100A/5500A - -VON 1.88V 2.0V 1.49V 3.0V 1.2V 1.2VRON 0.56mΩ 2.5mΩ 1.05mΩ 1.0mΩ 0.65mΩ 0.458mΩ

Table 1.1: Characteristic Values of Power Semiconductors

In Table 1.1, ITGQM denotes the peak turn-o current, ITAVM the maximum averageon-state current, and IC and ICM the dc collector current and the peak collectorcurrent, respectively.

The study in [9] showed that the press pack type IGCT had the lowest conductionlosses of the four devices. This was expected since IGCT has the lowest on-stateresistance (RON). Comparing IGCT, GTO and BCT it can be seen that all thesedevices have comparatively low on-state resistances than the IGBTs and the IEGT.IGCT and GTO however, need a high power supply for their gate unit and specialmechanical and electrical clamping circuits which increase the complexity and makethem less attractive for modular and high power applications. For these reasons andthat BCT has the lowest on-state resistance and lowest threshold voltage (VON) ofall semiconductor devices compared, BCTs are the most appropriate choice for thecell structure. Phase controlled thyristors (PCT) in antiparallel connection can bealso used since they have the same operating principles and characteristics.

Nonetheless, BCTs and PCTs need forced commutation (turn-o) for full control-lability. In the next section the new cell structure will be introduced along with thecommutation controllability.

1.3.4 New cell structure

According to the switching behaviour of a thyristor in [10] to turn on a thyristora forward biased voltage and a gate current pulse is needed. Once the thyristor isturned on, the gate has no control over the device. Hence, the device is conducting



even if the gate pulse has turned o. To commutate a thyristor various methodscan be used. According to [11] the commutation methods are classied into naturaland forced commutation. The natural commutation is obtained without using anyexternal circuits, by reverse biasing a thyristor by line voltage in ac circuits. Theforced commutation is obtained by reverse biasing a thyristor by introducing apulse of voltage or current in parallel or in series with it. In this project the forcedcommutation method is going to be used by reverse biasing the thyristor with avoltage pulse in parallel with it. Instead of using an external circuit for that matter,a full bridge (FB) can be used in the converter submodules to provide the reversebiasing at the thyristors terminal. Figures 1.8 and 1.9 illustrate this mechanism.The red lines depict the path of the current in each mode.

IGBT1OFF

IGBT3OFF

IGBT2OFF

IGBT4OFF

Tp

+Tn

+VC

-

IGBT1OFF

IGBT3ON

IGBT2ON

IGBT4OFF

Tp

+Tn

VC

-

i i

VC

-

Mode 1: Tp conducts Mode 2: Reverse Voltage on Tp

Figure 1.8: Commutate Tp thyristor in a Full Bridge

IGBT1OFF

IGBT3OFF

IGBT2OFF

IGBT4OFF

Tp

+

Tn

+VC

-

IGBT1ON

IGBT3OFF

IGBT2OFF

IGBT4ON

Tp

+Tn

VC

-

i i

Mode 1: Tn conducts Mode 2: Reverse voltage on Tn

VC

-

Figure 1.9: Commutate Tn thyristor in a Full Bridge

According to the Figure 1.8 if current ows from top to bottom, Tp thyristor con-ducts, as shown in Mode 1. In Mode 2, IGBTs 2 and 3 are turned on to providereverse voltage on the thyristor. In Figure 1.9 if current ows from bottom to topTn thyristor conducts, as shown in Mode 1. In Mode 2, IGBTs 1 and 4 are turned



on to provide reverse voltage on the thyristor. It is noted that the capacitor voltagein the full-bridge cell needs to be controlled separately in order to apply a propervoltage across the thyristor valve. This can be done through the normal operationof the MMC over a fundamental cycle.

Consequently, the MMC topology with the new cell arrangement becomes as shownin Figure 1.10, which portrays a single phase MMC with thyristors placed in parallelwith the submodules. The thyristors that conduct at the positive current are de-noted as Tp where p indicates positive current ow and the thyristors that conductat the negative current are denoted as Tn where n indicates negative current ow.

Initially the concept of commutating a thyristor through a full bridge is tested inthe Lamm Lab laboratory of ABB. Later on, a control method was proposed forthe new cell arrangement and then simulations in PSCAD have been conductedto conrm the operation of the converter, in two operational modes of the HVDCapplications.



SM

SM

SM

.

+

-

Full-Bridge

Positive

Arm

Negative

Arm

2VDC

VAC

R, L

R, L

SM

SM

SM

Tn

Tp

Tn Tp

Tp

Tp

Tp

Tp

Tn

Tn

Tn

Tn

Figure 1.10: Single Phase MMC



1.4 Generalized Concept

To reach the desired voltage output in HVDC MMCs the number of submodulesused in each arm must be high. Therefore, the proposed cell and bypass currentmechanism can be generalized in order to achieve a more optimized and cost-eectivecell design. In the generalized concept, instead of connecting a thyristor to eachindividual cell, a group of submodules so called "cluster" are connected in parallelto the thyristor valve arm (series connected antiparallel thyristors). Figure 1.12shows a single phase MMC, based on the generalized concept.

The voltage ratings of each cluster are determined as

V ratcl =

2VDCNcl

(1.16)

where Ncl indicates the number of clusters and 2VDC the pole to pole dc link voltage.Hence, the number of antiparallel thyristors used in each cluster (Nth/cl) can beobtained with

Nth/cl =V ratcl

V ratth

(1.17)

where V ratth denotes the voltage rating of each thyristor. The benet of using a

cluster is that only some number and not all of the submodules need to be FBsto provide reverse voltage for the commutation of the thyristors. The number ofFB in each cluster are determined from the reverse recovery voltage (VR) of eachthyristor. Hence, the number of full bridges per cluster should be:

Nfb/cl =VR ×Nth/cl

V fbo

(1.18)

where V fbo is the output voltage of a full bridge.

For example, considering VR at 200V as a typical value for 3kV device, only 2kVvoltage is required for each cluster of 10 cells. Therefore, considering 2kV voltage asthe nominal voltage of each MMC cell, the ratio of FB/HB cells is only 10%. Fromthis analysis it is clear that the number of full bridges for the force commutation ofthyristors, in each cluster, is very low. This results in a more cost-ecient design.

The proper choice of cluster rating depends on many criteria, such as thyristoroptimum voltage rating, cell voltage ratings and control complexity. This can beevaluated when the best devices are selected in terms of their loss and cost whichis project dependent.

One of the main challenges in the generalized method is nding a proper and smartcontrol of the MMC arms which results in maximum eciency and minimum controlcomplexity. One proposal is as shown in the Figure 1.11. The shaded block indicatethe new control scheme that is added in the MMC control strategy.



Pref

Qref

PQ control

iCC control

High Level

Cluster control

Thermal balancer

Voltage balancer

Thyristor

Signals

Intermediate

Level

Submodule control

Voltage balancer

IGBT

signals

Low LevelNumber

of SMPWM

Insertion

Index

Figure 1.11: Control Strategy of Generalized Concept

The control is divided into three levels. The rst and the last level are the alreadyexisting controls in a typical MMC. The rst level is the High Level control. Theactive and reactive power as well as the circulating current are controlled, hencethe insertion index is produced. The last level is the Low Level control, which thecontrol is at submodule level. The submodules are controlled in each cluster andthe signals for the IGBTs are produced. The voltage ripple of each capacitor areconsidered and balanced by using a voltage balancer. In the generalized conceptthere is another level added the Intermediate Level control. In this level the controlis conducted at a cluster level. The thyristor signals would be produced, to whichthe clusters will be bypassed and inserted. This functionality can be dependenton the total cluster voltage deviation, the thermal condition of the cluster and thethermal condition of the thyristors. Also in the gure the pulse width modulation(PWM) control is shown which is the one generates the number of submodules tobe inserted at each instant of time.



Cluster

1

Cluster

2

Cluster

Ncl

.

-

Positive

Arm

Negative

Arm

2VDC

VAC

R, L

R, L

Cluster

1

Cluster

2

Cluster

Ncl

T.V

T.V

T.V

T.V

T.V

T.V

FB

FB

HB

HB

Tp

TpTn

Cluster

Thyristor Valve Arm

HB

HB

Tn

Figure 1.12: Single Phase MMC



2 Thyristor forced commutation in a full

bridge

Thyristors are extensively used many years now in a lot of applications in HVDCand they are highly preferred in power switching applications in all industries. InMMC, thyristors are already used as a solution for internal cell faults, to bypassthe cells. Thyristors are considered robust, reliable and with high voltage blockingcapabilities, in comparison with other devices.

However, further investigation of the thyristor's operation, ratings and limitationsis imperative to successfully apply them in the study. The thyristor's behaviourand more precisely the turn-o behaviour when connected in a full bridge, needsto be tested. Also, the turn-o time of the thyristor needs to be investigated.Its dependencies have to be addressed in order to get a more clear picture of thephenomenon.

Initially, the basic operation of the thyristor will be discussed with a section ofturn-o time explained more thoroughly. Subsequently, a proposed circuit that istested in the Lamm Lab of ABB will be presented along with the results.

2.1 Basic operation of Thyristor

Thyristor is a four layer of alternating N and P type material, three terminal deviceas shown in the Figure 2.1. There are three connections A-anode, K-cathode andG-gate.

P

N

P

N

A

G

K

A

G

K

J1

J2

J3

Figure 2.1: Thyristor (P-N-P-N structure)



At the turn-on thyristors functionality is similar to a diode. The layer betweenjunctions J2 and J3 become negative when a gate current is applied. If the gateis not red (ig = 0), it behaves as an open circuit. If a positive voltage (VAK) isapplied that results junctions J1 and J3 being forward biased, whereas junction J2is reversed biased. If that voltage (VAK) is increased to a critical limit, results tothe breakdown of the J2 and it changes to the conduction state. By the time thegate current is applied the VAK is reduced and the thyristor conducts current at thepositive direction. The gate pulse now can be removed and the device remains in theon-state. If the anode current iAK falls below a certain limit (holding current Ih),the device stops conducting, reverting to the blocking state. If a negative voltageVAK is applied across the device, junctions J1 and J3 becomes reverse biased. If thisnegative voltage reach to a critical limit then avalanche breakdown occurs acrossJ1 and J3 resulting in damaging the device. The forward and reverse blockingcapabilities are similar for a given thyristor[12].

2.1.1 Switching characteristics

Figure 2.2: Waveshapes illustrating thyristor turn-on time for a resistive load[10]

Figure 2.2 depicts the turn-on characteristics of a thyristor[10]. The top graphshows the anode to cathode voltage VAK (shown as principal voltage), the middlegraph the anode to cathode current iAK (shown as principal current) and the bottomgraph the gate current igt with respect to the time.

The thyristor turn-on time is consisted of two stages. The delay time td and thenthe rise time tr follows. The anode to cathode voltage VAK and the rise rate current(di/dt) of the thyristor are the most crucial factors during rise time. If during thattime the di/dt is high localize hot spots in the die can be produced which will



permanently destroy the thyristor. Consequently, it is important that the powerdissipation during turn-on time to be at safe levels[10].

Figure 2.3: Waveshapes illustrating thyristor turn-o time[10]

Figure 2.3 depicts the turn-o characteristics of a thyristor[10]. At turn-o therecovery stages are two. The reverse recovery time trr and the gate or forwardblocking recovery time tgr. When thyristor is at the conduction state all junctionsare forward biased and close to N and P regions on either sides of J2 full of holesand electrons (stored energy). In order to turn o the thyristor is necessary to applya negative voltage (VAK < 0) to drive the holes and electrons into juctions J1 andJ3. Thats why the reverse current appears at the thyristor. The current continuousto decrease until it reaches its leakage level. After that the gate recovery time tgrmust elapse which is the recombination process and is independent of the externalcircuit. When holes and electrons concentration has decreased enough, then forwardblocking voltage can be reapplied. Finally, the total time from the instant that thereverse recovery current begins to ow, to the start of the forward blocking voltageis referred to as circuit commutated turn-o time tq [10].

2.1.2 Turn-o time tq

To investigate the tq turn-o time of a thyristor a study conducted by ONsemi-conductor company in [10] will be used. According to this study some parametersthat may inuence tq time are examined. Hence, seven dierent rating thyristordevices are tested. It is important to mention that the thyristor devices used, hadlow rating blocking capabilities. Nonetheless, to a greater extent, of high powerthyristors, this study can give a realistic picture of their turn-o behaviours.



In a specic topology, that is explained in the study, parameters are varied one ata time while others are held constant. The parameters are stated below and someof them can be seen in Figure 2.4, where the thyristor current and voltage duringturn-o are shown:

• On-state current prior to turn-o (ITM)

• Rate of change of current during the forward to reverse transition (di/dt)

• Maximum reverse current magnitude (IRM)

• Reverse anode voltage (VR)

• Rate of change of reapplied forward voltage (dv/dt)

• Magnitude limit of reapplied voltage (VDX)

• Junction temperature (Tj)

Figure 2.4: Thyristor current and voltage waveforms during circuit commutatedturn-o [10]

Firstly, a forward current for long period of time conducts through the thyristor.Then the thyristor current is reversed at specied di/dt rate by inserting negativevoltage. The thyristor will experience reverse recovery current. After that a forwardvoltage is applied with a specied dv/dt rate. The delay time is reduced until acritical point is reached where the thyristor can no longer block the forward voltage.Then the tq of the thyristor is measured.

According to this procedure, for the turn-o tq time measurement, the ONsemicon-ductor study derived to the following conclusions.

1. The forward current magnitude ITM and the di/dt rate have the strongesteect on tq. It was proven that varying the ITM magnitude at realistic rangethe tq can change by about 30%. The change in tq is due to varying cur-rent densities (stored energy) present in the thyristor's junction as the ITMmagnitude is changed.



2. The tq time increase for standard thyristors caused a nominal increase in di/dtrate and the increase for fast thyristors was measured at about 30-40%.

3. The reverse current magnitude IRM is actually due to the stored charge clear-ing out of the thyristor's junctions when a negative voltage is applied on thethyristor anode. IRM is closely related to the di/dt rate where an increasingdi/dt rate causes an increase of IRM and reversely. It was found that IRM haslittle or no eect on tq.

4. The VR has a strong eect on the IRM magnitude and di/dt rate but whenthe last two are held constant trivial eect has on the tq.

5. The increase of reapplied rate dv/dt caused about a 10% increase to tq time.This eect is due to the anode-gate capacitance. The dv/dt applied at thethyristors terminal injects current into the gate through this capacitance, ac-cording to iGT = Cdv/dt. As the dv/dt increases the gate current also in-creases and can trigger the thyristor on. Hence the dv/dt have to be limited.

6. Changing the magnitude limit VDX of the reapplied voltage has little or noeect on tq.

7. Increased temperature Tj also increases the tq time.

This study proofs that the turn-o time tq depends on the particularity of theexternal circuit and its operation. Hence, for dierent circuits and operations thetq time varies. Consequently, an investigation of the tq time on the topology ofour interest is essential. A tested topology is decided in the following section. Theselection of the topology was chosen considering the commutating of the thyristorusing a full bridge.

2.2 Thyristor commutation in a Full Bridge

The concept of commutating a thyristor in a full bridge is thoroughly examined inthis section.

2.2.1 Tested Setup

After some trials using, PSPICE and Matlab Simulink, the single pulse test setupin Figure 2.5 was chosen to be implemented for single pulse test in the LammLaboratory of ABB. As can be seen only one direction of the thyristor was used tobe commutated in the setup, since the commutation of the other direction thyristorwould have given us similar results. An inductor was connected in parallel with thethyristor to generate the current in the circuit as would be explained in the nextsection.



IGBT1 IGBT3

IGBT2 IGBT4

Tp

+_VC L=4mHC=16,7mF

Figure 2.5: Single pulse test setup

Dierent turn-o tq times were measured under dierent on-state currents (ITM).This experiment was conducted for two dierent thyristors. The rst thyristorthat was used is a unidirectional thyristor (PCT) and the second a bidirectionalthyristor (BCT). From the BCT only one thyristor was needed for the test. Theirmain characteristics are shown at the Tables 2.1 and 2.2. Also, the ratings of theIGBTs are shown at the Table 2.3.

Quantity Condition Notation Value

Peak forward blocking Tjmax = 125oC VDRM 1600 VPeak reverse blocking Tjmax = 125oC VRRM 1800 VMax av on-state current Tj = 85oC ITAVM 500 ACritical rate of current f = 50Hz diT/dt 200 A/µsCritical rate of voltage VDX = 0.67VDRM duD/dt 100 V/µsTurn-o timea ITM = 500A, VR = 100V tq 250 µs

a Other conditions: VDX = 0.67VDRM , du/dt = 20V/µsec,−di/dt = 10A/µsec

Table 2.1: Unidirectional Thyristor TZ500N


Peak reverse blocking f = 50Hz VDRM 6500 VMax av on-state current Tj = 70oC ITAVM 1580 ACritical rate of current f = 50Hz diT/dt 250 A/µsCritical rate of voltage VDX = 0.67VDRM duD/dt 2000 V/µsTurn-o timea ITM = 2000A, VR = 200V tq 800 µsa Other conditions: VDX = 0.67VDRM , du/dt = 20V/µsec,−di/dt = 1.5A/µsecTj = 110oC

Table 2.2: Bidirectional Thyristor 5STB 18U6500




Collector-emitter voltage Tvj > 25oC VCES 6500 VDC collector current Tvj = 125oC IC 500 A

Table 2.3: HiPak IGBT Module 5SNA 0500J650300

A picture of the single pulse test setup is shown in Figure 2.6 and the full circuitschematic in Figure 2.7. Digital signals were formed with a personal computer (PC)and through a pulse generator the signals were generated to trigger the IGBTs andthe thyristors. The IGBT signals were sent to optic transmitter (OT) boards, whichthey converted the digital signals of 3V to optic signals. The optic signals weretransmitted to the optic receivers (OR) where they were converted back to voltagesignals. Finally, through a gate unit (GU) the IGBTs were triggered. Similarlythyristor signals were sent from a transmitter board (TB) to a pulse transformer totrigger the thyristor. Optic converters and pulse transformer were used due to theneed of electrical isolation of the gates from the main circuit. The optic transmitterboards were supplied by 5V DC. The gate units by 15V DC supply and the pulsetransformer by 240V AC supply as is shown in the Figure 2.7.

Figure 2.6: Picture of single pulse test setup



IGBT1 IGBT3

IGBT2IGBT4

Tp LC

PC

Pulse Generator

OT TB 5 V

ORGU

ORGU

ORGU

ORGU

Pulse Transf.

15 V

240 V AC

Charging/Discharging

Circuit

Figure 2.7: Full Laboratory Circuit

2.2.2 Single pulse test sequence

The sequence of the single pulse test is shown in the Figure 2.8. The red lines depictthe path of the current in each mode. The capacitor was charged manually beforethe test, from a charging circuit through a power supply and was discharged afterthe test, from a discharging circuit through a resistance. Each mode of the sequenceis explained below:

Mode 1: Initially, IGBT2 and IGBT3 are turned on, hence the inductor is chargingfrom the capacitor. The circuit at this mode is considered as a series RLC circuitwith a very small resistor.

Mode 2: None of the IGBTs are turned on in this mode, hence the current of thecharged inductor ows from the free wheeling diodes, back to the capacitor. Thethyristor terminals VAK are forward biased during this time hence is ready to turnon.

Mode 3: The thyristor is triggered in this mode. Consequently, the current circulatein a loop of thyristor and inductor.

Mode 4: This mode is the turn-o stage. IGBT2 and IGBT3 are turned on sothe thyristor terminals are reversed biased from the capacitors voltage. Thus, the



thyristor commutates and the current is been diverted through IGBT2 and IGBT3as in Mode 1.

Mode 5: In this mode, since the IGBTs are turned o the current ows again throughthe free wheeling diodes so the thyristor is forward biased. In that stage it is ensuredthat the thyristor has totally turned o and the tq time can be measured.

Mode 6: The last stage, is the safe mode where the IGBT2 is turned on, so theremaining current ows from IGBT2 and the free wheeling diode until it falls tozero.

IGBT1 IGBT3

IGBT2 IGBT4

Tp

+_VC

Mode 1: Charging Inductor Mode 2: Apply Forward voltage on Thyristor

Mode 3:Turn on Thyristor by Triger Mode 4: Turn off Thyristor by Applying a Reverse Voltage

Mode 5: Apply Forward volatge To Ensure Turn off Mode 6: Bypassing

+_

L

IGBT1 IGBT3

IGBT2 IGBT4

+_VC

_

+

L

IGBT1 IGBT3

IGBT2 IGBT4

+_VC L

IGBT1 IGBT3

IGBT2 IGBT4

+_VC +

_

L

IGBT1 IGBT3

IGBT2 IGBT4

+_VC +

_

L

IGBT1 IGBT3

IGBT2 IGBT4

+_VC L

OFF

OFF

OFF OFF

OFF OFF

OFF OFF

OFF OFF

OFF

OFF

OFF OFF

OFFOFF

OFF OFF

OFF

ON

ON

ON

ON

ON

Tp

Tp Tp

Tp Tp

Figure 2.8: Single Pulse Test Sequences

2.2.3 Results and Discussion of Single pulse test

The single pulse test characteristics are shown in Figure 2.9. This gure depicts thesingle pulse test sequence when BCT thyristor was used. The current and voltageof the thyristor are plotted and the dierent modes are also indicated in the graph.The on-state current prior turn-o ITM is 200A and the reverse voltage VRM is closeto 200V . The reverse voltage time is 303µs (Mode 4), which in this case is the



tq time since less than that period the thyristor will fail into commutate and fallto the conduction state again. The voltage spikes that are seen at the thyristorsvoltage waveform are due to the loop inductance L. This inductance will not be inthe MMC bypass topology, hence the thyristors will not experience these spikes.

800 900 1000 1100 1200 1300 1400 1500 1600 1700

Time(µs)

-600

-400

-200

0

200

400

600

800

Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6

UTH

(V)

ITH

(A)

Figure 2.9: Single Pulse Test Sequences

Table 2.4 gives the tq turn-o time for dierent on-state currents for both unidi-rectional and bidirectional thyristors. Due to security and safety issues the testedon-state currents were kept at low levels. As it was expected, higher value of cur-rent owing in the thyristor prior turn-o (ITM), the more time is needed to turn-othe thyristors. The reverse voltage used for each thyristor was the same as for themeasurement of the tq on the data sheets. This is done to be able to make a roughcomparison between the measured tq times and the stated values on the data sheets.To do that, a linear trend-line of the measured values of tq time with dierent on-state currents was calculated for each thyristor:

tuniq = 0.2131× ITM + 258.17 (2.1)

tbidq = 0.1122× ITM + 139.47 (2.2)

If using the same on-state currents as in the data sheets when measuring tq, ITM =500A for the unidirectional and ITM = 2000A, the turn-o times were calculated:

tuniq = 196µs

tbidq = 685µs

These values appear to deviate 20% and 15% respectively, from the stated ones inthe data sheet and the reason is that the experimental on-state current values was



set to very low values, in comparison with the ones used in the data sheet, for safetyreasons. So we do not have a proper picture how tq behaves in spectrum where ITMis high. Also another important factor is that the measured tq at the data sheetwas taken under specic conditions of di/dt, dv/dt, and Tj as shown in the tables,which we did not have the ability to generate with the existing setup.

Unidirectional TZ500N BCT 5SNA 0500J650300VRM = 100V VRM = 200V

ITM(A) tq(µs) ITM(A) tq(µs)45 145 50 27076 160 100 280104 135 146 285204 166 198 303

Table 2.4: Turn-o tq time for dierent on-state currents

Since we had only one DC source available in the lab, it was not easy to conductthe device characteristic tests during the thyristor turn-o force commutation. Thisis mainly because the same DC capacitor was used for both keeping the thyristorreverse voltage VR and also to maintaining the specic current through the circuit.As a result, although the proposed single pulse circuit could conrm the force com-mutation using the full-bridge cells, it was failed to draw conclusions of how eachparameter of the circuit inuence the turn-o tq time. The parameters di/dt anddv/dt that inuence directly the tq time were not constant in every change of thecurrent ITM . Therefore, a better single pulse test circuit needs to be design thathave the ability to maintain the parameters constant and change them one at atime, in order to eectively perform the sensitivity analysis on the tq of thyristorvalves.



3 Control Strategy for the New Cell

Arrangement

In this chapter the control strategy for the new cell arrangement is described. Amodel design of a 3 phase MMC in PSCAD is used to apply the new cell structure.Initially the MMC model design is described and then the control strategy for twooperations of the MMC is explained.

3.1 Description of the MMC model design

The model design of the MMC used is shown in Figure 8.3 in the Appendix and itscharacteristics are shown in Table 3.1.

Quantity Notation Value

Number of cells/arm N 10Direct voltage VDC 320kVLine to line voltage VLLrms 392kVRated frequency f 50Specied modulation index m 1Eective frequency feff 4kHzArm inductor Larm 25mHSubmodule Capacitor Csub 280µF

Table 3.1: MMC Characteristics

The control strategy is shown in Figure 3.1. The rst three blocks are the controlsthat already exist in a typical 3 phase MMC and the shaded block is the one thatis added extra to operate the new cell structure.

Pref

Qref

PQ control and

3rd harmonic

injection

iCC control

Phase Disposition

PWM

np,nSorting

Number

of SM

Thyristor

Modulation

Submodule

Modulation

IGBT

SignalsThyristor

Signals

(Modified)

IGBT

Signals

Figure 3.1: Control Strategy



In the rst block, the active and reactive power are controlled, hence the referencevoltage Vref (i) is generated. Also, within this procedure in order to expand thepower transfer capability of the converter in the generated reference voltages, afraction of 3rd harmonic is injected in the Vref (i). These controls are shown inFigure 8.2 in Appendix. In addition, circulating current control is used for voltagebalancing as well as voltage ripple reduction of the submodules capacitors, whichgenerates Vcm(i). Consequently, the insertion index for the positive and negativearm extracted from the rst block is formed as:

np(i) =VDC − Vref (i)− Vcm(i)∑

Vcap(3.1)

nn(i) =VDC + Vref (i)− Vcm(i)∑

Vcap(3.2)

As can be seen the denominator of the insertion indices is set as the sum of allvoltage capacitors (

∑Vcap) of the arm instead of using the constant 2VDC . That

will give more accurate indication of the number of submodules that is needed tobe inserted.

The next step of the control is the pulse width modulation (PWM). The techniqueof Phase Disposition PWM (PDPWM) is used. This technique uses N displacedtriangular carriers (the same as the number of cells used in the arm), with respectto zero axis, which are compared to the reference signal as shown in the Figure 3.3.These carriers are in the same phase and have same magnitude. Hence, the numberof submodules at each instant of time are generated. The number of submodulesare used by the sorting balancer controller. This controller decides which capacitoris going to be inserted or bypassed. The used method is that the cells with lowcapacitor voltages and high capacitor voltages are prioritized for insertion in positivearm current intervals and negative arm current intervals, respectively. This methodis shown at the ow chart in Figure 3.2. Thus, the sorting balancer generates theIGBT signals.

The main focus of this project is on the last block where the IGBT signals are takenfrom the sorting balancer and according to them the thyristor is controlled. Thisfunctionality will be extensively explained in the next section.



ip,n(i) > 0

START

Load Vcaps

Find min VcapFind max Vcap

END

NO

Insert

max Vcap

Insert min

Vcap

YES

Figure 3.2: Sorting balancer

0 π 2π0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Figure 3.3: Phase Disposition PWM

3.2 Control of the new cell arrangement

As it was discussed at the description of the project the most preferable operationof the MMC is at unity power factor. Dierent control strategies are implementedfor rectier and inverter operation.

3.2.1 Thyristor and Submodule control strategy for Rectier

operation

At rectifying operation the active power Pc is transferred from AC to DC side. Forthat matter the active and reactive power, respectively were set to

Pc = −750MW

Qc = 0 (3.3)

For easier understanding Figure 3.4 is used. The top graph depicts the current ofthe positive arm of phase (a) (ip(a)), the middle graph depicts the number of theinserted capacitors in the arm (np(a)in ∗N) and the bottom graph the signal of the1st submodule in the arm (S(1)). It is noted that having in mind the full bridge inFigure 1.9 the values of S(1) are explained using the Table 3.2. As can be seen fromthe marked areas at the middle graph, between the red and green vertical lines, theinsertion index is lower or equal to 10% and 30% respectively. Consequently, atthat period of time it is preferably to conduct thyristors Tn. For instance, the areas



(1), (2) and (3) that are shown on the bottom graph, are the possible time intervalsthat the thyristor Tn of the 1st submodule can conduct.

0.17 0.172 0.174 0.176 0.178 0.18 0.182 0.184 0.186 0.188-1

0

1

i p(a) -

kA

ip(a) < 0

0.17 0.172 0.174 0.176 0.178 0.18 0.182 0.184 0.186 0.188

0

5

10

n pin(a

)*N

npin(a) ≤ 10%

npin(a) ≤ 30%

npin(a) ≤ 10%

npin(a) ≤ 30%

0.17 0.172 0.174 0.176 0.178 0.18 0.182 0.184 0.186 0.188

Time

0

0.5

1

S(1) (1) (2) (3)

Figure 3.4: Positive arm's current (top), number of inserted capacitors (middle)and signal of the 1st submodule (bottom) with unity PF at rectifyingoperation

According to the commutation procedure of thyristors Tn, that was explained usingFigure1.9, the turn-on of the IGBT1 and IGBT4 resulted to a reverse biased volt-age on the thyristor. Hence Tn turns-o. Referring to Table 3.2 the IGBTs signalneeds to be S = 1, in this case. As a result, in this control method no modica-tion is needed to the IGBTs signals (S), since the commutation of thyristors Tn isimplemented through the normal operation of the submodules in the MMC.

The control method that has been used to control the thyristor Tn for one submoduleis shown in the ow chart in Figure 3.5. Initially, the IGBTs signal (S) is loaded fromthe sorting balancer. If the arm current ip,n(i) is negative and the insertion indexis np,n(i) ≤ 10% then the condition of IGBTs signal S is checked. If the capacitoris chosen to be bypassed, thus the IGBTs signal is S = 0, the thyristor Tn can betriggered and turn on. On the other hand, if capacitor is chosen to be inserted, thusthe IGBTs signal is S = 1, the condition of the thyristor should be checked. If itconducts it will result to turn o. If it is at the o state, the algorithm will loadanother IGBTs signal. Furthermore, in cases where arm current ip,n(i) is positive orinsertion index is not as np,n(i) ≤ 10% the algorithm will also load another IGBTssignal.

It is noted that thyristors can be turned-on at a spectrum area of insertion indexnp,n(i) of our preference. In this project the thyritors are chosen to be turned



on when insertion index is np,n(i) ≤ 10% which means none or one submodule isinserted in the arm at each instant of time during this area.

IGBT Signal(S) IGBT1 IGBT2 IGBT3 IGBT4 Explanation0 OFF OFF OFF OFF Bypass capacitor1 ON OFF OFF ON Insert capacitor positive-1 OFF ON ON OFF Insert capacitor negative

Table 3.2: Signals (S)

ip,n(i) < 0

AND

np,n(i)≤10%

START

Load

IGBTs

signal (S)

Capacitor is chosen to

be Bypassed

(S=0)

Trigger

Thyristor

(Tn=1)

Tn is Conducting

(Tn=1)

END

YES

YES

YES

NO

NO

NO

Turn off

Tn

Turn on

Tn

Figure 3.5: Thyristor Tn control strategy for one Submodule



3.2.2 Thyristor and Submodule control strategy for Inverter

operation

At inverter operation the active power Pc is transferred from DC to AC side. Forthat matter active and reactive power, respectively were set to

Pc = 750MW

Qc = 0 (3.4)

For easier understanding Figure 3.6 is used. Similarly, the top graph depicts thecurrent of the positive arm of phase (a) (ip(a)), the middle graph depicts the numberof the inserted capacitors of the arm (ninp (a) ∗N) and the bottom graph the signalof the 1st submodule in the arm (S(1)). As can be seen from the marked areas atthe middle graph, between the red and green vertical lines, the insertion index islower or equal to 10% and 30% respectively. Consequently, at that period of time itis preferably to conduct thyristors Tp. For instance, the areas (1), (2) and (3) thatare shown on the bottom graph, are the possible areas that the thyristor Tp of the1st submodule can conduct.

0.17 0.172 0.174 0.176 0.178 0.18 0.182 0.184 0.186 0.188-1

0

1

i p(a) -

kA ip(a) > 0

0.17 0.172 0.174 0.176 0.178 0.18 0.182 0.184 0.186 0.188

0

5

10

n pin(a

)*N

npin(a) ≤ 10%

npin(a) ≤ 30%

0.17 0.172 0.174 0.176 0.178 0.18 0.182 0.184 0.186 0.188

Time

0

0.5

1

S(1) (1) (2) (3)

Figure 3.6: Positive arm's current (top), number of inserted capacitors (middle)and signal of the 1st submodule (bottom) with unity PF at invertingoperation

According to the commutation procedure of thyristors Tp explained using Figure1.8 the turn-on of the IGBT2 and IGBT3 results to a reverse biased voltage on thethyristor. Hence Tp turns-o. Referring to Table 3.2 the IGBT signal needs to be



S = −1, in this case. As a result, in this control method, modication is needed tothe IGBTs signals (S) to commutate the thyristors Tp.

The control method that has been used to control the thyristors Tp and the IGBTssignals (S) is shown in a ow chart in Figure 3.8. In the ow chart the shadedblock depicts the extra step that needs to be taken to turn o the thyristor Tp.Initially, an IGBTs signal (S) is loaded from the sorting balancer. Two conditionsneed to be valid to turn-on the Tp thyristor. If the arm current ip,n(i) is positiveand the insertion index is np,n(i) ≤ 10% then the condition of the submodule ischecked. If the capacitor of the submodule is chosen to be bypassed (S = 0) thenthyristor Tp can be triggered to turn on. If either of the two conditions are not validanother IGBTs signal (S) is loaded. If the capacitor of the submodule is chosenfrom the balancer to be inserted positive (S = 1) then the IGBTs signal is modiedto (S = −1) as the shaded block shows. Hence, the thyristor Tp is reversed biasedfor at least tq time and nally turns-o.

There is an issue arising with this method. If for instance the IGBT signal S(1)generated from the sorting balancer is as shown at the top graph of Figure 3.7and the Tp thyristor conducts during the time interval between 2 to 3, the modiedIGBT signal becomes as illustrated at the bottom graph. It is shown that at instant3 instead to insert positive the specic capacitor (S = 1) as the sorting balancerrequests, the capacitor is inserted negative (S = −1) for tq time. As a result, duringthis time the arm voltage requires twice the capacitor's positive voltage (+2Vcap), tocompensate with the reference one. This issue will cause disturbances in the outputvoltage and current. In the next section an improved method is introduced to dealwith this issue.

0 0.5 1 1.5 2 2.5 3 3.5 4

-1

-0.5

0

0.5

1

S(1

)

0 0.5 1 1.5 2 2.5 3 3.5 4

-1

-0.5

0

0.5

1

S(1

) -

mo

dif

ied

tq time

Figure 3.7: IGBTs signal of 1st submodule: Top - sorting balancer output, Bottom- modied signal



ip,n(i) > 0

AND

np,n(i)≤10%

START

Load

IGBTs

signal (S)


be Bypassed

(S=0)

Trigger Tp

(Tp=1)

Tp is Conducting

(Tp=1)

Insert Capacitor

Negative

(S = -1) for tq time

END

YES

YES

YES

NO

NO

NO

Turn off

Tp

Turn on

Tp

Figure 3.8: Thyristor Tp control strategy for one Submodule

3.2.3 Improved Thyristor and Submodule control strategy for

Inverter operation

The arm's voltage, during tq time, can be improved by compensating the reversevoltage to its reference by the other submodules in the arm. To fully compensatethe voltage two submodules should be selected from the arm. Hence, a choice shouldbe made between submodules that are not already inserted and their correspondingthyristor connected in parallel is not conducting. For the selection between thesesubmodules there is another thing that needs to be addressed. During the tq time,the submodules capacitors should not be chosen from the sorting balancer to beinserted. Thus the less prioritized submodules are chosen. Hence, as long as thecurrent ows in the positive direction the capacitors with the highest voltage are



chosen to be used for the compensation. The control strategy with the compensationmethod can be seen in the ow chart at the Figure 3.9. The shaded blocks arethe extra steps. Consequently, to turn o the thyristor Tp the two most chargedcapacitors are inserted positive during the turn-o.

ip,n(i) > 0

AND

np,n(i)≤10%

START

Load

IGBTs

signal (S)


be Bypassed

(S=0)

Trigger Tp

(Tp=1)

Tp is Conducting

(Tp=1)

Turn off Tp

Insert Capacitor

Negative

(S = -1) for tq time

END

YES

YES

YES

NO

NO

NO

Turn off Tp

Insert Capacitor

Positive

(SCmax = 1) for tq time

Turn off Tp

Insert Capacitor

Positive

(SC2nd_max = 1) for tq time

Turn off

Tp

Find the max and 2nd

max voltage capacitors

(Cmax ,C2nd_max)

Turn-off Procedure Compensation Procedure

Turn on

Tp

Figure 3.9: Thyristor Tp control strategy with compensation for one Submodule



4 Simulation results

The simulation results of the MMC with the new cell structure are given in thischapter. The results for rectier and inverter operation at unity power factor aredepited, using the suggested control methods from the previews chapter. The tqturn-o time was chosen 40µs, which is a relatively small value for high powerthyristors. This is the case because in these simulations only the feasibility of theproposed control strategies are tested.

Initially, the output currents and voltages of each phase of the converter withoututilizing the thyristors are given in Figure 4.1. The results shown in the gurerepresent inverter operation at unity power factor. Also, the positive and negativearms' currents and voltages of phase (a) are given in Figure 4.2. In the following,only gures of phase (a) simulations are provided because of similarity with theother phases.

0.43 0.44 0.45 0.46 0.47 0.48 0.49-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

is(a) - kA

is(b) - kA

is(c) - kA

0.43 0.44 0.45 0.46 0.47 0.48 0.49

Time(sec)

-400

-300

-200

-100

0

100

200

300

400

us(a) - kV

us(b) - kV

us(c) - kV

Figure 4.1: Output currents (top) and voltages (bottom) of the converter



0.43 0.44 0.45 0.46 0.47 0.48 0.49-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

1.2

1.4

ip(a) - kA

in(a) - kA

0.43 0.44 0.45 0.46 0.47 0.48 0.49

Time(sec)

-100

0

100

200

300

400

500

600

700

up(a) - kV

un(a) - kV

Figure 4.2: Positive and negative arm currents (top) and voltages (bottom)

4.1 Rectier operation using thyristor bypass

Figure 4.3 shows the results of rectifying operation at unity power factor, whenthyristors Tn are utilized. The top graph depicts the current of positive and negativearm as well as the current that ows through thyristors Tn of the 1st submodule ofeach arm. The second graph depicts the positive and negative arm voltage. Thethird and fourth graphs depict the signals of the IGBTs of the 1st submodule ofeach arm.

As can be seen thyristors Tn are conducting large period of time when current ishigh, where insertion index is ninp,n(a) ≤ 10%. The arm currents and voltages arenot at all disturbed from thyristors utilization and they appear to be the same asin Figure 4.2.



0.43 0.44 0.45 0.46 0.47 0.48 0.49

-1

-0.5

0

0.5

ip(a) - kA

in(a) - kA

iT

n

- kA

0.43 0.44 0.45 0.46 0.47 0.48 0.49

0

200

400

600 up(a) - kV

un(a) - kV

0.43 0.44 0.45 0.46 0.47 0.48 0.49

-1

-0.5

0

0.5

1S

p(1)

0.43 0.44 0.45 0.46 0.47 0.48 0.49

Time(sec)

-1

-0.5

0

0.5

1S

n(1)

Figure 4.3: Rectier operation: Arms and thyristors Tn currents, arms voltages andarms signals of rst submodule

4.2 Inverter operation using thyristor bypass

without compensation

Figure 4.4 shows the results of inverting operation, with unity power factor, whenthyristors Tp are utilized. The compensation method is not used in this case. Thetop graph depicts the current of positive and negative arm and the current thatows through thyristors Tp of the 1st submodule of each arm. The second graphdepicts the positive and negative arm voltage. The third and fourth graphs depictthe signals of the IGBTs of the 1st submodule of each arm.

The reverse turn-o time is observed (Sp,n(1) = −1) in the signal graphs. Due tothis, negative voltage can be seen in the arms. This aects the arm currents whichare consequently disturbed.



0.43 0.44 0.45 0.46 0.47 0.48 0.49-0.5

0

0.5

1

1.5

ip(a) - kA

in(a) - kA

iT

p

- kA

0.43 0.44 0.45 0.46 0.47 0.48 0.49

0

200

400

600 up(a) - kV

un(a) - kV

0.43 0.44 0.45 0.46 0.47 0.48 0.49

-1

-0.5

0

0.5

1S

p(1)

0.43 0.44 0.45 0.46 0.47 0.48 0.49

Time(sec)

-1

-0.5

0

0.5

1S

n(1)

Figure 4.4: Inverter operation without compensation: Arms and thyristors Tp cur-rents, arms voltages and arms signals of rst submodule

4.3 Inverter operation using thyristor bypass with

compensation

The improved control method strategy is used in the next gures. Firstly, a 50%compensations is implemented when inserting only one submodule in positive polar-ity and then 100% compensation is implemeted when inserting two submodules atthe same time in positive polarity. The results are shown in Figure 4.5 and Figure4.6, respectively.

As can be seen in both gures there is no negative voltage at the arms voltagegraphs. When having 50% compensation the arm currents are improved but stilldeviate from the arm currents in Figure 4.2. At the 100% compensation case, itcan be observed in the Figure 4.6 that no disturbances are seen from the turn-oreverse voltage and the arm currents are considered the same as the ones in Figure4.2.



0.43 0.44 0.45 0.46 0.47 0.48 0.49-0.5

0

0.5

1

1.5

ip(a) - kA

in(a) - kA

iT

p

- kA

0.43 0.44 0.45 0.46 0.47 0.48 0.49

0

200

400

600 up(a) - kV

un(a) - kV

0.43 0.44 0.45 0.46 0.47 0.48 0.49

-1

-0.5

0

0.5

1S

p(1)

0.43 0.44 0.45 0.46 0.47 0.48 0.49

Time(sec)

-1

-0.5

0

0.5

1S

n(1)

Figure 4.5: Inverter operation with 50% compensation: Arms and thyristors Tp cur-rents, arms voltages and arms signals of rst submodule

0.5 0.51 0.52 0.53 0.54 0.55 0.56-0.5

0

0.5

1

1.5

ip(a) - kA

in(a) - kA

iT

p

- kA

0.5 0.51 0.52 0.53 0.54 0.55 0.56

0

200

400

600 up(a) - kV

un(a) - kV

0.5 0.51 0.52 0.53 0.54 0.55 0.56

-1

-0.5

0

0.5

1S

p(1)

0.5 0.51 0.52 0.53 0.54 0.55 0.56

Time(sec)

-1

-0.5

0

0.5

1S

n(1)

Figure 4.6: Inverter operation with full compensation: Arms and thyristors Tp cur-rents, arms voltages and arms signals of rst submodule



5 Conclusions

5.1 Lab experiment

The experiment conrmed the thyristor commutation with a full bridge. The tqturn-o time was found to be increased when the on-state current prior turn-oITM was increased. However, the test setup was not able to give results on howparameters di/dt (rate of change of current during the forward to reverse transition)and dv/dt (rate of change of reapplied forward voltage) impact tq turn-o time.

5.2 Control of the new cell arrangement

From the simulation results can be concluded that the new cell arrangement does notdisturb the normal operation of the converter. The thyristors conduct for signicantportion of time during time intervals where the insertion index is low. The controlstrategy at rectier operation was less complex since the thyristors did not need anyextra control for their turn o as well as compensation of arm voltage. The controlstrategy at inverter operation was more complex which produce distortion at thearm voltage, therefore compensation technique was implemented. For that matterit is evident that the number of switching is increased at inverter operation.



6 Discussion

A rough comparison of losses between the MMC with the new cell structure anda typical MMC with half bridges is made. According to results the limitations ofthis converter are addressed and discussed. Small discussion about the generalizedconcept is made.

6.1 Loss comparison with MMC with half bridges

The total losses of a converter are mainly the sum of the conduction and the switch-ing losses of each device.

Losses of MMC with half bridges: The typical MMC consist half bridges. Thesubmodules individual conduction loss is calculated based on the average and rmscurrent of the corresponding submodule at one cycle. Each submodule operates atany mode as shown in Figure 6.1. Each device conducts only at one direction of thearm current as shown in the Figure 6.2 and at dierent time intervals.

Figure 6.1: Half bridge cell operating modes (a) bypass (ip > 0), (b) insert (ip > 0)(c) bypass (ip < 0), (d) insert (ip < 0)



-3 -2 -1 0 1 2 3 4

ωt(rad)

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

1.2

I arm

(pu

)

θ1

θ2

θ3

T2 or D

1

T1 or D

2

Figure 6.2: Zero crossing of arm current

Therefore the average current that passes through each device can be calculated as:

IT1avg =1

T

∫ θ3

θ2

Iarm(θ)× nins(θ)dθ (6.1)

IT2avg =1

T

∫ θ2

θ1

Iarm(θ)× nbyp(θ)dθ (6.2)

ID1avg =

1

T

∫ θ2

θ1

Iarm(θ)× nins(θ)dθ (6.3)

ID2avg =

1

T

∫ θ3

θ2

Iarm(θ)× nbyp(θ)dθ (6.4)

where nins(θ) is the insertion index and nbyp(θ) is the bypass index. Also T1 denotesthe upper IGBT, T2 the lower IGBT, D1 the upper diode and D2 denotes the lowerdiode. Also the rms current of each device can be calculated from:

Idevicerms =

√1

T

∫I2arm(θ)× n(θ)dθ (6.5)

Therefore, as it was mentioned on the 1st chapter the conduction loss of each semi-conductor device is:

P devicecond = vonI

deviceavg +Ron(I

devicerms )2 (6.6)



Hence, the conduction loss of each submodule is:

Pcond = P T1cond + P T2

cond + PD1cond + PD2

cond (6.7)

The switching losses of each device are the sum of energy dissipation at each switch-ing event, which is proportional to the current level. In terms of convenience theaverage current is considered at each switching instant of each device. Thus, ac-cording to this current the energy dissipation at turn-on and turn-o of each deviceis measured from the data sheets. The number of switching events in one cycle mul-tiplied with the energy dissipation of each event yields the switching loss of eachdevice.

P deviceswi = fdevice × Edevice

on + Edeviceoff (6.8)

Hence, the total switching loss of each submodule is:

Pswi = P T1swi + P T2

swi + PD1swi + PD2

swi (6.9)

Finally, the total losses of each submodule are:

Ptotal = Pcond + Pswi (6.10)

Losses of MMC with the new cell structure: The new cell structure of MMCcontains a full bridge and two thyristors. However, one thyristor is used at eachoperation (inverter or rectier). Figure 6.3 depicts the new cell operating modes.



T1 T3

T2 T4

Thy

+

D1

D2

D3

D4

GU

GU

GU

GU

T1 T3

T2 T4

Thy

+

D1

D2

D3

D4

GU

GU

GU

GU

T1 T3

T2 T4

Thy

+

D1

D2

D3

D4

GU

GU

GU

GU

T1 T3

T2 T4

Thy

+

D1

D2

D3

D4

GU

GU

GU

GU

T1 T3

T2 T4

Thy

+

D1

D2

D3

D4

GU

GU

GU

GU

T1 T3

T2 T4

Thy

+

D1

D2

D3

D4

GU

GU

GU

GU

T1 T3

T2 T4

Thy

+

D1

D2

D3

D4

GU

GU

GU

GU

C C

CC

CC

C

ip

ip

ip

ipip

ip

ip

(e) (f)

(c) (d)

(g)

(a) (b)

Figure 6.3: New cell structure operating modes (a) bypass (ip < 0), (b) insert posi-tive (ip > 0) (c) bypass (ip > 0), (d) insert positive (ip < 0)

(e) bypass with thyristor (ip > 0), (f) bypass with thyristor (ip < 0), (g) insertnegative (ip > 0)

The conduction loss of the new cell structure is:

Pcond = P T1cond + P T2

cond + P T3cond + P T4



cond + P Thycond

(6.11)



and the switching loss is:

Pswi = P T1swi + P T2

swi + P T3swi + P T4

swi + PD1swi + PD2

swi + PD3swi + PD4

swi + P Thyswi (6.12)

Loss comparison: The loss comparison will be made only when the MMC isoperating at inverter mode. It is important to see that at rectier operation thenew cell structure will never have lower losses than the typical MMC. This is thecase since for the typical MMC close to the absolute highest arm current area thecurrent passes the most of the time through one diode in each submodule whenbypassing (see Figure 6.1 (c)). Hence bypassing with thyristors Tn at that timeintervals would not make any dierence in the conduction loss since diodes andthyristors have the same on-state characteristics. This operation would be lossecient when the generalized concept is used, only if the number of thyristors inthe valve arm are less than the number of submodules in the cluster.

The average number of switchings per cell for one cycle has been measured for thecalculations. Without the thyristor use in the cell the average switching numberwas Nwithout = 7.2 and with the thyristor use was Nwith = 9.26. Also, the averagetime of thyristor conduction per cycle is needed. It was found to be close to 20%of the time cycle. An assumption is made that this 20% the thyristor conductionis ideally at the highest peak current area as shows in Figure 6.4. The thyristorcurrent is shown with red line. The areas denoted with (1) are the areas wherethe devices T2, D4 or D1, D4 or T2, T3 are conducting and the area denoted with (2)T4, D2 or T1, T4 are conducting.

-3 -2 -1 0 1 2 3 4

ωt(rad)

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

1.2

I arm

(pu

)

θ1

θ2

θ3

(1) (1)

(2)

Thy

Figure 6.4: Thyristor conduction area



Results and discussion: The loss evaluation was implemented in Matlab (code inAppendix). The devices that were used are the thyristor 5STP 21H4200 the IGBT5SNA 2000K451300 and the diode 5SDF 13H4501. The evaluation showed thatat inverter operation with Pc = 750MW and Qc = 0 and thyristor conduction of20% of the time cycle the converter produce more losses than a typical MMC. Morespecic the conduction losses was found 33% more than the typical MMC. Theswitching losses increased 54%, which was expected since the number of switchingwas increased and the number of devices were doubled. However, the conductionlosses will start decreasing when the thyristor conduction area becomes more than34% which this is not possible when eective frequency is high (at feff = 4kHz).Longer time of thyristor conduction can be achieved when decreasing eective fre-quency. Also, when varying active power transfer values, lower conduction lossescould not be achieved.

6.2 Generalized concept

By applying the generalized concept, where the number of cells are high and thesubmodules are grouped in clusters, it is observed that the time of thyristor con-duction can be still suciently long. This can be explained from the fact that theeective frequency is formed as follows.

feff = f ×Numaveswi ×N (6.13)

where Numaveswi indicates the average number of switching events of cells per cycle.

Hence, the same eective frequency can be achieved by having higher number ofcells N and low number of switching events. Therefore, even though the submodulesare grouped in clusters, the thyristor conduction time can be long.



7 Future Work

In this chapter a proposed future work will be given to make this concept imple-mentable.

7.1 Further investigation on tq turn-o time

As it was mention in Chapter 2 the turn-o tq time of thyristors is dependent on theexternal circuit and the operating conditions prior turn-o. Further experimentalwork is needed to investigate the sensitivity of the parameters that impact tq.

7.2 Apply the generalized concept

The primary work is to implement a proper control for this concept, as it wasdiscussed at the rst chapter. It should provide long time thyristor conduction,commutation of thyristors and at the same time capacitors voltage balancing. Ac-cording to the operation and the control, optimal values for the thyristors, capacitorsand inductors sizes have to be chosen properly to achieve a cost ecient system.

Furthermore, dierent control strategy can be introduced to decrease the numberof switching due to compensation while operating at inverter mode.

Lastly, a more accurate loss evaluation of the concept needs to be done and becompared with experimentation results.



Bibliography

[1] A. Nami, J. Liang, F. Dijkhuizen, and G. D. Demetriades, Modular multilevelconverters for hvdc applications: Review on converter cells and functionalities,IEEE Transactions on Power Electronics, vol. 30, pp. 1836, Jan 2015.

[2] A. Lesnicar and R. Marquardt, An innovative modular multilevel convertertopology suitable for a wide power range, in Power Tech Conference Proceed-ings, 2003 IEEE Bologna, vol. 3, pp. 6 pp. Vol.3, June 2003.

[3] O. E. Oni, I. E. Davidson, and K. N. I. Mbangula, A review of lcc-hvdcand vsc-hvdc technologies and applications, in 2016 IEEE 16th InternationalConference on Environment and Electrical Engineering (EEEIC), pp. 17, June2016.

[4] A. Hassanpoor, S. Norrga, and A. Nami, Loss evaluation for modular mul-tilevel converters with dierent switching strategies, in 2015 9th Interna-tional Conference on Power Electronics and ECCE Asia (ICPE-ECCE Asia),pp. 15581563, June 2015.

[5] O. C. Trainer D, Dyke K, Converter. European Patent ApplicationEP2494687, May 2011.

[6] C. Oates, K. Dyke, and D. Trainer, The augmented modular multilevel con-verter, in Power Electronics and Applications (EPE'14-ECCE Europe), 201416th European Conference on, pp. 110, Aug 2014.

[7] C. Oates, K. Dyke, and D. Trainer, The use of trapezoid waveforms withinconverters for hvdc, in Power Electronics and Applications (EPE'14-ECCEEurope), 2014 16th European Conference on, pp. 110, Aug 2014.

[8] K. Ilves, S. Norrga, L. Harnefors, and H. P. Nee, On energy storage require-ments in modular multilevel converters, IEEE Transactions on Power Elec-tronics, vol. 29, pp. 7788, Jan 2014.

[9] K. Lee, K. Jung, S. Song, Y. Suh, C. Kim, H. Yoo, and S. Park, Analysisand comparison of high power semiconductor device losses in 5mw pmsg mvwind turbines, in 2014 International Power Electronics Conference (IPEC-Hiroshima 2014 - ECCE ASIA), pp. 16461653, May 2014.

[10] ONSemiconductor, Thyristor theory and design considerations. [Online].Available: www.onsemi.com, 2005.

[11] G. K. Dubet, Classication of thyristor commutation methods, IEEE Trans-actions on Industry Applications, vol. IA-19, pp. 600606, July 1983.



[12] D. Jovcic and K. Ahmed, High-voltage direct-current transmission: Convert-ers, systems and dc grids, rst edition, 2015.



8 Appendix

Figure 8.1: Circulating current control

Figure 8.2: Active/reactive control and 3rd order harmonic injection



Figure8.3:

MMCmodeldesign



Loss Evaluation Matlab Code

P=750*10^6; t= linspace(-pi/2,3*pi/2,1003); Idc=P/(640*10^3); IARM= Idc/3 + 2*Idc/3*cos(t); %arm current inse = (1-1.1667*cos(t)+(1.1667*1/6*cos(t*3)))/2; figure(1) plot(t,IARM/1000), hold on plot(t,inse) iarmu= IARM'; mwfu = inse'; %insertion index

%% Values of devices Rthy = 0.191*10^-3; % Phase Control Thyristor 4.2kV Vthy=1.249; % Phase Control Thyristor 4.2kV Rigbt = 1.00*10^-3; % IGBT 4.5 kV Vigbt = 1.60; % IGBT 4.5 kV Rdiode = 0.48*10^-3; % Fast Recovery Diode 4.5kV Vdiode = 1.3; % Fast Recovery Diode 4.5kV

for i= 1:1:1003 if iarmu(i) > 0 sgn_iarmm(i)=1; else sgn_iarmm(i)=0; end end sgn_iarm=sgn_iarmm';

mwfl = 1 - mwfu;

%% Half-Bridge MMC Conduction Losses Idu_avg= mean( mwfu.*sgn_iarm.*iarmu ); % average current for Du (for conduction loss) Isu_avg = -mean( mwfu.*~sgn_iarm.*iarmu); % average current for Su (for conduction loss) Idl_avg = -mean( mwfl.*~sgn_iarm.*iarmu); % average current for Dl (for conduction loss) Isl_avg = mean( mwfl.*sgn_iarm.*iarmu); % average current for Sl (for conduction loss) % % Idu_ms= mean( mwfu.*(sgn_iarm.*iarmu).^2); % RMS current for Du (for conduction loss) Isu_ms= mean( mwfu.*(~sgn_iarm.*iarmu).^2); % RMS current for Su (for conduction loss) Idl_ms = mean( mwfl.*(~sgn_iarm.*iarmu).^2); % RMS current for Dl (for conduction loss) Isl_ms = mean( mwfl.*(sgn_iarm.*iarmu).^2); % RMS current for Sl (for conduction loss)

Pcond_half = (Isu_avg+Isl_avg)*Vigbt + (Idu_avg+Idl_avg)*Vdiode + (Isu_ms+Isl_ms)*Rigbt +

(Idu_ms+Idl_ms)*Rdiode;

%% New Cell Conduction Losses tconduction=0.2; loccmax = find(iarmu == max(iarmu)); t11=loccmax(1)-tconduction/2*1003; t22 = loccmax(1)+tconduction/2*1003; t1 = floor(t11); t2 = floor(t22);

for i=1:1003 if i<t1 || i>t2 Ithy(i) = 0; else Ithy(i)= iarmu(i); end end

figure(2) plot(Ithy)

%locczero = find((iarmu<3)&(iarmu>-3),1); for i=1:1003 if i>t1 && i<t2 iarmu_thy(i) = 0



else iarmu_thy(i)=iarmu(i); end end figure (3) plot(iarmu_thy)

Idu_avgT= mean(mwfu.*sgn_iarm.*iarmu_thy'); % average current for Du (for conduction loss) Isl_avgT = mean(mwfl.*sgn_iarm.*iarmu_thy'); % average current for Sl (for conduction loss) % Idu_msT= mean(mwfu.*(sgn_iarm.*iarmu_thy').^2); % RMS current for Du (for conduction loss) Isl_msT = mean(mwfl.*(sgn_iarm.*iarmu_thy').^2); % RMS current for Sl (for conduction loss)

Pcond_NewCell = 2*((Isu_avg+Isl_avgT)*Vigbt + (Idu_avgT+Idl_avg)*Vdiode + (Isu_ms+Isl_msT)*Rigbt

+ (Idu_msT+Idl_ms)*Rdiode) + mean(Ithy)*Vthy + mean(Ithy.^2)*Rthy; Conduction_Decrease_percent = (1-Pcond_NewCell/Pcond_half)*100

%% Switching Losses Icmthy_avg= mean(Ithy); % Average thyristor current Icmdusl_avg= mean((iarmu).*sgn_iarm); % average current for Du and Sl (pos current with the

thyrostor current) Icmdusl_avg2= Icmdusl_avg-Icmthy_avg; % average current for Du and Sl (pos current without the

thyristor current) Icmsudl_avg= mean(abs(iarmu).*~sgn_iarm); % average current for Su and Dl (negative current)

%% Values for tconduction= 0.2 Eon_Su=1; %for Icmsudl_avg Eoff_Su=1.15; %for Icmsudl_avg Eon_Sl=2.5; %for Icmdusl_avg Eoff_Sl=3; %for Icmdusl_avg Eon_Sl2=1.25; %for Icmdusl_avg2 Eoff_Sl2=1.35; %for Icmdusl_avg2

Eoff_Du=0.6; %for Icmdusl_avg Eoff_Du2=0.3; %for Icmdusl_avg2 Eoff_Dl=0.1; %for Icmsudl_avg

Eon_th=0.01; %for Icmthy_avg Eoff_th=2; %for Icmthy_avg

Fr=7.2; %the average number of switchings of a submodule without the new cell structure in one

cycle Fr_NewCell=9.26; %the average number of switchings of a submodule with the new cell structure in

one cucle

%%% Half-Bridge MMC Pswitch_half = (Eon_Su+Eoff_Su+Eon_Sl+Eoff_Sl+Eoff_Du+Eoff_Dl)*Fr;

%%% New Cell Pswitch_NewCell = 2*(Eon_Su+Eoff_Su+Eon_Sl2+Eoff_Sl2+Eoff_Du2+Eoff_Dl)*(Fr_NewCell-1) +

2*(Eon_Sl2+Eoff_Sl2 + Eoff_Du2)+ (Eon_th+Eoff_th);

Switching_ratio = (1-Pswitch_NewCell/Pswitch_half)*100 %%% TOTAL Ptot_half= Pcond_half + Pswitch_half; Ptot_NewCell = Pcond_NewCell + Pswitch_NewCell;

Total_Decrease_percent = (1-Ptot_NewCell/Ptot_half)*100


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