1314 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 37, NO. 10, OCTOBER 1990

A Multichannel Minimum-Seeking Analog-to-Digital Converter

D. R. ZRUDSKY, J. TERNUS, AND D. G. MILLER

Abstract -A special purpose A/D circuit, using MSI IC’s on a printed circuit board has been developed, which determines which of the eight input analog signals is the lowest, This circuit provides an 8-bit magni- tude and 3-bit address output of this minimum input signal at a 0.5 MHz conversion rate. The circuit utilizes a successive approximation register, adder registers, CMOS D/A, parallel comparators, and a priority encoder connected in closed-loop. Control is accomplished using simple flip-flop logic. Mentioned are several important signal processing applications for this circuit as a feedback component in optical and electronic systems, utilizing associative self-organizing memory.

I. INTRODUCTION

A novel circuit function is presented, which uses a variation of the successive approximation A/D converter [l], [2]. The circuit presented provides for eight channels of analog input and a minimum-seeking loser-take-all output consisting of the magni- tude and address of the lowest incoming signal. This multichan- nel minimum-seeking A/D should have many advanced signal processing applications. As an example, an incoherent optical system, valuable for computing and correlation [3], utilizes a patterned array of LED’s casting shadows of a binary mask or spatial light modulator (SLM). In this method, a binary template can be compared with a binary input scene by logical filtering. The array of LED’s provides the binary template and illumi- nates the input scene. Shadows at various intensity levels are transmitted. Behind the input scene, a decoding mask transmits light to an array of photodetectors. Regions of the decoding mask that are dark indicate positions in the input scene where the template form has been found. The use of dark-true logic for greater signal-to-noise ratios (SNR’s) requires a minimum- seeking A/D converter for a feedback element.

Another useful application for this special converter supports the use of a directed graph for classifying input patterns [4]. Here each input pattern may be a symbol or a feature extracted from a shape. Each graph node can represent a class of pattern. The node whose pattern image is the best match to the input pattern can be determined by obtaining the inner product of the two vectors optically. The adjacency matrix of the graph makes it possible to compare a subset of the nodes at one time. By using dark-true logic, the matching process can step along arcs that represent the most similar node. The number of channels in the minimum-seeking A/D converter will determine the out- degree allowed for each node. The steps continue until the current node being tested is more similar than its neighbors to the input pattern. The minimum seeking A/D converter pre- sented here would be most useful in providing a value for the similarity. If the similarity is above threshold, the input pattern is merged with the class of patterns represented by that node. The number of classes (nodes) can be increased (decreased) by lowering (raising) the threshold applied to the similarity. This

Manuscript received January 22, 1990; revised May 11, 1990. This paper was supported in part by the National Science Foundation Engineering Instrumentation and Laboratory Improvement under Grant 8851816. This paper was recommended by Associate Editor T. T. Vu.

The authors are with the Computer Engineering Department, University of Minnesota, Duluth, MN 55812.

IEEE Log Number 9037943.

C!k SfART

n

Magnitude

p& 6 8

Channel

Channel

Channel

Channel

Channel

Channel

Channel

Channel + 5V

Fig. 1. Multichannel A/D circuit.

application illustrates how a data base can be organized by using an optical associative memory with a reasonable number of parallel processing channels. Without intending to develop a complete list, still more examples of these ideas are provided from the literature [5], [6].

11. CIRCUIT DESCRIPTION The multichannel A/D converter, shown in Fig. 1, uses

successive approximation register (SAR) techniques to simulta- neously determine the magnitude and the channel number of the lowest of eight analog input signals. The design utilizes a feedback loop that commences with a START control signal. This signal will activate sample-and-hold (not implemented in this work) on all analog input signals while initiating the conver- sion process.

On the first clockpulse, the SAR starts the loop with a digital value of 0111 1111, (nearly half of full scale), which passes through the parallel adders and enters the D/A converter. The output of the D/A is compared to all eight of the analog input channels in parallel. If one or more input channels are lower than the D/A output, their comparators will yield high outputs, which deliver low outputs to the priority encoder, due to the Schmitt inverters. When one or more of these low inputs reach the priority encoder, the G, output sends a low to the D input of the SAR. The next clock pulse causes the S A R to serially store the first low input bit, d, a doll 1111, in its shift register for parallel output to the adder pair; thus the D/A output is lowered to nearly one-quarter of full scale. If this time the D/A output is lower than all eight channels of input, the circuit yields all low inputs to each Schmitt trigger, and presents to the

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I E E E TRANSAOIONS ON CIRCUITS A N D SYSTEMS, VOL. 37, NO. 10, OCTOBER 1990 1315

T7 T8 T9 T10 T l I T I 2

CLK

s7iR-mR 1 4 n Carry 02 I ennble Lntch Q3 n ennble

complete Converrlon 04

Fig. 2. Timing pulses for the A/D circuit.

priority encoder eight high inputs. The priority encoder re- sponds with a G, high output value, D, which results in SAR parallel output of do1 1111,. In this feedback fashion, the interaction of the SAR and the priority encoder closes in ever tighter resolution on the magnitude of the lowest of the eight channels of input analog data.

When the approximation is finished, channel selection must be made. A channel can be selected only if, at this point, the priority encoder is receiving one or more input lows. In other words, the D/A output voltage must be higher than the lowest voltage channel. Statistically, nearly 50% of the time this turns out not to be the case, so one more LSB must be added to the approximation. It would be easy to force this condition by always adding one more bit at the end of all approximations. However, that would reduce the magnitude resolution by a factor of two. Instead, logical decisions are implemented based on the condition of the encoder G, output at this point in the conversion process.

The decision to add or to not add the LSB to the approxima- tion is performed by the two D-type flip flops 5 and 6, shown in Fig. 1. These parallel flip-flops feeding a two-input NAND gate are used, because two possible conditions can occur. In the first case, already mentioned, the feedback loop completes its ap- proximation at pulse T9, shown in the timing diagram of Fig. 2. Here, the D/A stops less than one bit lower than the lowest input channel value, and the G, goes high, latching a high through flip-flop 6 and the NAND gate to the normally low carry of the LSB adder register. In the second case, which is a rare occurrence, the D/A nearly ties in value with the lowest input channel. Here, very small comparator input variations still occa- sionally make it through the 10 pfd filter capacitor and Schmitt inverter combination to create a rapid toggling action in the G, output of the encoder. The first of these G, oscillations causes flip-flop 5 to latch, permitting its high to pass the NAND gate, and to add one last LSB to the adder register by means of its carry input. Any ties between competing input channels for the lowest signal value, which occur within the LSB-resolution of the multichannel converter, are systematically resolved by the priority action of the encoder.

The 12-bit SAR chosen for this application uses eight bits for magnitude resolution and the lowest four bits for timing of the remaining control flip-flops. When both the data and control registers of the 12-bit S A R are included in the description, the SAR actually begins the conversion cycle with the output 0111 1111 1111,. Eight serial shifts later, i.e., at clockpulse T9 in Fig. 2, the leading zero of the original starting data moves into register 4, initiating the R, control pulse. This action latches D-type flip-flop 1 to enable the two-state sequential circuit of flip-flops 2 and 3 to develop the Q, carry-enable and Q3 latch-enable pulses, shown in Fig. 2. On the 11th shift (7'12 in Fig. 2), the leading zero of the original data enters register R,,

165

160

155

150

145 2.8 2.9 3.0 3.1

Analog Input Voltage (volts) Fig. 3. Single-channel input versus output data.

and then into a series inverter that latches flip-flop 4 into Q4,

ending the entire process with a conversion signal complete. The digital portion of the circuit is straightforward, while the

A/D interface requires careful design considerations. The rela- tively slow PM219 was chosen over other much faster compara- tors, because of its relatively low offset current specifications. The PM219 with 150 nA/typical case or 500 nA/worst case input bias currents in combination with the low 1 8 9 4 output resistance of the CA388 D/A causes imperceptible, i.e., 0.2 mV/typical or 0.7 mV/worst case, external voltage offsets for 8 parallel input analog channels, and only 1.7 mV/typical or 5.7 mV/worst case offsets for 64 parallel inputs. These figures compare favorably with a 20-mV bit resolution based on a 5 V/256-bit D/A. Because the observed glitch output energy of the CA388 D/A is small, it was decided to forego the added complication- and speed-reducing option of a delayed enable for the output. Instead, C, = 10 pfd was added to create a low-pass filter (2RC = 8 ns) to improve comparator input noise stability. The combination of the input filter and output Schmitt inverter proved effective in stabilizing the conversion down to a differen- tial signal of less than 1 mV. At this point, the latching circuit, based on flip-flop 5 explained earlier, resolves any remaining low-level instabilities.

The speed limitation on the Fig. 1 circuit comes from the sum of the delay times for all components in the conversion loop, which with the 2 R C = 8 ns filter yields 172 ns/typical or 276 ns/worst case complete-cycle delay times. Using the 12 clock pulses per conversion, these upper limit circulating times result in estimating 0.5/0.3 MHz conversion rate maxima.

111. RESULTS

A Mac-I1 based data acquisition system [7] was programmed to deliver input to the converter, at an audio rate well below its maximum conversion ramp rate, in the form of an ascending staircase ramp of 1000 analog inputs in 5-mV increments to cover the full range of the converter. The acquisition system also took in as inputs the binary magnitude and channel number input, converted these to decimal base, and stored these data points along with their respective analog converter input data for later use. A small segment of this data, taken at a conversion rate of 0.5 MHz, is plotted in Fig. 3, along with a portion of the 1000-data-point least squares fit. This data yielded an overall standard deviation of + / - 4.75 mV and a maximum deviation of 11.4 mV at near 4-V input as an illustration of linearity, accuracy, and 100% monotonicity of the converter.

1

1316 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 31, NO. 10, OCTOBER 1990

Conversion rate

2 0 2 5 30 35 4 0

Channel Difference (millivolts) Fig. 4. Minimum channel decision errors versus channel input difference

voltage.

An important series of interchannel resolution characteriza- tions was performed using the data acquisition system men- tioned above. In this case, the system output stepped-analog ramp was sent in parallel to two matched, stable op amp feedback amplifiers, one of which had a summing input that allowed for adjustment of an added constant-DC offset voltage. With one converter channel driven by one amplifier, the other converter channel driven by an identical amplifier with a fixed offset voltage, and all other channels connected high, the acqui- sition program was again operated to collect the same 5-mV increment input full-scale range of 1000 data points. This series of measurements was repeated using three different offset volt- ages each at three different conversion rates, and three different sets of channel configurations-the single-channel versus single-channel connection mentioned above, a dual-channel ver- sus dual-channel connection, and a triple-channel versus triple- channel connection. The wiring of the channel connections was done such that when the converter erred by choosing the high- valued channel instead of the designed-for minimum, the prior- ity encoder would report the selected channel as output data. With the availability of well over 100 000 data points, it proved obvious that error rate of minimum-channel selection does not depend significantly on the number of channels held in com- mon; thus single-channel, double-channel, and triple-channel results were clustered in reporting the results shown in Fig. 4.

These Fig. 4 results indicate an exponential and thus most likely a Gaussian dependency on noise and other sources of error, which is to be expected [2]. These Fig. 4 results further indicate, at an error rate of less than 0.1%, that approximately a 1.5-bit interchannel resolution results for both the 0.25- and 0.5-MHz conversion rates. It is obvious, also from Fig. 4, that a systematic failure of the converter's ability to discern a mini- mum occurs somewhere between 0.5 and 0.65 MHz.

The last characterization utilizes only one channel of the multichannel converter operating at a conversion rate of 0.5 MHz, driven by a 4 V p-p triangle wave at several different frequencies, with the output magnitude passed through a much faster D/A to an oscilloscope for display. These results are shown in Fig. 5(a)-(c). Fig. 5(a) with a 5 x lo3 V/s input ramp rate shows (within the oscilloscope resolution) a linear response, indicating near-perfect multichannel converter performance. Fig. 5(b), with a 1.1 X lo4 V/s ramp rate, shows several small steps, which indicate low-level missing-code errors and two major discontinuities, exhibiting similar high-level errors. Lastly, Fig. 5(c), with a 3.6 X lo4 V/s ramp rate, shows continuous 3-least- digit step missing code errors. Using one LSB at a 0.5 MHz conversion rate as the theoretical upper limit for maximum

0 400 800 1200 1600 2000 TIME (microseconds)

(a)

0 200 400 600 800 1000 TIME (microseconds)

(b)

O L L I L L I i I , , , / . I . I I ....1....1....! 0 40 80 120 160 200

TIME (microseconds) (C)

Fig. 5. Output ramp versus time for input 4 V p-p input triangle signals of various rates. (a) 5 x lo3 V/s. (b) 1.1 x lo4 V/s. (c) 3.6X lo4 V/s.

signal rate for full resolution yields 1 x lo4 V/s, which agrees well with the data of Fig. 5(a)-(c).

IV. CONCLUSIONS

An 8-channel input version of a minimum-seeking A/D con- verter with 8-bit magnitude resolution was fabricated in an MSI printed circuit embodiment, and successfully demonstrated to operate at 0.5 MHz. The choice of a PM219 comparator, based on combined low input offset current specifications of 500 nA/maximum at a fast response of 80 ns/typical was the critical component selected to permit straightforward expansion of the input capability to 64 analog channels, at a later time, without loss of other demonstrated performance specifications.

It may be very desirable for several applications to achieve the 64-channel analog input loser-take-all circuit with 8-bit output magnitude at a 0.5-MHz conversion rate, using the same MSI component types. To do this, one need only increase the parallel input comparator-Schmitt gate combination from 8 to 64, while increasing the priority encoder number from one to eight in parallel and adding one eight-input AND-gate to handle their parallel C, outputs. Such a circuit would still be manageable at the board level, adding only the negligible cycle delay time of the %input gate propagation delay to the conversion loop. Certainly, a VLSI version would prove useful if the conflicting speed and low offset current specifications prove compatible to a given dedicated process.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 3 7 , NO. 1 0 , OCTOBER 1990

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A myriad of other design combinations seem to be available, as simple extrapolations of this proven design, but they have not been seriously considered for likely appearance of other practi- cal problems. By using a CMP-02 type comparator with input offset current specifications of 10 nA/max. and response speed of 250 ns/typical, a many-hundred-channel analog input, 8-bit output magnitude, at a conversion rate of 0.25 MHz, appears possible. Speed of conversion gains much greater than those demonstrated are unlikely, because of the many components the signals must circulate through for each magnitude bit. An esti- mate would suggest as an example a 16-channel analog input with 4-bit output magnitude resolution at a conversion rate of 2 MHz as an upper limit for this type of circuit.

ACKNOWLEDGMENT

The authors express their gratitude to James Pappin for developing the LABVIEW data acquisition program used in this paper, and for pre-testing it on a conventional A/D converter.

REFERENCES S. Soclof, Applications of Analog Integrated Circuits. Englewood Cliffs, NJ: Prentice-Hall, 1985. B. M. Gordon, “Linear electronic analog/digital conversion architec- tures, their origins, parameters, limitations, and applications,” IEEE Trans. Circuits Syst., vol. CAS-25, pp. 391-418, July 1978. Y. Ichioka and J. Tanida, “Optical parallel logic gates using a shadow- casting system for optical digital computing,” Proc. IEEE, vol. 72, pp. 787-801, July 1984. D. Casasant and E. Baranoski, “Directed graph for adaptive organiza- tion and learning of a knowledge base,” Applied Optics, vol. 27, pp. 534-540, 1988. A Moopenn, J. Lambe, and A. P. Thakoor, “Electronic implementation of associative memory based on neural network models,” IEEE Trans. Syst. Man, Cybem., vol. SMC-17, pp. 325-331, Mar./Apr. 1987. R. A. Athale, H. H. Szu, and C. B. Friedlander, “Optical implementa- tion of associative memory with controlled nonlinearity in the correla- tion domain,” Opt. Lett., vol. 11, pp. 482-484, July 1986. Labviewm, National Instruments Corp., 12109 Technology Boulevard, Austin. TX 78727-6204.

Frequency Domain Analysis of Hopf Bifurcations in Electric Power Networks

H. G. KWATNY AND G. E. PIPER

Abstract -In this paper we discuss an approach for studying certain types of parametric instabilities in electric power networks that are associated with a Hopf bifurcation. The frequency domain version of the Hopf bifurcation theorem due to Mees and Chua [91 allows us to complete the example of power system flutter instability described by Kwatny and Yu [71.

I. INTRODUC~ION In power systems analysis, stability of an equilibrium point is

often determined by investigation of the linearized dynamics. When system parameters vary, so does the linearized model and stability of the equilibrium point may be lost. When this occurs, it typically takes place in either of two ways: a single real

Manuscript received October 17, 1989. This work was supported in part by the National Science Foundation under Grant ECS-871914. This paper was recommended by Associate Editor T. R. Viswanathan.

H. G. Kwatny is with the Department of Mechanical Engineering and Mechanics, Drexel University, Philadelphia, PA 19104.

G. E. Piper is with the Astro Space Division of General Electric, Prince- ton, NJ.

IEEE Log Number 9037944.

eigenvalue of the linearized dynamics or a pair of complex conjugate eigenvalues crosses the imaginary axis. Loss of linear system stability in the former case is sometimes called a “diver- gence instability” and in the latter a “flutter instability.” A complete understanding of the underlying mechanics of the instability can only be obtained, however, by an analysis of the nonlinear system dynamics. In nonlinear dynamics parlance, when the instability is associated with the variation of a single parameter the divergence instability is typically a saddle-node static bifurcation and the flutter instability is typically a Hopf bifurcation.

There has been an eroneous perception that Hopf bifurca- tions do not occur in power systems. Some of this attitude may be due to comments in Venikov et al. [12] that suggest that flutter instabilities are not likely in normal power system opera- tions, and also to some results of Arapostathis et al. [3] who argue that the classical swing equations with lossless lines and damping do not possess (so-called type one) periodic solutions. On the other hand, evidence of the occurrence of Hopf bifurca- tions does exist. In [lo], van Ness et al. suggest that an observed oscillation is associated with a Hopf bifurcation. Abed and Varaiya [l] illustrate subcritical Hopf bifurcations in a two- machine model with a lossy transmission line. Alexander [2] provides a complete analysis of this case and demonstrates the occurrence of both subcritical and supercritical Hopf bifurca- tions. Kwatny and Yu [7] give an example of a flutter instability in a three-machine classical network with lossy lines. Another example of a flutter instability is given by Rajagopalan et al. 1111 in which a three-machine system is modeled with a two-axis representation and excitation is included.

When a flutter instability is observed in the linearized model, it is important to complete the analysis and to characterize the bifurcation completely. This is so because a loss in stability of the equilibrium point which is accompanied by the appearance of a small stable periodic motion (supercritical Hopf) may be of relatively minor concern whereas the existance of an unstable periodic motion near a stable equilibrium (subcritical Hopf) could portend catastrophic consequences following relatively minor disturbances. In this paper we present an approach to the analysis of Hopf bifurcations that may be conveniently applied to systems of reasonable scale. We show that the power system flutter instability of [7] corresponds to a supercritical Hopf bifurcation.

11. MODEL AND PROBLEM DEFINITION

The dynamical equations of motion of the classical power system model may be written as [6]

M i + D$ + f l ( S , + , V , p ) = 0 (2.la)

f 2 ( ~ , + , ~ , p ) = 0 (2.lb)

where M denotes the diagonal matrix of generator rotor iner- tias, D the damping matrix, S the n-vector of generator internal bus angles, 4 the rn + I-vector of load bus angles, V the I-vector of PQ load bus voltage magnitudes, and p a k-vector of network and load parameters. The functions fl: Rn+mi2’ik -+ R” and

Let (8*,4*,V*,p*) be an equilibrium point of (2.1). Suppose that the equilibrium point is strictly causal in the sense that there exist unique functions 4(S, p), E ( S , p) satisfying

are the usual load flow relations. f2: ~ n + m i Z l + k ~ ~ r n i 2 1

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