IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-16, NO. 6, DECEMBER 1981 661

[5]

[6]

[7]

[8]

M. A. ~aidique, “A high precision monolithic super-beta opera-tional amplifier,” IEEE J. Solid-State Circuits, vol. SC-7, p. 480,Dec. 1972.P. R. Gray and IL G. Mey&, Analysis and Design of Analog Inte-grated Circuits. New York: Wiley, 1977, ch. 11.G. Erdi, “Instrumentation operational amplifier with low noise,drift, bias current, “ in Northeast Res. Eng. Meetr”ngRec. Tech.Papers, Oct. 1972; also OP-05 Data Sheet, Precision Monolithic,Inc., Jan. 1973.—, “A precision trim technique for monolithic analog circuits,”IEEE J. Solid-State Circuits. vol. SC-10, v. 412. Dec. 1975; alsoOP-07 Data Sheet, Precision”Monolithic;, ~rtc., June 1974.

A Low-Voltage

OTTO H. SCHtiE, JR.

Abstract-This paper describes the development of a threshold-implanted BiMOS amplifier IC optimised for 2-5 V operation at a sup-ply current of 300 PA. A nonlinear operational trrmaconductanceam-plifier (OTA) buffer having on-chip feedback provides a low-impedancerail-to-rail output, and a bulk-modulated PMOS input pair extends thecommon-mode range. Protective-network bootstrapping makes possibleaubpicoampere input-bias currents below 85°C, and improved offsetstability is achieved by the choice of threshold-level stage currents.Amp~ier design is straightforward and readily applied from “micro-power” to “broad-band” operating ranges. The combination of thesefeatures haa produced a unique high-performance integrated circuit.

I. INTRODUCTION

T HE monolithic operational amplifier continues to evolvein new and improved forms. Part of this change appears

to be the result of the influence of more sophisticated systemsin which approaches such as “autozeroing” permit perfor-

mance improvements. Another factor is the trend towardlower-voltage single-supply operation for microprocessor, auto-motive, portable, and remote applications. In addition, the

appeararice of linear CMOS products provides a broader per-spective and challenge for op amp design in a high-density in-expensive process.

For small to moderately sized silicon chips–perhaps up to10000-15000 milsz –process cost may permit the designer a

choice of bipolar, CMOS or “mixed-technology” (B-&lOS,BiFET) approaches. Performance requirements have usually

dictated that choice: bipolar for its accuracy potential [1],[2] and mixed-technology amplifiers for their combination of

Manuscript received April 3, 1981; revised June 23, 1981.0. H. Schade, Jr. is with the RCA Solid State Division, Somerville,

NJ 08876.E. J. Kramer was with the RCA Solid State Division, Somerville, NJ

08876. He is now a graduate student at Cornell University, Ithaca, NY14853.

[9] —, “A low drift, low noise monolithic operational amplifier forlow level signal processing,” Fairchild Semiconductor, Applica-tion Brief 136, July 1969.

[10] Y. Nishikawa and J. E. Solomon, “A general purpose wideband:~4~;~5nal amplifier,” in ISSCC Dig. Tech. Papers, 1973, pp.

[11] J. E. Sol~mon, “The monolithic op amp: A tutorial study,” IEEEJ. Solid-State Circuits, vol. SC-9, p. 322, Dec. 1974.

George Erdi (SM’75), for a photograph and biography, see this issue,p. 607.

BiMOS Op

AND ERIK J. KRAMER

Amp

speed, bandwidth, and input impedance [3], [4], with analogCMOS fast assuming an important posture [5], [6].

More specifically, recent developments in op amp designhave stressed extended-range operation and improved inputand output swings at lower supply voltages. At ISSCC ’78, it

was shown that low-voltage bipolar amplifiers can deliver sub -

stantial drive currents [7]. In order to accomplish this goal ata supply of 1,1 V, however, the amplifier design and its com-pensation can become quite complex. CMOS op amps’ de-

scribed at Electro ’79 show excellent input-voltage range andlow-voltage micropower capability [8] , but sacrifice gainunder load and low output resistance in order to achieve rail-to-rail output swing. Similar shortcomings exist when CMOSinverters are used as an output stage [4] , the inverters requir-ing a large class A current in order to drive even modest loadcapacitance without excessive phase shift.

A new design approach described in this paper circumventsmost of these limitations. A BiMOS process makes possible a

large common-mode input range, exceptionally low input-biascurrents, and a rail-to-rail low-impedance output, while re-maining economically competitive. Operation at supply po-tentials down to 2 V is readily achieved with simple circuitry,and tightened threshold control would appear to make thesame approach practical for hiy~-performance 1 V operation.

II. A DESIGN APPROACH

This section treats amplifier design in general terms; a moredetailed description of new aspects follows in a subsequentsection. Fig. 1 shows the annplifier in block form. A gainstage having a PMOS input drives a second buffer amplifierhaving substantial feedback. Bias is generated by a bandgap-type loop, which permits relatively good control of bufferidling currents. A pair of unity-gain amplifiers bootstrap theinput protective networks (shown here simply as diodes) to

0018-9200/81 /1200-0661 $00.75 @ 1981 IEEE

662 IEEE JOURNAL OF SC)LID-STATE CIRCUITS, VOL. SC-16, NO. 6, DECEMBER 1981

1’,,1~ \QI \

I \\

I

I

\

I\

GAIN \\

o/ o

/’/

//

/I /

/ DESIGN APPROACH

/

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//

I/ “

/I ,’

0

1/‘Fig. 1. BiMOS amplifier in block form.

T oI

_i

“+

IIN

4

DI FFPAIR

+10

1 ‘- OUT

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Fig. 2. Classical operational transconductance amplifier.

achieve very low leakage currents. The buffer is an operational

transconductance amplifier, OTA [9] (Fig. 2), having a PMOS

input pair similar to that of the gain stage. An OTA is charac-

terized by a voltage-driven differential input that provides a

single-ended output current, hence the term “transconduc-

tance.” In classical form, three current-mirror amplifiers ter-

minate ihe differential pair in an output node whose potential

can swing from rail to rail. Voltage feedback substantially re-

duces the normally high output resistance. A shortcoming of

the standard OTA is a limited drive efficiency. Complete tog-@ing of the input pair produces a signal of only *2 10, twice

the output-leg idling current. This limitation can be overcomeby using nonlinear current mirrors.

A simplified amplifier schematic is shown in Fig. 3. Thehigh-gain portion uses a well-known configuration of differen-tial pair, mirror for differential to single-ended conversion, andMiller-compensated second-state feeding a high-impedancenode. Applicable analyses are available in the literature [10] -[12] . This particular amplifier includes a PMOS pair whosechannel bulk is tied to the positive rail. The effect of the bulkmodulation caused by a common-mode excursion is to in-crease the gate-to-source potential Vg~of these devices as theyare pulled toward the negative rail. A small V@near the posi-

tive rail increases sufficiently at the negative rail because of thehigher bulk-to-source potential to permit linear operation witha 1 Vbe mirror load. Common-mode range is thereby increased.

Bim for the amplifier is produced by the bandgap-type loop

at the left in Fig. 3. The h-p-n geometry d: 1 (Q4/Q5) sets upa AVbe which is converted by RO 1 to a loop current. A 10:1emitter geometry establishes 60 mV across RO 1. The muhiple-output p-n-p mirror provides A Vbe-related current sources forthe gain and buffer amplifiers.

The buffer shown in Fig. 3 uses a PMOS pair similar to the

gain stage, and operates into nonlinear current mirrors. Resis-tors ,??.2 and R03 have impressed upon them a potential re-lated to and temperature-tracking the AVbe in the bias loop.

If, for example, 60 mV is impressed upon resistor R03 underquiescent conditions, slave transistor Q17 sees an enhancedemitter-base potential that tends to increase its output currentby a factor of ten. The current ratio can be returned to unityby setting a: 1 = 10:1, which establishes an output-leg currentequall in value to that feeding the mirror. Upon toggling thediffe:rentii pair; however, the Al’be across R03 doubles (to120 mV for the example), and Q16 master-diode potential in-

creases another 18 mV because of increased current density.The result is an output current approaching 20 times the idlingcurrent and much improving output efficiency. The schemeretains the inherent current-limiting feature of an OTA, but athigher levels. It is of advantage to use a feedback network,R 1/1/2, in place of a direct input-output connection. ForR 1 = R2, buffer pair P15/Pl 6 operates from negative rail toone-half the supply voltage for the most positive output swing.This condition provides gate-source operating-potential “head-room” for the buffer pair at low supply voltages.

The choice of operating current levels determines such am-plifier parameters as gain, bandwidth, and slew rate, but notinput bias current, as in a bipolar stage. The input bias currentin tlhe subject amplifier is a function of protective-networkleakage alone, and is essentially unrelated to amplifier geom-

etry or current level. A “broad-band” 5 V/LN amplifier wasbuilt that performed satisfactorily with *1O mA outputs.However, at reduced current levels it was found possible toprovide a *2 mA drive from a 300 LA amplifier, ample drivefor :many low-voltage circuits and sufficient to maintain theslew/bandwidth of “general-purpose” Op amps like the 741.

Furthermore, the threshold-level stage currents promised

greater precision and stability from a MOSFET pair because ofthe improved transconductance-to- current ratios. MOSFETtransfer-characteristic control is more readily achieved as stagecurrents are reduced from square-law operation through thethreshold transition and into the exponential region [13] . Be-cause of the improved accuracy potential, input protective-

network bootstrapping becomes a practical complement tosuch an amplifier. The bootstrapping technique minimizes thereverse potential across the junction(s) that causes an input-bias leakage, and radically reduces both the current levels andtheir temperature sensitivity. A subpicoampere bias is readilyachieved below 85 ‘C, and room temperature values as low as

10-;20 fA have been observed. This design approach waschosen in the development of the subject integrated circuit.

The choice of a 2 V minimum supply was made to achievegood IC yield despite process MOSFET threshold variations.

SCHADE AND KRAMER: LOW-VOLTAGE BiMOS OP AMP 663

tBIAS

“’”-—t---’”’’” --i v+

Fig. 3. Simplified amplifier schematic diagram.

f7+792CL- 33955

Fig. 4. Complete schematic diagram of the amplifier.

A cascoded bias loop (which requires about 1.6 V) is employed

to hold supply current more constant at a 20 V level. Although

the BiMOS process typically permits ratings of up to 44 V,channel lengths were reduced to allow better transconductance-to-capacitance ratios; the reduced channel lengths limit poten-tials to the order of 20 V. For example, there is little need forthe buffer PMOS pair to provide the offset or transfer charac-teristics match of the input pair. Hence, these devices are ofminimum length (without cross coupling) for greatest band-width. A 20 V rating permits the amplifier to be used withCMOS circuits.

111. FURTHER AMPLIFTER DETAIL

A. The ICProcess

The amplifier is made by means of a BiMOS process intro-duced commercially in 1973 and refined during subsequentcircuit development [14] . Basically, p- and n-type aluminum-gate MOSFET’S complement an array of standard junction-

isolated bipolar devices. In this amplifier, all PMOS devices re-ceive an ion-implanted threshold tailored to a nominal 10 #AIds (drain-to-source current) value at about 0.6 V Vg~. Onlyone additional photomask is required beyond the number em-ployed for a compensated bipolar amplifier. Channel-oxidestatic protection is provided at the IC terminals by relativelyfast low-resistance base-emitter junctions applied directlyacross the gate-to-source circuitry [12].

B. A Complete Schematic

Provided a starting current for the bias loop, the circuit ofFig. 3 is operable as shown, amd could be butlt with a modest

chip area for a particular application. However, a general-

purpose op amp should provide the user with additional fea-tures, such as a broad supply voltage range and provision for

offset null. The subject amplifier also includes two boot-strapped inputs. A complete schematic diagram is shown inFig. 4. Notable deviations frolm the basic approach are

664 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-16, NO. 6, DECEMBER 1981

1) a cascoded bias loop to provide a stable (10 uA) refer-ence current;

2) a PMOS current-source mirror for accurate stage currentapportionment;

3) a unity-gain bootstrap amplifier for each input;4) protective networks, depicted here as simple diodes; and5) mirror emitter resistors at the null terminals and their

collector-resistor partners to assure balanced drain/sourceand collector/emitter potentials.

The 60 mV nominal AVbe in the bias loop is reflected to thebuffer current-mirror resistors as a little more than 80 mVunder a no-load condition, and provides an output-leg idling

current of 120 vA. The feedback network is built of four50 kfl pinch resistors, which constitute an X2 buffer. Com-pensation is achieved with aluminum/channel-oxide capaci-tors. Optimum compensation in the form of the least capaci-tance needed to obtain a given phase margin for the cascadedamplifier portions was determined by breadboard test, and in-cludes additional small bypass capacitors across the feedbacknetwork.

C. The Buffer Stage

Design of the buffer required consideration of current levels,output resistance, open-loop gain, and the effect of nonlinear

mirror-current ratios. Open-loop buffer gain may be expressedas

AUb ‘Aigm~~L (1)

where A i is a dynamic mirror-current gain, gwb is the FETtransconductance at its channel current, and RL is the loadedoutput-node resistance. A i changes with amplifier load in re-sponse to the feedback signal and subsequent differential-pair

imbalance, and is implicitly expressed in the relationship

AV& =zRO =~ln(mAt) (2)

where KT/q is the Boltzman or thermal voltage and m is amirror geometry ratio. The resulting output resistance of thebuffer is

Rout = 12A[gmb “

(3)

The factor 2 is a consequence of the parallel signal paths in theOTA. The parameters Ai = 4 and m = 6 apply in the n-p-n out-put leg of the subject amplifier; a brdanced signal gain is pro-

vided in the p-n-p output leg. For g~b = 300 X 10-6, the cal-culated output resistance is approximately 400$2, which is inreasonable agreement with the measurement of IC perfor-mance. Under increasing load, the AVbe on the mirror emitter-resistor changes, producing a nonlinear current-gain increase inone path while current in the other path quickly loses signifi-cance. Buffer gain nonlinearity is not evident in typical appli-cations because of both on-chip and external feedback.

Compensation of this nonlinear system is readily determinedempirically, dominant considerations for phase shift being thedifferential-pair tail pole and p-n-p base-transit time. The feed-back network resistors influence buffer current balance andare chosen relatively large to avoid circuit loading. Phase mar-

Fig, 5. Phase and amplitude response of three breadboarded unity-gainbuffers.

LOAO

~JRRENT (kfic ROAMpERES)

Fig. 6. Typical output swing under load.

gin is evaluated under conditions of highest buffer loop volt-

age gain, which occurs at the greatest output-voltage swingand heaviest load. For lesser voltage and current excursions,the buffer is, then, “over compensated.” The compensation re-

quired for 20 V operation is significantly greater than for 5 V

operation. The loss of slew rate and the need for increasedcapacitor sizes raise the question of whether a low-voltage am-plifier need be designed to perform as well at high supply po-tentials. Buffer compensation on the subject amplifier isfreed, local to the buffer loop, and unavailable for adjustment,all factors that avoid undue complication for the user. Shouldgain-stage compensation be desired beyond that provided, theuser can add capacitance between terminals 1 and 8 in themanner standard for op amps.

Fig. 5 shows the phase and amplitude response of threebreadboarded unity-gain buffers having a total current drain inthe 8-800 WA range; the buffers demonstrate unity-gain band-widths up to 5 MHz. As stage currents are increased (by scal-ing the RO resistors), the dc beta and the base resistance of the

mirror slave transistors assume greater significance, and even-

tually limit the maximum current gains that can be practicallyattained. The integrated amplifier includes a 120 I-LAbufferhaving a bandwidth and supply current similar to those of thegain section. Fig. 6 describes the typical output swing of the

amplifier under load. Saturation voltages to the rails in theorder of 0.1-0.3 V at 1 mA load are achieved; the inherentcurrent limiting above 2 mA is evident. Negative rail voltageexcursions must allow for the buffer differential-pair signaloffset, which becomes greater with increased loading. A buf-fer feedback network referenced to a potential intermediate to

SCHADE AND KRAMER: LOW-VOLTAGE BiMOSOP AMP 665

the supply rails, rather than the negative rail, could provide ad-vantages from a system standpoint, but was judged less effi-

cient in supply current and chip area.

D. Bias-Supply Cascading

The bias supply for the amplifier is shown at the far left inFig. 4. Starting current is provided by an open-base n-p-n tran-

sistor [15], a neat approach to the need for a low-level currentthat does not perturb the 10 I.LAloop current. Testing showsthe integrated circuit to be reliable despite the imposition of alow-temperature environment or power supply transients.Cascoded n-p-n loop devices and a PMOS mirror of large chan-nel length both contribute to ratio accuracy and high outputresistance. The result is a relatively stable A V’e and loop cur-rent in the presence of supply-voltage variation. Althoughsuch current stability is not generally necessary in op amps,

the nonlinear current mirrors used in the subject amplifier are

highly sensitive to current change. Fig. 7 shows quiescent sup-ply current 1. as a function of potential variations up to 20 V.

As the figure shows, the cascode arrangement produces a rela-tively stable A V&, and the corresponding current undergoes amoderate increase with supply potential. In contrast, the“simple” loop produces a current change judged unacceptablebeyond 8-10 V. The PMOS mirror, which transfers the loopcurrent to the gain and buffer stages, makes use of large chan-nel lengths to provide high output resistance, thus consumingconsiderable chip area.

IV. INPUT CHARACTERIZATION

A. Input Voltage Range

The useful region of amplifier operation is determined by

the input common-mode range. As previously mentioned,FET input devices have an advantage over their bipolar coun-terparts in that bulk modulation maybe used to enhance inputrange. Fig. 8 shows the input offset of a unity-gain amplifier

operated with 2 and 5 V supplies. This particular sample hasa nominal threshold of about 0.4 V, as suggested by the offsetchange near the positive rail, which is similar for both 2 and

5 V operation. A nominal 2 V bulk modulation brings thenegative-swing capability to that rail; as shown, 5 V operationextends the range beneath the negative rail. Further increasesin supply voltage tend to produce an even greater negativerange, but the clamping action of the overdriven protectivenetworks limits operation to about 1 V&ebelow the negative

rail.

SUPPLY POTENTIAL(VOLTS)

Fig. 7. Quiescxmt supply current.

Fig. 8. Input offset with 2 and 5 V supplies.

r?”+

(a)

v+

0sOURCES

GATEA

/Y

[ ‘,”+ }+Process controls that permit a *0.3 V threshold variation re- ~b)

suit in good yields when the devices are operated with a 2 VFig. 9. Input protective network.

supply. A worst-case common-mode range from +0.3 V to+1.3 V is assured, the nomirwd range being +0.0 to +1.6 V.

preach has subsequently proven successful in two commercialproducts, and has been adapted to the subject amplifler. Fig.

The threshold variation results in approximately 0.3 V less q ~ows the bootstrap buffers to be similar to the main ampli-

common-mode range, worst case, than that of a 2 V bipolar ~amplifier having a 0.7 V base-emitter offset; however, more

ler input stage, the major difference being an unbalanced

than half the chip population will have a “better-than-bipolar”current-mirror load intended to reflect a predominately re-

common-mode range.versed junction bias to the critical protection network “di-ode.” The schematic diagram of Fig. 9(a) shows the diode

B. Bootstrapping representation to be oversimplified, and the multiple-emitter

Earlier work on smoke detectors required the development model is itself not strictly correct. A die cross section inof a protected low-current input [13]. The bootstrap ap- Fig. 9(b) describes the relative~y compact structure, which per-

666 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-16, NO. 6, DECEMBER 1981

+3az

—

—

—

-2 I I25 45 65 85 105 125

TEMPERATURE “C

Fig. 10. Protective network leakage (input bias) for a typical amplifier.

400z50>

~ 200

%

ma50L<cc~1-: . zoom

-1024681012 1416 18 20INPUT POTENTIAL (VOLTS)

Fig. 11. Dependence of buffer bootstrap bias upon input potentiaL

mits an 18 V gate-to-gate differential. The n-epitaxial boat istied to the positive rail, and the bootstrap potential is appliedto the appropriate p-base diffusion.

The protective network leakage (input bias) for a typical am-plifier is shown in Fig. 10, and is radically lower than that of aMOSFET protected in the normal way. The output of the in-ternal amplifier buffers can be overridden by external test po-tentials. The resulting parametric variations (bootstrap biaspotentials) show that a judicious choice in amplifier design canfurther reduce leakage in the high-temperature range, a mini-mum occuring at approximately -120 mV for this amplifier.

The ability of the simple on-chip buffers to produce a desiredbootstrap bias is shown in Fig. 11. At low supply voltages, thebias averages -10 to -40 mV, but increases substantially in the10-20 V range to -200 mV. The shape of the curves is attrib-utable to the nonlinearities in the output resistances of thebootstrap differential pair, the unbalanced mirror, and the tail-current source. It is not possible for the buffer output totrack excursions below the rail; the result is the demise of thebuffer function in that region. The amplifier input bias can beestimated by determining the bootstrap bias for the applica-tion from Fig. 11 and then referring to the characteristic ofFig. 10. The measured performance of three samples whoseinput was centered between 5 V rails is shown in Fig. 12, andis in general agreement with a –40 mV bias approximation.

Although this data points out that high-temperature bias cur-rent is not simply characterized, very low levels are readily

25~

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:m 10 /

gaz

5 — — —

I —t -– & --+- –t0

020405060 100 I20

TEMPERATURE “C

Fig. 12. Input bias of three samples at t 2.5 V operation,

L----+-3-50 -2b d /5 io +5 160 125

TEMPERATURE “C

Fig. 13. Input-offset temperature drift often randomly chosen devices.

achieved in practice, and a user can benefit from them over awide operating temperature range. The maintenance of a cir-cuit environment for subpicoampere operation will probablyrequire much attention. On the other hand, attention to oper-ating details promises the reward of really outstanding high-temperature performance.

C. Offset Stabili@

The maintaining of offset stability with temperature hasbeen a particularly difficult task with MOS transistors; themore sophisticated IC systems employ aut ozeroing techniques

to avoid such problems. Amplifiers designed to operate atthreshold (and subthreshold) current levels have an enhancedtransconductance with which to respond to circuit balance er-rors and the effects of impurity migrations. Fig. 13 shows theinput-offset temperature drift of ten randomly chosen devicesmounted in plastic packages. It may be observed that, in gen-eral, typical temperature drift is under *5 pV/°C over a broadtemperature range. An additional drift mechanism is intro-duced at 100”C. It has been analyzed as the result of leakagefrom the diffused plate of the main amplifier compensationcapacitor, which produces an input differential-pair current

imbalance. The high-temperature drift has been removed byusing off- chip compensation. More importantly, it can be ef-fectively forestalled by constructing a bootstrapped capacitor,

SCHADE AND KRAMER: LOW-VOLTAGEBiMOSOP AMP

BASE COLLECTOR

-+

Fig. 14. Bootstrapped capacitor.

CURRENT S? URCES BIAS LOOP

- -Fig. 15. Low-voltage BiMOS op amp chip.

such as shown in Fig. 14. In this configuration, the n-boat isbiased 1 V& above substrate, the nomimil potential at, whichthe diffused-p capacitor plate operates, resulting in much re-duced leakage. This technique is in use in an existing amplifierand is being incorporated in the layout of the subject op amp.

Life tests of pilot production devices have shown better

input-offset stability than those of previous B&OS op amps.Operation of the IC with a 5 V supply at 125°C (plastic pack-

ages) in a unity-gain configuration exhibited art average ran-dom drift of *300 WV over a 3000 h period: Art 85°C com-parator life te,st with continuously toggled (worst-case) inputshowed an ordered 400 #V/1000 h drift over a 3000 h period.

V. THE SILICON AMPLIFIER

Fig. 15 shows the 76 X 76 mil chip partitioned at the boimd-

aries of its functional portions. The bootstrap amplifiers andbias loop require a small fraction of the chip area, the gainstage tid output buffer have roughly similar areas, while a dis-proportionate amount of space is occupied by the current-

source (PMOS) function. The bias supply loop and nonlinearmirror resistors are reasonably close to one another hi theupper right quadrant, and the input stage is at the lower left.The ten bond pads provide the eight terminals shown in Fig. 4plus two bootstrap buffer outputs, which will be made avail-able on a sister chip. Cost-effective dual and quad amplifierscould also be built with this approach. Table I summarizes atypical amplifier characterization.

Input voltage 1/f noise varies moderately with supply voltage

choice; the 300 nV/@ figure applies to 10 V operation.

667

TABLE ITYPICALAMPLIFIERPERFORMANCE

Input Offset *2 mv

Offset Drift 3 )lVl”c

Input Bias <1 PA to 85°c

15 PA @ 125°c

Input Range -0.5V to +4.6v @ 5V supply

O.OV to +1.6v @ 2V SU~ply

Voltage Noise 300 nV/~ @ 10 Hz

Open-Loop Gain i03 dB

CM5R (Common-ModeRejection Ratio) 85 dB

PSRR (Power-SupplyRejection Satio) 90 dB

Unity-GainSlew 0.5 Vlps

Unity-GainBandwidth 0.5 MHz

Output Swing O.lV to 0.3V to rails @ 1 mA

Output Drive +2 mA

Output Resistance 300 ohms @ idle

Supply Current 300 pA

Supply Voltage Range 2 to 20 volts

With a 2 V supply, the noise is reduced to approximately 250nV/@. The reduction in noise is attributed to the comrnon-

mode bulk modulation, which is believed to cause channel-

current flow further beneath the region of greatest lattic6damage near the oxide interface as a more depletion-typeoperation pertains.

VI. SUMMARY

A high-performance low-voltage amplifier has been devel-oped in which

1) a different approach to output stage design provides rail-to-rail swing ih concert with low impedance;

2) buffer drive capability is enhanced by nonlinear mirrors;3) supply current control is achieved by relating the AVM

of the buffer mirrors to that of a bandgap current supply;4) a threshold-tailored BiMIOS process permits the deiign of

efficient 2 V amplifiers having high chip yields;5) input stage bulk modulation enhances common-mode

range;

6) bootstrapped protective networks permit subpicwinpereoperation below 85 “C, and (deliver exceptional high-tempera-ture performance;

7) the choice of threshold level channel currents markedlyimproves offset stability;

8) circuit design remains relatively uncomplicated, and therequired die size moderate; and

9) the design approach is readily extended to “micropower”or “broad-band” operation without essential change to the lowinput-bias currents.

Tlie amplifier input offset and drift, slew/bandwidth, com-mori-mode, and power supply rejection ratios attain ~e per-formance levels of general-purpose bipolar op amps, at a mod-est supply current. Near rail-to-rail input and output swings

668 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-16, NO. 6, DECEMBER 1981

are provided down to 2 V supply without sacrifice of outputresistance. The magnitude and temperature sensitivity ofthe input-bias current set a new standard for monolithicamplifiers.

ACKNOWLEDGMENT

Credit is due to A. Frim and S. Kim for a thoroughly exe-

cuted layout, and to G. Harayda, J. Hsu, and H. Wittlinger for

applications guidance and support.

REFERENCES

[1]

[2]

[3]

[4]

[5]

[6]

[7J

[8]

[9]

[10]

[11]

[12]

[13]

[14]

[15]

R. J. Widlar, “IC bipolar op amp holds down de errors, even overtemperatgre~’ Electron. Design, vol. 26, p. 44, Dec. 1979.S. Ohr, “Data acquisition drives analog signal processing~’ Elec-tron. Design, vol. 28, p. 65, Sept. 1980.R. W. Russel and D. D. Culmer, “Ion irrtphgnted.JFET-bipolarmonolithic integrated circuits,” in Proc. IEEE Int. Solid-StateCircuits Con~, 1974, p. 140.0. H. Schade, Jr., “CMOS/bipolar linear integrated circuits< inProc. IEEE Int. Solid-State Circuits Conf, 1974, p. 136.D. Bingham, “CMOS: Higher speeds, more drive and analog capa-bility expand its horizons: Electron. Design, vol. 23, p. 74, Nov.1978.D. Fullagar, “CMOS comes of age; IEEE Spectrum, p. 24, Dec.1980.R. J. Widlar, “Low voltage techniques; in Proc. IEEE Solid-StateCircuits Corr$, 1978, p. 238.J. Zis, “CMOS and laser trimming provide unmatched A/D LSIperformanco~’ Session 2, Electro Professional Program, NY, Apr.1979.C. F. Wheatley and H. A, Wittlinger, “OTA obsoletes op amp,” inProc. NEC, Dec. 1969.J, E. Solomon, “The monolithic op amp: A tuitorial study:’IEEE J. Solid-State Circuits, vol. SC-9, p. 314, Dec. 1974.P. R. Gray and R. G. Meyer, Analysis and Design of Analog In-tegrated Circuits. New York: Wiley, 1977, p. 320.0. H. Schade, Jr., “Advances in BiMOS integrated circuits;’RCA Rev., vol. 39, p. 250, June 1978.

“BiMOS micropower integrated circuits; IEEE J. Solid-Stat’e Circuits, vol. SC-13, p. 791, Dec. 1978.M. A. Polinsky, O. H. Schade, Jr., and J. P. Keller, “CMOS-bipolar monolithic integrated circmt technology,” in Proc. IEDM,1973, p. 229.B. Crowle, “Current regulating circuits,” U.S. Patent 4063149,Dec. 13, 1977.

., Otto H. Schade, Jr. received the B.E.E. degreefrom Rensselaer Polytechnic Institute, Troy,NY, in 1953.

Following his graduation from Rensselaer, heworked in the Design and Advanced Develop-ment groups at RCA, Harrison, NJ, where hedesigned vacuum tubes and mechanical filters

.,,. ,.- and studied heat flow and electron optics as

,.:, applied to beam power tubes. In 1961, he was... responsible for the electrical performance and‘ “ testing of thermoelectric converters for Atomics

Internatiorud’s SNAP 10A space program. He then developed a rangeof 1-60000 Btu/h high-efficiency gaseous and liquid-fuel burners forthermoelectric generators, and completed the system design for a 100-W Signal Corps portable model. He joined the RCA Solid State divisionin 1966, where he became involved in process-related IC projects, fol-lowed by the development of Fortran programs for thermal transientarralysis in RF power transistors. During 1967 and 1968, he assistedO. H. Schade, Sr., in the development of the high-definition TV art bydesigning solid-state vertical and horizontal deflection amplifiers for a1OO-MHZ4000-line system. In 1969, he returned to RCA’s Linear ICgroup to design industrial and commercial products such as operationalamplifiers, a CMOS DAC, GFI, and smoke-detector circuits. He is cur-rently developing linear-CMOS data-acquisition circuits.

Mr: Schade is a member of Eta Kappa Nu, the author of 14 papers,and has been granted 41 U.S. patents. In 1978,, he and M. A. Polinskyreceived the David Sarnoff Award for Outstanding Technical Achieve-ment for developing high-performance Bik40S integrated circuits.

Erik J. Kramer received the B.S.E.E. ,degreefrom Cornell University, Ithaca, NY, in 1981.

He joined the Linear IC Design Group of theRCA Solid State Division, Somerville, NJ, forthe summer intercessions of 1978, 1979, and1980. There he helped develop the subject op-erational amplifier and other integrated circuits,gaining exposure to bipolar, MOS, and 12L cir-cuitry. During the Summer of 1981 he joinedthe National Research and Resource Facilityfor Submicron Structures at Cornell Univer-

sity, Ithaca, NY, where he concentrated on scanning electron micro-scopy and electron-beam lithography. He received a fellowship forgaduate study at Cornell University and anticipates receiving hisM.E.E.E. in May, 1982.

Mr. Kramer is a member of Tau Beta Pi and Eta Kappa Nu.