A Low Drop-out Regulator forSubcutaneous Electrical Stimulation of Nanofibers

Used in Muscle ProsthesisYi Huang∗†, Fanpeng Kong∗, Joseph Freeman ‡ and Laleh Najafizadeh∗

∗Department of Electrical and Computer Engineering, Rutgers University, Piscataway, NJ 08854† Intersil Corporation, 440 U.S. Hwy 22 E., Suite 100, Bridgewater, NJ 08807

‡ Department of Biomedical Engineering, Rutgers University, Piscataway, NJ 08854

1 Abstract— A low-dropout regulator (LDO) for the electri-cal stimulation of ionic electroactive polymers (iEAPs) usedin subcutaneous muscle prosthesis is presented. The specialrequirement of the application and the characteristics of iEAPsimpose several design challenges for the stimulator. In this paper,these challenges are discussed and solutions are provided. Theproposed LDO, designed and simulated in IBM 0.13-µm CMOStechnology, uses external-capacitor-less architecture to enable afully on-chip solution for providing stable stimulation across awide load range, as required by the properties of iEAPs. TheLDO also offers precise line and load regulations, as well asimproved power supply rejection (PSR) to suppress the supplynoise when the LDO is powered up through wireless powertransfer (WPT) links. Simulation results are provided suggestingthat the proposed LDO can be used as a stable and precisestimulation source for controlling the movement of iEAPs witha potential application in muscle prostheses.

I. INTRODUCTION

Close to two million people in the United States currentlylive with limb loss caused by vascular disease, trauma orcancer [1]. Functional loss and impairment of skeletal musclecould also occur as a result of aging [2], stroke [3], and otherdiseases including amyotrophic lateral sclerosis [4], negativelyimpacting patient’s quality of life. Several approaches forthe repair and regeneration of skeletal muscle have beensought in the field of tissue engineering [5]. Existing solutionshowever, display contractility only “after” new muscle hasbeen regenerated, i.e., there will be a waiting period untilresorting movement can be initiated.

To address the problem of immediate movement restora-tion upon injury, muscle prosthesis that can become activefollowing implantation are needed. A subcutaneous module,combining biomaterials such as ionic electroactive polymers(iEAPs) [6], [7] with integrated circuits [8], [9], to facilitatecontrollable electrical and mechanical stimulations, could bea promising solution. In addition to creating movement, thismodule will also aid in speeding the formation of tissue regen-eration process by enhancing cellular proliferation alignmentvia stimulation upon implantation.

The degree of the movement in the iEAP-based subcuta-neous muscle prosthesis will be dependent on the level of theelectrical stimulation that is received by iEAPs. The electrical

This work is supported in part by NSF under grant 1408202.

Fig. 1. (a) Block diagram of an iEAP-based subcutaneous muscle prosthesis.A conceptual representation for the movement of iEAPs, when placed insidean electric field, is also shown (after [11]) (b) implantable microchip (top-view) without the encapsulation layer (c) equivalent electrical model of iEAPs(after [12]).

stimulation can be provided by an implanted voltage regulator,integrated with iEAPs and powered-up via a wireless powertransfer (WPT) link (see Fig. 1-a, b). Commonly used archi-tectures for implementing voltage regulators are low-dropout(LDO) [10] and inductor-based switching regulators. Due tosmall area requirement of the implant, LDO architecture willbe considered. An LDO is designed to provide a low noiseand highly precise DC voltage to the load [10]. For thesubcutaneous module, however, as it will be discussed inthis paper, there will be several added design challenges (e.gvariation in load and power supply). Here, we will discussthese challenges, and provide design solutions.

This paper is organized as follows: in Section II, the elec-trical modeling of iEAPs are presented. In Section III, designchallenges for LDOs are discussed and the proposed circuitarchitecture is described. Simulation results are presented inSection IV, and conclusions are given in Section V.

II. ELECTRICAL MODELING OF IEAPS

Fig. 1-a shows the conceptual representation of how iEAPsactuate in the presence of electric field [6]. The actuation iscaused by ion displacement inside the polymer, when placedinside an electric field. As the cathode side becomes morealkaline and the anode side becomes more acidic, ions diffusethrough the polymer gel, resulting in bending motion of thefilm. This bending action of iEAPs matches the force of

biological muscles [11].The electrical models for the transient and steady state for

unit length iEAPs are illustrated in Fig. 1-c [12]. In the tran-sient model, resistors Ra and Rb denote surface resistances,resistor Rx represents the resistance of the polymer gel layer,and resistor Rc and capacitor Cc model the exponential stepresponse characteristic observed in the experiments. In thesteady state model, each unit length can be modeled withan equivalent resistor. Since in the proposed module, iEAPswill be stimulated via a constant electric field, the steady statemodel shown in Fig. 1-c will be used for modeling iEAPs.

The LDO will be designed to stimulate iEAPs of differentlengths. Therefore, it is necessary to determine the minimumand maximum load resistances that will be driven by the LDO.The maximum (minimum) unit conductance Gmax(Gmin) hasbeen estimated to be 0.046 S/cm (0.022 S/cm) [6]. If thelength of iEAPs varies from 1 cm (Lmin) to 4 cm (Lmax)respectively, the load resistance that the LDO is required todrive will be between Rmin and Rmax as derived below

Rmin =1

GmaxLmax= 5.44 Ω, Rmax =

1

GminLmin= 45.44 Ω.

(1)The [Rmin−Rmax] represents the load resistance range for theLDO, with Rmin corresponding to the heavier load condition(larger current).

III. PROPOSED LOW-DROPOUT REGULATOR

The proposed LDO, powering-up via a WPT link, is ex-pected to provide a stable and reliable voltage for actuatingiEAPs. In this section, we will discuss the design challengesof the LDO for this specific application and present solutions.

A. Design challenges of the LDOThe design challenges for the LDO are imposed by the

requirements of the application, properties of iEAPs, and thenature of WPT links.

Area Limitation: The LDO will be integrated with the iEAPsand implanted inside the body. As a result, the circuit shouldoccupy a very small space. Therefore, regulator architecturesthat require inductors will not be appropriate for this appli-cation. Since LDOs do not require inductors, they can beutilized in this application, to meet the area requirement.LDOs generally require µF level external capacitors at theiroutputs, where the capacitance value depends on the switchingcharacteristics of the load. For the proposed application, dueto intrinsic non-switching property of iEAPs, as far as thestability of the LDO is not compromised, the external capacitorcan be removed to save area. However, the elimination ofthe output capacitor makes maintaining stability a challengingtask, when using conventional LDO structures. The reason isbecause in conventional LDOs, the only dominant pole in theloop gain transfer function is the reciprocal of the time con-stant formed by the output capacitance, the equivalent seriesresistance (ESR) of the output capacitor, and the equivalentload resistance [10]. Without the output capacitors, the LDOwill suffer from the instability problem. Therefore, efforts mustbe made to address the tradeoff between area limitation andstability.

Fig. 2. Schematic for the proposed external-capacitor-less LDO with PSRenhancer.

Load variation: The range of load variation imposed by theelectrical characteristics of iEAPs is unique to this applicationand places design challenges for the LDO. With a supplyvoltage of 2.5 V , output voltage of 1.5 V , and using (1),the load range is expected to vary between 33 mA to 276mA. As discussed before, the dominant pole will depend onthe equivalent load resistance. As a result, for wide load rangeapplications, the LDOs’ stability could be compromised. Thus,the load dependency of the dominant pole in the loop gaintransfer function must be suppressed or eliminated to meetwide load variation conditions.

Line variation: The LDO is powered via a WPT link, whichcan introduce variations in LDO’s power supply. Such varia-tions could occur by for example the misalignment betweenthe primary and secondary coil in the inductive link [13].Additionally, due to the switching nature of WPT, AC ripple(which depending on the switching frequency, could be inthe range of 100 kHz to several MHz) could appear inthe circuits power line [13]. Therefore, the LDO, includingits reference circuit, will have to exhibit strong power supplyrejection in DC and mid-frequency range, to provide a verystable voltage regardless of variations in the supply rail.B. Proposed LDO

To meet the design challenges discussed above, an external-capacitor-less LDO is designed (see Fig. 2), to create theelectric field required for stimulating iEAPs. The design ismotivated by the architecture proposed in [14]. The circuitconsists of three major blocks: the power supply rejection(PSR) enhancer, an error amplifier consisting of two stages,and the power block. The PSR enhancer block is used toimprove the PSR in mid-frequency range (100 kHz to severalMHz) [15]. In this structure, resistors RFF1 and RFF2 forma resistor divider to sample the AC noise from the power line.This sampled signal goes through a bandpass filter, constructedby one operational amplifier, two feedback resistors (resistorsRBPF1 and RBPF2), and capacitor CBPF1. The output of thebandpass filter then drives the transistor MFFP1 to generatea current which contains the AC component of the powerline. The transistor MFFP5 is driven by the feedback signal

Fig. 3. Schematic of the voltage reference circuit with PSR enhancer.

VREPLICA from the second stage of the error amplifier, toregulate the PSR enhancer loop. The current going throughtransistor MFFP5 and MFFP1 is then mirrored (via transistorsMFFN1, MFFN2, MFFP3 and MFFP4) and injected into thesecond stage of the error amplifier. Two input buffer circuits(consisting of transistors MBUFN1, MBUFN2, MBUFP1 andMBUFP2) are employed to provide the appropriate commonmode DC input level and better PSR at low frequencies [15].A telescopic configuration consisting of transistors MIN1,MIN2, MP1-MP3 and MN1-MN4 form the main body ofthis block. The output of this stage is also connected to VOUT

of LDO via a Miller capacitor, Cm. In the third block, thesecond stage of the error amplifier, transistors MN5, MP4 andMP5 form a non-inverting gain stage. Transistor MN6 and thecapacitor Ccf connect this stage to the second block in orderto damp the non-dominant poles (quality factor reduction)[16]. The last block forms the power stage. In this stage, thepass transistor, MPASS , operates as a variable resistor to keepthe output level relatively constant over the entire load range.Resistors RFB1 and RFB2 build the sampling network at theLDO output, and a 100 pF parasitic capacitor Clp is used tomodel the capacitive properties of bond pads.

The schematic of the reference circuit [17] used in theproposed LDO is shown in Fig. 3. The PSR enhancer [18],an operational amplifier, proportional to absolute temperature(PTAT) current and VREF generators form the four blocksof the circuit. Compared to CMOS-based bandgap referencesthat utilize parasitic BJTs, this reference circuit offers severaladvantages, including reliability, low power consumption andstable line regulation. The introduction of PSR enhancer willadditionally improve the power supply rejection ratio of thereference circuit, thereby, minimizing its impact on the per-formance of LDO. In Fig. 3, the PSR enhancer stage samplesthe AC component from the power line VREC , via transistorsMRFFN1 and MRFFN2. The output of the PSR enhancer isthen used to drive the transistors in PTAT current and VREF

generators stages. The operational amplifier uses a foldedcascode configuration (MRP1, MRP+, MRP−, MRP2-MRP5

and MRN1-MRN4), thereby, providing large-enough DC gainto maintain equal voltage levels at nodes “A” and “B” in the

PTAT current generator circuit. The PTAT current generatorcircuit consists of cascode current mirror pairs (MRP6-MRP9).The PTAT Four subthreshold-operating transistors MRN5-MRN8 are used to generate the PTAT voltage across resistorRR1. The generated PTAT current is then mirrored to theVREF generator block through transistors MRP10-MRP15.Transistors MRN9-MRN13) operate in weak inversion. Theoutput voltage of this reference circuit, VREF , is generatedfrom the gate-source voltages of transistors MRN9-MRN13.

In what follows, we will describe how the proposed designmeets the design requirements discussed in Section III-A.

Area Limitation: As discussed, in this iEAP application,a tradeoff exists between chip area and stability. Therefore,the external-capacitor-less LDO architecture [19] is selectedto address this challenge. In this type of architecture, dueto non-existence of output capacitors, no intrinsic dominantpole exists in low frequency range. However, in mid-frequencyrange, two poles can be split via Miller compensation. One willbe placed within the low frequency range and could work asthe dominant pole in the loop, while the other will be pushed tofrequencies well above the loop bandwidth. This pole splittingtechnique successfully solves the stability problem when theoutput capacitor is not present. As a result, it will be a suitabletechnique to address the area-stability tradeoff.

Load variation: The LDO is required to generate a stableand precise voltage for all load conditions. Since the external-capacitor-less structure is used, to ensure stability against loadvariation and to keep a relatively constant bandwidth and phasemargin across the entire load range, the dominant pole can bedesigned to be independent of the load, and the load-dependentnon-dominant poles will be kept at frequencies well above theapplication bandwidth. Additionally, the error amplifier usedin LDO should provide a large low frequency gain acrossthe entire load range. To achieve a large gain, the two-stagestructure has been used.

Line variation: To enhance line regulation (low frequencyPSR) of the LDO, cascode structures (consisting of transistorsMP2, MP3, MN1 and MN2) [10] have been incorporatedin the reference circuit and the main stage of the LDO.Additionally, two different PSR enhancers are included in thereference circuit and the main stage of the LDO, to addressthe mid-frequency (100 kHz to several MHz) suppression ofthe noise coming from the supply line.

IV. SIMULATION RESULTS

The proposed LDO was designed and simulated in IBM0.13-µm CMOS technology. The circuit was designed tooperate with a power supply of 2.5 V . Fig. 4-a shows thesimulation results of the loop gain (magnitude and phase) forfour load conditions (no load, light load (10 mA), mediumload (50 mA) and full load (300 mA)). It can be seen thatboth unity gain frequency and phase margin stay relatively thesame (500 kHz and 70) for all load conditions, ensuring theLDO remains stable across all load ranges. Fig. 4-b showsthe simulation results for the PSR of the LDO (for three loadconditions, with and without PSR enhancer) and the reference

Fig. 4. Simulation results at VREC=2.5 V for (a) the loop gain at fourdifferent load conditions (b) the power supply rejection (up to 3 MHz) ofreference circuit and LDO at three load conditions, with and without PSRenhancer.

circuit. The circuit demonstrates good suppression of the mid-frequency (100 kHz to several MHz) noise. The worst casePSR is found to be -40 dB at 1 MHz. Simulation resultsfor line and load regulations are shown in Figs. 5-a and 5-b, respectively. In Fig. 5-a, the percentage of output voltagevariation when the power line varies from 1.8 V to 3.3 V isplotted. It can be seen that the error is within -0.45 % and +0.1% for all three load conditions. Note that for this simulation,we have incorporated the variation in the reference voltagevalue that occurs as a consequence of changes in the supplyvoltage. Fig. 5-b shows the percentage variation in the outputvoltage as a function of the load, for three supply voltagevalues. The results indicate that the peak to peak variationstays within -0.06 % and +0.08 % over the entire load rangewith different line voltages. Both line and load regulationresults confirm the stability of the proposed LDO, indicatingthat it will be a good candidate for actuating iEAPs in muscleprostheses.

The performance of the proposed LDO and existingexternal-capacitor-less LDO designs have been compared inTable I. The proposed LDO demonstrates a comparable PSRat 1 MHz, and provides superior load regulation across a wideload range.

TABLE IPERFORMANCE COMPARISON

Ref. [14] [20] [21] This workYear 2012 2014 2014 2015

Technology (µm) 0.13 0.18 0.065 0.13Type (Meas./Sim.) Meas. Meas. Sim. Sim.Max load (mA) 50 50 50 300VOUT (V ) 1 1.6 1 1.5COUT (pF ) 20 100 100 100

Load reg. (mV/mA) N/A 0.14 0.03 0.001163PSR at 1 MHz (dB) -40 -70 -48 -40

V. CONCLUSION

An external-capacitor-less LDO with PSR enhancer circuitfor providing subcutaneous electrical stimulation to iEAPs inmuscle prosthesis applications was presented in this paper. Theproposed LDO provides a 1.5 V stable output voltage to stim-ulate iEAPs of different lengths. Simulation results showedgood stability, superior line and load regulations over 10 to 300mA load range. The results suggests that the proposed LDOcan be used as an effective solution for electrical stimulationof iEAPs in subcutaneous muscle prostheses.

Fig. 5. Simulation results for (a) Line regulation (b) Load regulation.

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