A High-Voltage DC–DC Converter With Vin div by 3—Voltage Stress on the Primary Switches

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2124 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007

A High-Voltage DC–DC Converter WithVin/3—Voltage Stress on the Primary SwitchesTing-Ting Song, Henry Shu-Hung Chung , Senior Member, IEEE , and Adrian Ioinovici , Fellow, IEEE

Abstract—A high-voltage dc-dc converter with low voltage stresson the power switches and high output current capacity is pre-sented. This converter exhibits three distinct features. First, thevoltage stress on the primary switches is only one-third of the inputvoltage,so that switchesof lowvoltage rating and thus of lowon-re-sistance canbe used. This leads to reduced conduction loss. Second,all the switches are soft-switched, so that the switching loss can bereduced. Third, the rectifier is a current tripler, so that the outputcurrent capacity, and thus the power handling capacity of the con-verter are increased. A 5.1-kW, 1000-V/48-V dc-dc converter pro-totype has been built and tested. Experimental results are favor-ably compared with theoretical predictions.

Index Terms—DC–DC conversion, high-voltage converter, highload current converter.

I. INTRODUCTION

THE energy supplied to the low-voltage equipment insystems powered by a high dc voltage, such as the railway

system, typically goes through multiple power conversion

stages. For example, the electric power in the railway system is

transmitted to the trains through high dc voltage (e.g., 1500 V)

overhead lines and is inverted into a 3-phase ac voltage (e.g.,440 V, 60 Hz). The ac voltage is further transformed and recti-

fied into a dc voltage (e.g., 110 V) for charging up the backupbatteries and powering various control units on the train. It

is energy-inefficient to use a low-frequency ac voltage as themeans to perform the dc-dc conversion from the high voltage

to low voltage (i.e., from 1500 to 110 V). An efficient approach

is to perform the power conversion process through a high-fre-quency ac voltage. As high-voltage switching devices have

high on-resistance, available dc-dc converters operating at highinput voltage generally dissipate a substantial amount of energy

in these elements. The on-resistance of high-voltage

devices increases with their voltage-rating (BV) according to anonlinear relationship: , where . This

leads power electronics designers to explore new convertercircuits that could reduce the device voltage requirement, so

that switches of low on-resistance could be used.

Manuscript received August 7, 2006; revised February 13, 2007. This work was supported by a grant from the Research Grants Council of the Hong KongSpecial Administrative Region, China (Project No.: CityU 112406). This paperwas previously presented at the IEEE Power Electronics Specialists Conference2006 and at the Applied Power Electronics Conference and Exposition 2007.Recommended for publication by Associate Editor F. Z. Peng.

T.-T. Song and H. S.-H. Chung are with the Department of Electronic Engi-neering, City University of Hong Kong, Kowloon Tong, Kowloon, Hong Kong(e-mail: [email protected]).

A. Ioinovici is with the Department of Electrical and Electronics Engineering,Holon Institute of Technology (HIT), Holon 58102, Israel.

Digital Object Identifier 10.1109/TPEL.2007.909227

A typical dc-dc converter consists of two power conversion

stages. In the first stage, the dc input voltage is transformed into

a high-frequency (HF) ac voltage which is applied across the pri-

mary of a HF transformer. The transformer is used for electrical

isolation and providing an HF ac voltage across its secondary as

determined by the turns ratio . In the second stage, consisting

of a rectifier, output filter and snubber, the output (load) voltage

is obtained as a regulated dc voltage whose value is determined

by the values of and of the duty cycle.

In a conventional full-bridge (FB) converter, the four pri-

mary-side switches sustain the input voltage when they are off.In high-voltage applications, each switch can be realized by

connecting two switches in series. Thus, each switch sustains

only one-half of the input voltage in voltage-balanced networks.

However, the equipment cost has to include that of the eight

switches. This approach does not work well as far as dynamic

balancing is concerned, since no switches are identical.

In order to improve the efficiency in systems with a high

input voltage, a three-level topology was proposed. Based on the

concept of the neutral-point-clamped inverters [1], a three-level

(TL) converter has been introduced [2]. By using two dc-link

capacitors to split the input voltage, operating the outer two

and inner two switches in anti-phase, and using an additional“flying” capacitor and two extra diodes to clamp the voltage on

the transistors in the off-state, the voltage stress on each switch

results in only one-half of the input voltage. As a consequence,

switches of low on-resistance can be used, resulting in much

lower conduction losses.

The dominant stream of research in FB and TL converters

has had the purpose of developing soft-switching schemes

to reduce the switching losses of the switches for further

increasing the conversion efficiency. A phase-shift control

strategy allows the primary-side switches to turn on/off with

zero-voltage-switching (ZVS) [3]–[6]. Different solutions

have been proposed to extend the ZVS condition to light

load: [7]–[16] for FB converters and [17]–[21] for TL con-verters. Another possibility of achieving soft-switching is

to operate two of the power switches with ZVS and the

other two with zero-current-switching (ZCS). To realize

ZCS, various solutions have been proposed for keeping the

primary current at zero during the freewheeling stage and

for clamping the rectifier voltage at an acceptable level. One

recent solution was to add a few elements on the primary

side, when a regenerative passive snubber was inserted in

the secondary side [22]–[25]. Another configuration of the

primary-side switches leading to also a voltage stress of a half

of the input voltage across the power transistors in off-state

was proposed in [26].

0885-8993/$25.00 © 2007 IEEE



SONG et al.: A HIGH-VOLTAGE DC–DC CONVERTER WITH VIN/3—VOLTAGE STRESS ON THE PRIMARY SWITCHES 2125

Fig. 1. Proposed converter with Vi/3 voltage stress on primary switches.

As the load current requirement continuously goes up, diodes

of high current rating and high forward voltage drop have to be

used in the secondary side. This results in an increase in the

conduction losses in the rectifier stage. This poses a significant

challenge for the high-voltage high-current dc-dc converters. In

order to increase the load current capability, current-doubler rec-tifiers have been used [27]. In [28], a current tripler that can in-

crease three times the output current capability was proposed.

However, the primary-side stage in [28] is a three-phase FB

structure, in which the voltage stress on the power switches is

equal to the input voltage. As a result, even if the converter in

[28] is suitable for high-power applications, it cannot be used

for high input voltage applications.

In order to match the big advantage of the tripler recti fier of

[28] with the need of using the converter for a dc-dc conversion

of a very high input voltage (as 1500 V), this paper presents an

innovative structure. The power primary-side switches are ar-

ranged in three switch pairs. The mid-points of the switch pairs

are connected to the primary side of a 3-phase HF transformer.The proposed converter achieves the following goals.

1) The voltage stress on each primary-side switch is only one-

third of the input voltage.

2) All the switches are turned on and off with ZVS.

3) The output rectifier is a current tripler [28] that has a high

output current capability.

The proposed converter is described in Section II, where its

steady-state cyclically switching operation is presented. The dc

analysis is performed in Section III, where the formula of the

effective duty cycle is also derived. The small-signal transfer

functions are derived in Section IV. Based on the design pro-

cedure presented in Section V, a 5.1-kW, 1000-V/48-V dc-dc

converter prototype has been built and tested. The experimentalresults confirmed the theoretical predictions (Section VI).

II. PRINCIPLES OF OPERATIONS

A. Circuit Structure

The proposed converter is shown in Fig. 1. Three input dc-link

capacitors , and areconnected across the input voltage

. They have the same capacitances, such that, due to the sym-metry of the circuit, they split equally the line voltage. The

voltage on each one is . Three switch pairs, SP1, SP2, and

SP3, are connected across , and , respectively. Each

switch pair is formed by two switches, which are operated in

anti-phase. When in SP1 is on, the voltage stress on ,

is . When is on, the voltage stress on , is .

The operation is similar for the switch pairs SP2 and SP3. Thus,

the voltage stress on all switches in off-state is only one-third

of the input voltage. No clamping diodes, as in TL converters,

are needed for this purpose. The switching patterns applied to

the switch pairs have a phase difference of 120 . The mid-pints

of the switch pairs are connected to the primary of a delta-con-nected transformer through the dc blocking capacitors and

, which are of equal large capacitance. These capacitors take

over the role of the “flying” capacitor in TL converters. As will

be explained in Section III, the steady-state dc voltage of these

capacitors is . The voltages produced at the nodes X, Y, and

Z have phase differences of 120 . The turns ratio of the trans-

former is .

The built-in diode-capacitor pairs, to in

the switch pairs, are used to provide ZVS for all primary-side

switches, in order to reduce the switching losses. A dead time is

added between the gate signals applied to the switches in each

switch pair.

The secondary-side circuit is a three-phase rectifier, namelya “current tripler” [28]. As the output current is shared by three




identical parallel diode-inductor branches: ,

and , the tripler has several

advantages over the mainstream rectifiers having one output in-

ductor and two or four diodes. Firstly, each output inductor car-

ries only one third of the load current . Secondly, the current

stress in each diode is reduced by one-third. Theoretically, it will

be a lower rms current through each device, resulting in lowersecondary conduction losses [28].

As the output voltage is determined by the voltages applied

to the transformer primary, it can be adjusted by controlling the

duty cycle of the switches in the switch pairs.

B. Steady-State Switching Modes

The converter goes cyclically through 15 modes in one

switching cycle. Due to the switching operation symmetry, it is

suf ficient to analyze the first five modes which cover a period

of . At any time, three out of the six primary switches (i.e.,

– ) are switched on. The timing diagram of one-third of

the switching cycle is given in Fig. 2. Fig. 3 shows the modes

of operation. Fig. 4 shows the timing diagram of the wholeswitching cycle. The voltage in the figure shows the voltage

between nodes and . As the durations of and

are equal, the average value of is . As the steady-state

average voltage across each transformer winding is zero (i.e.,

), the average voltage of is

. Similarly, by considering the nodes and , the average

voltage of is also . Detailed derivations will be given

in Section III-A.

During the operation in the first and are turned

on, and and are turned off.

1) Mode 0 [Before [Fig. 3(a)]: , and are turned

on. The converter is in the freewheeling stage. The voltages

across the transformer’s windings are zero. The currents in

the primary and secondary windings keep constant. The three

output inductors share . and are on, in order to provide

the constant current in and , respectively. That is

(1)

The above formulas will be proven when the transition to a

freewheeling mode (i.e., the last mode in each ) will be

explained.

By using Kirchhoff ’s Current Law (KCL) at nodes , and

, respectively

(2)

Thus, the rectifier diode currents are

(3)

Fig. 2. Timing diagram of one-third of a switching cycle.

On the primary side of the transformer

(4)

(5)




Fig. 3. Modes of operation. (a) Mode 0 [before t ]. (b) Mode 1 [ t ; t ] . (c) Mode 2 [ t ; t ] . (d) Mode 3 [ t ; t ] . (e) Mode 4 [ t ; t ] . (f) Mode 5 [ t ; t ] .

By applying the Kirchhoff ’s Voltage Law (KVL)

(6)

(7)

2) Mode 1 [Fig. 3(b)]: At turns off with ZVS

because o f the p resence o f . T he c urrent begins

to charge and discharge . As typically for a transition

from a freewheeling stage towards an energy transfer stage (pas-

sive topology to active topology transition), only the energy in

the transformer leakage inductances is available for achieving

such a function. As , the winding YZ can

be considered as a short-circuit, and thus its leakage inductance

does not participate in providing energy for the above operation.

As andincreases from zero

to a positive value and goes from zero to a negative value.

Thus

(8)

As decreases and maintains a constant current of

has to turn on in order to provide the difference of . With

, by considering the loop on the primary side,

one can find

(9)

(10)

(11)




(12)

(13)

(14)

where .

As , and are turned on, the voltages on the sec-

ondary windings are all zero

(15)

The currents flowing through the primary windings are

(16)

(17)

(18)

(19)

(20)

(21)

The currents flowing through the secondary windings are

(22)

(23)

(24)

The currents through , and result in

(25)

(26)

(27)

Mode 1 ends when is completely discharged and is

charged up to . That is

(28)

giving the duration of this stage

(29)

The values of the main voltages and currents at result in

(30)

(31)

(32)

(33)

(34)

(35)

(36)

(37)

(38)

(39)

(40)

(41)

3) Mode 2 [Fig. 3(c)]: At , as starts

conducting and is turned on with ZVS (as the two stages,the first one with conducting, and the second one with




conducting, are the same from the point of view of the equations

governing their operation, they are considered here as the same

topology). According to Fig. 3(c)

(42)

, and are still turned on because the increasing pri-

mary currents are still not suf ficient to provide the load current.

The voltages across the secondary windings are zero

(43)

As typically found in FB and TL converters with ZVS, this phe-

nomenon causes a loss of the secondary (effective) duty-cycle.

Even if the primary circuit is in the “on” topology, the secondary

one is still in the freewheeling state

(44)

(45)

(46)

(47)

The reflected currents on the secondary side are

(48)

(49)

(50)

(51)

Mode 2 ends when the primary current reaches the reflected

secondary current , and thus and

. A new energy transfer stage begins.

From (49), the loss oftheeffective dutycycle results

in

(52)

Based on (44)–(48)

(53)

(54)

(55)

(56)

4) Mode 3 [Fig. 3(d)]: This is the first energy transfer

stage in the cycle. As shown in Fig. 3(d)

(57)

(58)

The currents in the primary and secondary windings are almost

constant

(59)

(60)

(61)

(62)

5) Mode 4 [Fig. 3(e)]: According to the PWM action,

the “on” stage is ended at . At is turned

off with ZVS due to the presence of . divides into two

currents for charging from zero and discharging from

.

In this mode, the energy of the output inductor, which is re-

flected to the primary side, is suf ficient for assuring ZVS of

the switches, even at light load. This is typical for all FB and

TL converters at the transition from a transfer energy (“active”)

stage to a freewheeling one (“passive” stage). By using simple

circuit theory applied to Fig. 3(e), one gets

(63)

so that

(64)

(65)




The currents remain almost unchanged

(66)

(67)

(68)

(69)

Mode 4 ends when is charged up to [i.e.,

and is completely discharged [i.e., .

Thus, at

(70)

The converter enters into the freewheeling stage. The currents in

the transformers windings are kept constant during the transitiondue to the leakage inductances of the windings.

6) Mode 5 [Fig. 3(f)]: As at

starts conducting and, soon after this instant, turns on with

ZVS. As these two topologies are similar from the point of view

of the equations governing their operation, they will be consid-

ered here as the same mode. As , and are turned-on,

(71)

(72)

That is, the converter operates in the first freewheeling stage of

a switching cycle. The currents in the primary windings remain

constant so that

(73)

(74)

Thus, on the secondary side

(75)

(76)

(77)

and are conducting in order to provide the constant cur-

rent in and , respectively.

For the next two intervals, the converter will operate in

a similar way, the transition taking place in the switch pair SP2,

and then in the switch pair SP3, arriving in the last Mode at the

diagram described in Mode 0.

The main converter waveforms for a full steady-state cycleare given in Fig. 4.

Fig. 4. Timing diagram of the whole switching cycle.

III. STEADY-STATE CHARACTERISTICS

A. Steady-State Voltages across Capacitors , and

The converter can be seen as an equivalent structure of three

isolated identical buck converter modules with their inputs con-

nected in series and their outputs connected in parallel, oper-

ating with the same duty cycle in a switching period. Thus, the

symmetry in the component values and in switch pairs operation

assures the equal voltage distribution among the three input ca-

pacitors. The capacitors have large values, such that their volt-

ages can be considered as constant during a switching cycle. The

situation is the same as in three-level converters where the input

voltage is halved equally by the two input capacitors.

B. Steady-State Voltages across Capacitors and

The steady-state average voltages across the primary wind-

ings over are zero

(78)

where , and are the average voltages across

windings , and , respectively.

Thus, the capacitor voltages, and can be obtained

by averaging the voltages between the nodes and , and

the nodes and , respectively. and can also be ex-

pressed as

(79)(80)




Thus

(81)

(82)

According to the switching diagram (Fig. 4), the switches po-

sitions in each interval are as follows.

1) Interval I : and are turned on, resulting in

for DT

(except for the commutation time), for

(except for the commutation time). increases in a

sinusoidal manner from zero to in the first ZVS transition

time and decreases from to 0 in the second ZVS

transition time .

2) Interval II : and are turned on, resulting in

for

(except for the commutation time), for(except for the commutation time). decreases

from to zero, and increases from zero to (both

in a sinusoidal manner) during the first ZVS transition stage of

interval I increases from 0 to , and

decreases from to zero for the second ZVS transition time

.

3) Interval III : and are turned-on, resulting

in = 0, for

(except the commutation time), for

(except the commutation time), decreases from to

zero in a sinusoidal manner for the first ZVS transition time in

Interval III ), and increases from 0 to for thesecond ZVS transition time .

As the parasitic capacitances of all switches - are equal

, the transition of each upper switch and, re-

spectively, of each lower switch are governed by

the same equations, so that the transition times for the upper,

and respectively lower switches, are equal. That is,

. As

a result, by solving the integrals in (81) and (82), one gets:

.

C. DC Input-to-Output Voltage Ratio and Effective Duty Cycle

The duty cycle of the converter is defined as the conductiontime of the upper switch in each switch pair with respective to

one-third of the switching period. Based on the energy balance

between the input and output energy in a steady state switching

cycle, the dc input-to-output voltage ratio can be shown to be

(83)

According to (29) and (52)

(84)

and (83) becomes

(85)

If the short ZVS commutation times are neglected, (85) gives

(86)

The secondary (effective) duty-ratio can be expressed as

(87)

and thus (86) can be expressed

(88)

D. Elements Design for ZVS

The load range is determined by the minimum load current

that can ensure the zero-voltage switching of all switches. As

the commutation from a freewheeling stage to an active energy

transfer stage is more dif ficult (only the energy is available

in this case), the design of is made accordingly: the energy

stored in the leakage inductances involved in the commutation

process has to be higher than the energy in the equivalent ca-

pacitance of the capacitors of the switches involved in the

resonance path (i.e., 2 )

(89)

i.e., in order to assure ZVS for a “passive” to “active” transition

from a minimum load of , the minimum has to be

(90)

IV. AC SMALL-SIGNAL CHARACTERISTICS

For the sake of simplicity in the analysis, all components are

assumed to be ideal and . Since the

ZVS commutation durations of the switch pairs are very short,

as compared with the switching period, they are neglected in the

analysis. Each one of the main switching modes (energy transfer

or freewheeling) in a switching cycle are given in Fig. 5 and

can be described by an equation of the form

(91)




Fig. 5. Equivalent circuits of the main switching modes. (a) Energy transfer of the Interval I [ t ; t ] . (b) Energy transfer of the Interval II [ t ; t ] . (c) Energytransfer of the Interval III

[ t ; t ]

. (d) Freewheeling stage of Intervals I, II,and III.

where – is the mode of operation

The small-signal characteristics of the converter are studied

by introducing ac perturbations into , and

(92)

(93)

(94)

(95)

(96)

where , and are the steady-state values of

, and , respectively.

By using (87) and substituting (92)–(96) into (91), we have

(97)

where and .

A. Control-to-Output Transfer Function

By applying the state-space averaging method

(98)

(99)

where and are the averaged state vector and input vector,

respectively

By introducing small-signal perturbations into (98) and (99),

it can be shown that

(100)

(101)

where

By imposing and using (97)

(102)

Since

(103)

By substituting (102)–(103) into (100), it can be shown that

(104)




TABLE I

COMPONENT VALUES USED IN THE PROTOTYPE

Thus, by using (101) and (104), it can be shown that the con-

trol-to-output transfer function is equal to

(105)

B. Input-to-Output Transfer Function

By imposing into (97)

(106)

By substituting (106) into (100), it can be shown that

(107)

Fig. 6. XY-plot of the switch voltage ( v ) and the gate signal ( v ) in SP3

at the full load condition. (a) S .(b) S . [x-axis ( v ) : 100 V/div, y-axis ( v ) :5 V/div].

Thus, the input-to-output transfer function is determined

by using (107) and (101)

(108)

V. SIMPLIFIED DESIGN PROCEDURES

A simplified design procedure is given as follows.

1) The value of is determined by using (88)

(109)

where is the designed minimum effective duty

cycle.

2) The value of is determined by using (90).

3) The selection of the switches is based on the considera-

tions: a) the voltage stress on the switches is and b)the current stress is .




Fig. 7. XY-plot of the switch voltage ( v ) and the gate signal ( v ) in SP3at 62% load condition. (a)

S

. (b)S

. [x-axis( v )

: 100 V/div, y-axis( v )

:5 V/div].

4) The minimum values of the output inductor and capac-

itor are determined by considering the current ripple

through and the voltage ripple across . It

can be shown that

(110)

(111)

VI. EXPERIMENTAL RESULTS

A 1000-V/48-V dc-dc converter prototype has been built. The

designed output power is from 3.2 kW (62% load) to 5.1 kW

(100% load). Based on the design procedures in Section V, thecomponent values are given in Table I. From (109), for

V and V, and considering , it

results . A transformer with 6:5 windings turns has

been chosen. By choosing A and nF and

using step 2) in Section V, the results give H.

H is chosen in the prototype.

Figs. 6 and 7 show the XY plot of the switch voltage and the

gate signal of and in SP3 at the full load and 62% load

conditions, respectively. They are all in L-shape. This implies

that the switch voltage has become zero before dictating the

“ON” signal to the gate, and remains zero after dictating the

“OFF” signal to the gate. Thus, the ZVS commutation of theswitches and can be clearly noticed.

Fig. 8. Enlarged waveforms of i , and v , and gate signals to S and S v :(100 V/div), i (20 A/div), v ; v : (10 V/div) (Timebase: 1 s/div). (a)Full load. (b) 62% load.

The enlarged waveforms of , and , and gate signals to

and at the full load and 62% load are shown in Fig. 8.

Comparing Fig. 8(a) and (b), when the load current is reduced

(i.e., from full load to 62% load), has moved close to zero be-

fore is increased to one-third of the supply voltage, giving

the limit of achieving ZVS. As discussed in Section III-C, the

ZVS range can be adjusted by changing the value of . It

should be noted that parasitic ringing between the leakage in-

ductance and the diodes junction capacitances, which appears

at the turn-off of a rectifier diode, can be tackled with an appro-

priate snubber, such as the one proposed in [20].

At the full-load condition, Fig. 9 shows the theoretical andexperimental small-signal characteristics of the converter and

Fig. 10 shows the voltage and current waveforms (i.e., and

) of the output rectifier, and the voltages across the trans-

former winding XY (i.e., ). The waveforms are similar to

the theoretical waveforms shown in Fig. 2.

The ef ficiencies of the prototype under different load condi-

tions have been measured and are given in Fig. 11. The losses in

the power components are shown in Table II. The major losses

are in the passive components, including the capacitors, trans-

former, and the rectifier, while the losses in the switches con-

stitute only about 3.24% of the input power. The experimental

results have demonstrated the objectives of the proposed struc-ture that the voltage stress on the switches is only one-third of






TABLE IILOSSES IN THE POWER COMPONENTS

voltage stress on the power switches is reduced to only one-third

of the input voltage, allowing thus for the use of transistors

of low-voltage rating and low on-state resistance. The conduc-

tion losses are considerable reduced. This novel primary struc-

ture matches the output current tripler, which allows for an in-

creasing in the load and power handling capacity. The outputvoltage is controlled by adjusting the duty cycle of the switches

in each switch pair. All the switches are turned-on/off with soft-

switching, allowing for minimal switching losses. The operating

principles of the converter have been demonstrated and studied

on a 5.1-kW, 1000-V/48-V prototype. The measurements of the

ef ficiency under different loads proved the expected advantages

of the new converter.

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Ting-Ting Song received the B.S. and M.S. degreesfrom the Department of Electrical Engineering,Sichuan University, Chengdu, China, in 1999 and

2002, respectively. She is currently pursuing thePh.D. degree from the Department of ElectronicEngineering, City University of Hong Kong.

She was a Research Assistant with the Departmentof Electrical Engineering, Sichuan University, from

2002 to 2004. Her research interests include dc/dcand ac/dc converters.




Henry Shu-Hung Chung (M’95–SM’03) receivedthe B.Eng. degree in electrical engineering in 1991and the Ph.D. degree in 1994, both from The HongKong Polytechnic University.

Since 1995, he has been with the City Universityof Hong Kong (CityU). He is currently professorof the Department of Electronic Engineering andChief Technical Of ficer of e.Energy Technology

Limited —an associated company of CityU. His re-search interests include time- and frequency-domainanalysis of power electronic circuits, switched-ca-

pacitor-based converters, random-switching techniques, control methods,digital audio amplifiers, soft-switching converters, and electronic ballast

design. He has authored six research book chapter and over 250 technicalpapers, including 100 refereed journal papers in his research areas, and holdsten patents.

Dr. Chung was IEEE Student Branch Counselor and Track Chair of the Tech-nical Committees on Power Electronics Circuits and Power Systems of IEEECircuits and Systems Society during 1997–1998. He was Associate Editor andGuest Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I:FUNDAMENTAL THEORY AND APPLICATIONS during 1999–2003. He is currentlyan Associate Editor of the IEEE TRANSACTIONS ON POWER ELECTRONICS. Hewas awarded the Grand Applied Research Excellence Award in 2001 from theCityU.

Adrian Ioinovici (M’84–SM’85–F’04) received theelectrical engineering degreein 1974and the Dr.Eng.degree in 1981, both from Polytechnical Institute of Iasi, Iasi, Romania.

In 1982, he joined the Holon Institute of Tech-nology, Holon, Israel, where he is currently aProfessor in the Electrical and Electronics Engi-neering Department. During 1990–1995, he was

a Reader and then a Professor in the ElectricalEngineering Department, Hong Kong PolytechnicUniversity. His research interests are in simulation of

power electronics circuits, switched-capacitor-based converters and inverters,soft-switching DC power supplies, and three-level converters. He is the authorof the book Computer-Aided Analysis of Active Circuits (New York: MarcelDekker, 1990) and of the chapter “Power Electronics” in the Encyclopedia of Physical Science and Technology (Academic Press, 2001). He has publishedmore than 100 papers in circuit theory and power electronics.

Dr. Ioinovici has been Chairman of the Technical Committee on PowerSystems and Power Electronics of the IEEE Circuits and Systems (CAS)Society. He has served as an Associate Editor of the IEEE T RANSACTIONS ON

CIRCUITS AND SYSTEMS—I and of the Journal of Circuits, Systems, and Com- puters. He has been an Overseas Advisor of the IEICE Transactions of Japan.He was Chairman of the Israeli chapter of the IEEE CAS Society between1985–1990 and served as General Chairman of the Conferences ISCSC ’86,ISCSC’88 (Herzlya, Israel), SPEC’94 (Hong Kong), organized and Chaired

special sessions in Power Electronics at ISCAS’91, ISCAS’92, ISCAS’95,ISCAS’2000, and was a member of the Technical Program Committee at theConferences ISCAS’91- ISCAS’95, ISCAS’06, PESC’92-PESC’95, Track Chairman at ISCAS’96, ISCAS’99-ISCAS’2005, Co-Chairman of the SpecialSession’s Committee at ISCAS’97, co-chairman of the Tutorial Committee atISCAS’06, and designed co-chair, Special Session Committee at ISCAS ’10Paris. He was a Guest Editor of special issues of IEEE TRANSACTIONS ON

CIRCUITS AND SYSTEMS—I (August 1997 and August 2003) and of a SpecialIssue on Power Electronics of the Journal of Circuits, System and Computers(Aug. 2003).

Documents

A High-Voltage DC–DC Converter With Vin div by 3—Voltage Stress on the Primary Switches