A Floating-Point Unit for Arithmetic Operations

i

Tm Tt Ni Dung Kha Lun

My hin th sng hay cn gi l my dao ng s c nh (DSO) l mt thit b khng th thiu trong o lng iu khin. Cng vi s pht trin ca khoa khc cng ngh m ngy nay chng ta c nhng my hin sng c tnh nng rt phong ph v kch thc cng c gim xung ng k, bt cng knh v c bit gi thnh li h xung rt nhiu. Ngy nay cng ngh sn xut FPGA rt pht trin nn kha lun ny em xin trnh by v cch thit k mt my dao ng s c nh da trn cng ngh FPGA.

Kha lun c chia lm hai phn: Phn l thuyt em xin trnh by mt cch tng quan nht v cng ngh FPGA, gii thiu s qua v cc bc thc hin trong FPGA. Phn th hai em xin trnh by v cc loi my dao ng s c nh, cu to v nguyn tc hot ng ca my dao ng tng t v my dao ng s c nh. Cui cng l phn em trnh by v cc bc thit k mt my dao ng s trn FPGA v mt s kt qu thu c.

Kha lun tt nghip Th nghim thit k dao ng k s trn FPGA

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Mc lc CC T VIT TT ........................................................................................................... iv M u .................................................................................................................................. 1 Chng 1 ............................................................................................................................... 2 TNG QUAN V FPGA ...................................................................................................... 2

1.1 FPGA L G? ............................................................................................................. 2 1.2. LCH S RA I FPGA ............................................................................................ 3 1.3. NG DNG ............................................................................................................... 3 1.4. CU TRC MT FPGA ............................................................................................ 4

1.4.1 Khi logic FPGA ................................................................................................... 4 1.4.2 Cc phn t tch hp sn ........................................................................................ 5 1.4.3 Quy trnh thit k FPGA tng qut. ........................................................................ 5

1.4.3.1 M t ban u v thit k ................................................................................ 6 1.4.3.2 Thc thi ......................................................................................................... 8 1.4.3.3 Qu trnh Np (download) v lp trnh (program) ......................................... 10

1.5 TNG QUAN V VHDL .......................................................................................... 10 1.5.1 Gii thiu v ngn ng m t phn cng VHDL .................................................. 10 1.5.2 Cu trc mt m hnh h thng m t bng VHDL .............................................. 12

1.5.2.1 Thc th (entity) ca m hnh ....................................................................... 12 1.5.2.2 Kin trc ca m hnh ................................................................................... 13

TNG QUAN V OSCILLOSCOP ..................................................................................... 14 2.1 DAO NG K IN T .................................................................................. 14 2.2 PHN LOI OSCILLOSCOP ................................................................................... 15 2.3 CU TRC CA OSCILLOSCOP IN T TNG T ..................................... 16 2.3 CU TRC CA OSCILLOSCOP IN T S ..................................................... 17

CC BC THIT K MT OSCILLOSCOP S C NH ............................................. 22 3.1 CC THNH PHN TRONG THIT K................................................................. 23

3.1.1.B nh ................................................................................................................. 23 3.1.2 B bin i tng t - s ADC ........................................................................... 25 3.1.4 iu khin logic .................................................................................................. 28

3.2 THIT K CHI TIT ................................................................................................. 32 3.2.1 Cu hnh np vo FPGA ................................................................................. 32 3.2.2 Ch tin trigger ............................................................................................... 33 3.2.3 D im trigger ................................................................................................... 34 3.3.4 B to xung ......................................................................................................... 36 3.3.6 Giao din logic cng song song ........................................................................... 37 3.3.7 iu khin ADC .................................................................................................. 38

Chng 4 ............................................................................................................................. 39 CHNG TRNH V M PHNG TRN KIT DE2 ........................................................ 39

4.1 TNG QUAN V KIT DE2 V CHIP CYCLONE II................................................ 39 4.2 CHNG TRNH V M PHNG ......................................................................... 44

4.2.1. Chng trnh chnh iu khin DSO ................................................................... 44 4.2.2 Chng trnh iu khin logic cng song song ..................................................... 46


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4.2.3 Chng trnh iu khin FIFO ............................................................................. 47 4.2.4 Chng trnh to dng xung chia theo t l 1/2, 1/4, 1/8, 1/16, 1/32 ...................... 49 4.2.4 Chng trnh d im trigger ............................................................................... 50

Kt lun ............................................................................................................................... 52 PH LC ............................................................................................................................ 53 Ti liu tham kho ............................................................................................................... 70


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CC T VIT TT

ADC : Analog -to- Digital Converter

ASIC : Application-Specific Integrated Circuit

CPLD : Complex Programmable Logic Device DAC : Digital-to-Analog Converter

DRAM : Dynamic Random Access Memory . DSO : Digital Storage Oscilloscop

DSP : Digital Signal Processing. E2 : EEPROM.

EEPROM : Electrically Erasable Programmable Read-Only

Memory. FIFO : First In First Out

FPGA : Field-Programmable Gate Array

HDL : Hardware Description Language

I/O : Input/Output

LAB : Logic Array Block. LE : logic Element.

LUT : Look Up Table MAC : Multication and accumulation

PC : Personal Computer PLA : Programmable Logic Array

RAM : Random Access Memory

ROM : Read-Only Memory SPLD : Simple Programable Devices.

SRAM : Static Random Access Memory. VHDL : VHSIC hardware description language

VHSIC : Very High Speed Itergrated Circuit


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WCLK : Write Clock.

WE : Write Enable. WRST : Write Reset.


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Li cm n Li u tin em xin gi li cm n n ton th cc thy, c gio khoa in t -

Vin thng trng i hc Cng Ngh- HQG H Ni, nhng ngi tn tnh dy d, ch bo em trong sut bn nm hc va qua ti nh trng.

Tip theo em xin gi li cm n su sc n TS Nguyn Thng Long v CN Phan Vn Minh , nhng ngi trc tip hng dn em trong sut qu trnh hc tp v nghin cu ti trng, cc thy truyn cho em cch t duy c h thng, phng php nghin cu, tip cn thc t - nhng iu rt qu bu vi em khi ra trng lm vic thc t.

Em xin cm n ti ton th cn b b mn Vi c in t - vi h thng nhng ngi dn dt v nh hng nghin cu cho em trong sut hai nm qua.

Em xin gi li cm n ti Ths. Nguyn Kim Hng cng ton th cn b lm vic trong phng cc h thng tch hp thng minh ch bo v to in kin cho em trong sut qu trnh hc tp v nghin cu FPGA trong phng.

Em xin t lng bit n chn thnh ti cha m, gia nh em nhng ngi sinh thnh, nui nng, tin tng ng vin em. Xin gi li cm n ti tt c bn b, c bit l tp th lp K49B, nhng ngi c v, ng vin, chia s vi em trong sut nhng nm qua.

H ni, ngy 27 thng 5 nm 2008

Sinh vin thc hin

Nguyn Vn Thng

1

M u

Dao ng k (Oscilloscop) l mt thit b o lng in t ph bin nht hin nay, khng ging nh cc loi my o khc ch cho ta cc thng s ca tn hiu, Oscilloscop cn cho php ta quan st tc thi dng ca tn hiu. Nhim v chnh ca mt Oscilloscop l hin th mt cch tht chnh xc, chi tit dng tn hiu di dng hm s ca in p v thi gian. Ngoi ra mt nhim v khng km phn quan trng khc ca oscilloscop l so snh cc dng sng khc nhau v o lng mi quan h v thi gian v pha gia chng.

C th ni qu trnh pht trin ca oscillscop gn lin vi qu trnh pht trin ca k thut in t. M u l oscilloscop tng t, mt vi thp nin gn y l oscilloscop s, gn y nht l mt s cng ty o lng hng u th gii va cho ra i oscilloscop hn hp gia s v tng t c tnh hp vi cc tnh nng mnh m nht tha hng t ngnh cng nghip my tnh.

Th k 21 l th k ca thng tin v k thut s vi s pht trin v ng dng rng ri ca cc b vi x l. Bng vic a sc mnh k thut s vo thc tin, cc b vi x l ngy mt thay i cch sng ca x hi loi ngi. Kha in t, my in thoi, ni cm in..ca chng ta ang ngy mt thng minh hn, mnh m v nhanh nh cc b vi x l. Tt c cc ngnh cng nghip ln nh: vin thng, iu khin cng nghip, sn xut hng tiu dng u thc c v s dng trit cng ngh mi v h cng vp phi nhng vn mi cn gii quyt l cc vn lin quan ti tn hiu v iu khin s v tng t ca th gii thc. Oscilloscop vi vai tr l mt thit b gim st, o kim phi p ng c cc yu cu ngy cng kht khe do cc ngnh cng nghip ny t ra.

Vi mc ch l tm hiu v thit k mt oscilloscop s, kha lun ny trnh by v phn tnh cu to, nguyn l hot ng ca cc loi oscilloscop, cc tnh nng tin tin ca chng, c bit l cch thit k mt oscilloscop k thut s c nh dng chip FPGA lm trung tm iu khin.


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Chng 1

TNG QUAN V FPGA

1.1 FPGA L G?

FPGA (Field-Programmable Gate Array) l vi mch dng cu trc mng phn t logic m ngi dng c th lp trnh c. Vi mch FPGA c cu thnh t cc b phn:

Cc khi logic c bn lp trnh c (logic block) H thng mch lin kt lp trnh c Khi vo/ra (IO Pads) Phn t thit k sn khc nh DSP slice, RAM, ROM, nhn vi x l...

So snh FPGA vi ASIC v cc vi mch bn dn khc:

ASIC (Application-Specific Integrated Circuit) l mt vi mch IC c thit k dnh cho mt ng dng c th.

FPGA cng c xem nh mt loi vi mch bn dn chuyn dng ASIC, nhng nu so snh FPGA vi nhng ASIC c ch hon ton hay ASIC thit k trn th vin logic th FPGA khng t c mc ti u nh nhng loi ny, v hn ch trong kh nng thc hin nhng tc v c bit phc tp, tuy vy FPGA u vit hn ch c th ti cu trc li khi ang s dng, cng on thit k n gin do vy chi ph gim, rt ngn thi gian a sn phm vo s dng.

Cn nu so snh vi cc dng vi mch bn dn lp trnh c dng cu trc mng phn t logic nh PLA, PAL, CPLD th FPGA u vit hn cc im:

Tc v ti lp trnh ca FPGA thc hin n gin hn. Kh nng lp trnh linh ng hn Kin trc ca FPGA cho php n c kh nng cha khi lng ln cng

logic (logic gate), so vi cc vi mch bn dn lp trnh c c trc n.

Thit k hay lp trnh cho FPGA c thc hin ch yu bng cc ngn ng m t phn cng HDL nh VHDL, Verilog, AHDL, cc hng sn xut FPGA ln nh Xilinx, Altera thng cung cp cc gi phn mm v thit b ph tr cho qu trnh



thit k, cng c mt s cc hng th ba cung cp cc gi phn mm kiu ny nh Synopsys, Synplify... Cc gi phn mm ny c kh nng thc hin tt c cc bc ca ton b quy trnh thit k IC chun vi u vo l m thit k trn HDL (cn gi l m RTL).

1.2. LCH S RA I FPGA

FPGA c thit k u tin bi Ross Freeman, ngi sng lp cng ty Xilinx vo nm 1984, kin trc mi ca FPGA cho php tch hp s lng tng i ln cc phn t bn dn vo 1 vi mch so vi kin trc trc l CPLD. FPGA c kh nng cha ti t 100.000 n hng vi t cng logic, trong khi CPLD ch cha t 10.000 n 100.000 cng logic; con s ny i vi PAL, PLA cn thp hn na ch t vi nghn n 10.000.

CPLD c cu trc t s lng nht nh cc khi SPLD (Simple programable

devices, thut ng chung ch PAL, PLA). SPLD thng l mt mng logic AND/OR lp trnh c c kch thc xc nh v cha mt s lng hn ch cc phn t nh ng b (clocked register). Cu trc ny hn ch kh nng thc hin nhng hm phc tp v thng thng hiu sut lm vic ca vi mch ph thuc vo cu trc c th ca vi mch hn l vo yu cu bi ton.

Kin trc ca FPGA l kin trc mng cc khi logic, khi logic, nh hn nhiu nu em so snh vi mt khi SPLD, u im ny gip FPGA c th cha nhiu hn cc phn t logic v pht huy ti a kh nng lp trnh ca cc phn t logic v h thng mch kt ni, t c mc ch ny th kin trc ca FPGA phc tp hn nhiu so vi CPLD.

Mt im khc bit vi CPLD l trong nhng FPGA hin i c tch hp nhiu nhng b logic s hc s b ti u ha, h tr RAM, ROM, tc cao, hay cc b nhn cng (multication and accumulation, MAC), thut ng ting Anh l DSP slice dng cho nhng ng dng x l tn hiu s DSP.

Ngoi kh nng ti cu trc vi mch ton cc, mt s FPGA hin i cn h tr ti cu trc cc b, tc l kh nng ti cu trc mt b phn ring l trong khi vn m bo hot ng bnh thng cho cc b phn khc.

1.3. NG DNG



ng dng ca FPGA bao gm: x l tn hiu s DSP, cc h thng hng khng, v tr, quc phng, tin thit k mu ASIC (ASIC prototyping), cc h thng iu khin trc quan, phn tch nhn dng nh, nhn dng ting ni, mt m hc, m hnh phn cng my tnh...

Do tnh linh ng cao trong qu trnh thit k cho php FPGA gii quyt lp nhng bi ton phc tp m trc kia ch thc hin nh phn mm my tnh, ngoi ra nh mt cng logic ln FPGA c ng dng cho nhng bi ton i hi khi lng tnh ton ln v dng trong cc h thng lm vic theo thi gian thc.

1.4. CU TRC MT FPGA

Cu trc tng th ca mt FPGA c minh ha hnh sau.

Hnh 1: Cu trc tng th mt FPGA

1.4.1 Khi logic FPGA

Hnh 2: Khi logic FPGA

Phn t chnh ca FPGA l cc khi logic (logic block). Khi logic c cu thnh t LUT v mt phn t nh ng b flip-flop.



LUT (Look up table) l khi logic c th thc hin bt k hm logic no t 4 u vo, kt qu ca hm ny ty vo mc ch m gi ra ngoi khi logic trc tip hay thng qua phn t nh flip-flop.

Nu nhn cu trc tng th ca mng LUT th ngoi 4 u vo k trn cn h tr thm 2 u vo b sung t cc khi logic phn b trc v sau n nng tng s u vo ca LUT ln 6 chn. Cu trc ny l nhm tng tc cc b s hc logic.

H thng mch lin kt l khi chuyn mch ca FPGA Mng lin kt trong FPGA c cu thnh t cc ng kt ni theo hai phng ngang v ng, ty theo tng loi FPGA m cc ng kt ni c chia thnh cc nhm khc nhau, v d trong XC4000 ca Xilinx c 3 loi kt ni: ngn, di v rt di. Cc ng kt ni c ni vi nhau thng qua cc khi chuyn mch lp trnh c (programable switch), trong mt khi chuyn mch cha mt s lng nt chuyn lp trnh c m bo cho cc dng lin kt phc tp khc nhau.

1.4.2 Cc phn t tch hp sn

Ngoi cc khi logic ty theo cc loi FPGA khc nhau m c cc phn t tch hp thm khc nhau, v d thit k nhng ng dng SoC, trong dng Virtex 4,5 ca Xilinx c cha nhn s l PowerPC, hay trong Atmel FPSLIC tch hp nhn ARV, hay cho nhng ng dng x l tn hiu s DSP trong FPGA c tch hp cc DSP Slide l b nhn cng tc cao, thc hin hm A*B+C, v d dng Virtex ca Xilinx cha t vi chc n hng trm DSP slices vi A, B, C 18-bit.

1.4.3 Quy trnh thit k FPGA tng qut.



Hnh 3: Quy trnh thit k FPGA

1.4.3.1 M t ban u v thit k

Khi xy dng mt chip kh trnh (FPGA) vi ngha dnh cho mt ng dng ring bit, v xut pht t mi ng dng trong thc tin cuc sng, s t ra yu cu phi thit k IC thc hin ti u nht nhng ng dng . Bc u tin ca quy trnh thit k ny c nhim v tip nhn cc yu cu ca thit k v xy dng nn kin trc tng qut ca thit k.

* M t thit k: Trong bc ny, t nhng yu cu ca thit k v da trn kh nng ca cng ngh hin c, ngi thit k kin trc s xy dng nn ton b kin trc tng quan cho thit k. Ngha l trong bc ny ngi thit k kin trc phi m t c nhng vn sau:

Thit k c nhng khi no? Mi khi c chc nng g? Hot ng ca thit k v ca mi khi ra sao ?



Phn tch cc k thut s dng trong thit k v cc cng c, phn mm h tr thit k.

Mt thit k c th c m t s dng ngn ng m t phn cng, nh VHDL hay Verilog HDL hoc c th m t qua bn v mch (schematic capture). Mt thit k c th va bao gm bn v mch m t s khi chung, va c th dng ngn ng HDL m t chi tit cho cc khi trong s .

* M phng chc nng (Function simulation): sau khi m t thit k, ngi thit k cn m phng tng th thit k v mt chc nng kim tra thit k c hot ng ng vi cc chc nng yu cu.

* Tng hp logic (Logic Synthesis): tng hp logic l qu trnh tng hp cc m t thit k thnh s b tr mch (netlist). Qu trnh chia thnh 2 bc: chuyn i cc m RTL, m HDL thnh m t di dng cc biu thc i s Boolean v da trn cc biu thc ny kt hp vi th vin t bo chun sn c tng hp nn mt thit k ti u.

* Hiu chnh cc kt ni (Datapath Schematic): nhp netlist v cc rng buc v thi gian vo mt cng c phn tch thi gian (timing analysic). Cng c phn tch ny s tch ri tt c cc kt ni ca thit k, tnh thi gian tr ca cc kt ni da trn cc rng buc. Da trn kt qu phn tch (report) ca cng c phn tch, xc nh cc kt ni khng tha mn v thi gian. Ty theo nguyn nhn dn n khng tha mn m ta c th vit li m v tin hnh li tng hp logic hoc hiu chnh li cc rng buc.

Hnh 4: Logic Synthesis



1.4.3.2 Thc thi

Ta c s b tr netlist m t tng th thit k ti mc cng (ch gm cc cng logic c bn v cc mch logic khc nh: MUX). Qu trnh ny s t s netlist ny ln chip, gi l qu trnh thc thi (Device Implementation).

Qu trnh gm cc bc:

* nh x (mapping hay cn gi fitting - n khp): chun b d liu u vo, xc nh kch thc cc khi. Cc khi ny s phi ph hp vi cu trc ca 1 t bo c bn ca FPGA (gm nhiu cng logic) v t chng vo cc v tr ti u cho vic chy dy.

ECE 545 Introduction to VHDL 63

Mapping

LUT2

LUT3

LUT4

LUT5

LUT1FF1

FF2

LUT0

Hnh 5: S gn chn

* t khi v nh tuyn (Place & Route): t khi: t cc khi nh x vo cc t bo (cell) v tr ti u cho vic

chy dy.




PlacingCLB SLICES

FPGA

Hnh 6: S khng gian gn bn trong FPGA

nh tuyn: bc ny thc hin vic ni dy cc t bo.


Routing

Programmable Connections

FPGA

Hnh 7: S nh tuyn

thc hin vic ny, chng ta cn c cc thng tin sau:



Cc thng tin vt l v th vin t bo, v d kch thc t bo, cc im kt ni, nh thi, cc tr ngi trong khi i dy.

Mt netlist c tng hp s ch ra chi tit cc instance v mi quan h kt ni bao gm c cc ng dn b hn ch trong thit k.

Tt c cc yu cu ca tin trnh cho cc lp kt ni, bao gm cc lut thit k cho cc lp chy dy, tr khng v in dung, tiu th nng lng, cc lut v s dn in trong mi lp.

1.4.3.3 Qu trnh Np (download) v lp trnh (program)

Sau qu trnh thc hin, thit k cn c np vo FPGA di dng dng bit (bit stream).

Qu trnh np thit k (download) vo FPGA thng np vo b nh bay hi, v d nh SRAM. Thng tin cu hnh s c np vo b nh. Dng bit c truyn lc ny s mang thng tin nh ngha cc khi logic cng nh kt ni ca thit k. Tuy nhin, lu rng, SRAM s mt d liu khi mt ngun nn thit k s khng lu c n phin lm vic k tip.

Lp trnh (program) l thut ng m t qu trnh np chng trnh cho cc b nh khng bay hi, v d nh PROM. Nh vy, thng tin cu hnh vn s c lu tr khi mt ngun.

1.5 TNG QUAN V VHDL

1.5.1 Gii thiu v ngn ng m t phn cng VHDL

VHDL l ngn ng m t phn cng cho cc mch tch hp tc cao, l mt loi ngn ng m t phn cng c pht trin cho chng trnh VHSIC ( Very High Speed Itergrated Circuit) ca b quc phng M. Mc tiu ca vic pht trin VHDL l c c mt ngn ng m phng phn cng tiu chun v thng nht cho php th nghim cc h thng s nhanh hn cng nh cho php d dng a cc h thng vo ng dng trong thc t.

VHDL c pht trin nh mt ngn ng c lp khng gn vi bt k mt

phng php thit k, mt b m t hay cng ngh phn cng no. Ngi thit k c th t do la chn cng ngh, phng php thit k trong khi ch s dng mt ngn ng duy nht. V khi em so snh vi cc ngn ng m phng phn cng khc k ra trn ta thy VHDL c mt s u im hn hn cc ngn ng khc:



Th nht l tnh cng cng: VHDL c pht trin di s bo tr ca chnh ph M v hin nay l mt tiu chun ca IEEE. VHDL c s h tr ca nhiu nh sn xut thit b cng nh nhiu nh cung cp cng c thit k m phng h thng.

Th hai l kh nng h tr nhiu cng ngh v phng php thit k. VHDL cho php thit k bng nhiu phng php v d phng php thit k t trn xung, hay t di ln da vo cc th vin sn c. VHDL cng h tr cho nhiu loi cng c xy dng mch nh s dng cng ngh ng b hay khng ng b, s dng ma trn lp trnh c hay s dng mng ngu nhin.

Th ba l tnh c lp vi cng ngh: VHDL hon ton c lp vi cng ngh ch to phn cng. Mt m t h thng dng VHDL thit k mc cng c th c chuyn thnh cc bn tng hp mch khc nhau tu thuc cng ngh ch to phn cng mi ra i n c th c p dng ngay cho cc h thng thit k.

Th t l kh nng m t m rng: VHDL cho php m t hot ng ca phn cng t mc h thng s cho n mc cng. VHDL c kh nng m t hot ng ca h thng trn nhiu mc nhng ch s dng mt c php cht ch thng nht cho mi mc. Nh th ta c th m phng mt bn thit k bao gm c cc h con c m t chi tit.

Th nm l kh nng trao i kt qu: V VHDL l mt tiu chun c chp nhn, nn mt m hnh VHDL c th chy trn mi b m t p ng c tiu chun VHDL. Cc kt qu m t h thng c th c trao i gia cc nh thit k s dng cng c thit k khc nhau nhng cng tun theo tiu chun VHDL. Cng nh mt nhm thit k c th trao i m t mc cao ca cc h thng con trong mt h thng ln (trong cc h con c thit k c lp).

Th su l kh nng h tr thit k mc ln v kh nng s dng li cc thit k: VHDL c pht trin nh mt ngn ng lp trnh bc cao, v vy n c th c s dng thit k mt h thng ln vi s tham gia ca mt nhm nhiu ngi. Bn trong ngn ng VHDL c nhiu tnh nng



h tr vic qun l, th nghim v chia s thit k. V n cng cho php dng li cc phn c sn.

1.5.2 Cu trc mt m hnh h thng m t bng VHDL

Thng thng mt m hnh VHDL bao gm ba phn: thc th, kin trc v cc cu hnh. i khi ta x dng cc gi( packages) v m hnh kim tra hot ng ca h thng( testbench).

1.5.2.1 Thc th (entity) ca m hnh

Phn khai bo thc th ch r TN ca thc th v lit k cc li vo v ra v c dng chung nh sau

Entity tn_thc_th is

Generic (khai bo generic);

Port (khai bo cc tn hiu vo ra);

End tn_thc_th;

Mt thc th lun bt u vi t kha entity, theo sau l tn ca thc th v t kha is. Ri n cc khai bo cng vi t kha port. Mt thc th lun kt thc vi t kha end v tn ca thc th.

Tn thc th l tn ca thc th do ngi dng t.

Cc tn hiu vo ra: tn ca cc tn hiu do ngi dung t, ngn cch vi nhau bi du phy, ch ra cc tn hiu ni vi bn ngoi.

Cc ch ca tn hiu khai bo trong port: ch ra chiu ca tn hiu, c cc mode sau:

- in: ch ra rng tn hiu l mt tn hiu vo.

- out: ch ra rng tn hiu l mt tn hiu ra khi thc th v ch cc thc th khc dng n tn hiu ny mi c th c gi tr ca n.

- buffer: tn hiu l tn hiu ra v gi tr ca n c th c c c bn trong thc th.

- inout: tn hiu c th l tn hiu vo hoc tn hiu ra.



1.5.2.2 Kin trc ca m hnh

Cu trc ca n nh sau:

ARCHITECTURE tn_architecture OF tn_entity IS [cc phn khai bo:signal, component] BEGIN [code] END tn_architecture;

Trong kin trc m hnh chng ta c th khai bo tt c mi th lin quan ti chng trnh, trong c cc process, cc chng trnh con vi li gi hm component, v khai bo cc signal v cc cu lnh port map kt ni cc thnh phn con c trong kin trc. Ni chung cng nh ngn ng C th y kin trc(architecture) l thn ca chng trnh ca ta.



Chng 2

TNG QUAN V OSCILLOSCOP

2.1 . DAO NG K IN T

Khi t vn chn dng oscilloscop c ngha l chn c loi oscilloscop m cc c tnh k thut ca n ph hp vi cc yu cu t ra ca bi ton o lng, nghin cu, vi cc c tnh v thng s ca tn hiu hay mch in t.

Nhng yu cu c bn m mt oscilloscop phi p ng c l:

Phi c kh nng hin th ng thi tn hiu s v tn hiu tng t. iu ny gip ngi k s c th gim st c qu trnh giao tip gia b vi x l vi th gii tng t, ti u ha cho cng tc tm v sa li.

Hnh 8: S khi ca dao ng k in t



Phi lu c mt khong thi gian di tn hiu vi tc ly mu cao, tc cp nht mn hnh nhanh gip ngi k s quan st mt cch chi tit v chnh xc tn hiu- i hi phi c mt b nh ln.

Phi cung cp cc ch cp pht linh hot, a dng v mnh m.

Phi c vi tnh ha vi cc tnh nng nh : c kh nng giao tip vi my tnh qua cng RS-232 hay cng song song.

Phi c giao din thn thin vi ngi dng cung cp cc thao tc n gin, d hiu, nhanh gn. C kh nng tr gip linh hot v d hiu.

Phi c chnh xc, tin cy v n nh cao.

2.2 PHN LOI OSCILLOSCOP

Khi ch quan st tn hiu bin i lin tc hay tn hiu xung vi tn s lp li tng i cao, v ch cn cc thng s chnh ca n l bin , tn s th c th dng loi oscilloscop tng t thng thng.

Khi cn o lng, quan st ng thi hay nhiu tn hiu th dng oscilloscop nhiu knh c th trc tip so snh dao ng ca hai hay nhiu tn hiu trn mn hnh. Vi cch quan st o lng ny cho php ta nh gi, so snh cc thng s c tnh ca chng mt cch nh tnh song nhanh chng v c nhn xt hiu qu. Thng th cc oscilloscop vi cu to hai h thng sng in t ring bit trong cng mt ng phng tia in t.

Khi cn nghin cu, o lng cc tn hiu c lp th ta dng loi oscilloscop khng ng b.

Khi cn nghin cu tn hiu nh tn hiu xung c rng rt nh hay tn hiu c chu k vi tn s cao th dng loi oscilloscop loi hot nghim, l loi oscillo c thc hin theo phng php ly mu.

Khi c yu cu nghin cu c th hn v cc thng s, c tnh ca tn hiu, mun o cc thng s khc ca n, mun x l c kt qu quan st, so snh chng vi cc gi tr chun m c cho trc, hoc khi s dng oscilloscop nh l mt phn ca h o lng t ng th ta cn chn oscilloscop c ci t b vi x l.



2.3 CU TRC CA OSCILLOSCOP IN T TNG T

Oscillloscop v c bn cu to ca n l mt loi my v di ng theo hai chiu X,Y

Cu trc ca s nh sau: Knh lch ng Y Knh lch ngang X Knh khng ch sng Z ng phng tia in t CRT

Knh lch ng Y dng x l tn hiu cn quan st, c nhim v phi hp v tr khng, mc in vi tn hiu ca mch in cn o (to tr pha tn hiu khi s dng ch qut i quan st tn hiu xung c rng nh), v khuch i tn hiu ( khuch i i xng) quan st trc khi a vo cp phin lch Y ca ng in t. B to tr nhm m bo cho s khi ng gc thi gian ca in p qut (ca knh lch ngang) trc khi tn hiu cn quan st ti cp phin Y, nh vy m bo s hin hnh ton b tn hiu, nht l tn hiu xung, dng ca n khng b mt sn trc khng c v. B khuch i ra Y cn l i xng m bo tn hiu quan st c v khng b mo dao ng do thay i in trng tng tc m chnh do in p tn hiu gy ra.

Cc ch tiu ca knh Y: nhy (vn/ chia), di bng tn, tr s tr khng u vo (in tr v in dung u vo).

Knh lch ngang X c nhim v cung cp in p lm lch theo chiu ngang ca ng in t. in p a vo b lch X cn c to ra t b to in p qut, khi cn biu din tn hiu cn quan st theo thi gian.

in p to c t b in p qut c ng b t tn hiu quan st ly t

knh Y, l ng b trong. N cng c ng b t tn hiu ng b ngoi, khi khng ng b c t tn hiu ng b trong v ng b t tn hiu 50Hz ly t ngun cung cp xoay chiu, khi cn quan st tn hiu tn s thp v kh hin tng nhiu. Nh vy c ba ch ng b trong oscilloscop, c c dao ng ng yn trong qu trnh quan st.

Cc ch tiu ca knh lch ngang ch yu da vo cc ch tiu ca in p qut. Cc ch tiu l: khng tuyn tnh ca in p qut, thi gian qut thun th ln



hn rt nhiu thi gian qut ngc trong mt chu k qut, di tn s qut, tc bin i ca in p theo thi gian v hiu sut to bin in p qut.

Trn hnh v, khng ng thng l t s ca khong bin thin tc in p qut trong thi gian qut thun (Tth) trn gi tr tc trung bnh:

tbdTdU

dTdU

dTdU

y)(

min)(max)(%

Trong mt chu k qut Tq th : Tth>>Tng

Hiu sut to bin qut: EngUq%

iu kin c mt dao ng ng yn, tc l iu kin gi ng b:

Tq = nTth ( Tth=fth

1 l chu k ca in p tn hiu cn quan st).

2.3 CU TRC CA OSCILLOSCOP IN T S

Vi loi Oscilloscop thng thng (loi tng t), ch quan st tn hiu c chu k. Song cc tn hiu khng chu k th loi thng thng khng th quan st c m phi dng loi c nh s.

Oscilloscop c nh loi tng t c cu to c bit gi l loi ng tia c nh.

Oscilloscop c nh s (DSO) c cc u im l: Duy tr hnh nh dng ca tn hiu trn mn hnh vi khong thi gian

khng hn ch. Tc c c th thay i trong gii hn rng Cc hnh nh lu tr c th xem li c tc thp hn nhiu tc

qut c th ti 1cm/1h. To c hnh nh dao ng tt hn, tng phn nhiu hn loi

osilloscop tng t n gin hn trong s dng vn hnh



C th truyn trc tip s liu ca tn hiu cn quan st di dng s v c th ghp trc tip vi my tnh hoc c x l trong osilloscop.

S ca loi Oscilloscop c nh s nh hnh v

Hnh 9: S khi ca osilloscop sc nh

Khi chuyn mch S t v tr 2 th oscilloscop lm vic l mt oscilloscop c nh. in p tn hiu cn quan st c a vo u Y, ti b bin i tng t ->s ADC. Ti thi im (t1), khi iu khin gi mt lnh ti u vo ca b ADC v khi ng qu trnh bin i. Kt qu l in p tn hiu c s ha, c ngha l b bin i ly mu dng tn hiu nhiu im v bin i gi tr tc thi ca bin ti mi im thnh gi tr m nh phn t l vi bin . Ti thi im kt thc qu trnh bin i, b bin i ADC gi mt lnh kt thc n b iu khin

Mi s nh phn c chuyn ti b nh v c nh v tr nh ring bit. Bi v y l b nh khng linh hot (nonvolatile memory) nn n c th lu tr s nh phn vi bt k di thi gian no. Khi cn thit mt lnh t khi iu khin c th lm cho cc s nh phn ny c th sp sp theo chui th t xc nh v c a ti b bin i DAC. B ny s bin i cc gi tr nh phn thnh in p tng t, v in p ny c a qua b khuch i Y.Do b nh c lin tip qut nhiu ln trong mt giy ln mn hnh c sng lin tc v hin ln dng sng v hnh v cc im sng, biu th dng sng cn quan st.



t c mt ng sng lin tc, cn c th c thm mt mch ni suy (lm mt gia b DAC v b khuch i Y).

Hn ch ca loi trn do tc bin i ADC thp, nhng gn y c nhng loi ADC bin i vi tc rt cao tuy nhin gi thnh th rt t.

Mt loi oscilloscop c nh khc l dng b vi x l lm khi iu khin.

S khi ca oscilloscop s c nh nh hnh v:

Hnh 10: S khi ca oscilloscop s c nh

Hnh di c phn khc hnh trn ch: B giao ng qut thc s l b bin i DAC knh X, c iu khin t s liu ca Microprocessor. u ra b bin i DAC to ra in p nhy bc, sao cho s nhy bc thang khng khc bit qu nhiu so vi in p bc thang c to ra t b dao ng qut tng t.

Vi DAC loi 8 bit, s bc nhy l 28=256. Ton b on in p ra c chia thnh 255 bc ring bit, v s lch ngang ca tia in t thc t l t l theo thi gian. Tc bin i DAC v b iu khin qut quyt nh tc qut cc i, tc qut c th iu khin bng vic thay i s n u vo s ca b DAC.

Cn t hp cc b pha trn gm: ADC, B nh, DAC ca knh Y cho php kh nng thay i tr ca tn hiu vo ca h thng lm lch y trong mt gii hn rng,



ng thi n c th kt hp c vi DAC ca knh X nh vy m bo s ng b chnh xc.

2.4 OSCILLOSCOP TNG T C CI T VI X L

Khng ch c oscilloscop in t s mi c th ci t vi x l m oscilloscop tng t cng c th ci t c vi x l v n c th hot ng gn ging nh oscilloscop in t s. Thc cht ca n l n c dng thm mt s thit b x l s nh dng b vi x l, cc b bin i ADC

Hnh 11: S mt oscilloscop tng t dng vi x l

Vi loi ny ta thy ngay s n c chia lm ba phn: Phn th nht n ging nh mt oscilloscop tng t Phn gia c cc b bin i tng t s (ADC) v b bin i s tng

t (DAC) cng vi cc module nh v mt h vi x l vi chc nng kim tra, chng ta c th coi phn ny nh l mt phn hay mt oscilloscop c nh.

Phn di cng l b vi x l phc v cho vic iu khin chng trnh v x l tn hiu s, card giao din dng ni oscilloscop vi giao din h thng.



Khi cn nhn dng ca tn hiu c nghin cu theo t l thi gian thc t th oscilloscop lm vic nh mt oscilloscop vn nng. Nu nh khng dng kh nng iu khin bng chng trnh v x l theo nhng kh nng ca b vi x l s theo kh nng ca b vi x l th oscolloscop trn lm vic nh mt oscilloscop tng t thng thng. Khi c th i mt s khi chun (b khuch i Y,X, my pht

chun) nh i vi mt s oscilloscop thng thng m cu to c thit k c th thay th cc khi ny hay ni thm cc khi mi. Xu hng hin nay ta c th chia n ra lm hai phn: phn tng t v phn s cng c th hin ch phn b v tr ca cc phn thuc h iu khin. Nhng ci iu khin thng thng hay gp oscilloscop thng thng th vn c gi nguyn v tr nguyn thy c cch ring vi bn phm.

Vi x l lm cho loi oscilloscop ny c thm cc c im mi. N c cha tt c cc modul mi m mt h thng nh th phi c. Mt xch ni gia vi x l vi khi tng t chnh l b bin i tng t s (ADC).

H thng c ni vi nhau thng qua cc bus h thng ca vi x l v c lin kt chung ti cc ROM, RAM v cc card giao din giao tip vi thit b hin th nh mn hnh hay c th kt ni trc tip ti my tnh thng qua cc loi card.

Mt loi Oscilloscop c nh s(DSO) l ta c th dng mt con chip FPGA lm trung tm iu khin

Cu to v chi tit thit k mt Oscilloscop c nh s (DSO) dng chip FPGA s c trnh by chi tit trong chng 3.

----------------------------------



Chng 3

CC BC THIT K MT OSCILLOSCOP S C NH

Hnh 12: S khi ca DSO c n gin ho dng FPGA

Nguyn l hot ng tng i n gin. Tn hiu c a qua mt b khuch i tn hiu sau c a vo mt con ADC, ti ADC tn hiu s c ly mu lng t ha tn hiu tng t thnh tn hiu s. u ra ca c ADC v b nh m u cng chia s chung bus 3 trng thi. N l mt bc trung gian quyt nh chn knh no, u ra no, tit kim c ng truyn v trnh xung t d liu khi c

hai u ra ca ADC v b nh m cng ra mt lcchng trnh iu khin logic s quyt nh chn 1 trong 2 u ra hoc ca ADC hoc ca b nh m a n ti bus, v vy n chn 1 trong 2 l thuc dng logic tng t hay logic dng s. Sau



d liu c a ln bus v c a vo b nh chnh lu tr d liu. Lgic iu khin s ng thi theo di d liu quan st im trig. Cch tip cn ny loi tr mch in b sung m bnh thng trig cn phi c, v thu hp ng tn hiu tng t, do gim bt nhiu. iu ny cng cung cp kh nng gy nn tn hiu dng s khi dng my phn tch logic. Ngoi tm im trig, logic iu khin cng thc hin mi chc nng Glue logic v phng thc tin trig. Khi b nh y, d liu dng ghi v c chuyn vo PC thng qua cng song song.

V 2 knh hon ton ring bit nn chng hot ng mt cch c lp. V d: knh A l trong ch phn tch logic (logic analyser), knh B li trong ch tng t (analogue). Hiu qu ca tc ly mu c th tng gp i bng cch kt ni 2 u ra tng t vi nhau v i pha knh th 2 i 1800. Sau khi d liu c a vo PC, n c xen vo bi phn mm v dng sng c thit k li. Mc d tn hiu c th 2 ln tn s thng, di ca bn ghi vn ko gim v c hai b nh ang c dng lu tr dng sng n.

3.1 CC THNH PHN TRONG THIT K

3.1.1.B nh

T c im k thut ca DSO dng chip FPGA m ta thit k th b nh cn nhng iu kin cn thit sau:

D liu bus rng 8bit. C th cha 3Mbit. Tc truyn d liu 40Mbytes/giy.

Cng c v ghi ring.

Bi v tc ly mu ca ADC l nhanh hn rt nhiu so vi tc c ca b nh ( y chng ta dng RAM) cho nn nht thit phi dng b nh c hai cng c v ghi ring bit trnh tnh trng khng c d liu. Cho nn tho mn c nhng yu cu ny,chng ta phi chn b nh(RAM) c 2 ng c v ghi ring bit. Bi v tc ly mu khi dng mt con ADC flash tc cao cho nn yu cu b nh cng cn c tc ghi d liu cao v c tc c d liu ph hp vi tc ca cng song song m ta s dng truyn d liu ln my tnh V nhng l do ny quyt nh dng b nh trong thit k ta nn dng nhng b nh hnh nh c s dng chnh trong cc ng dng video nh thi gian da trn s hiu chnh v hnh nh



trong phim. Chng l loi b nh hi t nhng yu cu ca ng dng ca ta .Bi v n c cng sut cha ln, tc truyn d liu nhanh v cng c v ghi ring. Hn na chng c hp nht mc cao, lm n gin vic thit k bn mch.

Sau khi nghin cu v tm hiu cc thit b c sn trn th trng Vit Nam th em chn b nh ca hng Averlogic l AL422. N l mt b nh hnh nh v cng ging nh hu ht cc b nh hnh nh khc, n c thit k v ch to da trn cng ngh DRAM. Mc d bus d liu bn ngoi ch rng 8 Bit, phn ln b nh hnh nh s dng bus bn trong c chiu rng hn. Iu ny lm tng tc hiu qu nh tnh tng ng. Logic tc cao c dng chia tch bus bn trong thnh nhiu phn 8 bit,m sau ny n c t trn bus d liu u ra. Thm vo b iu khin DRAM v address , n to ra logic c gi trong AL 422.V tr d liu c ghi vo c nh vo mt thanh ghi a ch. Gi tr ca thanh ny c th l ln ln hoc v 0 (im bt u ca b nh). Tuy nhin n ko th c dch chuyn ti 1 v tr ngu nhin no m phi c tng hay gim mt cch tun t v qu trnh ghi phi din ra lin tc. Nhng b nh hnh nh chy ging nh nhng b m trong m khi thanh ghi tin ti on cui ca b nh, n s t ng reset v im bt u v li bt u ghi ln im c trc . Qu trnh c s dng thanh ghi c tng t. V th nhng b nh hnh nh thng c gi l First In First Out Buffers (FIFO).

Hnh 13: S thc hin chc nng ca AL422

AL422 s dng 3 chn kim sot qu trnh ghi. WCLK, /WE, v /WRST. D liu s c ghi vo b nh theo sn xung ghi d liu (WCLK) khi chn write enable cao (WE), v b m a ch s tng dn theo sn ca xung clock. Trong trng hp



thanh ghi (hay b m a ch) ko c gia tng th d liu ko c ghi. ghi li d liu vo b nh ti im u tin cu thanh ghi a ch c gi tr 0 ta phi a chn write reset (WRST) xung thp v xung ghi (WCLK), a ch s c reset v im bt u ca b nh v d liu c ghi vo im bt u cng vi cc a ch tip theo khi thanh ghi a ch tng ln..

Qu trnh c c kim sot bi 4 chn, RCLK, /RE, /RRST v /OE. D liu cng c c theo sng xung ca xung read clock (RCLK), thanh a ch c ra c gia tng khi chn read enable (/RE) v chn OE ( output enable) cao,th d liu mi c a ra. Nu chn OE m mc thp th thanh ghi a ch c dng li v d liu khng c ra hoc thanh ghi a ch vn tng th nhng d liu vn c cht ti v khng c ra. Thanh ghi a ch c cng c th c reset v im bt u ca b nh bng cch t chn read reset (/RRST) mc thp v xung RCLK. Mc d c iu khin bng tay bn trong, DRAM refresh thu c t RCLK or WCLK

(bt c ci no nhanh hn), v th duy tr tnh nguyn vn ca d liu t nht 1 trong cc tn hiu trn phi c gi chy nhanh hn 1MHz.

3.1.2 B bin i tng t - s ADC

Hnh 13: S khi ca ADC TDA 8703

ADC c dng bin i dng sng tng t sang dng xung PAM. V bn cht t nhin ring bit ca tn hiu s, dng sng tng t s c lng t ho n mc



tng ng s gn nht v chuyn thnh tn hiu s. S chuyn ADC cng ln th sai s s lng t ho c a vo cng nh. Ta thy c rt nhiu loi ADC trn th trng nhng tha mn nhng t c nhng yu cu v l do dng FPGA lm b iu khin cho dao ng s c nh em tm hiu trn th trng th em thy TDA8703 l ph hp nht.Bi v n c tc ly mu rt cao (c th t c tc ti a l 140MHz). Tuy nhin ta cng c th thay th bi cc ADC khc c sn trn th trng.

Phn ln ADC tc cao dng phng thc Flash Conversion, ci ny s dng theo cc mng song song ca 2n-1 b so snh (n l phn gii ca ADC trong cc bit). iu ny c ngha l c mi 8bit, my i in li yu cu 255 b so snh. Mc phc tp ny khng ch lm tng chi ph m cn lm hn ch tc ti a m b bin i c th hot ng. TDA8703 s dng phng thc Flash Conversion truyn li, trong ADC ny th b bin i c chia tch thnh 7 cp vi mi cp dng 1 trnh chuyn i cc nhanh 2 bit. Chnh iu ny lm gim s b so snh c yu cu xung cn 28 v y cng l mt u im ca b bin i ADC nhanh dng phng thc bit i Flash Conversion. Mc d n a ra mt gc tr 7 chu k ng h gia tn hiu tng t c a vo v d liu xut hin trn cc u ra. i vi chng trnh ng dng ny th iu l c th chp nhn c.

Hnh 15: s ni chn ca ADC TDA 8703



3.1.3 B khuch i m

Khi tn hiu tng t c a vo m DSO ang hot ng ch xen k gia tn hiu alnalog v logic analyser, th tn hiu tng t c a vo 2 ADC thng qua mt b khuch i m. Khi b trung gian ny s va c chc nng lm mt b khuch i tn hiu va c chc nng l mt b m tn hiu. C 2 chc nng ny c th t c vi 1 b khuch i m ( y em dng Elantec EL4332C). Bi v n tha mn nhng yu cu t ra ca thit k.

Hnh 16:S thc hin ni chn ca EL4332

EL4332C c b rng bng tn ti a 300MHz v cha ng 3 b tin khuch i nn rt ph hp vi cc u vo a thnh phn. iu lm n tr nn rt ph hp i vi ng dng ny v n c th thc hin c chuyn mch m v o mch u vo. 1 tn hiu logic n c dng nh u vo cho c 3 b tin khuch i. Tuy nhin mt hn ch ca n l cng nh phn ln cc b khuch i c rng bng tn cao khc, h s khuch i ca n c c nh l 2.



Hnh 17:s thc hin khuch i

Hnh 18:S khi bn trong ca EL4332

3.1.4 iu khin logic

Nhng DSO trc c dng nhng con chip bn dn thit k v lm chng iu khin th ch dng cc PLA (Programmable Logic Devices). Th nhng nhng con chip ny c tch hp thp v khng tha mn nhng nh cu s dng ngy cng cn tc cao nn n dn b thay th.



c c tc cao p ng c cc yu cu ng dng v o cc tn s cao th hin nay ngi ta thng dng cc chip FPGA thc hin. Chng c dng nh tri tim ca c h thng. Bi v chng c tch hp rt cao nh trnh by chng 1 nn chng c th m nhim nhiu nhim v v hn th na vi nhng tnh nng ca n ta c th d dng lp trnh v cu hnh n thc hin nhng yu cu ca ng dng. Chnh v th chng ta s gim c kch thc ca mch bi tt c vn iu khin u nm con chip FPGA. iu khin cc khi khc trong mch ca

DSO th ta c th chng trnh ha cho FPGA n thc hin nhim v ny. Cng bi do chng trnh ha cho FPGA ngy nay rt d dng vi cc ngn ng nh VHDL hay verilog HDL cng vi cc chng trnh ca Altera. Hn na ngy nay gi thnh ca FPGA ngy cng gim mch v c rt sn trn th trng cc linh kin bn Vit Nam.

Di y l cc s logic ca chip FPGA FLEX 8K ca Altera

Hnh 19: S khi ca FLEX 8K



Hnh 20:S khi logic ca FLEX8K

Ta c th thy trn hnh v th cc chn I/O u c b ch xung quanh chip v chng c k ni vo cc thanh phn logic v cc LUT ca chip, chng hp thnh cc ct cc hng v thng qua cc mng kt ni ben trong chip. V cng ging nh tt c cc chip FPGA khc n cung cp nhng xung nhp tn s nhanh u ra v thi gian nhanh ti ni ly u vo. y mi LAB(Logic Array Block) l gm 8 LE (logic element ) cung cp 4 tn hiu iu khin v mi tn hiu iu khin c th iu khin 8 LE. Trong 4 tn hiu iu khin ca LAB th trong c 2 tn hiu c th c s dng ging nh cc clock v 2 tn hiu cn li c th c s dng nh tn hiu reset v enable.Nhng tn hiu iu khin c th ly t tn hiu u vo ca ta.

Chip FPGA ca Altera l EPF8282A-84, l mt trong nhng dng chip ca h FLEX 8K. N l 1 chip 84 pin PLCC vi 68 chn c th kt ni I/O . Loi ny ph hp vi ng dng hn v c nhng li th m con chip c th c lp pht trin d dng. Do bn cht ca FPGA, chng c th hot ng tc no l ph thuc vo vic thit k m chng thc hin. Mc d chip c chn l loi c tc chm nht nhng n vn c kh nng vn hnh my m ln mc trn 80MHz. Cng nh tt c nguyn l thit k m FPGA s thc hin vn hnh mc 50mHz hay thp hn th n l .



FLEX 8K l thit b cung cp nhng ng dng rng ri nh x l tn hiu s, dng cho nhng vn hnh m c ng d liu rng v bin i d liu. Trong thit b ny c nhng la chn cho giao din bus, tch hp cc TTL c bit l iu khin vi tc cao. Nhng sn phm m c s chn ln c th tch hp c ti 32 b mutiple trong mt thit b.

FLEX 8K cung cp 4 b u vo chuyn dng cho vic ng b iu khin tn hiu cng vi tr ti ln. Mi chn I/O c kt hp mt thanh ghi trn mt ngoi ca thit b. Ging nh u ra th thanh ghi cng c nhng loi c xung ng h nhanh m bo vic ra tn hiu nhanh chng v chng c nhng thit t nhanh v mt thi gian. Hu ht cc FLEX 8k c cu hnh cng vi cc kin trc CMOS SRAM. N c th cu hnh lng d liu c lu tr trong chun cng nghip. N c th cu hnh vic lu tr song song trong hay cu hnh ni tip trong cc EEPROM hoc cung cp nhng d liu bng iu khin h thng. Vic cu hnh ny c th cho php lu tr d liu nn ti 32K x 8 bit hoc ln hn trong cc EPROM. Hn na chng c th ly t RAM ca h thng cung cp nhng d liu cn thit cho n hot ng

Chng ta c th dng cc cng c phn mm nh MAX+PLUS II hay QUATUS II cu hnh chng theo nhng ng dng mong mun ca ngi dng. cu hnh chng th tt nhin chng ta phi bit mt trong nhng ngn ng l VHDL v Verilog HDL lp trnh m t phn cng cn thc hin.

3.1.5 Giao tip vi my tnh

C mt s tu chn cho giao giao tip gia DSO vi PC: Serial Port Parallel Port USB ISA PCI

Do 1 lng tng i ln d liu c lu gi trong DSO, cng ni tip ko c

tnh n bi thi gian yu cu download d liu vo PC ko th chp nhn thi gian di do tc truyn d liu ca cng ni tip chm. USB cng ko thc t v tnh phc tp ca n bi v vit chng trnh iu khin cho USB rt phc tp. Tuy rng hin ny tt c cc PC u c cng USB th nhng cu hnh c USB trong FPGA rt kh. Mc d nhanh nhng c PCI and ISA u i hi s kt ni bn trong ti PC v



v th rt kh c th ci t v lm cho thit k thm phn phc tp do phi lm mch PCI . Cng song song c chn v n c tc chuyn i d liu tng i cao v d dng pht trin thit b, d s dng v ang hin din trong cc my tnh bn tuy rng trong thi gian gn y c nhng my laptop th khng c cng ny nhng m n vn c s dng rt rng ri do thc hin n gin, lm cho DSO c dng trong nhiu lnh vc v cng c linh c ng.Hn na tc truyn ca cng song song c th chp nhn c trong thit k ca ng dng ny.

n gin v tng thch vi thit k v nhu cu s dng th ch hai chiu chun c quyt nh s dng, ci ny th c sn t thi nhng chip 386 v tng thch vi hu ht cc chun c trong my tnh hin nay. N cho php rng byte chuyn n hng khc v c thm 5 line u vo (Status lines) v 4 line u ra (Control lines). Vi cc thit lp chun v tng thch th DSO cho php ngi s dng la chn a ch thch hp cho cng song song c bit. V ch c 3 a ch c th c s dng nn iu ny l tng i d dng. iu ny c bit c ch nu PC ang

s dng c nhiu cng.

3.2 THIT K CHI TIT

3.2.1 Cu hnh np vo FPGA

V FPGA da trn nn SRAM nn n khng th lu chng trnh iu khin c ngay trong chip bi khi mt ngui in cung cp cho n th chng tnh khng cn na chnh v th n phi c chng trnh ho mi ln h thng khi ng li. gii quyt iu ny th phng thc thch hp nht cho ng dng ny l phng thc Active Serial. Phng thc ny bao hm c vic kt ni 1 serial EEPROM (E2) ti FPGA v c thun li l ch yu cu 1 chn I/O s dng. 2 kt ni cn li ti E2 c dnh cho cc chn cu hnh. Hn na cc chn cu hnh c ni cao hay thp l dng ch lc cu hnh no ang c s dng. Chnh v th m ta c th gi c chng trnh iu khin nu mt ngui cung cp cho DSO, v tit kim s chn ca FPGA v c th dng chng vo cc ng dng khc. Khi khi ng li th chng trnh s c np vo chip FPGA thng qua chn JTAG ca FPGA v ta li c mt DSO, thi gian ny c tin hnh rt nhanh m to cm gic nh khng c g.



Bng cch s dng b hp knh kt ni E2 ti FPGA v khi ta c th hoc c th c kt ni ti FPGA hoc ti programming header trn bo mch. V th c th lp trnh li chng trnh iu khin cho FPGA trong khi chng trnh c vn trong bn mch v DSO vn ang hot ng. u vo c chn ti b hp knh c y mnh bi 1K in tr v c kt ni ti ISP header. Khi ta np li chng trnh vo E2 th khi chn c t ng ni t trong thi gian np li vo trong E2 v c y vo chip FPGA trong thi gian sau khi khi ng li. Vic ny lm chuyn E2 t ch c kt ni ti Altera thnh c kt ni ti programmer. Sau khi vic lp trnh hon tt, ngi s dng ch phi np li hay reset li DSO np li v bo mch l c th s dng li DSO vi nhng tnh nng c cp nht d liu cu hnh mi t chip b nh.

3.2.2 Ch tin trigger

Vic ghi d liu trc im trigger rt hu ch khi chng ta d li h thng. thc hin vic ny bng cch ta cho DSO ghi nhng tn hiu lin tc i vo, tin trnh ghi d liu ny c kt thc khi 1 xung (pulse) trigger c d thy trong h thng. Ni dung d liu s c ghi vo b nh ti thi im trc ca im trigger c d thy. Qu trnh ny c thc hin bng cch iu khin thi gian ca c hai tin trnh d tm im trigger v khi s kt thc vic ghi d liu khi im trigger c d thy trong tin trnh.

Vic ny c thc hin cng vi 1 b m (counter) 19bit l mt kha t tn hiu mu ging nh FIFO, v vy khi gi tr ca counter bng ln a ch ca b nh th vic ghi c dng li.Gi tr ca nhng sn trc trigger c th c thit t bi pre-loading gi tr counter l mt gi tr gia 0 (khng tin trigger) v 393216 (c ca b nh v l ln nht ca pre-trigger). S 393216 l 0x60000 trong h HEX, iu c ngha l s logic duy nht l 2bit u tin ca counter c dng dng vic ghi.

D liu c bt u ghi ti bt k a ch no ca b nh m thang ghi a ch tr ti nhng khi bt u ghi ti im ny ta phi ghi tun t k t . Khi thc hin m tip counter 19bit ln th hai .N c s dng nhn dng qu trnh tip theo v li bt u ghi vo b nh t a ch nh u tin, d liu s c ghi ln nhng d liu c trong b nh trc . B counter c reset li ti cng mt thi im ging nh im bt u ghi ti FIFO v chy t tn hiu ly mu u tin, v vy



gi tr c lu tr nu counter c gi tr nh hn khng gian ca b nh nu bng th n s c reset v im bt u v sau l bt u im ghi li ti im u ca b nh. Trc khi d liu c truyn ti my tnh gi tr ca counter c s dng c tun t nhng d liu c trong b nh nh hnh 21 pha di:

B counter c reset li khi gi tr m ca n l ln hn c ca b nh. Bi v counter bao gm s zero n s m ti 0x60001, theo l thuyt b counter s c reset v im bt u khi n m ti s ln nht c th v c ng b cng vi thi im ghi (y l hiu ng cht dn). Tt c qu trnh ny c thc hin v x l bn trong mt con chip FPGA.

Hnh 21: S sp xp ca b nh

3.2.3 D im trigger

Trigger unit l n v thc hin bn trong chip FPGA n c nhim v, gim st c hai knh cho gi tr im trigger (ging nh hnh di y) . Tt c nhng s t c lu tr l ln hn, bng hay nh hn gi tr ca mi thanh ghi n m bo rng mi thanh ghi khng b trn khi lu tr. Bng cch thay i gi tr ca mi thanh ghi c ngi s dng c th thay i mc ca trigger. Di y l bng chn l thc hin mi trigger unit

Bt u ca b nh

Kt thc Bt u Gia

Bt u Gia Kt thc

Bt u ghi

im trigger

Trc khi sp xp Kt thc ca b nh

Sau khi sp xp



Khng phi u ra t ADC m cng khng phi u ra t logic buffer m n c ch i thay i chnh xc ti cng mt thi im gi tr c th xut hin trn bus. V d nh vic thay i t 12 ti 10 v gi tr 14 xut hin trong bus, ging nh m t di y.

N c th xut hin khi mt sn trigger. Gii php cho vic ny l xung clock phi ng b d li v vy u ra t trigger unit c chn l mu duy nht khi d liu

trn bus.Chng ta thc hin bng cch t mt trigger D ngay ti u ra ca mch trigger ng b xung nhp h thng ny v thu c mt tn hiu ra l ng b..

Trng thi cui cng trong n v d im trigger chuyn i cp trigger di hn bnh thng bng trng thi u tin trong sn trigger.Cng vic hon thnh bng cch duy nht l chuyn tip 1 nu ng trigger c gi tr 0, v vy m u ra duy nht mc cao khi trong c s truyn t thp ti cao v xut hin sn. Bng



cch thit t ti trig-sel bus ti 0x3 c ngi s dng khng cho php trigger v bt u qu trnh ghi trc tip.

3.3.4 B to xung

Vic to ra xung clock rt hu ch bi n c th thay i tn s ly mu, cho php ngi s dng ti vic chuyn i di qu trnh ghi li tn s ly mu. Trong h thng chnh xung clock cung cp bi tn s 50MHz TTL ca my to xung, n c dng bng tinh th thch anh. l c cu hnh bn trong chip FPGA ni n c chi tn. y ta c th chia tn theo bng cch dung mt b m counter 5bit

khi ta s thu c tn s mi c t l l l ,1/4,1/8,1/26,1/32 so vi tn s h thng.Chng ta s dng mt b hp knh chn tn s thch hp cho xung clock ca DSO, ta c th thy trng hnh.

cung cp cng tn s ly mu cho hai knh ta phi cung cp cho chng lch nhau 1800 m bo c tn hiu ly mu tt, v vy ta c th dng mt mch not cung cp cho mt thanh ghi dch.

Rt nhiu thit b trong FPGA v c hai FIFOs cn truyn d liu ti PC v vy thc hin iu ny ta cn s dng bus ba trng thi(tri-state bus), n c biu din di hnh sau:

Hnh 22: BUS d liu ra

Bi v vic iu khin trong FPGA l nh hng chn trn mi chip m v n cng cho php u ra (/OE) trn FIFOs, n hot ng ging nh mt bc m trung gian kt ni gia chng trnh xung t d liu khi c hai cng xut d liu ra bi v bus ch cho mt d liu ra trong cng mt thi im cc u ra cn li u c mc tr khng cao. Chng ta dng buffer chun l 74LS245, bi v in dung k sinh

Cng song

song

B m

FPGA FIFO A FIFO B

Bus ba trng thi



ca n thp hn cng song song m y chng ta dng cng song song giao tip vi my tnh. Ging nh l chip m cc chn ca n cng c th thay i d dng nu n b h.

Bus ba trng thi gia ADCs v m logic th c kt ni cng c nhng tnh cht iu khin nh bus ca cng song song, trong u ra mt ADC v m logic ti mt bus m c hai FPGA v FIFO cng kim sot.

Hnh 23: S logic ca 74LS245

3.3.6 Giao din logic cng song song

iu khin logic ph thuc vo rt nhiu yu t nh cc ng iu khin thit t h s chia tn, im trigger.trong c to ra bng giao din logic cng song song. 4bit u tin ca bus iu khin cng song song c s dng ging nh bus d liu. D liu trn bus c cht li trong thanh iu khin bng cc xung cn li ca ng iu khin, chn li nhng tn hiu khng bnh thng trn cng song song xut hin bn trong DSO. u ra ca con cht ny c cu hnh vo li vo ca mt b gii m ti vic tng ln s ng c th. Mt vi ng ny l c s dng cht d liu t bus d liu chnh ca cng song song bn trong mt thanh ghi 4



hoc 8 bit. N cung cp tt c ng iu khin c th c. Nhng ng iu khin cn li ca b m ha c s dng cho xung c FIFO (RCLK) v cho php u ra trn bus t FPGA.

3.3.7 iu khin ADC

Khi DSO l c mt knh th c hai ch u ra l l tn hiu xung PAM ging nh tn hiu s v tn hiu u vo l tn hiu tng t c xen k nhau. Bt k s khc nhau no ca tn hiu u ra cng gy ra nhiu, ging nh s xen k ca mu tn hiu s c s khc nhau ti gi tr hin thi nu c ni dung ca tn hiu tng t u vo. S chuyn i tn hiu tng t thnh tn hiu s ph thuc vo 2 gi tr tham chiu ca in p (1 cho bin v 1 cho th offset). N c quyt nh s dng tn hiu tham chiu bn ngoi nh l xy dng mt ci ADC, n ngha l theo l thuyt th n ngha l s cu hnh chuyn i c hai yu t ca in th, y cao ngha l chng ta c th ly ngay tn hiu bn ngoi l cc ng logic a ra cng song song, n thng c nhiu l nh nht.

Mc d c th tm thy s khc bit v bin cung vi s khc bit v u ra v bng thng ln. V l do ny n c quyt nh s dng mt kt thc khi in p l 2.5V th cu hnh trong ADC th u vo c th thay i 0.5V ni m VDC l dc ca dng mt chiu. iu khin ca u vo ca ADC th phi tun theo cc cng thc sau:

0.5



Chng 4

CHNG TRNH V M PHNG TRN KIT DE2

4.1 TNG QUAN V KIT DE2 V CHIP CYCLONE II

Bi v thi gian thc hin ti ngn nn em khng lm ra c mch em ch m phng trn Kit pht trin DE2 ca Altera vi h FPGA ca hng ny l Cyclon II vi chip l EP2C35F672C6. Vi dng chip ny th ti nguyn ca n ln hn rt nhiu so vi FLEX 8K ca hng.

Hnh 24: S khi ghp ni gia Cyclone II vi cc thnh phn trn KIT



Hnh 25:s cc thnh phn trn kit DE2

Hnh 26:S khi ca Cyclone II

Chp Cyclone II cn c ti nguyn rt phong ph trong :

C 33.216 LE: thnh phn nh nht trong chip l thnh phn logic (logic element). Mi LE (Logic Element) c th c cu hnh thnh mt Fip-Flop D,T,JK hay RS. Mi mt thnh phn ny cng c cc u v l data, clock, enable,clear v u ra cng l data. Chng cung c th cu hnh thnh cc thnh phn c bn khc trong mi ng dng. chng cng



c th cu hnh thanh cc LUT (Loop Up Table). s dng cu hnh cc LE thnh cc thanh ghi hay l thnh cc LUT l tu thuc vo ngi s dng lp trnh trn cc phn mm nh QUATUS II. Khi lp trnh xong v download vo chip th chng trnh ca mnh s t ng to ra nhng thanh ghi hay nhng LUT tu thuc vo chong trnh ca mnh.

Hnh di m t qu trnh cu hnh cc LE thnh cc ng dng ca mnh nh mong mun khi lp trnh cc ng dng ca mnh v download vo bn trong chip Cyclone II th chng trnh bn trong s t ng dn cc thnh phn logic ca ta vo chung mt khu vc gim bt ti nguyn. Tuy nhin m bo vic s dng ti nguyn mt cch hiu qu cn phi ph thuc nhiu v k nng lp trnh v thit k ca ngi k s.

Hnh 27:S khi ca LAB

C 105 khi M4K RAM: cc khi M4K ni dung c cha trong cc ct ca M4K cu cc khi b nh, Mi khi ny th bao gm cc u vo l cc thanh ghi c c ghi ng b v u ra l cc c thit k theo ch ng ng. Cc u ra cc thanh ghi c th c y qua nhng cc u vo th khng th lm th c. T cc thnh phn ny ta c th c cc b nh l dual-port hay l sinple-port. Cc b nh y ta c th dng nh RAM hay ROM hay cc b m FIFO. M4K c th h tr cho:



4,608 bit RAM. C th thc hin tn s 250MHz. h tr cho c b nh n cng hay hai cng ring bit. c th cu hnh thnh cc thanh ghi dch, cc b m FIFO. c th cu hnh thnh cc ROM.

Hnh 28:S khi ca M2K RAM

C tng cng 483,840 bits RAM. 4 PLLs (vng kha pha). C 475 chn I/O s dng: tt c cc chn I/O u c gn cng

nhau trn cc banks I/O. Trong Cyclone II th c tt c 4 banks I/O. Trong th bank 2 v banks 4 c th h tr cho cc kt ni vi DDR2 v c th up ti 167MHz/333Mbps v QDR c th p ln ti 167MHz/668 Mbps. Cn cc bank 1 v 3 th ch h tr duy nht cho cc giao din ca SDR v DDR SDRAM. tt c cc bank ca Cyclone II c th h tr cho cc b nh SDR c th o ln hot ng 167MHZ/167Mbps v b nh DDR v c th hot ng 167MHz/333Mpbs.



Hnh 29:S b ch cc thanh chn trn Cyclone II

N c ng gi vi 672 chn.

Chng trnh c th c np trc tip t phn mm QUATUS II xung chp qua mt cp USB.

Ngoi ra trong KIT ny cn c rt nhiu ti nguyn na nh:

C 512 KB SRAM trong c 256 KB a ch v c th cha d liu vi di 16 bit.

C 8MB b nh SDRAM trong trong c th c ti 1 MB a ch v c th cha d liu ln ti 16 bt v c 4 banks tt c.

C 8MB b nh Flash v c th cha d liu c rng bt ti a l 8bits

Ni chung trn KIT ny thc hnh nghin cu v pht tin th rt hu ch.

Bi v phi m phng v lm th nghim trn kt ny v ti nguyn ca con Cyclone II rt nhiu ln ln em dng c RAM trong chip bng cch cu hnh bn trn nh cc tool h tr, em cng th nghim cc ng bng cch lm mt sng SINE gi



lp s vi cc mu l 8 bt. Coi nh y l cc xung PAM c ly mu qua ADC v c kt ni ti cc thnh phn khc trong thit k.

4.2 CHNG TRNH V M PHNG

4.2.1. Chng trnh chnh iu khin DSO

Hnh 30: S khi iu khin ca DSO

Hnh trn ny l s khi tng qut ca b iu khin ca DSO c to ra t phn mm Quatus II sau khi chy chng trnh c vit th n to ra. Phn code ca chng trnh ny c t phn ph lc bn di.

Trong hnh ny c chia thnh cc khi chnh l :khi iu khin logic cng song, khi iu khin FIFO, khi to xung chia tn, khi iu khin d im trigo.



Hnh 31: Dng m phng ca khi chng trnh ca DSO\

Hnh trn l s m phng dng xung khi thc hin chy m phng trn phn mm Quatus II da trn device l chip Cyclone II.

Trong cc tn hin clk l tn hiu clock a vo b chia tn, control l tn hiu u vo c dng iu khin logic cng song song, EXT_TRG l tn hiu a vo iu khin ng b, cc tn hiu LOGIC_INPUTH, LOGIC_INPUTL l cc ng

vo ca ng logic m. Cc tn hiu ra cn li l cc tn hiu iu khin vic chn knh.

Hnh 32: Ti nguyn m khi iu khin dng



Hnh 33: Tn s cao nht m khi ny vic c

Hnh 32, 33 l hnh m t cc ngui ti nguyn m chng trnh ny s dng thc hin cc chc nng, trong ta c th nhn thy ti hnh 32 th chng trnh ny dng ht tt c l 128 LE, 24 thanh ghi v c u ra l 49 chn. Ti hnh 33 th chng trnh ny ch c th hot ng cao nht l tn s 33.92 MHz.

4.2.2 Chng trnh iu khin logic cng song song

Hnh 34: S khi iu khin cng song song



Hnh 35: S dng xung ca khi cng song song

Hai hnh 34, 35 ln lt l s khi v m t dng xung ca chng trnh iu khin cng song song c to ra khi chy chng trnh trn phn mm Quatus II.

T hnh 34 ta c th thy l trong ny c cc khi ln lt l: B gii m, cc b cht, b hp knh u vo, v cc thanh cht d liu u ra. c bit trong ny c mt b bus ba trng thi dng iu khin u vo ly t ng logic hoc l ly t b nh sau khi c i qua mt con ADC.

4.2.3 Chng trnh iu khin FIFO

Hnh 36: S khi iu khin FIFO



Hnh ny l m hnh tng qut ca khi iu khin FIFO n c to ra t phn mm Quatus II sau khi chy chng trnh. Code ca phn ny c trnh by trn phn ph lc pha cui kha lun. Trong c cc khi l mt b m counter m ng a ch xc nh b nh c y hay khng a ra quyt nh c tip tc

ghi tip vo b nh hay khng, v c th iu khin cho php c d li b nh ra, trong phn thc hin ny ta cn iu khi tc c v ghi vo b nh. Tip theo l mt b triger counter n dng m im trigger khi i qua xc inh xem c th ghi tip d liu hay l cho d liu c ly lun t phn logic a ti cng song song.

Hnh 37: Dng xung ca khi iu khin FIFO



Hnh 38: Tn s p ng ca control FIFO

Hai hnh 37, 38 l m t nhng ti nguyn m nguyn phn ny s dng. Hnh 38 m t l phn ny th lm vic c tn s cao nht c th l 46.93MHz.

4.2.4 Chng trnh to dng xung chia theo t l 1/2, 1/4, 1/8, 1/16, 1/32

Hnh 39: S khi b chia tn



Hnh 40: Dng xung m t ca b chia tn

Hnh 39 v 40 l s khi v dng xung ca khi chi tn. Khi ny c nhim v tao ra tn s ly my thch hp cho c khi iu khin ca DSO. Theo thit k th trong phn ny c th thc hin mt php chia tn thnh , , 1/8, 1/16, 1/32 ln tn s h thng a vo bng mt b m counter 5 bit.

Dng xung m t phn ny c m t trong phn hnh 40 sau khi i qua mt b hp knh v u ra l tn s chia, b hp knh ny c chn sel 3bit chn u ra trong khi sel l 000 th chn khng chia, 001 th chia , 010 chia , 011 chia 1/8, 100 chia 1/16, 101 chia 1/32.

4.2.4 Chng trnh d im trigger

Hnh 41: S khi ca b d im trigger



Hnh 42: M phng dng xung ca d im trigger

Hai hnh 41 v 42 l s khi v dng xung m phng c to ra khi chy chng trnh trn phn mm Quatus II.

Hnh 41 l s khi iu khin khi tm im trigger. Phn ny c nhim v d tm im trigger ng b cho khi iu khin ca mnh.

Hnh 42 l dng xung m t ca chng trnh ny trong u ra ca n l triger_out.



Kt lun

Vi kt qu ny, em bc u xy dng mt b iu khin s dng trong my dao ng s c nh da trn cng ngh FPGA. c bit qua qu trnh nghin cu v thc hin ti em tch lu c nhiu kin thc b ch:

Bc u nm c kin thc c bn v FPGA v ngn ng m t phn cng VHDL.

Hiu c nguyn tc hot ng v cu to ca mt my dao ng s c nh c xy dng t cc mch tng t v cc mch s.

Nm c cch s dng v lp trnh bng phn mm QUATUS II, v hiu cch np v chy mt chng trnh trn kit pht trin DE2.

Hiu c t tng ca lung thit k trn cng ngh FPGA.

Xy dng cho bn thn mnh tnh k lut v cch hc tp nghin cu khoa hc, cch t duy h thng khi thc hin mt ti.

Nhng iu cn hn ch v hng pht trin ca ti.

Do thi gian thc hin ti c hn nn em mi ch lm c b iu khin l mt khi trong my hin sng.

Chng trnh mi ch c m phng trn phn mm Quatus II ch cha c lm thc t nn vn cn nhiu hn ch.

Trong thi gian ti sau khi tt nghip em s tip tc hon thin ti ca mnh c c mt sn phm ca mnh c thit k trn FPGA.



PH LC -----Chng trnh chnh iu khin DSO

library ieee; use ieee.std_logic_1164.all; entity main is port( clk :IN STD_LOGIC; CONTROL :IN STD_LOGIC_vECTOR(3 DOWNTO 0); LOGIC_INPUTL :IN STD_LOGIC_VECTOR(7 DOWNTO 0); LOGIC_INPUTH :IN STD_LOGIC_vECTOR(7 DOWNTO 0); EXT_TRIG :IN STD_LOGIC; STATUE :OUT STD_LOGIC_VECTOR(4 DOWNTO 0); FIFO_A_W_CLK :OUT STD_LOGIC; FIFO_B_W_CLK :OUT STD_LOGIC; FIFO_W_EN :OUT STD_LOGIC; FIFO_W_RST :OUT STD_LOGIC; FIFO_A_OE :OUT STD_LOGIC; FIFO_B_OE :OUT STD_LOGIC; FIFO_R_CLK :OUT STD_LOGIC; FIFO_R_RST :OUT STD_LOGIC; BUF_DIr :OUT STD_LOGIC; AB_CHANEL_MEGA :OUT STD_LOGIC; LOGIC_BUT_H_OE :OUT STD_LOGIC; ADC_B_OE :OUT STD_LOGIC; LOGIC_BUT_L_OE :OUT STD_LOGIC; ADC_A_OE :OUT STD_LOGIC;



DATA :INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END; ARCHITECTURE CHON OF MAIN IS signal poit1 :std_logic_vector(18 downto 0); signal dataout :std_logic_vector(7 downto 0); signal pre_trig_load,clkdiv:std_logic_vector(2downto 0); signal trig_sel,trig_load:std_logic_vector(1downto 0); signa:buf_dir1,fifo_r_clk1,rec_en1,init1,fifo_r_rst1,fifo

_a_oe1,fifo_b_oe1,high_speed1,fifo_a_logic1,trig_falling1,fifo_b_logic1 :std_logic;

signal triggerout1,clkout,mem_full2,fifo_w_en2, fifo_w_rst2,fifo_w_clk2 : std_logic; component giaotiep port ( dieukhien :in std_logic_vector(3 downto 0); poit :in std_logic_vector(18downto 0); data :out std_logic_vector(7 downto 0); data_output :out std_logic_Vector(7 downto 0); pre_trig_load :out std_logic_vector(2 downto 0); trig_sel :out std_logic_vector(1 downto 0); trig_load :out std_logic_vector(1 downto 0); clkdiv :out std_logic_vector(2 downto 0); buf_dir :out std_logic; fifo_r_clk :out std_logic; rec_en :out std_logic;



init :out std_logic; fifo_r_rst :out std_logic; fifo_a_oe :out std_logic; fifo_b_oe :out std_logic; high_speed :out std_logic; fifo_a_logic :out std_logic; trig_falling :out std_logic; fifo_b_logic :out std_logic ); End component COMPONENT coltron_fifo port( trig :in std_logic_vector(7 downto 0); trig_load :in std_logic_vector(2downto 0); trigger :in std_logic; rec_en :in std_logic; init :in std_logic; clk :in std_logic; mem_full :out std_logic; fifo_w_en :out std_logic; fifo_w_rst :out std_logic; fifo_w_clk :out std_logic; poit :out std_logic_vector(18 downto 0) ); END COMPONENT;



---------- COMPONENT trigger_unit port ( trig_load :in std_logic_vector(1 downto 0); trig_value :in std_logic_vector(7 downto 0); logic_inputL:in std_logic_vector(7 downto 0); logic_inputH:in std_logic_vector(7downto 0); trig_falling :in std_logic; fifo_a_logic :in std_logic; fifo_b_logic :in std_logic; high_speed :in std_logic; ext_trigger :in std_logic; clk :in std_logic; rec_en :in std_logic; trig_sel :in std_logic_vector(1downto 0); trigger_output :out std_logic ); END COMPONENT; -------- COMPONENT xungnhip port ( CLOCK_50,clear :in std_logic; sel :in std_logic_vector(2downto 0); clk :out std_logic



); END COMPONENT; --------- begin t1:giaotiep port map (control(3downto0), poit1(18 downto 0), DATA(7 downto 0),dataout(7 downto 0), pre_trig_load(2 downto 0),

trig_sel(1 downto 0), trig_load(1 downto 0),clkdiv(2 downto 0),

buf_dir1,fifo_r_clk1,rec_en1,init1,fifo_r_rst1,

fifo_a_oe1,fifo_b_oe1,high_speed1,fifo_a_logic1, trig_falling1,fifo_b_logic1); ---------------- FIFO_A_OE



rec_en1,init1,clkout,mem_full2, fifo_w_en2,fifo_w_rst2,fifo_w_clk2,

poit1(18downto 0)); --------------------------------- FIFO_A_W_CLK



port ( dieukhien :in std_logic_vector(3 downto 0); poit :in std_logic_vector(18downto 0); data :out std_logic_vector(7 downto 0); data_output :out std_logic_Vector(7 downto 0); pre_trig_load :out std_logic_vector(2 downto 0); trig_sel :out std_logic_vector(1 downto 0); trig_load :out std_logic_vector(1 downto 0); clkdiv :out std_logic_vector(2 downto 0); buf_dir :out std_logic; fifo_r_clk :out std_logic; rec_en :out std_logic; init :out std_logic; fifo_r_rst :out std_logic; fifo_a_oe :out std_logic; fifo_b_oe :out std_logic; high_speed :out std_logic; fifo_a_logic :out std_logic; trig_falling :out std_logic; fifo_b_logic :out std_logic ); end ; architecture chon of giaotiep is signal

outmux,outtribus,q1,q2,q3,q4:std_logic_vector(7downto 0); signal t1:std_logic_vector(1 downto 0); signal a1,a2,a3,a4,a5,a6,a7:std_logic; signal out1:std_logic_vector(2 downto 0);



-------------- component hopkenh port( a,b,c :in std_logic_vector(7 downto 0); sel :in std_logic_vector(1 downto 0); q :out std_logic_vector(7 downto 0) ); end component; ----------- component giaima PORT ( data : IN STD_LOGIC_VECTOR (2 DOWNTO 0); eq1 : OUT STD_LOGIC ; eq2 : OUT STD_LOGIC ; eq3 : OUT STD_LOGIC ; eq4 : OUT STD_LOGIC ; eq5 : OUT STD_LOGIC ; eq6 : OUT STD_LOGIC ; eq7 : OUT STD_LOGIC ); end component; ----------- component reg3 port ( en :in std_logic; a :IN std_logic_vector(2 downto 0);



q :out std_logic_vector(2 downto 0) ); end component; ---------- component reg port ( en :in std_logic; a :in std_logic_vector(7 downto 0); q :out std_logic_vector(7 downto 0) ); end component; ------------------ component tri3 port ( a :in std_logic_vector(7 downto 0); en :in std_logic; q :inout std_logic_vector(7downto 0) ); end component; ---------- begin mux1: hopkenh port map("00000"&poit(18 downto 16),

poit(15 downto 8),poit(7 downto 0),t1, outmux(7 downto 0));



chot1: reg3 port map(dieukhien(0), dieukhien(3 downto 1),out1(2 downto 0));

gm: giaima port map(out1(2 downto 0),a7,a6,a5,a4,a3,a2,a1); busstate:tri3 port map(outmux(7 downto 0),a1,

outtribus(7 downto 0)); chot2:reg port map(a2,outtribus(7 downto 0), data_output(7 downto 0)); --data_output(7 downto 0)



trig_load



signal a:std_logic_vector(18 downto 0); signal t1,t2,t3,t4:std_logic; ------------- component triggercounter port(

trig :in std_logic_vector(7 downto 0); clk :in std_logic; counter_en :in std_logic;

load :in std_logic_vector(2 downto 0); mem_full :out std_logic ); end component; ------------ component counter19 PORT ( clock : IN STD_LOGIC ; cnt_en : IN STD_LOGIC ; sset : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (18 DOWNTO 0) ); end component; ------------ begin t4



(trig(7 downto 0),clk,t2,trig_load(2 downto 0),t1); dem19:counter19 port map(clk,not t1,t3,a(18 downto 0)); poit



); end component; ------hop kenh------- component hopkenhtaoxung port ( clk1,clk2,clk4,clk8,clk16,clk32 :in std_logic;

sel in std_logic_vector(2 downto 0); clock_out :out std_logic ); end component; begin

t1:taoxung port map(CLOCK_50,'1',div0,div1,div2,div3,div4); t2:hopkenhtaoxung port map(CLOCK_50,div0,div1,div2,div3,div4,

sel(2 downto 0),clk); end chon;

-------Chng trnh d im trigger

library ieee; use ieee.std_logic_1164.all; entity trigger_unit is port ( trig_load :in std_logic_vector(1 downto 0);

trig_value :in std_logic_vector(7 downto 0); logic_inputL :in std_logic_vector(7 downto 0); logic_inputH :in std_logic_vector(7 downto 0);

trig_falling :in std_logic;



fifo_a_logic :in std_logic; fifo_b_logic :in std_logic; high_speed :in std_logic; ext_trigger :in std_logic; clk :in std_logic; rec_en :in std_logic;

trig_sel :in std_logic_vector(1 downto 0); trigger_output :out std_logic ); end; architecture chon of trigger_unit is signal chotout1,chotout2:std_logic_vector(7 downto 0);

signal a1,a2,a3,b1,b2,b3,q11,q12,q13,q14,q2,q3,s:std_logic; signal outmux21,outmux22,outmux3,outtrigD:std_logic; -------------- component mux2 port( a,b :in std_logic; sel :in std_logic; q :out std_logic ); end component; -------- component mux3 port( a,b,c :in std_logic; sel :in std_logic_vector(1 downto 0);



q :out std_logic ); end component; ------- component reg port ( en :in std_logic; a :in std_logic_vector(7 downto 0); q :out std_logic_vector(7 downto 0) ); end component; ------- component trigD port ( a :in std_logic; clk,clear :in std_logic; q :out std_logic ); end component; ------- component sosanh PORT ( dataa :IN STD_LOGIC_VECTOR(7 DOWNTO 0); datab :IN STD_LOGIC_VECTOR(7 DOWNTO AeB : OUT STD_LOGIC ; AgB : OUT STD_LOGIC ;



AlB : OUT STD_LOGIC ); end component; -------- begin chot1 :reg port map(trig_load(0),

trig_value(7 downto 0),chotout1(7 downto 0)); chot2:reg port map(trig_load(1), trig_value(7 downto 0),chotout2(7 downto 0));

sosanh1:sosanh port map(chotout1(7 downto 0), logic_inputL(7 downto 0),a1,a2,a3);

sosanh2:sosanh port map(chotout2(7 downto 0), logic_inputH(7 downto 0),b1,b2,b3);

---------------------- t1:mux2 port map(a2,a3,trig_falling,outmux21); t2:mux2 port map(b2,b3,trig_falling,outmux22); ------------------------ q11



s

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