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A DUAL-MODE FAULT-DIAGNOSIS TECHNIQUE FOR
ANALOG NON-LINEAR ELECTRONIC SYSTEMS
by
QUOC DINH NGO, B.S.
A THESIS
IN
ELECTRICAL ENGINEERING
Submitted to the Graduate Faculty of Texas Tech University in
Partial Fulfillment of the Requirements for
the Degree of
MASTER OF SCIENCE
Approved
Accepted
May, 1980
ACKNOWLEDGEMENTS
I am deeply indebted to Professor Richard Saeks for his direction
of this thesis and to the other members of my committee. Professor
Larry M. Austin, and Professor John F. Walkup, for their helpful com
ments.
11
TABLE OF CONTENTS
ACKNOWLEDGEMENTS ii
LIST OF TABLES iv
LIST OF FIGURES v
I. INTRODUCTION 1
II. THEORETICAL DEVELOPMENT 6
III. EXAMPLES 9
Multi-Frequency Test (Mode 1) 10
D. C. Analysis (Mode 2) 12
IV. COMPARISON OF FAULT-DIAGNOSIS TECHNIQUES FOR NON-LINEAR SYSTEMS 20
Method of V. Visvanathan and A. Sangiovanni-Vincentelli 20
Method of Nasrollah David and
A. N. Wilson 21
Dual-Mode Fault-Diagnosis 21
Summary 21
V. FAULT-DIAGNOSIS ALGORITHM FOR TRANSISTORS 22
VI. EXPERIMENTAL RESULTS 25
Case Case II. A Bad Linear Component in the Circuit 28 Case III. A Bad Transistor in the Circuit 28
Case IV. Transistors Q^ and Q-
are Faulty 32
VII. CONCLUSION 34
REFERENCES 35
APPENDIX TEST POINT SELECTIONS 37
• • •
m
LIST OF TABLES
Table
1 Measure of Testability for the Single-Transistor Amplifier Circuit of Figure 1 11
2 Transistor Operating Modes 22
3 Comparison of Measured and Claimed Values of Resistors 26
4 Test Point Measurements for All Cases of the Experiment 26
5 Transistor Operating Conditions for the Experimental Case I 27
6 Transistor Operating Conditions for the Experimental Case II 29
7 Transistor Operating Conditions for the Experimental Case III 31
8 Transistor Operating Conditions for the Experimental Case IV 33
TV
LIST OF FIGURES
Figure
1 Fault-Diagnosis by the Dual-Mode Technique 4
2 Single Transistor Ampli f ier 9
3 Cascode Ampl i f ier 13
4 Direct-Coupled Two-Stage Ampli f ier 15
5 Four Transistor Video Amplif ier 17
6 Simpl i f ied Single Transistor Ampli f ier 20
7 Fault-Diagnosis Algorithm for N-P-N Transistors 23
8 Collector to Base Characteristics of a Faulty Transistor 30
CHAPTER I
INTRODUCTION
The advent of microelectronics, the ever-increasing complexity and
compactness of electronic circuits, together with a need for higher
reliability in space, military, and even comnercial projects, has
brought new problems to industry; test and diagnosis of electronic
circuits is one of them.
Presently, a printed circuit board may include several hundred
components; modular construction as well as small geometrical dimensions
make impractical, even infeasible, and certainly uneconomical, the
conventional test methods based on classical laboratory equipment such
as signal generators, meters, oscilloscopes, and probes.
In either the analog or digital case, fault detection and location
in electronic systems is generally performed via measurements at a
limited number of input and output connections. These measurements are
then executed by computer test programs to provide diagnosis.
Until now, algorithms for automatically generating test programs
have been concerned mainly with digital circuits. Analog circuits, on
the other hand, have received far less attention, due to several
reasons: Analog systems are frequently non-linear, and the values of
the parameters of the elements exhibit large deviations [6]; analog
signals are inherently more complex than digital signals. They occur
continuously in time, rather than at discrete times, and their values
have infinite resolution, instead of being truncated into a finite
number of bits; most importantly, digital automatic test generation has
been successful due to the simplified modeling at the logic gate or
higher level, rather than the internal parameter level as in the case
of analog systems. As a result, most analog automatic test generation
and fault isolation techniques require a large computational capability
on the ATE or off-line computers [5].
Several e f fo r t s have been made to attack the f au l t diagnosis
problem in analog c i r c u i t s . The multi-frequency technique for f au l t
analysis in general l inear dynamical systems was developed by N. Sen
and R. Saeks [ l ] . [7] , [ 8 ] , [9] , was considered to be more e f f i c i e n t and
advanced in terms of output select ion and reduction. By varying the
test frequency at the same test points, the number of test points can
be reduced s ign i f i can t l y compared to the case of single frequency
measurements.
This technique has been generalized to non-linear analog systems
by l inear iza t ion of the non-linear components. Unfortunately, the
l inear iza t ion concept f a i l s in many cases [lO] . For example, consider
ing a single-loop c i r c u i t consist ing of a power supply, a res is to r ,
and a tunnel diode. At a given b ias, the non-linear character is t ic of
the tunnel diode has a par t icu lar slope. With the breakdown of the
bias res is to r , the l inear iza t ion of the non-linear character is t ic of
the tunnel diode at the new biasing point w i l l be d i f f e r e n t , and the
diode w i l l appear to be fau l t y i f one ignores the fact that the diode
is operating at a d i f fe ren t bias.
Recognizing the l inear iza t ion problem in multi-frequency tes t ,
the faul t-diagnosis of non-linear analog systems in the D.C. case was
studied by V. Visvanathan and A. Sangiovanni-Vincentelli 2 , and N.
David and A.N. Wilson [3 ] at the component parameter l eve l . These tech
niques have these disadvantages: the required number of test points is
more than required by the mult ip le frequency technique; the tremendous
amount of computer time is required to solve yery complicated non-l inear
equations. Since th is is a D.C. t es t , these techniques can only be
applied to memoryless systems ( without react ive components such as
capacitors and inductors ).
The dual-mode technique for faul t -d iagnosis for non-l inear analog
systems is introduced as a compromise between the above approaches.
Mode 1 (A.C. Test): u t i l i z i ng the multi-frequency technique to
search for the fau l t y l inear components, then the fau l ty l inear component
values are calculated. The non-l inear components of the c i r c u i t under
diagnosis are replaced by small signal A.C. or l i near iza t ion equivalent
c i r c u i t s . Therefore, th is A.C. test is performed at the internal
parameter level for both l inear and non-linear components.
Mode 2 (D.C. Test) : th is test is used to diagnose a reduced non
l inear problem a f te r the l inear components are determined in Mode 1.
The nominal values or the fau l t y values given by Mode 1 are used for
computations depending on whether the l inear components are in tolerance
or not. A non-l inear device or element is treated as a blackbox with
inputs and outputs. The task is to f ind the D.C. inputs and outputs or
the operating conditions of the blackbox, not the internal parameters
of the non-linear devices. This approach is compatible to previous
successful techniques in d i g i t a l systems performed at the logic gate l e
vel or higher. The faul t -d iagnosis algorithm is shown in Figure 1 .
The Mode 2 formulation and examples are presented in th is thesis
together with a comparison with exist ing techniques in faul t -d iagnosis
for non-linear analog systems. F ina l l y , an experiment on a four - t rans is
tor ampl i f ier c i r c u i t is conducted to ver i fy the theorect ical solut ions
and to determine the sens i t i v i t y of the dual-mode approach.
START
MULTI-FREQUENCY TEST
(MODE 1)
YES
CALCULATE BAD VALUES
FOR COMPUTATION
IN MODE
2
LINEAR COMPONENT
FAULT-DIAGNOSIS ROUTINE
USE GOOD VALUES
OF LINEAR COMPONENT
FOR COMPUTATION
IN MODE 2
D.C. TEST FOR NON-LINEAR
COMPONENTS ONLY
START MODE 2
Fig. 1 Fault-Diagnosis Algorithm by the Dual-Mode Technique
i NON-LINEAR
FAULT DIAGNOSIS
ROUTINE
REPLACE FAULTY
COMPONENTS
Fig. l Fault-Diagnosis Algorithm by the Dual-Mode Technique
(Continued)
CHAPTER II
THEORETICAL DEVELOPMENT
The theoret ical formulation of the D.C. test for the non-linear
problem is based on the component connection equations [4] :
a = M^ b + M,pU
b = M2 b + M22U
Where u and y represent the vectors of accessible inputs and outputs
which are avai lable to the test systems, a and b represent the compo
nent input and output vectors, respect ively. The relat ionship between
a and b i s :
b = Z a
Although the symbol Z is used, the components are not assumed to be
represented by an impedance matrix. Indeed, hybrid models are used
in most of our examples.
Before the c i r c u i t is analyzed in the D.C. tes t , the capacitors
and inductors, which are assumed to be l inear components, are replaced
by open-circui ts and shor t -c i rcu i ts respect ively.
The component vectors a and b are part i t ioned in to :
a =
'N
b =
N
Where a, and b. are the linear component input and output vectors, and
aj and b^
Therefore:
a^ and bj are the non-linear component input and output vectors
=
" ^ L
_ .|
\
^N
when a linearized model is employed.
The component connection matrix is partitioned accordingly:
^N
J
11
Mil l
M ^ 21
11
"21
" l 2
M ^
M ^22
N
Equation (1) and (2) can be solved simultanously to yield:
«N = [<(\'<) -' "i? <>N ^ [<( [ -<)- "l ^ "12"] ( ) Thus the inputs and outputs of the non-linear devices can be
computed by a few simple matrix operations. These values are checked
against the operating characteristics of the corresponding functional
devices for fault isolation.
The coefficient matrices of (3) and (4) can be pre-computed if
the linear components are not faulty. The matrix Z. should be changed
to incorporate the faulty values of the linear components, if any, to
avoid the computational errors caused by the use of nominal values of
the linear components.
For each pair of non-linear component input-output signals, one
test point is required. For instance, a bipolar transistor can be modeled
with two (2) input-output pairs:
N =
I B
' ' N ^
V
V
BE
CE
Therefore, two (2) measurements must be taken. Non-linear integrated
circuits can be modeled in the same manner. The number of tes t points
required in this mode goes up linearly with the number of non-linear devices in systems.
8
The matrix ^2^^^^' ' ^ i i ' ' H l "" " 21 3^'^ singular i f the test
points are not chosen properly. The selection of test points to make
the above matrix non-singular w i l l be discussed in deta i l in the
Appendix.
CHAPTER I I I
EXAMPLES
Single-Transistor Amplifier Circuit
Fig. 2(a) Single-Transistor Amplifier
CI x
• I I I
"1 ^=F
y 0 «Af f B
]^
R
C2
Qv^b'
k 1$ ^ ±1 c.
Fig. 2(b) Small Signal A.C. Equivalent Circuit
10
Multi-Frequency Test (Mode 1) [1], [121
The small-signal A.C. equivalent circuit of the circuit of
Fig. 1(a) is shown in Fig. 1(b). The connection equations associated
with the A.C. or mode 1 test are as follows :
ICl
^ ^
IC y
IC2
VR' VRE
S VCE
^m VRC
VRL
V 0 ICl VR; IE
0 0
0 0
0 0
0 0
0 0
1 0
1 -1
0 0
1 -1
0 0
1 -1
1 -1
1 -1
0 0
1 0
0 0
0
0
0
0
0
0
-1
1
-1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-1
-1
-1
-1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
-1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
-1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
1
0
0
~"
0
0
0
0
0
1
1
0
1
0
1
1
1
0
1
0
"^
VCl
v ^ v ^ vc
y VC2 IR
IRE
s ICE
^ \
IRC
IRl
Vi
Here we initially allow V^ , ICl , VR^ ,and IE to be taken
as test outputs. The measure of testability min is used to extract a
reduced set of test outputs from these options. According to table I
two (2) is the minimum number of test outputs in this example , which
suffices to yield ' min = 0 (perfect testability) or to provide locally
unique solutions for the fault-diagnosis equations .
The test measurements are taken at the two output VR^ and IE
at twelve (12 = n - <?min ) distinct frequencies , where n is the dimen
sion of the parameter vector r .The faulty parameters can be identified
by using the Householder's Formula and the optimization algorithm[13] .
Only the faulty parameter values for the linear components of the circuit
need to be calculated to be included in the calculations in mode 2.
Table 1 Measure of Testability for the
Amplifier Circuit of Figure 1
11
1 »
OUTPUT
^0
ICl
VR'
IE
VQ,IC1
^O'^^A V Q . I E
ICI,VR;^
ICl,IE
VR^,IE
VQ , ICl ,
VQ , ICl ,
^0 ' v^A ' ICl . VR^ .
V^A
IE
IE
IE
VQ , ICl , VR^ , IE
• MIN.
3
2
2
3
0
1
0
2
1
0
0
0
0
0
0
12
D.C. Analysis (Mode 2)
Assuming that the capacitors of the amplifier circuit are not
shorted. They are treated as open-circuits in D.C. test , and removed
from the circui t before Mode 2 analysis begins. The test point measure
ments are chosen at the same test points used in the multi-frequency
test. The connection equations for this circuit in D.C. test are:
VRA
IRB
IRE
IRC
VBE
VCE
VRB
IRE
0
1
0
0
0
0
0
0
-1
0
0
0
1
0
-1
0
0
0
0
0
-1
-1
0
0
0
0
0
0
0
-1
0
0
0
-1
1
0
0
0
0
1
0
0 \
1
1
0
0
0
1
1
0
0
0
0
1
0
1 0
IRA
VRB
VRE
VRC
IB
IC
V+
L
and
IRA
VRB
VRE
VRC
IB
IC
1/RA
RB
RE
RQ
}df
\ N
VRA
IRB
IRE
VRC
VBE
VCE
The n o n - l i n e a r component input and output vectors a ^ and b^ can be
found v ia (3 ) and ( 4 ) :
'N
IB
IC
RA+RB RA.RB
RA+RB
RA.RB
„ 1 1
-. -^
VRB
IRE
" -
RB
RA+RB
0
—
V+
'N
VBE
^_VCEj
-RE-RA.RB PJ\+RB
- R E
-RE r\L.
RC-RE
IB ^
IC .
+
r RB 1 RA+RB
. 1 -
V +
13
Fig. 3 Cascode Amplifier Circuit
The capacitors in the circuit are assumed to be good components.
They are removed from the circuit before Mode 2 diagnosis begins. The
connection equations for the circuit are:
VRl
VRC
IR2
IR3
IRE
VBE2
VBEl
102
ICl
VRE
IRl
IRC
VM
0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
-1
0
0
0
0
1
0
0
0
0
0
0
0
-1
0
0
0
0
1
1
0
0
0
0
0
0
0
-1
0
0
0
-1
-1
0
0
1
0
0
1
0
0
-1
-1
1
0
0
0
1
0
0
0
0
0
0
0
-1
1
0
0
0
0
0
0
0
0
0
-1
0
0
0
0
0
0
0
0
0
0
0
0
-1
0
0
0
-1
0
0
0 1
0 0
0
1
. 1
1
0
0
0
0
0
0
0 r
0 0
0
0
IRl
IRC
VR2
VR3
VRE
IB2
IBl
VCE2
VCEl
V +
14
b =
IRl
IRC
VR2
VR3
VRE
IB2
IBl
VCE2
VCEl
1/Rl
1/RC
R2
R3
RE
df
da
VRl
VRC
IR2
IR3
IRE_
VBE2
VBEl
IC2
ICl
The non-linear inputs and outputs are determined via (3) and (4)
IB2
IBl
VCE2
VCEl
1 RE.R2
-R3
R3+R2
0
-R2.RE
RE.R R3.RE
-RE.R -(R2+R3)RE
0 -R2.RE.RC
0 0
0
0
R2.RE
R2.RE
[VRE"
IR l
IRC
LVM .
RE/(RE+RC)
1/R
1/(RE+RC)
RE/(RE+RC)_
V+
VBE2
VBEl
IC2
ICl
R1(R2+R3) w -R1.R3 ;, " R ^ ~R'~^
-R1.R3 R
^K RC
_K RE
-K
RC
RC
K RC
R3(R1+R2) ^. K_ R '^ RC
-K RE.RC
-K
RE
J< RC
-K RE.RC
-K
IB2
IBl
VCE2
RE.RC RE.RC CJVCEIJ
R2+R3 K R RC
R3 R
K_ RC
K RE.RC
K RE.RC
V+
where R = Rl + R2 + R3
K = RE.RC RE+RC
Direct-Coupled Two-Stage Amplifier
15
V+
\ ^ V 0
Fig. 4 Direct-Coupled Two-Stage Amplifier
The component-connection equations for Mode 2 analysis are:
VRl
VR2
IR3
IR4
IRS
IBl
VBE2
VCEl
yCE2
VM
1+
VRB
VB2
0 0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
-1
0
0
0
0
0
0
0
0
0
0
0
0
0
-1
-1
0
0
0
0
-1
0 0
0
0
0
0
0
0
-1
-1
0
0
0
0
0
0
0
0
0
0
0
-1
0
0
1
0
-1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
1
0 ,
0
' 1
. 0
0
0
0
0
1
1
' 1
1
0
0
1
IRl
IR2
VR3
VR4
VR5
VBEl
IB2
ICl
IC2_
V+
16
b =
IRl
IR2
VR3
VR4
VR5
VBEl
IB2
ICl
102
1/Rl
1/R2
R3
R4
R5
\ ^^N j ^ ' N
VRl
VR2
IR3
IR4
IR5
IBl
VBE2
VCEl
VCE2
The matrix (M2^ (Z[^ - M^^)"^ M^ + t^^^) is non-singular:
- 1 / R l 0
-1 /R l 1
0
0 0
R5 0 R5
0 -R3 -R3 0
in
Rl
+
+ R2 F
K Ql
+ R3 ' - ' ^
17
\ :
Q2
^ - R6 + VvV-
X
I
v+
" R5
+ R4
Q3 K Q4 + R9
R.
V-
Fig. 5 Video Ampl i f ier C i rcu i t
The same circuit is used as an example in [3]. In [3] ten (10) test points are required besides the input terminals. The solutions or the values of the parameters are obtained by solving eighteen (18) non-linear equations. On the other hand, the dual-mode technique requires eight (8) test points besides the input terminals and the solutions can be obtained by straight-forward matrix manipulations.
18
After the capacitors are removed, the connection equations are:
IRl
IR3
IR2
IR4
IR5
IR6
IR7
IRB
IR9
VBEl
VCEl
VBE2
VCE2
VBE3
VCE3
VBE4
VCE4
VR2
VR3
VR7
VRl
VR9
VRB
VR4
104
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
1-1 0 0
0-1-1 0
0 0-1-1
0 0 0-1
0 0 0 1
0 0 0 0
0 0 0 1
0 0 0 0
0 0 1 0
0 1 0 0
0 0 0 0
1 0 0 0
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0-
1
0
0
0
0
0
0
0
0
0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0-1
-1-1
0 0-
0 0-
0 0
0 0
1 0
0 0
0 0
0 1
0 0
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
•1
•1
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1-
0-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-1
-1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0
0 0
0 0
0-1
0 0
0-1
1 0
1 0
0 1
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0
0
0
0
0
0
0
0
1
0
0 I
0 :
0 !
0
0
0
0 1
0 '
0
0
0
0
0
0
1
:o 0
0 0
0 0
:o 0 0 0
0 0
0 0
0 0
0 0
0-1
1-1
1 0
1 0
0 0
1 0
0 0
1 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
VRl
VR3
VR2
VR4
VRB
VR6
VR7
VR8
VR9
IBl
ICl
IB2
IC2
IB3
IC3
IB4
IC4
V+
V-
19
The non-linear inputs and outputs can be found via (3) and (4):
'N =
IBl
ICl
IB2
102
IB3
IC3
IB4
104
0 R2
R3 R3
0 0
Rl 0
0 0
0 0
0 0
0 0
R2
0
0
0
0
0
R4
0
0 0 0 0 0
0 0 0 0 0
0 0 R7 0 0
0 0 0 0 0
0 0 0 R9 R9
0 R8 R8 0 0
R4-R4 0 -R4 0
0 0 0 0 i j
- 1 VR2
VR3
VR7
VRl
VR9
VRB
VR4
104
^N=
VBEl
VCEl
VBE2
VCE2
VBE3
VCE3
VBE4
VCE4
R1-R3
-R3
0
0
0
0
0
0
-R3
-R3-R2
-R2
0
0
0
0
0
0
-R2
-R2-R4
-R4
R4
0
R4
0
0
0
-R4
-R4
R4
0
R4
0
0
0
R4
R4
-R4-R5
:^e -R4
0
0
0
0
0
-R8
-R7-R8
0 -R4
0
0 0
0 0
R4 0
R4 0
-R4 0
0 0
-R6-R9 -R9
-R9 -R9
'N
• ^ ^
0
1
1
1
0
1
0
1
-1
-1
0
0
0
0
0
0
v+
V-
CHAPTER IV
COMPARISON OF FAULT-DIAGNOSIS TECHNIQUES FOR NON-LINEAR SYSTEMS
Method of V. Visvanathan and A. Sangiovanni-Vincentol1i [2]
Referring to the single-transistor amplifier circuit of Fig. 6(a)
and its equivalent circuit of Fig. 6(b) using Ebers-Moll Model [11].
V+
y+ R^
^'r^CF
Fig. 6(a) Fig. 6(b)
where R = R1//R2
I^P = K^(exp(AiV^)-l)
I^p = K2(exp(A2V2)-l)
The node equations at C and B are :
(V+/RC) - ajl( p + Ipp = (v^ - V2)/RC
(V+/R1) + aj Ipp - I CF v^/R
(5)
(6)
Substitute Irp and I^p into (5) and (6) to obtain:
V+/RC - ajK2(exp(A2V2)-l) + K^(exp( XjV^-l) = (v^ - V2)/RC
V+/R1 - aj^Kj(exp(XiV^)-l) - K2(exp(X2V2)-l) = v^/R
Suppose V, is chosen to be the test point measurement, by
solving (7) and (8) simultanously, v^ can be expressed as :
y = v^ = f (u,RpR2,Rc)
where u is the input voltage, V+ in this case .
(7)
(8)
20
21
The Jacobian matrix of y with respect to R,, Rp, and Rp, which
is the basis of V. Visvanathan and A. Sangiovanni-Vincentelli formu
lation, must be computed numerically. This example, on the most
simple circuit, has thus shown the impracticality of the above method.
Method of Nasrollah David and A. N. Wilson [3]
Referring to the single transistor amplifier circuit in [3], This
circuit requires five (B) test points, excluding the input terminals.
Also, the parameter values can be obtained by solving eight (8) non
linear equations.
Dual-Mode Fault-Diagnosis
Mode 1: referring to the single-transistor amplifier circuit in
[1], the set of test point measurements V'p and Ip yields the perfect
testability (6 . = 0) implying that the fault diagnosis equations
have locally unique solutions.
Mode 2: referring to the circuit in Figure 1 of Example 1 in the
previous sections, the same test points can be used to measure V^g
and Ip. In general case, the set of test points for the two modes will
overlap each other.
Summary
Computationally, the dual-mode fault-diagnosis technique uses only
straightforward matrix manipulations. This is an advantage over sol
ving non-linear equations. The required number of test points in the
dual-mode technique is much less than that of Wilson's technique.
Only one test point is required by Sangiovanni-Vincentelli's method
but the trade-off is to solve a wery complicated set of non-linear
equations.
CHAPTER V
FAULT-DIAGNOSIS ALGORITHM FOR TRANSISTORS
The calculations in Mode 2 of the dual-mode fault-diagnosis
technique are performed to provide the D.C. operating points of the
non-linear devices. In the case of bipolar transistors, the opera
ting conditions can be determined by the collector current Ic, the
base current IB, the base-emitter voltage Vg^, and the collector-
emitter voltage VQE- The fault-diagnosis algorithm for bipolar tran
sistors is developed on the basis of their known operating charac
Table 2 Transistor Operating Modes
Modes
Active
Saturation
Cut-off
IB
IB
'B
0
Ic
B^.IB
BS-IB
0
VBE
^ .6 V
^.7 V
< .4Bv
VcE
VcE > VBE
^CE < BE
VcE ^Vcc
where 3 is the nominal current transfer ratio in active mode, g
is the saturated current transfer ratio, and V^p is the power supply
voltage connected to the collector.
The algorithm for field-effect transistors is even simpler
because the input or gate current Ip is always zero. Field-effect
transistors are characterized by the gate voltage Vp, the drain
voltage Vp, and the drain current I^.
The fault-diagnosis algorithm for bipolar transistors shown
in Figure 7, is used to analyze the experimental results in the fol
lowing section.
22
23
CALCULATION
VALUES
^B'^C'^CE'^BE
Fig. 7 Fault Diagnosis Algorithm for N-P-N Bipolar Transistors
24
NO
^ YES
CALCULATE 3
COMPARE WITH 3 OF
NOMINAL DEVICES
AT THE SAME OPERATING
CONDITION
EITHER
FORWARD
OR
SATURATION
MODE
Fig. 7 Fault Diagnosis Algorithm for N-P-N Bipolar Transistors
(Continued)
CHAPTER VI
EXPERIMENTAL RESULTS
The video amplifier circuit of Example 4 was built and tested
at nominal operating conditions and at intentionally faulty condi
tions. The measured values of the non-linear devices'operating con
ditions are compared to those obtained by calculation. The computation
in this particular example is simple enough to be carried out by a
programmable hand-held calculator. The computational error are inves
tigated experimentally in the following cases.
Case I. Nominal Operating Conditions
The components of the circuit, which consist of four (4) tran
sistors and nine (9) resistors, were carefully analyzed before the .
experiment was started. The four transistors 2N2222A were checked on
a curve tracer. Their betas or current gains varied between one hun
dred twenty (120) to two hundred sixty (260). Thus there is more than
one hundred percent (100%) variation among the various transistors.
Furthermore, these transistors are highly sensitive to temperature.
For example, a transistor that carries twice the amount of collector
current than another will generate more heat and change its charac
teristics. The temperature sensitivity has a major effect on the accu
racy of the test results. All the resistors were within five percent
(B%) tolerance. The measured values and the nominal values of the
resistors are compared in Table 3. The experimental test-point mea
surements for all cases of the experiment is tabulated in Table 4.
The experiment was performed in a temperature-controlled environ
ment at twenty degrees Celcius (20° C). The measurements at the test
points were taken and used to compute the transistors' operating con
ditions with two (2) sets of the resistor or linear component values.
The two (2) sets of computed values for the transistors' operating
conditions are tabulated in Table 5.
The errors that are produced by using the manufacturer's claimed
values for the resistors are less than ten percent (10%) for the col
lector currents, the base-emitter and the collector-emitter voltages.
2B
26
Table 3 Comparison of Measured and Nominal Values of Resistors
Resistor
1 _-rT
Rl
R2
R3
R4
R5
R6
R7
R8
R9
Measured va lues
1.189 K
3.298 K
5.654 K
1.173 K
.316 K
.325 K
1.010 K
1.461 K
3.280 K
Claimed values
(Nominal)
1.20 K
3.30 K
5.60 K
1.2 K
.33 K
.33 K
1.00 K
1.50 K
3.30 K
Percent error
-.90
-.06
.96
-2.25
-4.24
-1.50
-1.00
-2.60
- .61
Table 4 Test Point Measurement for All Cases of the Experiment at V+ = 26.2 Volts and V- = -28.0 Volts
Test
point
VR2
VR3
VR7
VRl
VR9
VRB
VR4
104
Units
volt
volt
volt
volt
volt
volt
volt
mA
Case I
16.04
27.31
6.04
.0264
8.83
8.800
9.492
2.665
Case II
28.52
25.66
0.00
1.611
0.00
0.00
0.00
0.00
Case III
15.87
27.32
9.827
.0263
0.00
14.32
15.04
12.82
Case IV
15.86
27.32
5.336
.0263
0.00
0.00
16.44
.00866 — 1 ^ — - . •
27
Table B Transistor Operating Conditions of Case I
Parameter
IBl
IB2
IB3
IB4
ICl
IC2
IC3
104
VBEl
VBE2
VBE3
VBE4
VCEl
VCE2
VCE3
VCE4
:
Computed operating points based on
Measured R
22.2
B6.76
47.11
31.07
4.808
8.113
B.978
2.66B
.6636
.6640
.6740
.6B20
10.8B
16.71
11.36
17.37
Claimed R (i)
22.00
70.33
-169.3
14.76
4.8BB
7.748
6.038
2.66B
.6636
.6640
.7449
.6B71
10.85
16.71
11.36
17.37
Measured operating
points(ii)
22.04 uA
56.33 uA
41.75 uA
28.09 uA
4.805 mA
8.094 mA
5.993 mA
2.665 mA
.656 V
.655 V
.674 V
.649 V
10.82 V
16.70 V
11.36 V
17.36 V
% Error
(i) vs.(ii)
.18
24.90
-505.5
-47.50
10.40
-4.27
.75
0.00
1.16
1.30
10.50
1.17
.28
.06
0.00
.06
28
The errors are, however, worse for the base currents due to the fact
that the base currents are so small. Considering the transistor Q
the base-emitter voltage is positive; therefore, the base current
cannot be negative or the transistor is not faulty. This is thus a
case of calculation error.
Case II. A Bad Linear Component in the Circuit
The resistor R2 is increased from 3.3K to 8.9K. A set of measure
ments is taken from the test points, and used to compute the transis
tors' operating conditions with the faulty value of R2 taken or not
taken into account. The results are tabulated in Table 6. The signi
ficance is that the transistor Q2 appears to be faulty if the faulty
value of R2 is not taken into account. The base current, which is
equal to the collector current in magnitude, suggests that the base and
the collector of Q2 are shorted together while the emitter is open.
On the other hand, if the faulty value of Rp is used for computation
of the base and collector current of Qp, these currents are almost zero
(0), indicating that the transistor Qp is operating at the origin of
the characteristic curve.
Case III. A Bad Transistor in the Circuit
Transistor Q. is replaced by a known faulty transistor, whose
emitter is open-circuited and base to collector junction is almost
short-circuited. This is a common type of failure when the emitter to
base junction is forward-biased too much. The base-collector voltage-
current characteristics of the above transistor is shown in Figure 8.
The transistors' operating points are calculated and tabulated in
Table 7.
Referring to the calculated operating points based on the mea
sured resistor values of Table 7, the value of IB4 equals in mag
nitude to IC4, and VBE4 is much greater than point six volts (0.6V).
These data indicate that the emitter-base junction is short-circuited,
therefore, the transistor Q. is faulty.
29
Table 6 Transistor Operating Conditions for Case II
Transistor
Ql
Q2
Q3
Q4
Parameter
IBl
ICl
VBEl
VCEl
IB2
IC2
VBE2
VCE2
IB3
103
VBE3
VCE3
IB4
IC4
VBE4
VCE4
Faulty value of R2
is used for operating
point calculations.
1.355
3.183
.729
.020
.001
-.001
-2.32
26.20
0.0
0.0
0.0
26.20
0.0
0.0
0.0
26.20
t — . — - - - -]
Faulty value of Rp
not taken into account.
1.355 mA
3.183 mA
.729 V
.020 V
5.464 mA
-5.464 mA
-2.32 V
26.20 V
0.0 mA
0.0 mA
0.0 V
26.20 V
0.0 mA
0.0 mA
0.0 V
26.20 V
30
Fig. 8 Collector-Base I-V Characteristics of the Faulty Transistor
Used in Case III and IV of the Experiment
31
Table 7 Calculated Operating Points and Fault-Diagnosis
for Case III
, ,
Ql
Q2
Q3
Q4
Parameter
IBl
ICl
VBEl
VCEl
IB2
IC2
VBE2
VCE2
IB3
103
VBE3
VCE3
IB4
104
VBE4
VCE4
Calculated value based on measured resistance.
22.12
4.81
.6540
11.01
2.15
73.47
-4.71
11.16
71.80
9.73
.6970
2.05
-12.82
12.82
19.21
26.20
Diagnosis
Good
3 = 217
At rest
IB ^ 0
IC ^ 0
Good
3 = 136
Bad
IB=-IC
VBE».6v
:B-E opened
C-B short.
Calculated value based on claimed resistance
21.92 uA
4.86 mA
.654 V
11.01 V
-47.56uA
-517.4 uA
-4.71 V
11.16 V
-280.3 uA
9.83 mA
.813 V
2.05 V
-12.82 mA
12.82 mA
19.27 V
26.20 V
—1
Diagnosis
Good
3 = 222
VBE>.5v ,
IB,IC must
be zero :
Calculation error
VBE >.6v
IB must> 0
:Cal.error
Bad
IB= -IC
VBE».6v
.
32
Again, using the nominal values of the resistors for calculation
produces significant errors. Consider the transistor Qp, the base to
emitter voltage is negative, therefore, the transistor is operating
in the cut-off region or both the base and the collector currents have
to be close to zero (0). However, the calculations show a relatively
large negative value for both of these currents. The error also occurs
in the base current calculation for transistor Q^, which causes an
ambiguous state for the above transistor.
Case IV. Transistors Q3 and Q4 are Faulty
Transistors Q^ and Q- are replaced by known faulty transistors,
whose base-collector characteristics are shown in Figure 8. The tran
sistors' operating points are calculated and tabulated in Table 8.
The calculation of operating points based on the measured resistor
values is accurate, while those based on the nominal resistor values
creates errors.
33
Table 8 The Calculated Operating Points and Fault-
Diagnosis for Case IV
Q
Ql
Q2
Q3
Q4
Parameter
IBl
ICl
VBEl
VCEl
IB2
IC2
VBE2
VCE2
IB3
IC3
VBE3
VCE3
IB4
104
VBE4
VCE4
Calculated value based on measured resistor values
22.12
4.81
.654
11.02
-1.19
74.22
-6.10
9.76
-5.28
5.28
18.11
20.86
-8.66
8.66
19.25
26.20
Diagnosis
Good
6 = 217
At rest
IB,IC ^ 0
VBE <0
Bad
IB= -IC
VBE».6v
Bad
same as
Q3
Calculated value based on claimed resistor values
21.92 uA
4.86 mA
.654 V
11.02 V
-50.9 uA
-244.3uA
-6.1 V
9.76 V
-5.34 mA
5.34 mA
18.20 V
20.86 V
-8.66 mA
8.66 mA
19.30 V
26.20 V
Diagnosis
Good
3 = 222
At rest
IB,IC ^ 0
VBE <0
Bad
IB=-IC
VBE».6v
Bad
same as
Q3
i
CHAPTER VII
CONCLUSION
The dual-mode fault-diagnosis technique for non-linear systems
has been formulated in the preceding sections via the component-
connection equations. Mode 2 or non-linear D.C. analysis is performed
at the device or element level rather than at the internal parameter
level of the corresponding non-linear devices, which is not only com
pat ib le to previous successful fault-diagnosis techniques in d i g i t a l
systems, but also wery pract ical in today's increasingly complex elec
t ronic systems.
Computation-wise, th is technique is much more advantageous than
the other ex is t ing techniques in analog non-linear systems because of
the use of l inear matrix manipulations rather than solving complex
non-l inear equations. However, th is technique requires a re la t i ve l y
larger number of test points compared to the method of V. Visvanathan
and A. Sangiovani-Vincentell i [ 2 ] .
The experimental results indicate that the D.C. or non-linear
faul t -d iagnosis techniques cannot be used to diagnose the tolerance
or s o f t - f a u l t problems due to the s ign i f i can t errors introduced by
the use of the manufacturer's claimed component values. However,these
errors can be eliminated by the dual-mode technique since the measured
values of the l inear components can be computed in Mode 1 or the mult i -
frequency tes t . Furthermore, for the Mode 2 analysis, the bad value of
a fau l ty l inear component has to be calculated so that the more accu
rate resul ts and faul t -d iagnosis can be obtained.
34
REFERENCES
[1] N. Sen and R. Saeks, "Fault Diagnosis for Linear Systems via Multi-Frequency Measurements," IEEE Transaction on Circuits and Systems, Vol. Cas-26, No. 7, pp. 4B7-46B, July 1979.
[2] V. Visvanathan and A. Sangiovanni-Vincentelli, "Fault-Diagnosis of Non-Linear Memoryless Systems," unpublished note. University of California at Berkeley.
[3] N. David and A. N. Wilson, Jr., "A Theory and an Algorithm for Analog Circuit Fault-Diagnosis," IEEE Transaction on Circuits and Systems, Vol. Cas-26, No. 7, pp. 440-4B6, 1979.
[4] M. N. Ransom and R. Saeks, "The Connection Function—Theory and Application," Int. J. Circuit Theory and Its Applications, Vol. 3, pp. B-21, 197B.
[B] F. Wang and H. H. Schreiber, "A Pragmatic Approach to Automatic Test Generation and Failure Isolation of Analog Systems," IEEE Transactions on Circuits and Systems, Vol. Cas-26, No. 7, pp. B84-B8B, July 1979.
[6] P. Duhamel and J. C. Rault, "Automatic Test Generation Techniques for Analog Circuits and Systems: A Review," IEEE Transaction on Circuits and Systems, Vol. Cas-26, No. 7, pp. 411-439, July 1979.
[7] W. J. Dejka, "Measure of Testability in Device and System Design,' Proceedings 20th Midwest Symposium on Circuits and Systems, Lubbock, Texas.
[8] W. J. Dejka, "A Review of Measurements of Testability for Analog Systems," Proc. 1977 QUTOTESTCON, Hyannis, Massachusetts, pp. 279-284, 1977.
[9] N. Sen, M. S. Thesis, Texas Tech University, Lubbock, Texas
[10] R. Saeks, R. DeCarlo, and S. Sangani, "Fault Isolation via Af-finization," Fault Analysis in Electronic Circuits and System II, Texas Tech University Publication, pp. 109-114, January 1978.
[11] Chua L., "A Glimpse at Some Physical Models," in Computer Circuit Models of Electronic Devices and Components, pp. 76-77, 1977.
[12] R. Saeks and N. Sen, "Formulation of the Faulty-Diagnosis Equations," Fault-Analysis in Electronic System II, Texas Tech University Publication, pp. 1^3, January 1978.
3B
36
[13] H. S, M Chen and R. Saeks, "A Search Algorithm for the Solution of the Multi-Frequency Fault-Diagnosis Equations," IEEE Transac-J r ?979^^^"^^^ ^"^ Systems, Vol. Cas-26, No. 7, pp. B89-B94,
APPENDIX
TEST POINT SELECTIONS
Analysis of the Singular i ty of the Matrix
This analysis is intended to expose the readers to the problem
of the tes t point select ion in the D.C. analysis of the dual-mode
faul t -d iagnosis technique. The matrix F can be arranged in the
fol lowing form:
F = / M L f-r-l K,LLx-l ,LN . MN \ ( M2 I (ZL -M^^) M^^ + Mpi )
- fei^a
= "3. EM
(z[ i- MLL)-I M^ 11 11
= Mp^.K 1
where: K = (z[ i - n\\)-' MN 11 11
I = i den t i t y matrix
The matrix M21 depends t o t a l l y on output select ions; therefore,
the s ingu la r i t y of matrix F is also determined by the test point or
output select ions.
37
Referring to Example 2 of Section III, the matrix K is:
38
R2+R3
R
Rr
h'\
-h^2
R
-^1^3
R
^E^C
R^ + R^
R.
R
- Rr
R2R3
R
R
0
0
S''^l'*'^2^ 0
0
h^h \^\ h^h
0
0
R^R^ -R^ -R^
^E ^ ^C ^E ^ ^C ^E ^ ^C
39
,1 If Vj^, IRl, IRC, VR3 are chosen as test measurements, where
V . = v., + VCE 2 the matrix is: 'M 'M
M 21
0 0 0 0 1
1 0 0 0 0
0 1 0 0 0
0 0 0 1 0
0 0 1 1
0 0 0 0
0 0 0 0
0 0 0 1
The resu l t ing matrix F is singular because row 1 and 3 are
l inear dependent.
F =
RcR E C
RE+RC
R2+R3
R
R3
Rf
RE+RC
0
R
Rr
Rc+Rr
0 R
-RE
RC+RE
-^1^3
R
-RE
RC+RE
-R3(Rl+R2)
-1
RC+RE
0
-1
RC+RE
0
IRC V R T r * " ' . " ' ' ' - n o r change in output selection. V„. IRl. IKC, VR3 are chosen, thp fiVcf y. ., «^ » i. M '
^cii, Lne Tirst row of M2^ becomes:
40
[O 0 0 0 1 I 0 0 0 l)
and the f i r s t row of matrix F becomes:
R^+R
•'c -h R,
E+Rc V^C V c V^C
Therefore, F is non-singular.
Referring to the Example of Section III, the matrix K is
r 1/Rl
1/R2
0
0
0
1
0
0
R3
0
RB
1
0
0
R3
0
0
0
0
0
R4
Rb
41
If V ., I + . VBl, VB2 are chosen as test points, .the matrices Mp and F are:
M 21
0 0 0 - 1 0
1 0 0 0 0
0 0 0 0 0
0 0 - 1 0 0
0 0 0 o l
0 1 1 1
1 0 0 0
0 0 0 0
F =
0 0 0 -R4
-1/Rl 1 1 1
1 0 0 0
L 0 -R3 -R3 0
The F matrix is s ingu lar because the columns 2 and 3 are
l inear ly dependent.
However, i f V^, I + , VRB, VB2 are chosen, the matrix F is non-singular:
M 21
0 0 0 - 1 0
1 0 0 0 0
0 0 0 0 1
^ 0 0 - 1 0 0
0 0 0 o l
0 1 1 1
0 0 0 0
0 0 0 0^
F =
L
-1/Rl
-1/Rl
0
0
0
1
RB
- R 3
0
1
0
- R 3
0
1
RB
0
42
Considering the second and third column of matrix K , the
differences between these two columns are the elements K -o ' ^c* 1 1 1 B2 b
Kg3 = 0 and K^^ = 1» ^ 83 " - ^ subset of M2,, which consists of
two outputs, has to be chosen, in such a way that its product
with the second and third column of K is non-singular. This
condition is satisfied when one of the outputs contains VRB,
as in the third row of Mp, of the preceding discussion, which
results a non-zero element at row 3 and column 2 of matrix F. Referring to Example 4 of Section III, the matrix K is:
Rl
R3
0
0
0
0
0
0
0
0
R3
R2
0
0
0
0
0
0
0
0
R2
R4
0
0
0
0
0
0
0
0
R4
0
0
0
0
0
0
0
0
-R4
-RB
0
0
R8
0
0
0
0
0
0
0
R7
R8
0
0
0
0
-R4
0
-R6
0
0
R9
0
0
0
0
0
0
0
0
R9
Suppose VR2, VR3, VR7 VRQ \IDQ A wn. test Dointc: fh . ' ^ ^"^ ^^^ '^^ ^^°^^" ^0 be the test points, the matrices M^ and F are:
43
F = Mj^K^ =
0
R3
0
Rl
0
0
0
0
R2
R3
0
0
0
0
0
1
R2
0
0
0
0
0
R4
1
0
0
0
0
0
0
R4
1
0
0
0
0
0
R8
-R4
0
0
0
R7
0
0
R8
0
1
0
0
0
0
R9
0
-R4
n
0
0
0
0
R9
0
0
1
The determinant of F is :
det(F) = -RiR3R2R7R8.det
because
0
R.
s - \
0
\
0
1 J
0
det
r 0 R9 R9
R4 -R4 0
1 0 1 det
0
R4
R9
-R4 det R9
-R4
R9
0
- R4R9+ ^4^9= 0
In order t o make d e t 0 R9 R9
R4 -R4 0
1 0 1 ¥= 0, one of the elements of
44
the third row of this matrix has to be changed to zero as follows:
0
R4
0
R9 R9
-R4 0
0 1
or
0 R9 R9
R4 -R4 0
1 0 0
Physically, this means one has to select the last output measure
ment such that it does not contain both IC4 and IC3.
