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A DIMMABLE HIGH POWER FACTOR ELECTRONIC BALLAST
FOR COMPACT FLUORESCENT LAMPS
by
John Lam
A thesis submitted to the Department of Electrical & Computer Engineering
In conformity with the requirements for
the degree of Doctor of Philosophy
Queen’s University
Kingston, Ontario, Canada
(April, 2010)
Copyright ©John Lam, 2010
ii
Abstract
Incandescent lamps are now being gradually replaced by Compact Fluorescent Lamps (CFLs) as
CFLs consume less power to produce the same light output and its lifetime is much longer than
that of an incandescent lamp. However, current CFLs have the following drawbacks: (1) the line
current drawn from the CFL produce a large amount of unwanted harmonics that results in very
poor input power factor; (2) the dimming performance of a CFL with conventional incandescent
lamp dimmers is very poor. The performance of the CFL depends on the design of the electronic
ballast circuit that is located at the base of each CFL. For a CFL electronic ballast to be practical,
its size and cost is of utmost importance. Thus, the main challenge in the design of practical
dimmable CFL ballasts is to solve the aforementioned CFL performance issues while minimizing
its size and cost.
In the first part of this dissertation, two novel high power factor single-stage electronic ballast
topologies are proposed to solve the poor power factor issue of the CFLs that are currently on the
market. Both proposed circuits have the following advantages: (1) only one switch is required in
the power circuit; (2) the switch has both lower current and voltage stress than other conventional
circuits; (3) the built-in power factor correction (PFC) circuit allows incandescent phase-cut
dimmer to be used for dimming the CFL; (4) the circuit design is simple and it requires less
system space compared to other conventional high PF electronic ballast topologies. The second
part of this dissertation proposes a new control circuit that enables the lamp to maintain high
power factor throughout the majority of the dimming range. In the proposed control scheme, the
dimmer phase-cut angle is fed-forward to the control circuit. The controller then determines the
proper duty cycle based on the phase-cut angle to facilitate the desired dimming operation. This
novel control circuit was first implemented using analog circuitry. After assessing the
iii
performance of the analog version of the proposed controller, it was then digitally implemented
through the Field Programmable Gate Array (FPGA) technique. The feasibility and performance
of both the proposed electronic ballasts and control concept have been verified through
theoretical analysis, simulation and experimental results on a 13W 4-pin D/E CFL from Osram
Sylvania.
iv
To my parents:
Siu-Chung Lam; Susan Sau-Kam Lam
and my fiancée:
Joanne Hui
v
Acknowledgements
First of all, I would like to express my deepest gratitude to my supervisor, Dr. Praveen K. Jain for
his guidance and direction on this thesis. His expertise in power electronics has transformed this
thesis from being a purely academic piece of work into a practical engineering solution for real-
world application.
I would also like to thank all the members of ePOWER (Queen’s Center for Energy and Power
Electronics Research) for their willingness to share their opinions with me throughout these years.
Here, I would especially like to mention Ali Khajehoddin, Ali Moallem and Darryl Tschirthart.
A special thank you goes to Mr. Haibo Zhang from Cistel Technology for spending his time to
train me as an engineer and for providing me with numerous opportunities to earn more hands-on
experience. Another special thank you must go to Dr. Shangzhi Pan for his help on the digital
design portion in this thesis.
Also, Dr. Nancy Churchman from ePOWER and Ms. Debie Fraser from the Electrical and
Computer Engineering Department, thank you for organizing all my financial issues. I also want
to thank Mr. Djilali Hamza, the lab manager of ePOWER for preparing and organizing all the
experimental equipments for this work.
I would like to take this opportunity to also extend my thanks to the PARTEQ Innovation
personnel for all their hard work. I would like to especially thank Mr. Stephen Adolph for his
time and effort spent on this work in terms of the licensing activities. Without the support from
my supervisor and Mr. Adolph, I would never have had the numerous opportunities to interact
with industry experts and gain invaluable experience.
At this point, I would like to express my gratitude to my fiancée, Joanne Hui, who is also a
member of ePOWER, for her continuous support and love. Thank you for your patience during
vi
my times of frustration throughout these years. I must also thank her for providing me with very
valuable technical suggestions as well.
Last but not least, I must also thank my parents for their unconditional love and support. Without
their support and understanding, I would not have had the perseverance to complete this work.
vii
Table of Contents
Abstract ............................................................................................................................................ ii
Acknowledgements .......................................................................................................................... v
Chapter 1 Introduction ..................................................................................................................... 1
1.1 Incandescent lamps VS Fluorescent lamps ............................................................................ 4
1.2 Magnetic Ballast VS Electronic Ballast ................................................................................. 6
1.3 Basic Requirements of Electronic Ballasts ............................................................................ 8
1.3.1 Measures of Electronic Ballast Performance ................................................................ 10
1.4 Review on Resonant Inverter Topologies in Electronic Ballast .......................................... 12
1.4.1 Half-Bridge Resonant Inverters .................................................................................... 13
1.4.2 Push-Pull Inverter Configuration .................................................................................. 16
1.4.3 Class E LCC Resonant Inverter .................................................................................... 17
1.4.4 Current Source Inverters for Electronic Ballast ............................................................ 18
1.5 Power Factor Correction (PFC) Techniques in Electronic Ballast ...................................... 19
1.5.1 Active PFC in Electronic Ballasts ................................................................................. 22
1.5.2 Passive PFC in Electronic Ballasts ............................................................................... 29
1.6 Dimming Control ................................................................................................................. 34
1.6.1 Duty Ratio Control ........................................................................................................ 35
1.6.2 Variable Frequency Control .......................................................................................... 36
1.6.3 Phase-Shift Control ....................................................................................................... 37
1.6.4 DC-link Voltage Control ............................................................................................... 38
1.7 Electronic Ballasts in CFL: Features and Drawbacks .......................................................... 39
1.8 Research Motivation ............................................................................................................ 41
1.9 Thesis Organization ............................................................................................................. 42
Chapter 2 Single-switch High Power Factor Electronic Ballast .................................................... 44
2.1 Proposed Single-switch Current Fed Resonant Inverter ...................................................... 44
2.1.1 Characteristics of Proposed Resonant Circuit ............................................................... 46
2.1.2 nth Harmonics Analysis of Proposed Resonant Circuit ................................................. 51
2.2 High PF Single-Stage Switch Electronic Ballast ................................................................. 54
2.2.1 Single-switch High PF Electronic Ballast with Buck-Boost PFC ................................ 54
viii
2.2.2 Operating Principles of Single-switch Electronic Ballast with Buck-boost PFC ......... 57
2.2.3 Single-switch High PF Electronic Ballast with SEPIC PFC ......................................... 60
2.2.4 Operating Principles of Single-switch Electronic Ballast with SEPIC PFC ................. 62
2.2.5 Current and Voltage stress Analysis ............................................................................. 65
2.3 Design Example ................................................................................................................... 69
2.3.1 Design of the resonant circuit ....................................................................................... 69
2.3.2 Design of the buck-boost PFC stage ............................................................................. 70
2.3.3 Design of the SEPIC PFC ............................................................................................. 71
2.3.4 Simulation Results ........................................................................................................ 72
2.3.5 Experimental Results .................................................................................................... 75
2.4 Chapter Summary ................................................................................................................ 85
Chapter 3 Proposed Dimming Control with Phase-Cut Dimmers and Stability Analysis ............. 86
3.1 Operating Principles of Phase-cut Dimmers ........................................................................ 86
3.2 Proposed Dimming Control Concept ................................................................................... 89
3.2.1 Duty ratio analysis with proposed control .................................................................... 91
3.2.2 DC-link capacitor voltage ripple analysis ..................................................................... 95
3.2.3 Lamp ignition at low dimming level ............................................................................. 96
3.3 Negative Impedance of Fluorescent Lamp .......................................................................... 99
3.4 Small-signal Modeling of the Proposed Ballast System .................................................... 102
3.4.1 Modeling of the resonant inverter ............................................................................... 105
3.4.2 Small signal output impedance of proposed resonant inverter ................................... 107
3.5 Design Example of Proposed Control Circuit .................................................................... 113
3.5.1 Simulation Results ...................................................................................................... 113
3.5.2 Experimental Results .................................................................................................. 115
3.6 Chapter Summary .............................................................................................................. 125
Chapter 4 Digital Implementation of Proposed Control Concept ................................................ 126
4.1 Motivations for Digital Control Implementation in Proposed Electronic Ballast .............. 127
4.2 Control Requirements with Digital Implementation .......................................................... 128
4.2.1 Implementation of digital pulse-width modulation (DWPM) ..................................... 130
4.2.2 Implementation of the digital feed-forward control loop ............................................ 132
4.2.3 Implementation of the low power shut-off detection mode ........................................ 133
4.2.4 Soft-start lamp ignition ............................................................................................... 135
ix
4.2.5 Implementation of the overall digital control circuit .................................................. 136
4.3 z-Domain Analysis of Proposed Control ........................................................................... 137
4.4 Design Example ................................................................................................................. 143
4.4.1 Simulation Results ...................................................................................................... 143
4.4.2 Experimental Results .................................................................................................. 145
4.5 Chapter Summary .............................................................................................................. 152
Chapter 5 Summary and Conclusions .......................................................................................... 153
5.1 Contributions ..................................................................................................................... 153
5.2 Future Works ..................................................................................................................... 155
5.3 Conclusions ........................................................................................................................ 156
Bibliography ................................................................................................................................ 157
Appendix A Derivation of Resonant Inverter Current Expression .............................................. 169
Appendix B Derivation of RMS Current Expression for Diodes Din and Db ............................... 171
Appendix C Input Filter Design for Proposed Single-switch Electronic Ballast ......................... 172
Appendix D Schematic in PSIM Simulation ............................................................................... 174
Appendix E Bill of Materials of Control Circuit Components and CFL Data ............................. 178
Appendix F Printed Circuit Board (PCB)Layouts ....................................................................... 181
Appendix G VHDL Codes Created in ModelSIM 6.3 for Digital Control .................................. 183
x
List of Figures
Figure 1-1 Energy consumption curves for different kinds of lamp [4] .......................................... 3
Figure 1-2: (a) Incandescent lamp V-I curve; (b) Fluorescent lamp V-I characteristics ................. 6
Figure 1-3 Efficacy of fluorescent lamp VS lamp operating frequency [6] ..................................... 8
Figure 1-4 Illustration of typical voltage and current waveforms in electronic ballast ................... 8
Figure 1-5 Block diagram of electronic ballast with PFC in commercial fluorescent lamps ........ 10
Figure 1-6 Input line current THD vs input PF .............................................................................. 11
Figure 1-7 Basic Voltage Source Resonant Inverter Topologies ................................................... 14
Figure 1-8 Voltage gain plots: (a) series LC resonant; (b) parallel LC resonant; (c) series-parallel
LC resonant .................................................................................................................................... 15
Figure 1-9 ZVS operating waveforms for voltage fed half-bridge resonant inverters ................... 16
Figure 1-10 Class E resonant inverter and its key waveforms: (a) theoretical waveforms; (b)
simulation waveforms .................................................................................................................... 18
Figure 1-11 Current fed resonant inverter in electronic ballast ..................................................... 19
Figure 1-12(a): Electronic ballast without DC-link capacitor; (b) with DC-link capacitor; .......... 21
Figure 1-13 (a) Two-stage electronic ballast; (b) Single-stage electronic ballast .......................... 23
Figure 1-14 Single-stage electronic ballast with boost PFC .......................................................... 25
Figure 1-15 Single-stage electronic ballast with flyback PFC ....................................................... 26
Figure 1-16 Single-stage electronic ballast with Buck PFC .......................................................... 28
Figure 1-17 Input waveforms of buck PFC: (a) theoretical; (b) simulation waveforms ................ 29
Figure 1-18 Passive L-C filter PFC electronic ballast ................................................................... 30
Figure 1-19 (a): Valley-fill PFC electronic ballast; (b) its key waveforms: (i) theoretical
waveforms; (ii) simulation waveforms .......................................................................................... 31
Figure 1-20 Modified valley-fill PFC circuit ................................................................................. 32
Figure 1-21 Charge-pump PFC electronic ballast .......................................................................... 33
Figure 1-22 Key waveforms of phase-cut dimmers used in incandescent lamps .......................... 35
Figure 1-23 Key waveforms at the resonant inverter stage in phase-shift control ......................... 38
Figure 2-1 Comparisons between Class E resonant inverter and proposed inverter ...................... 45
Figure 2-2 Equivalent circuit at the inverter stage during lamp ignition ....................................... 47
Figure 2-3 Voltage gain plot of proposed resonant circuit ............................................................ 50
Figure 2-4 Phase plot of proposed resonant circuit ........................................................................ 50
xi
Figure 2-5 AC nth harmonics equivalent circuit with lamp and filament resistances included ...... 51
Figure 2-6 Current waveforms at the resonant inverter stage plotted in PSIM .............................. 53
Figure 2-7 Derivation of proposed single-switch high PF electronic ballast; (a) initial design; (b)
circuit derivation; (c) Final design of proposed circuit .................................................................. 56
Figure 2-8 Operating stages of single-switch electronic ballast with integrated buck-boost PFC . 59
Figure 2-9 Key waveforms of single-switch electronic ballast with integrated buck-boost PFC .. 60
Figure 2-10 Derivation of proposed single-switch high PF electronic ballast with SEPIC PFC ... 61
Figure 2-11 Operating stages of the SEPIC single-stage electronic ballast ................................... 63
Figure 2-12 Operating waveforms of the proposed SEPIC type single-stage electronic ballast ... 64
Figure 2-13 Equivalent circuit of the inverter when the switch is on ............................................ 66
Figure 2-14 Key waveforms at the inverter stage .......................................................................... 67
Figure 2-15 Simulated waveforms for proposed circuit with integrated buck-boost PFC(a) vds, iLb
and iin; (b) Line current and lamp current; (c)DC-link voltage (vdc) .............................................. 74
Figure 2-16 Simulated waveforms for proposed circuit with integrated SEPIC PFC (a) vds, ids and
iin; (b) Line current and lamp current; (c)DC-link voltage (vdc) ..................................................... 75
Figure 2-17 Lamp current and voltage at start-up .......................................................................... 76
Figure 2-18 Measured lamp voltage and current waveforms within low frequency cycle ............ 77
Figure 2-19 Measured lamp voltage and current waveforms ......................................................... 77
Figure 2-20 FFT of lamp current in commercial 13W CFL .......................................................... 78
Figure 2-21 FFT of lamp current from proposed circuit ................................................................ 78
Figure 2-22 Measured line current from a commercial 13W CFL ................................................ 79
Figure 2-23 Line current and line voltage with integrated buck-boost PFC .................................. 79
Figure 2-24 Measured line current from proposed single circuit with integrated SEPIC PFC ...... 79
Figure 2-25 Line current harmonics spectrum from a commercial 13W non-dimmable CFL ...... 80
Figure 2-26 Line current harmonics spectrum from proposed circuit with integrated buck-boost
PFC ................................................................................................................................................ 80
Figure 2-27 Line current harmonics spectrum from proposed single circuit with integrated SEPIC
PFC ................................................................................................................................................ 80
Figure 2-28 MOSFET voltage (vds), inductor Lb current (iLb) and inverter input current iin .......... 81
Figure 2-29 MOSFET voltage (vds) and inductor Lb current (iLb) within line frequency ............... 81
Figure 2-30 MOSFET current and voltage waveforms in the proposed SEPIC type single-stage
electronic ballast ............................................................................................................................ 82
xii
Figure 2-31 MOSFET current and voltage waveforms within line frequency .............................. 82
Figure 2-32 DC-link voltage from single-switch ballast circuit with integrated buck-boost PFC . 83
Figure 2-33 DC-link voltage and lamp current from single-switch ballast circuit with integrated
SEPIC PFC .................................................................................................................................... 83
Figure 2-34 PF performance of the proposed circuits .................................................................... 84
Figure 2-35 Efficiencies of the proposed circuits .......................................................................... 84
Figure 3-1 PF versus α with typical phase-cut dimmer ................................................................. 88
Figure 3-2 THD versus α in conventional phase-cut dimmer ........................................................ 89
Figure 3-3 Proposed dimmable electronic ballast .......................................................................... 90
Figure 3-4 Key waveforms at the control circuit ........................................................................... 91
Figure 3-5 Diode Db current........................................................................................................... 92
Figure 3-6 Duty ratio versus α for different values of K in proposed control ................................ 94
Figure 3-7 Normalized power versus α for different values of K in proposed control .................. 94
Figure 3-8 vripple during dimming ................................................................................................... 95
Figure 3-9 Equivalent circuit when the MOSFET is on during lamp ignition ............................... 97
Figure 3-10 Key waveforms at the resonant inverter during lamp ignition ................................... 98
Figure 3-11 Relationship between Vign and α ................................................................................. 99
Figure 3-12 Lamp current and voltage waveforms with low frequency envelope ....................... 101
Figure 3-13 (a) Lamp incremental impedance on complex plane; (b) Lamp V-I curve .............. 102
Figure 3-14 Block diagram for the small-signal model of the proposed ballast system .............. 103
Figure 3-15 Output stage of the small signal equivalent circuit of a DCM SEPIC converter ..... 104
Figure 3-16 Small-signal equivalent circuit at the inverter stage ................................................ 105
Figure 3-17 Phasor models for (a) capacitor; (b) inductor [69] ................................................... 106
Figure 3-18 Small signal equivalent circuit for the resonant inverter .......................................... 107
Figure 3-19 Bode plot of zo(s) and zlamp(s) ................................................................................... 108
Figure 3-20 Simplified circuit with only low frequency component ........................................... 108
Figure 3-21 Nyquist plot of zlamp(s)/zo(s) (a): Lp = 1.5mH; (b) Lp = 2.2mH ................................. 110
Figure 3-22 Bode plot of ^^
/ dvdc for different power levels ........................................................ 111
Figure 3-23 Overall open-loop loop Bode plot at full power condition ...................................... 112
Figure 3-24 Simulated line current and lamp current .................................................................. 114
Figure 3-25 Simulated lamp current and its duty ratio ................................................................ 115
xiii
Figure 3-26 Line current and line voltage from a commercial dimmable 14W CFL .................. 117
Figure 3-27 Line current performance from proposed single-switch ballast without control ..... 118
Figure 3-28 Line current performance with proposed control ..................................................... 119
Figure 3-29 DC-link voltage and lamp current waveforms under dimming ................................ 120
Figure 3-30 Duty cycle and lamp current during dimming .......................................................... 121
Figure 3-31 Lamp current and voltage at low dimming transition .............................................. 122
Figure 3-32 Normalized input power versus dimmer firing angle ............................................... 123
Figure 3-33 Luminous level versus dimmer firing angle ............................................................. 124
Figure 3-34 PF performance ........................................................................................................ 124
Figure 4-1 General diagram of proposed electronic ballast with digital control block ................ 129
Figure 4-2 (a): Basic principle of PWM in analog circuit; (b) Implementation of DPWM ......... 131
Figure 4-3Key waveforms in DPWM .......................................................................................... 131
Figure 4-4 Logic flow diagram of the proposed feed-forward loop ............................................ 133
Figure 4-5 Logic flow diagram in low power detection mode ..................................................... 134
Figure 4-6 Logic flow chart for soft-start function ...................................................................... 136
Figure 4-7 Overall diagram of proposed single-switch electronic ballast with digital controller 137
Figure 4-8 (a): Mixed control system; (b): Pure discrete equivalent system ............................... 138
Figure 4-9 Overall system model with continuous-time and discrete-time domains ................... 140
Figure 4-10 Bode Plot of overall open-loop transfer function ..................................................... 141
Figure 4-11 Implementation of discrete-time integrator .............................................................. 142
Figure 4-12 Bode Plot of the loop transfer function in z-domain ................................................ 142
Figure 4-13 Block diagram for power circuit simulation with digital control in Simulink ......... 144
Figure 4-14 Simulated waveforms during dimming transition .................................................... 145
Figure 4-15 Line current performance with digital control ......................................................... 146
Figure 4-16 Lamp current during dimming with digital control .................................................. 147
Figure 4-17 Ignition at full power with soft-start feature ............................................................ 148
Figure 4-18 Ignition during dimming with soft-start feature ....................................................... 148
Figure 4-19 Illustration of low power shut-off mode .................................................................. 149
Figure 4-20 Illustration of input current and voltage waveforms at low dimming start-up ......... 150
Figure 4-21Line current and DC-link voltage in over-voltage protection mode ......................... 151
Figure C-1 Input circuit stage at the rectifier ............................................................................... 172
Figure C-2 Simplified equivalent circuit at the input filter side with superposition .................... 172
xiv
Figure C-3 LC filter design curve ................................................................................................ 173
Figure D-1 Power-dependent lamp model in PSIM ..................................................................... 174
Figure D-2 Single-switch electronic ballast with integrated buck-boost PFC in PSIM ............... 174
Figure D-3 Single-switch electronic ballast with integrated SEPIC PFC in PSIM ..................... 175
Figure D-4 Single-switch SEPIC type electronic ballast with proposed control in PSIM ........... 175
Figure D-5 PSIM schematic of the power circuit and A/D circuit interface ................................ 176
Figure D-6 Simulation of the proposed ballast system with digital control implemented in
Simulink ....................................................................................................................................... 177
Figure E-1 Electrical diagram of proposed control with analog circuit ....................................... 178
Figure E-2 Measured 13W CFL V-I characteristics .................................................................... 180
Figure F-1 PCB layout of single-switch SEPIC type ballast circuit with fixed duty ratio .......... 181
Figure F-2 PCB layout of the control circuit with duty ratio control ........................................... 181
Figure F-3 PCB layout for A/D conversion circuit ...................................................................... 182
xv
List of Tables
Table 1-1 Incandescent lamps phase-out calendar ........................................................................... 3
Table 1-2 Harmonic limits for IEC1000-3-2 Class C equipment [25] ........................................... 20
Table 2-1 Design Specifications .................................................................................................... 69
Table 2-2 Circuit parameters for proposed circuit with integrated buck-boost PFC ..................... 73
Table 2-3 Circuit parameters with integrated SEPIC PFC............................................................. 73
Table 3-1 Design Specifications .................................................................................................. 113
Table 4-1 Design Specifications of the Design Example with Digital Control ........................... 143
Table 4-2 Performance comparisons between proposed control with analog and digital logic ... 151
Table E-1 BOM of Control Circuit .............................................................................................. 179
Table E-2 13W CFL D/E Dulux type (Osram Sylvania) data ..................................................... 180
xvi
List of Acronyms and Symbols
Acronyms:
AC: Alternating Current
A/D: Analog-to-Digital
ANSI: American National Standards Institute
ASIC: Application-specific integrated circuit
CCM: Continuous Conduction Mode
CF: Crest Factor
CFL: Compact Fluorescent Lamp
CSI: Current Source Inverter
DAC: Digital-to-Analog Conversion
DC: Direct Current
DCM: Discontinuous Conduction Mode
DPF: Displacement Power Factor
DPWM: Digital Pulse-Width Modulation
DSP: Digital-Signal Processing
EMI: Electromagnetic Interference
EU: European Union
FPGA: Field Programmable Gate Array
LED: Light-Emitting Diode
MUX: Multiplexer
PF: Power Factor
PFC: Power Factor Correction
PLR: Parallel Loaded Resonant
PWM: Pulse-Width Modulation
RMS: Root-Mean Square
SLR: Series Loaded Resonant
SPLR: Series Parallel Loaded Resonant
THD: Total Harmonic Distortion
VHDL: Verilog Hardware Description Language
xvii
VSI: Voltage Source Inverter
ZCS: Zero-Current Switching
ZVS: Zero-Voltage Switching
Symbols:
Cr: resonant capacitor
Ci: input EMI capacitor
d: duty ratio
Ts: switching period
Tsp: sampling period
fc: crossover frequency
fs: switching frequency
fL: line frequency
fo: corner frequency
fr: relative operating frequency
fign: ignition frequency
G: scale-down factor
ki: integrator gain
ωL: angular line frequency
ωo: angular corner frequency
ωs: angular switching frequency
Vp: amplitude of line voltage
is: input line current
iin: inverter input current
iLb: buck-boost inductor current in proposed circuit
iout: output lamp current
ids: MOSFET current
ires: resonant current
is,1: fundamental component of input line current
Lr: resonant inductor
Li: input EMI inductor
Pi,avg: input average power
xviii
Po,avg: average power at the output of PFC stage
Po,avg,nor: normalized average power at the output of PFC stage
Rlamp: steady-state lamp resistance
Tloop(s): loop transfer function in frequency domain
rfil: filament resistance
vout: output lamp voltage
vdc: DC-link voltage
Vdc: average value of DC-link voltage
Vpp: peak voltage of saw-tooth signal at PWM
Vp: amplitude of input line voltage
vs: input line voltage
vds: MOSFET voltage
vcr: resonant capacitor voltage
Zin: steady-state input impedance of resonant circuit
zo: small signal output impedance of resonant inverter
zlamp: fluorescent lamp incremental impedance (small signal model)
α: Firing angle of phase-cut dimmer
Δ1: discontinuous portion of PFC inductor current
Q: quality factor
( )ti : phasor current
( )tv : phasor voltage
1
Chapter 1
Introduction
Over time, incandescent lamps, also known as electric lamps, have proven to be a reliable
source of light and have therefore dominated the lighting industry. The incandescent lamp
became even more desirable to the public by the introduction of incandescent lamp dimmers. The
dimmers added value to the incandescent lamp by giving consumers the flexibility of selecting
their desired lighting levels. While incandescent lamps are able to provide excellent light quality
and performance, they suffer from very low power efficiency. The power efficiency of an
incandescent lamp can be as low as 10%; the majority of the energy consumed by the lamp is
dissipated as heat rather than visible light [1]. The incandescent lamp’s low power conversion
efficiency prompted the development of alternative lighting solutions such as high power lighting
emitting diodes (LED) and compact fluorescent lamps (CFL).
LEDs, presents many advantages over the incandescent lamps such as lower energy
consumption, longer lifetime, improved robustness, smaller size, and greater durability.
However, due to the use of semiconductor diodes in LED lamps, current LED general lighting
products are far more expensive to buy than incandescent lamps and CFLs of comparable light
output. Another disadvantage would be that LEDs requires very precise current and heat
management. The performance of an LED lamp is highly sensitive to the ambient temperature of
the operating environment [2][3]. When the LED is operating in a high ambient temperature
environment with a high driving current, the LED package can overheat and eventually lead to
device failure. LED lamp is also incapable of producing uniform light intensity; it cannot
produce the same light intensity in all directions [2]. This particular shortcoming of LED lamp
2
limits its application; where a continuous spherical field of light is always required. The
aforementioned problems associated with the LED have hindered its entrance into the mainstream
lighting industry.
CFL is a type of fluorescent lamp that was first introduced into the market in the 90s to
provide consumers with a more energy-efficient lamp. Due to their differences in structure and
operating principles, a CFL consumes only one-third of the power consumed by its incandescent
lamp counterpart and its lifetime is 1000 times that of an incandescent lamp [4]. Figure 1-1
illustrates the power consumption comparison between a standard CFL and different kinds of
incandescent lamps. It can be observed that to produce the same amount of light output, the
power consumed in a CFL is indeed much less than the power dissipated in an incandescent lamp.
Hence, the CFL is invaluable since it can provide the same light output as incandescent lamps
while significantly lowering energy cost and conserving energy. When compared to LED lamps,
the CFL’s performance resembles that of incandescent lamps more closely and is less sensitive to
ambient conditions. As a result, the energy efficient CFLs have become the incandescent lamp’s
successor and will dominate the lighting industry.
Since 2005, countries such as Brazil and Cuba began phasing out the use of incandescent
lamps and promoted the wide-spread use of CFL to the public. Similar policies have been
sanctioned in North America, and will be in effect in the very near future. Canada, for example,
has already announced that the federal government's intends to prohibit the sale of incandescent
light bulbs from 2012 onwards. According to Canada Federal Environment Minister, John Baird,
the country will be able to save somewhere from $3 to $4 billion Canadian dollars over the
lifetime of the energy-saving light bulbs [5]. In Europe, the phase-out process of the
incandescent lamps is more systematic. Incandescent bulbs that have power rating of over 100W
3
will be the first types of lamps to be banned on the market. The banned power range for
incandescent lamps will gradually expand to include lower wattage bulbs. Presently, all the
European countries under the European Union (EU) have agreed to the progressive phase-out of
incandescent light bulbs by 2012. Table 1-1 summarizes the countries and their corresponding
phase out target completion year of incandescent lamps.
Figure 1-1 Energy consumption curves for different kinds of lamp [4]
Table 1-1 Incandescent lamps phase-out calendar
Country Incandescent lamps phase-out year
Brazil, Cuba 2005
Argentina, Australia, Ireland, Switzerland 2009
Philippines 2010
Italy, Russia, United Kingdom 2011
Canada 2012
U.S. From 2012 to 2014
4
With the impending mandatory substitution of incandescent lamps with CFLs, the need
for high performance CFLs that can emulate the incandescent lamp’s performance becomes
apparent. However, although CFLs’ efficiency is superior to that of incandescent lamps, standard
CFLs are not compatible with existing dimmer switches and dimmable CFLs do not have stable
light output when dimmed. The reason for the performance differences between incandescent
lamp and CFL lie in their structural differences and their methods of producing light. Before any
extensive discussions regarding the CFL (or fluorescent lamp) operating requirements, it is
necessary to provide some background information regarding the basic structural and operating
differences between incandescent and fluorescent lamp.
1.1 Incandescent lamps VS Fluorescent lamps
One of the major differences between fluorescent and incandescent lamps is the way they
generate light. Incandescent lamps use the Joule-heating process by electrically heating the
tungsten filaments inside the glass tube to increase the lamp brightness. Since the resistance of an
incandescent lamp is governed by the tungsten filament (which behaves like a resistor), the lamp
current is simply equal to the applied input voltage divided by the filament resistance of the lamp.
Essentially, incandescent lamp behaves as a resistive load as shown in Figure 1-2(a). The power
of the lamp is easily adjusted since the lamp voltage and current are more or less directly
proportional to each other. However, as mentioned before, only 10% the energy consumed by the
incandescent bulb is converted to visible light. The incandescent lamp has such poor efficiency
because the majority of the energy is wasted in the form of heat and infrared radiation.
In a bid to solve the poor energy conversion efficiency of incandescent lamps, low
pressure gaseous discharge lamps (also known as fluorescent lamps) were developed. Rather
than heating up the tungsten filament to generate light, the fluorescent lamp generates light by
5
utilizing the phenomenon of inelastic scattering of electrons. Visible light is produced by a
chemical reaction called fluorescence. Three key elements are required in the transformation of
electrical energy into visible light: highly mobile electrons, mercury atoms, and phosphor. When
a highly mobile electron collides with a mercury atom in the gas inside the fluorescent tube, the
electron transfers energy to the atom’s outer electron and causes that electron to jump to a higher
energy level. Since this energy level is highly unstable, the electron falls back to a lower energy
level and an ultraviolet photon will be emitted from the atom. However, the ultraviolet photon is
emitted at a wavelength that is not visible to human eyes. A phosphor layer is then coated on the
interior of the tube so that the photon is emitted at wavelengths that are visible to human eyes.
From the above description, it can be observed that the structural design of a fluorescent
lamp is more complicated than the incandescent lamp. When the fluorescent lamp is turned on,
the electric power quickly heats up the electrodes that are located at the end of the tube to emit
electrons. These electrons then collide with and ionize the gas atoms surrounding the filament.
As a result of avalanche ionization, the conductivity of the ionized gas rapidly rises, allowing
higher currents to flow through the lamp. If the voltage and current of the fluorescent lamp is
displayed graphically according to the aforementioned explanation, it can be deduced that
fluorescent lamp essentially inherits negative resistance as shown in Figure 1-2(b). The presence
of this negative resistance physically means that as the fluorescent lamp current increases, the
lamp voltage decreases, which lead to the lamp resistance to decease and allow more current to
flow through the lamp. If the lamp is connected directly to a constant-voltage supply, the lamp
will be damaged due to the uncontrolled current flow. As a result, a lamp current stabilization
element called ballast must be required in all the fluorescent lamps to prevent the uncontrolled
amount of current flowing into the lamp.
6
(a) (b)
Figure 1-2: (a) Incandescent lamp V-I curve; (b) Fluorescent lamp V-I characteristics
1.2 Magnetic Ballast VS Electronic Ballast
As mentioned in the previous section, fluorescent lamps cannot be directly connected to
the AC main since it will cause the lamp current to become unstable and will eventually destroy
the lamp. In order for stable lamp operation, it is necessary to have a device (known as a ballast)
to act as an interface between the AC mains and the lamp. In electronic circuits, the simplest way
to limit the lamp current is to place a reasonably sized resistor between the input voltage source
and the lamp. However, the placement of a resistor in the circuit will result in significant power
loss. Since the signals at the fluorescent lamp terminals are AC, a reasonably large inductor can
be used to provide the necessary impedance to limit the lamp current (once the lamp has been
ignited) in place of a resistor. There are two main types of ballasts: Magnetic and electronic. The
first ballasts used with fluorescent lamps were magnetic and its two major advantages are its cost
effectiveness and its simplicity. Magnetic ballasts mainly consist of a large magnetic coil that
operates at the line frequency. Their application has become limited due to the following
disadvantages: (1) the magnetic coil is large and is very heavy; (2) since the ballast operates at
the line frequency, the arc within the lamp glass tube is reignited twice during each line frequency
cycle (this results in significant wear on the lamp electrodes and visible flickering); (3) there is no
7
way to implement advanced dimming control to adjust lamp power; (4) the lamp efficacy, which
is defined as lumens per watt, is very poor when the lamp operates at very low frequency. The
last point is illustrated by Figure 1-3, which shows the relationship between the output lumens of
a fluorescent lamp as a function of the lamp operating frequency [6]. It is observed that as the
operating frequency is increased to above 20 kHz, an improvement of more than 10% is achieved
in the lamp efficacy.
The drawbacks of the magnetic ballasts led to the development of high frequency
electronic ballasts based on advanced electronic circuitry. Unlike magnetic ballasts, electronic
ballasts are designed to operate at high frequency. High frequency operation improves the lamp
efficacy, reduces the circuit component size, and allows easy lamp starting. In addition, when the
ballast operates at high frequency, the ions inside the discharge tube do not have enough time to
recombine with the highly mobile electrons. Because the recombination does not take place, the
magnetic ballast’s re-ignition problem and flickering noise do not exist in electronic ballasts.
Figure 1-4 shows the typical current and voltage waveforms of a fluorescent lamp that uses a high
frequency electronic ballast. It can be observed in the figure that a high output voltage must be
provided until the arc is established inside the lamp so that the lamp current will start to flow.
Due to the negative lamp impedance phenomenon, the envelope signal of the lamp voltage and
current changes in the opposite direction when the lamp power changes. The lamp current
decreases at a much faster rate than the lamp voltage’s rate of increase. Therefore, due to their
many advantages over magnetic ballasts, electronic ballasts are widely used in the fluorescent
lighting industry and its design plays a key role in providing consumers with highly energy
efficient fluorescent lighting.
8
Figure 1-3 Efficacy of fluorescent lamp VS lamp operating frequency [6]
Figure 1-4 Illustration of typical voltage and current waveforms in electronic ballast
1.3 Basic Requirements of Electronic Ballasts
An electronic ballast is essentially an electronic device that converts the low line frequency AC
signal to a high frequency AC signal to drive the fluorescent lamp. The basic functions of the
9
electronic ballast are: (1) to provide sufficient high voltage across the lamp electrodes during the
lamp ignition process; (2) to stabilize the high frequency lamp current after the lamp is
successfully ignited; (3) to perform power factor correction (PFC) so that the harmonics of the
line current is minimized.
Power factor correction is critical in ballast designs because the fluorescent lamp is
essentially a load that consumes power from the AC main and (depending on the circuit design)
can inject harmonics into the utility. The more harmonics the line current has, the more
harmonics are injected and the overall power factor drops. The significance of PFC will be
further discussed in the next section. Magnetic ballasts also incorporate PFC since the inductive
coil introduces a lagging power factor (PF) at the line input. PFC is implemented in magnetic
ballasts by placing a capacitor in parallel with the ballast so that the input sinusoidal line current
becomes in phase with the line voltage. Electronic ballasts, on the other hand, implement PFC
by using advanced power electronic circuits. The details regarding the PFC techniques used in
electronic ballasts will be discussed later in this chapter. Figure 1-5A is a general block diagram
of a commercial CFL electronic ballast. The commercial ballast consists of three main parts: (1)
a diode rectifier that converts the AC line voltage to a rectified sinusoidal voltage; (2) a PFC
circuit that allows the input current becomes a sinusoidal signal that is in phase with the line
voltage; (3) a DC-AC inverter that converts the DC voltage into high frequency signal to drive the
fluorescent lamp. In addition, a control circuit can be included to provide more advanced
functions such as dimming control of the lamp, lamp end-of-life detection, or lamp over-voltage
protection.
10
Figure 1-5 Block diagram of electronic ballast with PFC in commercial fluorescent lamps
1.3.1 Measures of Electronic Ballast Performance
As mentioned in the previous section, PF is an important measure for the ballast circuit’s
performance because it defines the quality of the line current drawn by the fluorescent lamp. PF
is defined to be the input real power (P) divided by the input apparent power (S) as shown in (Eq.
1-1), where S is the product between the input RMS voltage (vrms) and input RMS current (irms).
PF is also defined as the product between the input displacement PF (DPF) and kd . DPF is
defined as the cosine of the phase angle between the line voltage and the fundamental component
of the line current (is,1), and kd is the ratio between is,1 and irms. Therefore, a high PF can be
achieved if kd equal to one; kd is equal to one when the fundamental component of the line current
is equal to the RMS line current and DPF equals to unity.
( ) ( ) ddrms
s
rmsrms
srms kii
iviv
SPPF θθ
θ==== 1
1,11, coscos
(Eq. 1-1)
Total harmonic distortion (THD) is the term used to define the amount of harmonics present in
the line current. THD is defined in (Eq. 1-2) as a function of PF. Figure 1-6 is a plot of (Eq. 1-2)
and it can be used to illustrate the relationship between PF and THD.
11
Figure 1-6 Input line current THD vs input PF
Ideally, when PF is equal to one, THD is equal to zero. As one can see from Figure 1-6, THD
increases exponentially with respect to a linear decrease in the PF; when the PF value is 0, the
corresponding THD value is infinite. Therefore, the relationship between the PF and THD implies
that in order to minimize the harmonic content in the line current, it is necessary for the
fluorescent lamp to achieve high input PF.
112 −=
PFTHD (Eq. 1-2)
Another important measure of the ballast performance is the crest factor (CF) of the lamp current
(see (Eq. 1-3); it is defined as the ratio between the RMS lamp current (ilamp,rms) and the peak lamp
current (ilamp,pk). A pure sinusoidal lamp current has a CF of 1.4. The American National
Standards Institute (ANSI) [7] specifies that the maximum CF allowed is 1.7. Studies have
shown that higher CF can lead to shorter lamp life and wears out the lamp electrodes much faster.
The use of a modulated current to drive the lamp may result in a high CF, and therefore cause
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10
100
200
300
400
500
600
700
800
900
1000
Input power factor
Line
cur
rent
TH
D (%
)
12
flickering. In order to achieve an acceptable CF value, the modulation drive signal must be small
enough so that large variations in the lamp current envelope will be avoided.
rmslamp
pklamp
ii
currrentlampRMScurrentlamppeakCFlamp
,
,==
(Eq. 1-3)
In general, fluorescent lamp ballast circuits, whether magnetic or electronic, should always draw
a high quality line current with high PF and the output lamp CF should be minimized to extend
the lamp life time and enhance its performance.
1.4 Review on Resonant Inverter Topologies in Electronic Ballast
As shown in Figure 1-5, electronic ballasts have a resonant inverter stage that converts the DC-
link voltage into high frequency AC signal to drive the fluorescent lamp. Most of the DC-AC
conversion process in electronic ballasts is performed by using voltage source resonant inverters
(VSI) due to its robustness, circuit simplicity (ease of achieving soft-switching), and it is easily
implemented. The three basic types of resonant tank circuits used in VSIs are [8]: series loaded
resonant (SLR); parallel loaded resonant (PLR); and series-parallel loaded resonant (SPLR). All
of the aforementioned VSI resonant circuits are displayed in Figure 1-7. The voltage fed PLR
inverter, has the most desirable voltage gain characteristic for electronic ballast applications
[9][10][11]; this circuit will be discussed in detail later in the section. In the analysis presented
in the next section, the lamp resistance is considered to be extremely high during the lamp
ignition stage so the load of the resonant circuit is represented by an open circuit. After the lamp
ignition, the lamp becomes a finite resistive load at the output of the resonant circuit and it begins
to consume power at this stage. In Figure 1-7, rfil represents the lamp filament resistance and
Rlamp represents the steady-state lamp resistance.
13
1.4.1 Half-Bridge Resonant Inverters
The voltage source half-bridge resonant inverter is a common type of VSI that is used in
electronic ballasts. There are three variations of the voltage source half-bridge resonant inverter
configuration and they are illustrated in Figure 1-7. Since a high quality factor (Q) is normally
selected for resonant circuit design (to reduce the harmonics at the output load), fundamental
approximation is always used to simplify the circuit analysis. When performing fundamental
approximation, only the fundamental component of the input square wave voltage (vab) is
considered. The voltage gain plots (|vout/vab1|) of the SLR, PLR and SPLR resonant circuits are
given by Figure 1-8, where vab1 represents the fundamental component of vab.
In the SLR circuit case, it can be observed that |vout/vab1| is always equal to one regardless
of any changes in Qs. Qs is defined by (Eq. 1-4), where fo equals to the corner frequency of the
resonant circuit and is given by (Eq. 1-5). When the SLR circuit operates close to resonance, the
impedance provided by Lr and Cr cancels out each other. The ballast circuit elements then cannot
provide current limiting function as vab is connected directly to the lamp. As a result, SLR circuit
cannot not be used in electronic ballast applications in an open-loop fashion. A control circuit
must be required to provide stable operation for the lamp current.
In the PLR circuit, the Qp is defined by (Eq. 1-6), it can be observed that a high output
voltage is obtained when Qp is high (i.e. when Rlamp is large). Physically, this means that a high
output voltage can be achieved during the lamp ignition process even in the absence of a step-up
transformer [10]. A high output voltage can be obtained even when the input of the inverter is
connected to a rectifier with low input line voltage [10]. After lamp ignition, Rlamp decreases and
hence, Q decreases. According to Figure 1-8, |vout/vi| then decreases and allows the lamp voltage
14
drops to its rated value. Therefore, the voltage gain characteristics of the PLR circuit are very
desirable for electronic ballast applications.
The SPLR circuit has the characteristics of both the SLR circuit and the PLR circuit. As
a result, it has the advantages of the PLR circuit and the disadvantages of the SLR circuit. With
regards to the SPLR, the series capacitor Cs and the parallel resonant capacitor Cp need to be
properly tuned so that a sufficiently high voltage can be ensured during the lamp ignition process.
Figure 1-7 Basic Voltage Source Resonant Inverter Topologies
lamp
ros R
LfQ
π2= (Eq. 1-4)
rro CLf
fπ2
1= (Eq. 1-5)
15
ro
lampp Lf
RQ
π2= (Eq. 1-6)
(a) (b)
(c)
Figure 1-8 Voltage gain plots: (a) series LC resonant; (b) parallel LC resonant; (c) series-
parallel LC resonant
In voltage source half-bridge resonant inverters, above resonance operation is always preferred.
By operating the resonant inverter at slightly above resonance, zero voltage switching (ZVS) is
achieved at the switch turn-on transition. The key waveforms for above resonance operation are
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.80
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
relative operating frequency
Vol
tage
gai
n
Q = 1Q = 2Q = 3Q = 4
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.80
0.5
1
1.5
2
2.5
3
3.5
4
4.5
relative operating frequency
Vol
tage
gai
n
Q = 1Q = 2Q = 3Q = 4
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.80
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
relative operating frequency
Volta
ge g
ain
Q = 1Q = 2Q = 3Q = 4
16
illustrated in Figure 1-9, where vab represents the input voltage of the resonant circuit and ids
represents the MOSFET drain-to-source current. When the resonant current (ires) is lagging
behind the fundamental component of the MOSFET voltage (vab1), the negative ires flows through
the anti-parallel diode of the MOSFET to allow the MOSFET to turn on with almost zero voltage
drop. The turn-off switching loss can be minimized by adding a snubber capacitor across the
switch (encircled in Figure 1-9) to slow down the turn-off rate of the switch voltage.
Figure 1-9 ZVS operating waveforms for voltage fed half-bridge resonant inverters
1.4.2 Push-Pull Inverter Configuration
Rather than having the MOSFETs arranged in a half-bridge configuration, they can be
alternatively arranged to be in a push-pull configuration to form a different VSI topology for
ballast applications. The main advantage of this topology is the isolation transformer located in
front of the resonant tank circuit; it provides electrical isolation to the entire system with both
switches referenced to ground. By doing so, isolation devices are not required to provide
isolation in the driver circuit. However, it should be noted that the added transformer in the
resonant circuit increases the weight and size of the power circuit. In addition, each switch will
17
suffer a voltage stress of twice the input voltage when the other switch is off. Therefore, the
push-pull configuration will usually require a MOSFET with a voltage rating much higher than
that of the half-bridge inverter to achieve the same output power.
1.4.3 Class E LCC Resonant Inverter
One of the drawbacks in the half-bridge resonant inverter is that the half-bridge MOSFET
requires some means of isolation circuit in the driver circuit. The class E resonant inverter [20]-
[23], as shown in Figure 1-10, has the advantage of using a single MOSFET when compared to
the half-bridge inverter configuration. The MOSFET gate driver circuit is also much simpler than
those in the half-bridge inverters. Figure 1-10 illustrates the operating waveforms of the class E
inverter.
By allowing the anti-parallel diode (D1) turn on prior to the turn-on of the MOSFET
(to~t1), ZVS is achieved at the turn-on of the MOSFET. The presence of Cr helps to reduce the
turn-off switching loss (i.e. at t2). The resonant circuit composes of a series inductor (Ls), a series
DC-blocking capacitor (Cs) and a parallel capacitor (Cp). The main drawback with the class E
resonant inverter is the high voltage and current stress across the MOSFET. When the MOSFET
is on, the current flowing through the MOSFET is comprised of both the input current (iin) and the
resonant current (ires). Thus, the conduction loss of the MOSFET will be higher than the total
conduction loss of the two MOSFET in the half-bridge inverter configuration. In addition, when
the class E inverter MOSFET is off, its peak voltage is equal to three to five times the input DC
voltage. The increased current and voltage stress on the MOSFET, makes the class E resonant
inverter less appealing for ballast applications where high line voltage (220-240 Vrms) is required.
18
(a) (b)
Figure 1-10 Class E resonant inverter and its key waveforms: (a) theoretical waveforms; (b)
simulation waveforms
1.4.4 Current Source Inverters for Electronic Ballast
Current source inverter (CSI) is implemented by placing an inductor in series with the
input DC voltage source so that a constant current input source can be formed for the inverter
circuit. A common way to implement a CSI is to implement the switches in a push-pull
configuration [12][13][14] as shown in Figure 1-11(a). In some cases, instead of using the push-
pull configuration at the inverter stage, the two primary windings are implemented by using two
separate input inductors, as shown in Figure 1-11(b) [15][16][17], to save one winding compared
to the push-pull configuration. In both circuits, one diode is connected to each of the MOSFETs
19
to disable the anti-parallel diode of the MOSFET. This allows a current square waveform
generated at the input of the resonant circuit. To minimize the reverse-recovery loss in the series
diodes, the input voltage of the resonant circuit should lead the fundamental component of the
input current of the resonant circuit [18][19].
Figure 1-11 Current fed resonant inverter in electronic ballast
One advantage of using CSI at the inverter stage is that electrical isolation can be
provided naturally for the MOSFET drivers and the power circuit without additional isolation
devices. CSIs inherently have PFC when it is connected directly to the output of a rectifier. Its
continuous input current is reflected back to the input of the rectifier and the line current is
continuous and will naturally follow the sinusoidal shape of the line voltage. However, the direct
connection between the CSI and the rectifier cannot be used for electronic ballast applications as
the rectified line voltage will generate a sinusoidal envelope on the lamp current waveform,
causing the lamp CF at the output to be very high. So, in order to use CSI for electronic ballast
applications, some additional means of passive PFC is required.
1.5 Power Factor Correction (PFC) Techniques in Electronic Ballast
Fluorescent lamps, like other electronic loads, draw current from the utility to function.
Since the current drawn by the lamp is the same current that will be seen by the utility, it should
20
have minimal amount of harmonics (high input PF) so that the least amount of energy will be
wasted as reactive power. In electric lighting applications, the ballasts are required to comply
with a certain set of regulations entitled IEC-1000-3-2 Class C (International Electro-technical
Commission) [25] (see Table 1-2). According to Table 1-2, it can be observed that the maximum
allowable THD is proportional to the PF of the ballast circuit. From the standards, it can be seen
that it is preferable for electronic ballasts to draw high PF; higher the PF, the less stringent the
restriction on THD becomes.
The simplest approach to implement PFC in electronic ballast designs is to connect the
output of the rectifier directly cross the input of the inverter stage as shown in Figure 1-12.
Although high PF is achieved, the lamp CF is high at the output. With a pure sinusoidal envelope
imposed on the high frequency lamp current at the output, the lamp CF can easily go over the
limit according to the ANSI standards [58]. However, if Cb is increased to reduce the output
lamp CF, the presence of a large Cb significantly reduces the conduction time of the line current,
which results in poor PF.
Table 1-2 Harmonic limits for IEC1000-3-2 Class C equipment [25]
Harmonic Order (n) Max harmonic as a % of fundamental of line current (%)
2 2
3 30*PF
5 10
7 7
9 5
11 < n < 39 3
21
(a)
(b)
Figure 1-12(a): Electronic ballast without DC-link capacitor; (b) with DC-link capacitor;
Therefore, electronic ballasts should have a PFC stage that allows the circuit to achieve
both a high PF at the input and a good CF at the output. There are two different types of PFC
techniques: active PFC and passive PFC. Different PFC circuits have been proposed for
electronic ballast applications.
The major difference between active PFC and passive PFC is the way that they are
implemented. Active PFC uses a DC-DC converter with modulation techniques that control the
switch to shape the input line current. Passive PFC, on the other hand, only uses passive circuit
22
components such as inductors, capacitors and diodes to achieve PFC. Numerous studies and
comparisons have been conducted on the two different types of PFC techniques [26][27]. This
section will highlight and describe the different kinds of PFC techniques that are used in
electronic ballasts. This section will focus on the comparison between the performance of active
PFC and passive PFC in electronic ballasts.
1.5.1 Active PFC in Electronic Ballasts
Active PFC uses the switch in the power converter to control the line current so that a
very high PF can be obtained at the input. High PF is achieved by the control of the inductor
current in a DC-DC converter that is connected at the output of the diode rectifier. The control of
the inductor current can be achieved through two different approaches: Continuous Conduction
Mode (CCM) and Discontinuous Conduction Mode (DCM). In CCM, the inductor current is
continuous with very low ripple and it does not decrease to zero within a switching period. To
use CCM an input feed-forward loop is required to feed-forward the rectified line voltage as a
reference signal so that the inductor current follows the sinusoidal shape given by the rectified
voltage. CCM requires a more complicated control structure compared to DCM so it is not
commonly used in high PF electronic ballasts. Contrary to CCM, the inductor current in DCM
control, decreases to zero within a switching period and the peak of the DCM inductor current
always follows the shape of the input line voltage. With this approach, the peak of the inductor
current naturally follows the shape of the rectified line voltage and a close-to sinusoidal line
current can be drawn at the input. In comparison to CCM, the DCM control structure is more
cost-effective for low power applications since it does not require any feed-forward control loops
to achieve PFC.
23
A typical system configuration of an electronic ballast that incorporates active PFC is
shown in Figure 1-13(a). The circuit configuration depicted in Figure 1-13(a) requires a control
circuit for the PFC converter and a control circuit for the resonant inverter, which results in a
large and expensive circuit. It also uses the two-stage approach, so there are two energy
conversion processes that take place. Each energy conversion process results in some energy
loss, so more energy conversion stages lead to lower overall power efficiency.
Figure 1-13 (a) Two-stage electronic ballast; (b) Single-stage electronic ballast
In order to address the issue of increased efficiency loss due to multiple energy
conversion stages and size of the overall circuit, single-stage inverters (SSI) have been developed
(see Figure 1-13(b)) by combining the front-end DC-DC converter and the voltage fed resonant
24
inverter into one stage [30]. Because the switch in the DC-DC converter can operate
synchronously with one of the switches in the half-bridge resonant inverter, the two switches can
be replaced by one (as shown in Figure 1-13(b)) to form the SSI. With this approach, there is
only one energy conversion process and will therefore be more cost-effective and will have a
higher efficiency than the two-stage approach. The SSI approach also saves a control circuit
compared to the two-stage approach for the PFC stage and increases the overall system reliability.
A drawback of the SSI however, is that the shared switch will suffer from higher voltage and
current stress than the switches used in the two-stage approach, depending on the type of PFC
circuit used. Different types of single-stage high PF electronic ballasts will be studied in detail in
this section.
1. Single-stage ballast with boost PFC
The conventional DC-DC converter used in the electronic ballast’s active PFC stage is the boost
converter. This is because the boost converter has its inductor connected in series at the output of
the diode rectifier. By applying the synchronous switch concept outlined in [27, 39, 40], a single-
stage electronic ballast that uses the boost converter for PFC was developed and is depicted in
Figure 1-14.
The input line current expression for a DCM operating boost converter is given in (Eq.
1-7), where Lb is the boost PFC inductor. In order to achieve a close-to-sinusoidal line current,
the term (Vp/Vdc) in (Eq. 1-7) should be as small as possible. In other words, if Vc > Vp, the input
current will closely follow the shape of the input line voltage and thus, high PF can be achieved.
This means that a high DC-link voltage is required in the DCM boost PFC to draw a sinusoidal
line current. However, since a large Vdc is required to keep (Vp/Vdc) small, then there will be high
25
voltage stress on the MOSFET since the voltage across the MOSFET is equal to the DC link
voltage. As a result, there is a trade-off between the performance of the boost PFC (high PF) and
the DC-link voltage (MOSFET voltage stress). In order to get a desirable PF, the DC-link voltage
can be as high as twice the line voltage. This trade-off characteristic of the DCM boost PFC
restricts it from being used for high line voltage applications (e.g. Asian countries where 220Vrms
is the household standard).
Figure 1-14 Single-stage electronic ballast with boost PFC
( ) ( )
( ) ⎟⎟⎠
⎞⎜⎜⎝
⎛−
=t
VV
Lf
dtVti
Ldc
pbs
LpLs
ω
ωω
sin12
sin 2
(Eq. 1-7)
26
2. Single-stage ballast with Flyback PFC
As a solution to the high DC-link voltage problem in the single-stage boost type resonant
inverter, a step-up/down converter is used instead of the boost converter. Figure 1-15 is an
example of an SSI that was created by the integration of a step-up/down converter and a half-
bridge resonant inverter. In this example, the step-up/down converter used is a flyback converter.
Figure 1-15 Single-stage electronic ballast with flyback PFC
The main advantage of the flyback PFC is that by operating in DCM with constant switching
frequency and duty cycle, it can draw a close-to sinusoidal line current that is in phase with the
line voltage [43]. (Eq. 1-8) describes the average input current drawn by a flyback converter.
The parameters in (Eq. 1-8) are as follows: fL is the line frequency; L1 is the primary inductance
27
of Tr; Ts is the switching frequency and d is the operating duty ratio. It is observed that a
sinusoidal line current can naturally be achieved while the DC-link capacitor and MOSFET do
not suffer from high voltage stress. The turns ratio of the coupled windings (Tr) in the PFC stage
is an additional design parameter that allows the selection of the inverter input voltage to
optimize the ballast operations. A drawback of this circuit configuration is the increased weight
and size of the overall circuit due to the magnetic circuit component (Tr). Another drawback of
using the flyback PFC compared to the boost PFC is that it also requires two more diodes.
( ) ( )tfL
TdVtfi L
spLs ππ 2sin2
1
2
= (Eq. 1-8)
3. Single-stage ballast with Buck PFC
Figure 1-16 is the circuit diagram of a single-stage electronic ballast that uses a buck
converter to achieve PFC [44, 45]. This topology has lower voltage stress across the shared
MOSFET than the boost PFC SSI due to the step-down voltage gain characteristics of the buck
converter. By using the buck converter, the buck PFC SSI inherits the buck converter’s natural
protection against the no-load condition. However, the buck PFC stage has the disadvantage of
drawing a line current with limited conduction time. This is due to the fact that the average
output voltage vdc of the buck converter is always smaller than the rectified voltage vrect. As a
result, the diode rectifier only conducts when vrect is higher than vdc. Figure 1-17 presents the key
waveforms of a buck PFC circuit. Since the line current conduction time is limited, the PF
achieved is lower than the other single-stage topologies with active PFC. According to Figure
1-17, the input PF can be increased by extending the conduction time of the line current. The
conduction time extension can be achieved by decreasing the duty ratio of the MOSFET so that
28
the output DC voltage will decrease. However, it is important to note that the output voltage of
the buck PFC stage is a key parameter that controls the lamp ignition voltage. If the duty ratio of
the shared MOSFET is too small, the ignition voltage will not be high enough at the output of the
inverter stage to ignite the lamp. Therefore, the duty ratio of the shared MOSFET must be
appropriately selected so that the buck PFC can provide the lamp with a sufficiently high ignition
voltage while achieving a considerably high PF. In practical situations, a capacitor (Cin) is
required across the output of the rectifier to suppress the high frequency noise in the rectified
voltage (as shown in Figure 1-16).
Figure 1-16 Single-stage electronic ballast with Buck PFC
29
(a) (b)
Figure 1-17 Input waveforms of buck PFC: (a) theoretical waveforms; (b) simulation
waveforms
1.5.2 Passive PFC in Electronic Ballasts
Passive PFC, as its name implies, only passive circuit elements are used to achieve PFC. There is
no control circuits required since switches are not used for PFC. The main advantage of using
passive PFC over active PFC is that it has less circuit complexity, and is more cost effective. The
main drawback of this approach however, is that large filters are required at the input to achieve
comparable performance with that of active PFC. The three major types of passive PFC
techniques used in electronic ballast applications are: (1) L-C filter approach, (2) valley-fill
circuit approach and (3) Charge pump capacitors approach.
(1) L-C Filter Approach
Several types of L-C filter circuits for passive PFC have been discussed in literature [28][29]. By
placing a properly designed L-C filter between the rectifier and the inverter stage, as shown in
Figure 1-18, the harmonic components of the input line current can be filtered out. Since the L-C
30
filter is required to filter out the harmonics located at the multiples of the line frequency, an
extremely large inductor and capacitor is necessary. It should also be noted that when a large
capacitor is used in the L-C filter, it can introduce a phase difference between vs and is. Hence,
the L-C circuit is not used for PFC purposes; rather, it is only used as an electromagnetic
interference (EMI) filter in electronic ballasts where smaller inductors and capacitors are used.
Figure 1-18 Passive L-C filter PFC electronic ballast
(2) PFC with valley-fill Circuit
The valley-fill PFC approach is used in electronic ballast applications because the valley-fill
circuit can achieve an input PF of 0.9 and is more cost-effective than all the active PFC options.
The valley-fill circuit consists of two capacitors and three diodes as shown in Figure 1-19(a)
[31][33][34]. The key waveforms of the valley-fill circuit are shown in Figure 1-19(b). From
Figure 1-19(b), it can be observed that at t = t1, diode D3 turns on, and the line voltage charges up
both capacitors C1 and C2. This charging action of the both capacitors causes a peak in is. During
the period t3 < t < t4, the voltage at the output of the rectifier (vc) is less than the line voltage and
as a result, is equals to zero. One drawback of this PFC approach is the limited line current
conduction time. The limited conduction time leads to a high THD where the magnitudes of the
harmonics can exceed the IEC 1000-3-2 Class C standard. Another disadvantage of the valley-
fill circuit is the low frequency voltage envelope generated at the input of the resonant inverter
31
that results in high lamp current CF. In [34], frequency modulation control was proposed to
regulate the lamp current so that the lamp current envelope will not affected by the low frequency
voltage (generated by the valley-fill circuit).
(a)
v
vc
s Vp
t t0 3 4t 1 t2 t 7t5t t6
ωt
ωt
ΔV
2Vp
is
ωt
(i) (ii)
(b)
Figure 1-19 (a): Valley-fill PFC electronic ballast; (b) its key waveforms: (i) theoretical
waveforms; (ii) simulation waveforms
To improve the THD problem in the conventional valley-fill circuit, the authors in [35] proposed
a modified VF circuit (see Figure 1-20). An additional capacitor and three diodes were added to
32
the conventional circuit to extend the line current conduction angle. With the modified VF
circuit, a PF of at least 0.97 was achieved. This circuit also generates larger voltage variation at
the input of the inverter stage when compared to the conventional valley-fill circuit. This means
that the lamp CF will be higher when the modified valley-fill circuit is used rather than the
conventional valley-fill circuit. However, frequency modulation (as discussed in [34]) can be
used for the modified valley-fill circuit to regulate the lamp current so that an acceptable lamp CF
is maintained.
Figure 1-20 Modified valley-fill PFC circuit
(3) PFC with Charge-pump Technique
Another passive PFC circuit used in electronic ballasts is based on the charge pump PFC
concept [36] [37]. This PFC circuit was developed to eliminate the need of a large inductor that
would normally be used in the boost PFC circuit. The circuit diagram of a charge-pump PFC
electronic ballast is given in Figure 1-21. By using the charge-pump PFC circuit, the line current
is regulated to follow the input line voltage by diode Din and capacitor Cin. The idea behind this
PFC strategy is to have Cin regulate the input current by forcing the voltage DC-link voltage vdc to
always be higher than the input voltage vs. In this way, the positive input current will be equal to
33
the charging current of Cin. If the voltage variation across Cin follows the input sine rectified
voltage, the input current will follow the shape of the input voltage and thus high PF will be
achieved. This PFC technique is very attractive for high PF ballast circuit designs because the
conventional PFC inductor used in the DCM boost converter is too bulky and needs to handle
high current. Careful design of the boost PFC inductor is always required.
Figure 1-21 Charge-pump PFC electronic ballast
Although charge-pump PFC concept is able to reduce the overall cost by reducing the number of
inductors, it has its disadvantages as well. Since a high value of vdc is necessary to provide the
required ignition voltage across the lamp, the first disadvantage is the high DC-link voltage
across Cb during the lamp ignition process. Secondly, the charge-pump has a high lamp CF at the
output. Since the capacitor Cin becomes part of the resonant circuit at the inverter stage, the
voltage across Cin, has the shape of a rectified sinusoidal signal and is reflected on the envelope of
the output lamp current. Consequently, a continuously varying voltage signal with twice the line
frequency will be imposed on the lamp current envelope and results in high lamp CF. One way to
improve the high lamp CF problem is to modify the charge-pump circuit by adding clamping
diodes to the original circuit. These diodes limit the peak of the sinusoidal envelope imposed on
34
the high frequency output signal. It should also be noted that the addition of the clamping diodes
does not affect the high PF achieved at the input (as with the original circuit). Therefore, low
lamp CF can be achieved at the expense of additional diodes in the ballast power circuit.
1.6 Dimming Control
In lighting applications, it is not always desirable to have the lamp operating at its full
power condition. Some consumers may want to adjust the light output to suit their preferences.
When the lamp power is decreased, the level of the light output will also be decreased; this
process is called dimming. Since the incandescent lamp behaves as a purely resistive load from
the electrical circuit point of view, the easiest way to achieve dimming in incandescent lamps is
to decrease the magnitude of the input line voltage. In practice, rather than controlling the
amplitude of the line voltage, dimming in incandescent lamps is achieved by decreasing the
conduction time of the input line voltage (as shown in Figure 1-22) by the use of phase-cut
dimmers.
Since the lamp power is equal to the product between the line voltage and the line
current, the lamp power is controlled accordingly by adjusting the conduction time of the line
voltage. Most of the phase-cut dimmers are triac (Silicon-Controlled Rectifier) or transistor
based. This means that when a firing angle is applied to the phase-cut dimmer, it will conduct
until the end of half of the line cycle as current is drawn continuously over this period. Since the
incandescent lamp acts as a linear resistive load at the output of the AC main, the lamp power (or
the brightness of the lamp), can be easily controlled smoothly in a linear manner.
35
Figure 1-22 Key waveforms of phase-cut dimmers used in incandescent lamps
Fluorescent lamps, however, act as non-linear loads from the AC main point of view due
to the presence of the ballasts. Therefore, the smooth dimming of these lamps is not as straight
forward. In practice, the following dimming control methods are used in dimmable electronic
ballasts to achieve smooth dimming operation: (1) duty ratio control; (2) variable frequency
control; (3) phase angle control and (4) DC-link voltage control. In this section, each dimming
control method will be discussed in detail.
1.6.1 Duty Ratio Control
Duty cycle control method, also known as Pulse Width Modulation (PWM), is one of the most
widely used control methods in power electronics. The basic idea in duty cycle control is to
adjust the pulse width of the input voltage square-wave generated at the input of the resonant
circuit [46]. The duty cycle (d) value changes depending on the control objective and it ranges
36
from 0 to 1. In the half bridge inverter case, the two switches are required to turn on and off
alternately with a maximum d of 0.5. By controlling d, the average voltage of the input square-
wave transferred to the output will be controlled, and therefore adjust the lamp power.
However, in practical situations, d should be less than 0.5 to prevent the two switches from being
both on or off at the same. Therefore in half-bridge resonant inverters, duty cycle control results
in a relatively narrow dimming range because the duty cycle has a narrow range of values that it
can vary from (0 < d < 0.5). Another disadvantage of the duty ratio dimming control in half-
bridge resonant inverters is the loss of ZVS at light load (i.e. low dimming level) conditions. This
occurs because there is less time for the lagging resonant inductor current to flow through the
anti-parallel diode of the MOSFET prior to the turn-on of the MOSFET. In order to ensure ZVS
operation under light load conditions, an extra inductor must be connected in front of the series
resonant inductor [47][48]. Although ZVS operation can be extended to include light load
conditions, the switch conduction loss will be increased. As a result, duty ratio control is not
commonly used in half-bridge resonant inverter for dimmable ballast applications.
1.6.2 Variable Frequency Control
It is well known that the input impedance of the resonant circuit is a function of the switching
frequency. When the switching frequency of the input impedance of the resonant circuit varies,
the energy transferred to the output will also change. Thus, the output lamp power can be
controlled by changing the switching frequency of the resonant inverter [49][50]. From the
voltage gain plot shown in Figure 1-8 for VSI, it is observed that the lamp output voltage is
attenuated as the switching frequency is increased further away from resonance. The use of
variable frequency control to adjust the lamp power is a big improvement over duty cycle control,
since the limited control range of the duty cycle limits the dimming range of the lamp. With
37
variable frequency control, ZVS operation and soft-switching can be ensured for all operating
conditions (i.e. a wide range of dimming levels). However, in order to achieve a wide dimming
range, a wide switching frequency control range is necessary. Because of this, dimmable ballast
circuits that employ variable frequency control requires more complicated EMI filter designs than
dimmable ballast circuits with constant frequency control. A wider range of switching frequency
results in increased generated noise. Since the role of the EMI filter is to suppress any noise
generated by the ballast, EMI filters become more complex when the range of switching
frequency is widened.
1.6.3 Phase-Shift Control
Phase shift control [51][52] is the most recently conceived dimming control method for
use in dimmable electronic ballasts. According to the basic real power equation as shown in ((Eq.
1-9), the power is a function of the phase difference (θV-I) between the AC voltage and current.
The idea behind phase shift control is to vary the phase difference between the voltage generated
at the inverter's input and the resonant current; the changes in the power transferred to the lamp is
therefore induced by the changes in the phase difference.
For the PLR inverter case, the input phase angle of the resonant circuit is plotted in
Figure 1-23 as a function of the relative operating frequency. It can be observed that when Q is
high, there is a strong phase inversion from -90˚ to 90˚. Dimming is achieved by controlling the
phase difference (θrun) between the input voltage and the resonant current (in the range between
0˚ and 90˚). Figure 1-23 illustrates the key waveforms of the resonant inverter stage under phase
shift control. The resonant current (ires) is shifted -90˚ from the input voltage during ignition, and
is shifted somewhere between 0˚ and -90˚ during steady-state operation. A zero phase-shift
38
implies maximum power transfer to the output. However, in order for ZVS to be achieved under
all load conditions, the control of the phase angle must be carefully designed.
IVVIP −= θcos (Eq. 1-9)
Figure 1-23 Key waveforms at the resonant inverter stage in phase-shift control
1.6.4 DC-link Voltage Control
Another dimming control method that can be used in dimmable electronic ballast is the
DC-link voltage control [53, 54, 55]. Instead of controlling the switches in the resonant inverter,
this method controls the lamp power by controlling the output voltage of the front-end PFC
converter. Since a PFC converter required for this control method, this method can facilitate the
dimming feature only when dimmable electronic ballasts that use active PFC are used. The DC-
link voltage is controlled by adjusting the duty ratio of the front-end converter. The main
advantage of this approach is that a wide dimming range can be achieved without controlling any
control parameters at the inverter stage. Since the half-bridge switches can be driven by a
constant frequency with fixed 50% duty ratio signal, ZVS can be ensured for both switches
during the entire dimming range. While this control approach is a promising solution for highly
efficient dimmable electronic ballasts, it requires a control circuit at the front-end converter to
39
achieve dimming and another control circuit at the inverter stage to drive the two MOSFETS in
the half-bridge inverter. Therefore, a relatively large control circuit is required to implement this
method and thus increases the size of the overall system.
1.7 Electronic Ballasts in CFL: Features and Drawbacks
Sections 1.4 to 1.6 serve as an extensive literature review that provides basic background
information regarding general electronic ballast circuit design, basic PFC techniques, and
dimming control methods used in fluorescent lighting applications. This section provides
information that is specific to CFL ballast circuits. The operating principle of a CFL is
essentially identical to the other types of fluorescent lamps, with the exception of the CFL tube
being much smaller than conventional fluorescent lamps. Theoretically, all the circuits and
control methods discussed in the previous sections are applicable to CFLs. However, because the
size of a CFL is on a smaller scale, minimizing the size and cost of the overall system becomes a
major design requirement and challenge. A typical low cost commercial electronic ballast that
can be installed at the base of a CFL consists of a diode rectifier, DC-link capacitor, and a half-
bridge parallel resonant inverter [56][57]. Although the overall circuit is very simple and
occupies small system space, the input line current drawn by this circuit configuration is highly
distorted. As mentioned before, distortion in the drawn input line current results in poor input PF
and high THD in the line current. Poor PF implies that a significant portion of the power drawn
by the lamp is wasted as reactive power in the energy conversion process that takes place between
the utility and the lamp. The incandescent lamp ban policies are put in place by the government
officials to save energy. However, if low PF CFLs are used, then the accumulated real power loss
of each individual lamp will be substantial and thus, the ban will not have the desired energy
40
savings effect [58][59]. Currently, the CFLs on the market have poor PF. So, contrary to popular
belief, the replacement of incandescent lamps with these CFLs will not offer any significant
energy savings.
With the impending replacement of incandescent lamps by CFLs in the near
future, it is also important for CFLs to be compatible with the existing incandescent lamp
dimmers. By doing so, it would allow exisiting wiring connections to remain the same, and will
therefore eliminate extra hardware or labor costs when the replacement occurs. Unfortunately,
the design of the current ballast circuit used in CFL restricts the use of these dimmers to perform
similar dimming performance as in the incandescent lamps. As mentioned earlier, the mechanism
behind these phase-cut dimmers is that they reduce the amount of the output power by shortening
the conduction time of the line voltage. As the conduction time of the dimmer decreases (to
achieve lower dimming levels) the input PF will decrease since the current waveform moves
further away from a sinusoidal shape. The poor PF obtained from a conventional CFL at full
lamp power implies that the use of phase-cut dimmers will result in lower PFs and extremely high
current spikes at the input during dimming. The high current spikes will lead to current saturation
in magnetic components such as inductor or transformer. As a result, the phase-cut incandescent
dimmer is not allowed to be used with commercial CFLs. The poor PF issue is not the only
reason why phase-cut dimmers cannot be used with commercial CFLs, it is also because the
dimmer causes high current spikes that will exceed the current rating of the circuit components
and subsequently destroy the ballast. To improve the poor PF issue and the dimming
performance of the CFL associated with the use of incandescent phase-cut dimmers, dimmable
CFLs with passive PFC have recently made its debut in the market [60]. These dimmable CFLs
are able to achieve a PF of 0.82 when the line voltage operates at its maximum conduction time
41
(at full lamp power). Despite the fact that a higher PF is achieved compared to the non-dimmable
CFL, the following drawbacks are observed in the current dimmable CFLs.
1. The PF of the lamp decreases significantly when the lamp is dimmed with incandescent
phase-cut dimmers. The peak of the input current increases significantly when the
dimmer switch is set at a low dimming position.
2. No significant changes in the light output level can be observed in the upper half of the
dimmer control range (approximately from the phase angle of 0 to 70). Noticeable
changes in the light output only occur in the lower control range where the line voltage
conduction time is very short. Therefore the effective PF of the lamp when dimmed is
very poor.
3. Flickering is present at low dimming levels;
4. The lamp cannot be ignited at low diming levels. This situation does not exist when
phase-cut dimmers are used with incandescent lamps since the lamp behaves like a
resistive load and can therefore be re-ignited at any dimming level.
1.8 Research Motivation
The previous section concludes that when phase-cut dimmers are used, the performance of
current dimmable CFL is not comparable with the performance provided by the incandescent
light bulbs. The research goal of this thesis is to develop a new dimmable high PF electronic
ballast technology that can solve all the aforementioned problems in current CFL. The features of
this research proposal are divided into three major objectives as listed below:
1. Develop a high power electronic ballast power circuit. The ballast power circuit should be cost
effective and compact. At the same time, it should achieve all the necessary ballast functions and
work with phase-cut dimmers.
42
2. Develop a novel control circuit that uses advanced power electronic control in conjunction with
phase-cut dimmer to control the lamp power. The objective is to control the lamp power by
avoiding the use of the lower control range of a standard phase- cut dimmer, so that high power
factor can still be maintained throughout the majority of the dimming range.
3. To implement a digital controller by using Field Programmable Gate Array (FPGA) technique.
This multi-function digital controller should provide the functions that were outlined in the
second objective, in addition to lamp low power detection shut-off feature; soft-start for lamp
ignition and lamp over-voltage protection.
1.9 Thesis Organization
In Chapter 1, a general introduction on the basic requirements of electronic ballast, their PFC
techniques and different kinds of dimming control methods were described. The basic problems
and design challenges in the current CFL electronic ballasts have also been addressed. It has
been highlighted that due to the lack of a PFC circuit in the majority of the CFL electronic ballast,
the lamp’s dimming capability with standard phase-cut dimmers and its input PF cannot be
comparable to that of an incandescent lamp.
In Chapter 2, a novel single-switch current fed resonant inverter is proposed to overcome the
drawbacks in the conventional single-switch class E resonant inverter. The proposed single-
switch resonant inverter has both lower current and voltage stress across the MOSFET compared
to the class E inverter. Then the proposed single-switch resonant inverter is combined with two
different types of active PFC circuit to form two different high PF electronic ballasts. The first
active PFC circuit that is used is a buck-boost PFC and the second active PFC circuit is a SEPIC
converter. Both proposed solutions enjoy the following advantages: (1) only one switch is
required in the power stage; (2) close-to-unity input PF is able to be achieved; (3) large-size high
43
voltage DC-link capacitor is eliminated in both designs. The feasibilities of both circuits are then
verified through experimental testing on a 13W Dulux type CFL from Osram Sylvania.
In Chapter 3, a novel control circuit is proposed to improve the PF performance of the proposed
electronic ballast power circuit during dimming when phase-cut dimmer is in use. The control
circuit controls the duty ratio of the MOSFET at the same time when phase-cut dimmer is used to
provide dimming. The advantage of this control concept is that it allows the lamp power to be
controlled using only a portion of the dimmer control range. Therefore, high PF is maintained
throughout most of the dimming range. This control concept also allows the brightness of the
lamp to be dimmed in a more linear manner than the dimmable CFL currently on the market. The
stability of the overall ballast system is then performed through the frequency domain analysis.
The merits of the proposed control circuit are then highlighted through experimental results on a
proof-of-concept prototype that is tested on the same lamp used in Chapter 2.
In Chapter 4, a digital implementation of the proposed control concept is presented. The control
concept that was described in Chapter 3 is realized using programmable code. With the design
flexibility provided by digital control, additional functions such as shut-off feature at lamp low
power detection; lamp soft-start technique and DC-link voltage protection are included in the
proposed ballast circuit. The performance of the final system is verified through a co-simulation
environment provided by Simulink, where the analog power circuit in PSIM and the digital
control portion in ModelSIM are combined and simulated. Experimental results are then
provided to further support the feasibility of the proposed system.
In Chapter 5, the contributions of this thesis are summarized. Future works that are related to this
dissertation are also outlined and described.
44
Chapter 2
Single-switch High Power Factor Electronic Ballast
The first objective of this research is to develop a high PF electronic ballast that is suitable for
CFL applications. As mentioned in Chapter 1, the main design restriction for the CFL ballast
circuit is the size of the lamp. The electronic ballast circuit used in CFLs must be compact and
the overall cost of the lamp has to be comparable with the incandescent lamp. In the conventional
half-bridge resonant inverter, the driver circuit for the high-side MOSFET requires some means
of isolation that occupies a large portion of the ballast circuit space. In addition, the MOSFET is
still the most expensive component in the ballast power circuit in the lighting industry other than
the ballast control chip. Although Class E resonant inverter uses only one MOSFET in the
circuit, the high voltage and current stress in the MOSFET means that the Class E inverter is not
practical for use in CFL applications.
In this thesis, the employed strategy to minimize the size and cost of the ballast circuit is to
minimize the number of MOSFETs used. Fewer MOSFETs also implies that the power circuit
and its corresponding control scheme (including the MOSFET driver design) can be simplified.
While minimizing the number of MOSFETs, the proposed ballast design must also maintain the
current and voltage stress of the MOSFET at an acceptable level to be practical (to minimize
power loss).
2.1 Proposed Single-switch Current Fed Resonant Inverter
To design a single MOSFET resonant inverter that has both lower current and voltage stress than
the Class E resonant inverter, the approach is to first minimize the current stress across the
MOSFET. This is achieved by designing the circuit such that the high resonant current does not
45
flow through the MOSFET; this can be accomplished by placing a diode in series with the
MOSFET. Since the anti-parallel diode of the MOSFET is blocked, ZVS is lost at both turn-on
and off of the MOSFET. So, in the proposed design, an inductor is placed at the input so that the
current flowing through the MOSFET begins at zero and slowly increases. By doing so, zero-
current switching (ZCS) can be obtained and the switching loss is minimized. Incorporating
these two ideas, the proposed single-switch current fed resonant inverter was developed and is as
shown in Figure 2-1 (b). The single-switch inverter is comprised of the following elements: a
MOSFET switch, an input inductor (Lin) and a resonant circuit consists of Lr and Cr, and a parallel
inductor (Lp) for lamp ignition purpose.
Figure 2-1 Comparisons between Class E resonant inverter and proposed inverter
An advantage of the proposed inverter circuit compared to the class E resonant inverter is
that when the switch is on, only the input current (iin) will flow through the switch (as illustrated
in Figure 2-1). This means that the conduction loss of the MOSFET is significantly reduced in
46
the proposed design compared to the class E resonant inverter. Another advantage of the
proposed single-switch resonant inverter is that the MOSFET voltage stress is much lower than
that of the class E resonant inverter. The MOSFET peak voltage of a class E resonant inverter is
3 to 5 times the peak of the input voltage. However, in the proposed circuit, the voltage across
the MOSFET is a function of both Lin and Cr. Hence, by properly designing Lin and Cr, the
voltage across the MOSFET can be minimized.
2.1.1 Characteristics of Proposed Resonant Circuit
The resonant circuit of the proposed inverter consists of a resonant inductor (Lr), parallel resonant
capacitor (Cr) and a parallel inductor (Lp). The parallel inductor is the lamp ignition element that
is responsible for providing a sufficiently high voltage to ignite the lamp. It also helps to reduce
the circulating current in the resonant tank by providing more current to flow to the lamp at the
desired switching frequency.
Before the lamp is ignited, the lamp resistance is infinite and the output of the resonant
circuit can be modeled as an open circuit. The corresponding equivalent circuit during this phase
is shown in Figure 2-2, where rfil represents the resistance of the filament. The preheat frequency
during the lamp ignition phase is given by (Eq. 2-1), where ipre is the preheat current. The preheat
voltage is given by (Eq. 2-2). The lamp ignition frequency (fign) is derived using (Eq. 2-2) and the
final expression is given by (Eq. 2-3), where Vign is the amplitude of the lamp ignition voltage and
iin,rms is the RMS value of iin. The output voltage across Lp, which is also the voltage across the
lamp during the preheat phase, is also obtained as shown in (Eq. 2-4).
47
Figure 2-2 Equivalent circuit at the inverter stage during lamp ignition
( ) prepr
prepre iLL
vf
+=
π2 (Eq. 2-1)
( ) ⎟⎟⎠
⎞⎜⎜⎝
⎛
−=
rtpre
ppreinpre CLf
Lfiv 221
2
π
π
(Eq. 2-2)
rt
ign
inprt
ign
rmsinp
ign CL
VIL
CLViL
fπ4
42
, −−⎟⎟⎠
⎞⎜⎜⎝
⎛
=
(Eq. 2-3)
( )rt
pinLpign CL
LivV 21, 1 ω
ωω
−==
(Eq. 2-4)
After lamp ignition, the lamp resistance becomes a finite value. The corner frequency
and quality factor of the resonant circuit is defined by (Eq. 2-5) and (Eq. 2-6) respectively. By
selecting a high enough Q in the resonant circuit, the resonant circuit filters out most of the
harmonics generated by the input current (iin) and a high quality sinusoidal waveform can be
obtained at the output. By applying fundamental approximation to the resonant circuit and
assuming that the losses in the passive circuit components are negligible, the output to input
current gain equation can be obtained as given in (Eq. 2-7), where ωr = ωs/ωo represents the
relative operating angular frequency; ωs represents the angular switching frequency and k = Lp/Lr.
48
The voltage gain equation is then obtained by assuming the resonant circuit to be a lossless circuit
network. Hence, iinvin ≈ ioutvout and the voltage gain equation is the inverse of (Eq. 2-7). The
voltage gain plot is displayed in Figure 2-3 for illustration purposes. It illustrates that when the Q
is low (i.e. lamp resistance is infinite), a high output voltage can be provided to the lamp during
the lamp ignition process. It also shows that when Q is high (i.e. lamp resistance drops after start
up), the output voltage decreases to its rated value during steady-state operation.
rro CL
fπ2
1=
(Eq. 2-5)
lamprolamp
ro
RCfRLf
Qπ
π2
12==
(Eq. 2-6)
( )2
221, 1111
1
⎟⎟⎠
⎞⎜⎜⎝
⎛−⎟
⎠⎞
⎜⎝⎛ ++−
=
r
rr
in
out
QkkQ
ii
ωω
ω
(Eq. 2-7)
To gain more insight regarding the resonant characteristic of the proposed inverter, the input
impedance expression has been examined and is expressed by (Eq. 2-8). The magnitude of the
input impedance, |Zin(ωr)|, is given by (Eq. 2-9) and the phase angle of the input impedance,
φZin(ωr), is given by (Eq. 2-10). Figure 2-4 is the plot of (Eq. 2-10) and it is used to study the
resonance point of the proposed circuit. The resonant frequency fres is obtained by noting that fres
is the frequency at which φZin(ωr) becomes zero. It defines the boundary between the capacitive
and inductive region of the resonant circuit. The resonant frequency can be expressed as a
function of the corner frequency Q and k; the resultant expression is given by (Eq. 2-11). From
Figure 2-4, it is observed that the resonant frequency shifts as Q changes. In the actual design,
49
the resonant frequency should be chosen according to the Q value at the full lamp power
condition
( )
( )( )( )( ) ( )( )
( ) ( )rZinj
lamp
in
rrr
rrlamp
plamp
lamppr
rin
eR
Z
kQkjkQkjkQR
LjRRLj
LjCj
jZ
ωφω
ωωωωω
ωω
ωω
ω
=
−++−
++−=
⎟⎟⎠
⎞⎜⎜⎝
⎛
++=
22
22
1111
||1
(Eq. 2-8)
( ) ( )( )( )( ) ( )( )
( ) ( )( )( )( ) ( ) ( )22222
2222
22
22
111
1
1111
kQkk
QkkQ
kQkjkQkjkQ
RZ
rrr
rr
rrr
rr
lamp
in
ωωω
ωω
ωωωωωω
−++−
++=
−++−++−
=
(Eq. 2-9)
( ) ( ) ( )( ) ⎟⎟
⎠
⎞⎜⎜⎝
⎛+−−
−⎟⎟⎠
⎞⎜⎜⎝
⎛−
+= −−
2
21
221
111tan1tan
r
rr
r
rrZin k
QkkQ
kQωωω
ωω
ωφ
(Eq. 2-10)
( ) ( ) ( ) ( ) ( )( ) ( ) ( )( )2
222222
21411
,Qk
kQkQkkQkkfkQf ores
++−++++−=
(Eq. 2-11)
50
Figure 2-3 Voltage gain plot of proposed resonant circuit
Figure 2-4 Phase plot of proposed resonant circuit
51
2.1.2 nth Harmonics Analysis of Proposed Resonant Circuit
This section analyzes the proposed resonant circuit in detail. First, the nth harmonics equivalent
circuit of the resonant inverter is derived. Using the equivalent circuit, the Fourier series that
represents the inverter input current (iin) and the output current (iout) are subsequently derived.
The analysis was performed under the assumption that both the MOSFET and diode are ideal
components with lossless characteristics.
Figure 2-5 AC nth harmonics equivalent circuit with lamp and filament resistances included
The resonant inverter stage employs a single input inductor (Lin) and a current source
resonant circuit that consists of a resonant inductor (Lr), a parallel capacitor (Cr) and a parallel
inductor (Lp). The resonant circuit serves as a lamp-starting element to provide sufficient high
voltage to ignite the lamp. Figure 2-5 shows the nth harmonic equivalent AC circuit of the
resonant inverter with Rlamp and rf to represent the steady-state lamp resistance and the resistance
of the filament respectively. The nth harmonic impedance of the circuit elements in the resonant
circuit are given by (Eq. 2-12), (Eq. 2-13) and (Eq. 2-14) respectively, where n=1 represents the
impedance at the fundamental switching frequency. The Fourier series that represents current
iin(ωst) is derived based on (Eq. 2-16) where a0, a1 and b1 are given by (Eq. 2-17), (Eq. 2-18) and
(Eq. 2-19) respectively with K1 given by (Eq. 2-20). The phase difference between iin and vcr is
represented by α, and the resonant current at α is represented by Ires. .
52
( ) rssnLr LjnZ ωω =, (Eq. 2-12)
rssnCr Cjn
Zω
ω 1)(, =
(Eq. 2-13)
pssnLp LjnZ ωω =)(, (Eq. 2-14)
lampps
lamppssnp RLjn
RLjnZ
+=
ωω
ω )(,
(Eq. 2-15)
( ) ( ) ( ) ( )∑∞
=
++++=,...3,2
110 sincossincos
2)(
nsnsnsssin tnbtnatbtaati ωωωωω
(Eq. 2-16)
( ) ( ) ( )( )( )απ
αααcos
cossincos)sin(0
dKdIdIKIa resresres −−+++−
=
(Eq. 2-17)
( ) ( ) ( ) ( ) ( )( )( )απ
ααααα
cos
2cossin2cos22sinsin2)sin(81
1
dKddIdIdIdIKIa
resresresresres +−++−−+−−−
=
(Eq. 2-18)
( )( )απ
ααααα
cos
)2cos()sin(2)cos(2)cos(22)2sin()cos(381
1
dIdIdIdIKddKIb
resresresres −+−−−+−+−=
(Eq. 2-19)
in
rdc L
CVK =1
(Eq. 2-20)
The Fourier series that represents the output lamp current (iout) is derived by applying
basic current division technique to the AC equivalent circuit in Figure 2-5. The corresponding
Fourier series of iout is expressed by (Eq. 2-21) with the nth harmonic phase angle (θn) given by
53
(Eq. 2-22). The fundamental phase difference is obtained by setting n = 1 in (Eq. 2-22). (Eq.
2-16) and (Eq. 2-21) are then plotted in Matlab with the following circuit parameters: Vdc = 200V;
d = 0.4; Lin = 0.39mH; Lr = 1mH; Cr = 3.3nF; Lp = 3.9mH. Figure 2-6(a) shows the current
waveforms iin and iout obtained from the Matlab calculations. Figure 2-6(b) shows the simulation
results from PSIM 7.0. It can be observed that both figures are very similar, and therefore prove
that the derived mathematical equations are able to accurately describe the current waveforms in
the proposed resonant circuit.
(a) (b)
Figure 2-6 Current waveforms at the resonant inverter stage plotted in PSIM
( ) ( )( )
( ) ( )⎟⎟⎠
⎞⎜⎜⎝
⎛−+−⎟
⎟⎠
⎞⎜⎜⎝
⎛
+⎟⎟⎠
⎞⎜⎜⎝
⎛
+++
−+−⎟⎟⎠
⎞⎜⎜⎝
⎛
+⎟⎟⎠
⎞⎜⎜⎝
⎛
++=
∑∞
= ,...3,2
1111
sincos
sincos)(
nnsnnsn
lampLpn
Lpn
parnLrncrn
crn
sslampLp
Lp
parLrcr
crsout
tnbtnaRZ
ZZZZ
Z
tbtaRZ
ZZZZ
Zti
θωθω
θωθωω (Eq. 2-21)
( )( )( )
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
−
−
−= −
rts
rrslamp
ps
sn CLn
CLnR
Ln
2
2
10
1
1tan90)(
ω
ωω
ωθ
(Eq. 2-22)
0 0.5 1 1.5 2 2.5 3 3.5
x 10-5
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
time (sec)
curre
nt (A
)
iiniout
54
2.2 High PF Single-Stage Switch Electronic Ballast
Based on the single current fed resonant inverter that was proposed in the previous section, high
PF electronic ballast can then be derived by utilizing any of the PFC techniques discussed in the
previous chapter. Since the passive PFC approaches require large some components to achieve
high PF, with the fact that the overall ballast power circuit can be simplified with active PFC
approach if a single-stage inverter can be designed; active PFC circuits are more appropriate to be
used in the proposed solution than passive PFC circuits for CFL ballast designs. In Chapter 1, it
has been mentioned that the main drawback with the DCM boost PFC is the high DC-link voltage
and voltage stress across the MOSFET. Buck PFC, on the other hand, draws a line current with
limited conduction time that lowers the input PF. The duty ratio of the MOSFET also needs to be
properly chosen so that the ignition voltage across the lamp will not be affected. Under these
circumstances, it becomes obvious that a step-up/down converter is the most suitable circuit to be
used for active PFC in the proposed design. Therefore, two different step-up/down converters:
buck-boost converter and SEPIC converter, are chosen as the PFC stage to combine with the
proposed single-switch resonant inverter to form two different single-stage single-switch high PF
electronic ballasts. The characteristics of these two topologies and their operating principles will
be explained in detail in the following sections.
2.2.1 Single-switch High PF Electronic Ballast with Buck-Boost PFC
The first single-stage electronic ballast circuit is derived by combining a buck-boost converter
with the single-switch current fed resonant inverter. Figure 2-7(a) shows the initial circuit design
where the output of the buck-boost converter is connected to the input of the single-switch current
fed resonant inverter. The lamp at the output of the inverter stage is modeled as a power
dependent resistor (Rlamp) where rfil represents the filaments of the lamp. Figure 2-7(b) shows the
55
intermediate step of the proposed circuit derivation. Since the source terminal of the two
switches (Mpfc and Ms1) share the same node, the two switches can be replaced by a single-switch
to obtain the final circuit. Figure 2-7(c) shows the final design of the proposed single-stage
single-switch circuit where the dotted line highlights the integrated buck-boost PFC stage.
When the buck-boost converter operates in DCM, the peak of inductor Lb current will
follow the rectified sinusoidal voltage from the line. The average input line current can then be
analyzed as follows: let vs(t) = Vp sin(ωLt) be the line voltage, where Vp and ωL represent the
amplitude of the line voltage and angular line frequency respectively. According to Figure
2-7(a), the average current after the rectifier is equal to the average current across the switch. The
average line current is then obtained to be (Eq. 2-23), where iLb,pk is determined to be according
to (Eq. 2-24).
Since it can be observed from (Eq. 2-23) that line current is in phase with the line
voltage, the DCM buck-boost converter can therefore achieve a very high PF. Unlike the DCM
boost PFC circuit, the MOSFET does not suffer from high voltage stress in order to achieve PFC
[62]. The average power of the buck-boost PFC stage is obtained by averaging the instantaneous
power given by the line voltage and the average input current. The average power equation is
shown in (Eq. 2-25). The DC-link voltage (vdc), across the capacitor Cb, is given by (Eq. 2-26),
where Rinv represents the mean input resistance of the inverter stage and d is the steady-state duty
ratio. To ensure that the lamp CF is maintained to be below the maximum value according to the
ANSI standard [58], Cb should be designed according to the maximum allowable DC ripple
voltage (|vrip|) across Cb so that the amplitude of the low frequency envelope appear at the lamp
current is small compared to the amplitude of the high frequency component. The voltage ripple
across Cb for a buck-boost PFC circuit is then given in (Eq. 2-27). From (Eq. 2-27), Cb can then
56
be expressed as a function of the magnitude of the DC-link voltage ripple |vrip| as shown in (Eq.
2-28), where Vdc is the average DC-link voltage; Pavg is the average input power and fL is the line
frequency
s1M 1D
bL
L
Cb
inDin
bD
Buck-boost PFC stager
rC
L
outi
Lamp
pL v+
_out
filr
lampR
/2 filr /2
filr /2 filr /2
v+
_dc
dsi
v
+
_cr
iniv+ L
_
Lbi
Dini
(c)
s1M
v
1D
bL
L
sCb
EMI filter
inbD r
rC
L
outi
Lamp
pL v+
_out
filr
lampR
/2 filr /2
filr /2 filr /2
siv
+
_
dc
dsi
v
+
_cr
iniv+ L
_
s1M 1D
bL
L
Cb
inb r
rC
L
outi
Lamp
pL v+
_out
filr
lampR
/2 filr /2
filr /2 filr /2
v+
_dc
dsi
v
+
_cr
ini
v+ L_
D
Lbi
Buck-boost PFC stageDiode rectifier with EMI filter Current fed single switch resonant inverter
Lamp with starting element
(a)
(b)
Mpfc
Mpfc
ossC
ossC
ossC
v +_ds
iL
iC
vs
EMI filtersi
iL
iC
vs
EMI filtersi
iL
iC
Figure 2-7 Derivation of proposed single-switch high PF electronic ballast; (a) initial design;
(b) circuit derivation; (c) Final design of proposed circuit
57
( ) ( )tfL
TdVT
titi L
b
sp
s
onpkLbavgs π2sin
22
2,
, ==
(Eq. 2-23)
( ) ( )b
sLppkLb L
dTtfVti
π2sin, =
(Eq. 2-24)
( ) ( ) ( )b
spLL
b
spLpavg L
TdVtdt
LTdV
tVP4
sin2
sin1 222
0
== ∫ ωωωπ
π
(Eq. 2-25)
b
sinvdc L
TRdv
2=
(Eq. 2-26)
( )tfVCf
Pdti
Cv L
dcbL
avgCb
brip π
π4sin
41
−== ∫
(Eq. 2-27)
dcripL
avgb Vvf
PC
π2=
(Eq. 2-28)
2.2.2 Operating Principles of Single-switch Electronic Ballast with Buck-boost PFC
The operating principles of the proposed single-switch electronic ballast circuit with integrated
buck-boost PFC are illustrated in Figure 2-8. The key waveforms of each of these operating
stages are displayed in Figure 2-9. The analysis of the proposed single-switch ballast circuit with
integrated buck-boost PFC is explained as follows:
[Stage 1:] During this stage, Ms1 is on, diode Din conducts and inductor Lb begins to charge.
Current iLb rises linearly. When Ms1 is on, diode D1 is forced to turn on at the same time. As a
result, iin begins to increase due to the presence of Lin. To minimize the switching turn-off loss,
the size of inductor Lin should be small enough so that iin will return to zero before the MOSFET
turns off. At this stage, the total current flowing through Ms1 is ids, which is equal to the sum of
iDin and iin.
58
[Stage 2:] This stage begins when iin decreases to zero. Diode D1 is off. Meanwhile, iDin
continues to increase linearly. This stage ends when the gate signal Vg goes back to zero.
[Stage 3:] The gate signal to the MOSFET VG goes to zero and Ms1 turns off, which forces diodes
Din to turn off. As a result, Db begins to conduct and iLb decreases linearly through the loop Db,
Cb and Lb. Due to the presence of the parallel capacitance (Coss) of the MOSFET, vds rises slowly
at the beginning of stage 3.
[Stage 4:] At this stage, iLb decreases to zero, which indicates the start of the discontinuous period
of the inductor current. Meanwhile, D1 is still off and the resonant circuit continues to deliver the
required energy to the lamp.
59
s1M
1Db
L
L
Cb
inD
in
bDv+
_dc
dsi
iv+ L
_r
rC
L
outi pL v+
_out
filr
lampR
/2 filr /2
filr /2 filr /2
v
+
_cr
s1M
1Db
L
L
Cb
inD
in
bDv+
_dc
dsi
iniv+ L
_r
rC
L
outi pL v+
_out
filr
lampR
/2 filr /2
filr /2 filr /2
v
+
_cr
s1M
1Db
L
L
Cb
inD
in
bDv+
_dc
dsi
iv+ L
_r
rC
L
outi pL v+
_filr
lampR
/2 filr /2
filr /2 filr /2
v
+
_cr
Dini
Lbi
Lbi
Lbi
Dini
Dini
vrect
vrect
vrect
Stage 1:
Stage 3:
Stage 4:
ossC
ossC
ossC
in
in
s1M
1Db
L
L
Cb
inD
in
bDv+
_dc
dsi
iv+ L
_r
rC
L
outi pL v+
_out
filr
lampR
/2 filr /2
filr /2 filr /2
v
+
_crDini
Lbi
vrectStage 2:
ossC
in
Figure 2-8 Operating stages of single-switch electronic ballast with integrated buck-boost
PFC
60
Figure 2-9 Key waveforms of single-switch electronic ballast with integrated buck-boost
PFC
2.2.3 Single-switch High PF Electronic Ballast with SEPIC PFC
The second proposed topology employs the SEPIC converter as the PFC circuit to achieve high
input PF. Compared to the buck-boost PFC, SEPIC converter has the following advantages: (1)
the output DC link voltage polarity is not inverted as in the buck-boost converter, this allows the
negative terminal of the rectifier output to be connected directly to ground of the MOSFET and
hence, reduces the EMI requirements of the input filter [63]; (2) the SEPIC input inductor always
operates in CCM so that its current ripple is always smaller than other PFC inductors in other
active PFC converters, this also allows EMI filter with much smaller inductor to be used in the
SEPIC PFC topology; (3) the two inductors (L1, L2) can be coupled with each other to further
simply the circuit configuration.
61
Since the detailed analysis of a SEPIC PFC converter has been discussed in [63], only the key
equations will be given here. Assume the input line voltage is given by: vs(t)= Vpsin(2πfLt), where
Vp is the amplitude of the line voltage and fL is the line frequency. The average input current
(is,avg(t)) drawn from the line is then given by (Eq. 2-29), where Leq= (L1L2)/(L1+L2), Ts =
switching period and d = duty ratio. From (Eq. 2-29), it can be observed that is,avg(t) is purely
sinusoidal and is in phase with vs(t). Therefore, a very high PF is achieved at the input. The input
average power equation is then derived from (Eq. 2-29) and is expressed as (Eq. 2-30). Figure
2-10 illustrates the finalized single-stage single-switch electronic ballast circuit that is essentially
an integration of a SEPIC converter with the proposed single-switch resonant inverter.
Figure 2-10 Derivation of proposed single-switch high PF electronic ballast with SEPIC
PFC
62
)2sin(2
)(2
, tfL
TdVti L
eq
spavgs π=
(Eq. 2-29)
∫ ==π
πππ
2
0
22
, 4)2()()2sin(
21
eq
spLavgsLpavg L
TVdtfdtitfVp
(Eq. 2-30)
2.2.4 Operating Principles of Single-switch Electronic Ballast with SEPIC PFC
The operating stages and key waveforms of the proposed SEPIC type single-switch electronic
ballast are presented in this section. The circuit operating principles can also be explained in the
similar fashion given on the buck-boost single-stage ballast circuit shown in Figure 2-7. Figure
2-11 shows the operating stages of the proposed SEPIC single-stage ballast circuit. The key
waveforms of the circuit within a switching period are illustrated by Figure 2-12. The operating
principles of the proposed SEPIC single-stage electronic ballast can be explained as follows:
[Stage 1:] Ms1 is on and diode Din conducts. Inductor LL1 begins to charge and current iL1 rises
linearly. When Ms1 is on, diode D1 is forced to turn on at the same time. As a result, iin begins to
increase due to the presence of Lin. Since Db is off, current iL2 equals to iC1. The peak current
flowing through the MOSFET is then given by the sum of iDin and iin and occurs at the end of this
stage.
[Stage 2:] This stage begins when iin decreases to zero. Diode D1 is off. Meanwhile, both iL1 and
iDin continue to increase linearly. This stage ends when the gate signal Vg goes back to zero.
[Stage 3:] The gate signal to the MOSFET VG goes to zero and Ms1 turns off, which forces diodes
Din to turn off. Db turns on and iL1 decreases linearly. Current iC1 is divided between diode Db
and inductor L2. This stage ends when current iL1 equals to iL2
[Stage 4:] At this stage, both diodes Db and Din are off. Current iL1 then equals to iL2. Meanwhile,
D1 is still off and the resonant circuit continues to deliver the required energy to the lamp.
63
It can be observed from stage 1 to stage 4 that iL1 never goes to zero within a switching period.
This indicates that the rectified current always stays in CCM condition, which allows much
simpler EMI filter design compared to the first single-switch ballast circuit proposed previously.
s1M 1D
Lin r
rC
L
outi pL v+
_out
filr
lampR
/2 filr /2
filr /2 filr /2
dsi
v
+
_cr
iniv+ L
_
Dini
ossC
v +_ds
inDCb
bD
v
+
_dc2L
1L C1
vrect
s1M 1D
Lin r
rC
L
outi pL v+
_out
filr
lampR
/2 filr /2
filr /2 filr /2
dsi
v
+
_cr
iniv+ L
_
Dini
ossC
v +_ds
inDCb
bD
v
+
_dc2L
1L C1
vrect
s1M 1D
Lin r
rC
L
outi pL v+
_out
filr
lampR
/2 filr /2
filr /2 filr /2
dsi
v
+
_cr
iniv+ L
_
Dini
ossC
v +_ds
inDCb
bD
v
+
_dc2L
1L C1
vrect
L1i
L1i
L1i
L2i
L2i
L2i
C1i
C1i
C1i
Stage 1:
Stage 3:
Stage 4:
Dbi
Dbi
Dbi
s1M 1D
Lin r
rC
L
outi pL v+
_out
filr
lampR
/2 filr /2
filr /2 filr /2
dsi
v
+
_cr
iniv+ L
_
Dini
ossC
v +_ds
inDCb
bD
v
+
_dc2L
1L C1
vrect
L1i
L2i
C1i
Stage 2:
Dbi
Figure 2-11 Operating stages of the SEPIC single-stage electronic ballast
64
Figure 2-12 Operating waveforms of the proposed SEPIC type single-stage electronic
ballast
65
2.2.5 Current and Voltage stress Analysis
One common drawback in many single-stage or single-switch converters is that the active
components, such as the MOSFET and diodes, may suffer from higher voltage or current stress
compared to the conventional two stages converters for the same power level. High current or
voltage stress across any active components can result in bulkier power circuits and higher overall
circuit cost. In this section, the current/voltage stress across the switch and all the diodes is
studied for the SEPIC type single-switch electronic ballast due to its aforementioned advantages
over the buck-boost single-switch electronic ballast.
1: RMS current of diode Din
Diode Din conducts only when the switch is on. Therefore, the current (iDin) flowing through Din
is equal to the sum of the rising portion of inductor current (iL) and current (ic1). The RMS current
(iDin,rms) is obtained by first taking the average of the square of iDin over the switching period and
then averaging it over the AC line period [61]. The final expression of iDin,rms is given in (Eq.
2-31).
( )eq
psL
T
Dins
rmsDin LVTd
tdtdiT
is
6)(11 2/3
0 0
2, =⎟
⎟⎠
⎞⎜⎜⎝
⎛= ∫ ∫ ω
π
π
(Eq. 2-31)
2: RMS current of diode Db
Diode Db conducts only when the inductor discharges its energy to the inverter. Hence, using the
similar technique from (Eq. 2-31), the RMS current iDb,rms of Db can be derived and expressed as
(Eq. 2-32).
66
( ) ( )20 0
2, 6
1)(11
LVdTd
tdtdiT
i psL
T
Dbs
rmsDb
s −=⎟
⎟⎠
⎞⎜⎜⎝
⎛= ∫ ∫ ω
π
π
(Eq. 2-32)
3: RMS current of diode D1
The current flowing through diode D1 can be analyzed by observing that its current is equal to the
current flowing through inductor Lin,. The simplified equivalent circuit of the inverter stage when
the switch is on is shown in Figure 2-13 where the output current source represents the resonant
current (ires) flowing through Lr. The current iD1 and the capacitor voltage vcr are then obtained
simultaneously from (Eq. 2-33) and (Eq. 2-34) respectively. The key waveforms are illustrated in
Figure 2-14 and the final expressions representing iin(ωst) and vcr(ωst) within one switching cycle
are expressed by (Eq. 2-35) and (Eq. 2-36) respectively. θVcr(ωs), which represents the phase
difference between iin and vcr, is given in (Eq. 2-37) as a function of ωs. The equation that
represents the RMS current of iD1 is given by (Eq. 2-38). The average current of iin within one
switching cycle has been derived and is given by (Eq. 2-39).
Figure 2-13 Equivalent circuit of the inverter when the switch is on
67
( ) ( )( ) ( )tvVdt
tidLtv scrdc
sininsL ω
ωω −==
(Eq. 2-33)
Figure 2-14 Key waveforms at the inverter stage
( ) ( )( ) ( ) ( )( )sVcrressinscr
rscr itidt
tvdCtv ωθω
ωω −==
0 ≤ ωst ≤ 2πd
(Eq. 2-34)
( ) ( )( ) ( )( )( )( )
( )( )( ) ( )tit
LC
Vt
iti sDsVcr
s
in
rdc
sVcr
sVcrssVcrressin ω
ωθω
ωθωθω
ωθω 1cossin
coscos
1 =+⎟⎟⎠
⎞⎜⎜⎝
⎛ −−= (Eq. 2-35)
( ) ( )( )( ) ( )( ) ( )( )
( )( )sVcr
sVcrs
r
insVcrres
sVcr
sdcscr
tCL
it
Vtvωθωθω
ωθωθ
ωω
cossin
coscos
1−
−⎟⎟⎠
⎞⎜⎜⎝
⎛−=
(Eq. 2-36)
( )
( )
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
−
−
−⎟⎟⎠
⎞⎜⎜⎝
⎛
−= −−
rts
lamp
rrsps
prs
lamptsVcr CL
RCLL
LLRL
2
2
11
1
1
tantanω
ωω
ωωθ
(Eq. 2-37)
68
( ) ( )
( )( ) ( )( )
( )( )∫ ∫
∫ ∫
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛
⎟⎟⎠
⎞⎜⎜⎝
⎛+⎟⎟
⎠
⎞⎜⎜⎝
⎛ −−=
⎟⎟⎠
⎞⎜⎜⎝
⎛=
π
π
ωωαω
ααω
ωθπ
ωπ
0 0
2
0 0
21,1
)()(cos
sincos
cos111
11
tdtdtLCVti
T
tdtdiT
i
L
dT
ss
in
rdc
ssres
s
L
T
Ds
rmsD
s
s
(Eq. 2-38)
( ) ( )
( )( ) ( )( )( ) ( ) ( )( ) ( ) ( )( )⎟⎟
⎠
⎞⎜⎜⎝
⎛−++−−=
= ∫
dVLCdidi
tdtii
dc
in
rsressres
d
ssDavgD
s
πα
ααπαωθ
πωθ
ωωπ
π
2cos1cos
sin2sincos2
1
21 2
01,1
(Eq. 2-39)
The peak current flowing through Din, Db and M1, as observed from Figure 2-12, is the same,
which is expressed by (Eq. 2-40).
eq
sppkdspkDbpkDin L
dTViii === ,,,
(Eq. 2-40)
4: Current stress of MOSFET
When the MOSFET conducts, the current flowing through the MOSFET is comprised of iDin and
iD1. The RMS current of the switch is then obtained as shown in (Eq. 2-41).
( ) ⎥⎦
⎤⎢⎣
⎡−⎟⎟
⎠
⎞⎜⎜⎝
⎛−+⎟⎟
⎠
⎞⎜⎜⎝
⎛−
−+=
+=
))(2sin(22
)2sin(22
3cos2
16
2222
22
223
2,1
2,,
dIKKIL
VTd
iii
resres
eq
ps
rmsDrmsDinrmsds
αααπ
(Eq. 2-41)
The voltage stress across the MOSFET is obtained by using KVL in the proposed inverter. Since
the voltage across Lin is approximately zero when the MOSFET is off, the peak value of the
69
MOSFET voltage can be approximated by (Eq. 2-42), where (ωst)pk is the phase corresponds to
the maximum peak voltage across the MOSFET as given by (Eq. 2-43) and r
inres C
LIK =0 .
( ) ( ) ( ) ( )( ) ⎥
⎦
⎤⎢⎣
⎡ −−=
αα
ωωωcos
sin)(cos)(sin)( 00,
dcpkspkspksrmsds
VKttKtv
(Eq. 2-42)
( ) ( )( ) ⎟⎟
⎠
⎞⎜⎜⎝
⎛−
−= −
dcpks VK
Ktα
αω
sincostan
0
01 (Eq. 2-43)
2.3 Design Example
A design example is given in this section to validate the theoretical analysis and the feasibility of
the two proposed electronic ballast circuits. The performance of the two circuits is then
compared with a commercial CFL obtained from the market. The design specifications are
shown in Table 2-1.
Table 2-1 Design Specifications
Line voltage: 90 ~ 120Vrms, 60Hz
Tested Lamp: 13W 4-pins Dulux D/E 3500K from Osram Sylvania
Commercial CFL: 13W, 175mA 3500K from Osram Sylvania (CF13EL)
2.3.1 Design of the resonant circuit
The first step to design the resonant circuit is to obtain the lamp steady-state resistance. The
calculation is shown in (Eq. 2-44). Then the resonant circuit components are designed for the
chosen Q value so that the proper lamp ignition voltage will be provided for the lamp start-up
process. From inspection of Figure 2-3, it can be seen that the switching frequency should be
70
chosen to be below the corner frequency to ensure that high voltage gain is guaranteed when Q is
low. At the same time, the switching frequency should be above the resonant frequency to
minimize the voltage and current stress of the switch. The corner frequency is chosen to be 90
kHz to minimize the resonant inductor size and the Q is chosen to be 0.9. The final values of Lr
and Cr are then calculated as shown in (Eq. 2-45) and (Eq. 2-46) respectively. The starting
inductor for lamp ignition, Lp, is then selected to be 2.2mH. Since fres is calculated to be 52 kHz
from (Eq. 2-11), the switching frequency is subsequently chosen to be 70 kHz for this design.
From the calculated circuit parameters, the lamp ignition frequency is then determined to be 49
kHz according to (Eq. 2-3).
Ω=== 663)14.0(
1322 A
WIP
Rout
outlamp
(Eq. 2-44)
mHkHzf
QRL
o
lampr 1
)90(2)663(9.0
2≈
Ω==
ππ (Eq. 2-45)
( ) nFmHkHzLf
Cro
r 7.21)902(
1)2(
122 ≈==
ππ (Eq. 2-46)
2.3.2 Design of the buck-boost PFC stage
In the buck-boost PFC circuit, the inductor Lb can be determined according to the average power
equation in (Eq. 2-25). In this design example, the maximum d is selected to be 0.37 with Vp =
170V and fs = 70kHz; Lb is then calculated to be 1mH from (Eq. 2-47). Since the buck-boost
circuit operates in DCM, the minimum vdcmin should follow (Eq. 2-48), which is determined to be
98V in this design example. The capacitor Cb is designed according to the ripple voltage
specified in vdc. A ripple voltage of 20% of vdc is chosen in this design. The minimum Cb is then
calculated according to (Eq. 2-49). In the prototype, 22µF is used.
71
( ) ( )( ) mH
WkHz
PTdV
Lavg
spb 1
13470/137.0170
4
2222
max, ===
(Eq. 2-47)
Vd
dVv p
dc 981
=−
≥
(Eq. 2-48)
( )( )( ) FVVHz
WCb μπ
159818602
13min, ≈=
(Eq. 2-49)
2.3.3 Design of the SEPIC PFC
Similar to the buck-boost PFC, the PFC inductors in the SEPIC circuit: L1 and L2 are
needed to be calculated first. In order to minimize the current ripple in the line current, L1 is
selected to be 5.6mH and L2 is designed to be 1mH in this design example. Leq is then determined
to be 0.84mH. The required duty cycle (d) is then calculated according to the SEPIC average
power equation in (Eq. 2-30). The d that is used in this design example is given by (Eq. 2-50),
where Vp = 170V; Leq = 0.84mH; Ts = 1/70kHz; and η = 90%:
35.04
2 ==sp
eqavg
TVLP
dη
(Eq. 2-50)
The SEPIC DCM voltage gain equation is given in (Eq. 2-51) [18], where Ri represents
the mean input resistance of the inverter circuit and is defined as given by (Eq. 2-52). iin,avg can
be obtained from (Eq. 2-39) and is calculated to be approximately 80mA. Assuming that η =
90%, Ri is then calculated to be 1823Ω. Vdc is then calculated to be 146 V according to (Eq.
2-51), with Vrect,avg = 2Vp/π represents the average rectified voltage. The output capacitor C2 is
then designed by allowing 10% ripple in Vdc. With both Ri and Vdc obtained earlier, C2 is
subsequently calculated to be at least 12µF in order to minimize the voltage ripple across the DC-
link capacitor. In the actual design, C2 is selected to be 22µF.
72
eq
is
avgrect
dc
LRTd
VV
2
2
,
=
(Eq. 2-51)
( )2,avgin
avgi i
PR
η=
(Eq. 2-52)
Fast recovery diodes are required for Din and Db to minimize the turn-off recovery losses in the
diodes. From (Eq. 2-40), the peak current flowing through Din, and Db is calculated as follows:
( )( )( )A
mHkHzV
ii pkDbpkDin 87.084.0
70135.0146
,, ≈==
MUR160 fast-recovery diodes are used in the experimental prototype. The peak current flowing
through the MOSFET is same as iDin,pk and iDb,pk, which is also 0.87A. The MOSFET voltage
stress can be calculated from (Eq. 2-42) with Vdc = 146V, Cr = 2.7nF and Lin = 0.39mH. The peak
voltage stress during steady-state operation is calculated to be 335V according to (Eq. 2-42).
2.3.4 Simulation Results
To verify the functionality of the proposed design, the buck-boost single-stage ballast circuit was
first simulated in PSIM 7.0. Table 2-2 summarizes the circuit parameters and the components
part numbers that have been used in both simulation and the experimental prototype for the
proposed circuit with integrated buck-boost PFC. Since the same resonant circuit components are
used for the case with SEPIC PFC, only the circuit parameters for the SEPIC stage is given as
shown in Table 2-3.
73
Table 2-2 Circuit parameters for proposed circuit with integrated buck-boost PFC
Circuit Designator Part # / Component value Manufacturer
Li 1.5mH Coilcraft / RFB1010-152L
Ci 10nF 250V EPCOS Inc Film capacitor
Lb 1mH Coilcraft / RFB1010-102L
Cb 22µF, 250V Panasonic electrolytic capacitor
M1 STP4NK60Z (600V, 4A) STMicroelectronics
D1, Db, Din MUR160 (600V, 1A) ON Semiconductor
Lin 0.39mH Coilcraft / RFB1010-391L
Lr 1mH Coilcraft / RFB1010-102L
Cr 2.7nF, 400V 400V EPCOS Inc Film capacitor
Lp 2.2mH Coilcraft / RFB1010-222L
Table 2-3 Circuit parameters with integrated SEPIC PFC
Circuit Designator Part # / Component value Manufacturer
L1 5.6mH Coilcraft / RFB1010-562L
L2 1mH Coilcraft / RFB1010-102L
C1 33nF 250Vac Vishay Film capacitor
C2 22µF, 250V Panasonic electrolytic capacitor
Figure 2-15shows the simulated steady-state operating waveforms of the proposed single-switch
circuit with integrated buck-boost PFC. Figure 2-15(a) is the MOSFET voltage and currents: iin
and iLb in the. The waveforms are very similar to the waveforms obtained in the theoretical
section. Figure 2-15(b) is the line current and lamp current. The PF achieved from this line
current is 0.996. The DC-link voltage is shown in Figure 2-15(c).
74
(a) (b)
(c)
Figure 2-15 Simulated waveforms for proposed circuit with integrated buck-boost PFC(a)
vds, iLb and iin; (b) Line current and lamp current; (c)DC-link voltage (vdc)
Figure 2-16 shows the simulated waveforms of the proposed single-switch circuit with integrated
SEPIC PFC. Figure 2-16(a) is the simulated MOSFET voltage and current waveforms; Figure
2-16(b) is the line current and lamp current waveforms; Figure 2-16(c) is the corresponding DC-
link voltage. Simulation result shows that a PF of 0.991 is achieved from the proposed circuit
SEPIC PFC.
75
(a) (b)
(c)
Figure 2-16 Simulated waveforms for proposed circuit with integrated SEPIC PFC (a) vds,
ids and iin; (b) Line current and lamp current; (c)DC-link voltage (vdc)
2.3.5 Experimental Results
An experimental prototype was built for each of the two proposed high PF single-switch
circuits to support the simulation results. For the 13W D/E Osram CFL, the lamp ignition voltage
is determined to be 290Vrms. Figure 2-17 shows the lamp current and voltage waveforms at start
up. It shows that successful lamp ignition is provided, which supports the theoretical calculations
discussed in the resonant circuit section. Figure 2-18 shows the output lamp current and lamp
voltage waveforms within a few line cycles. The CF of the lamp current is measured to be 1.59,
76
which is below the limit according to the ANSI standards [7]. The steady-state lamp current and
voltage waveforms are then displayed in Figure 2-19. Figure 2-20 shows the harmonics
spectrum of the iout obtained from the commercial 13W CFL and Figure 2-21 shows the harmonic
spectrum of iout from the proposed resonant inverter, where fs,2 and fs,3 represent the 2nd and 3rd
harmonic of iout. It is observed that the DC component of iout in Figure 2-20 is negligible
compared to the component at the switching frequency. The magnitude of the even harmonics
components are also observed to be very small compared to the magnitude of the switching
frequency component. Hence, the high content of even harmonics of the lamp current does not
present in the proposed circuit.
(vout: 200V/div; iout: 0.2A/div; time: 500ms/div)
Figure 2-17 Lamp current and voltage at start-up
77
(vout: 200V/div; iout: 0.2A/div; time: 5ms/div)
Figure 2-18 Measured lamp voltage and current waveforms within low frequency cycle
(vout: 200V/div; iout: 0.2A/div; time: 10µs/div)
Figure 2-19 Measured lamp voltage and current waveforms
78
(iout: 60mA/div; frequency: 40kHz/div)
Figure 2-20 FFT of lamp current in commercial 13W CFL
(iout: 50mA/div; frequency: 50kHz/div)
Figure 2-21 FFT of lamp current from proposed circuit
Figure 2-22 shows the measured line current and voltage from a commercial 13W CFL. The PF
obtained is 0.62. Figure 2-23 and show the input line current of the proposed circuit with
integrated buck-boost PFC and SEPIC PFC respectively. The achieved PF is 0.995 and 0.988
respectively. The harmonic spectrum of the line current for all three circuits is then displayed in
Figure 2-25, Figure 2-26 and Figure 2-27. A THD of close to 120% is measured from Figure
2-25, whereas a THD of less than 5.1% and 8.8% is measured from Figure 2-26 and Figure 2-27
respectively.
79
(vs: 100V/div; is: 0.5A/div; time: 10ms/div)
Figure 2-22 Measured line current from a commercial 13W CFL
(vs: 100V/div; is: 0.2A; time: 10ms/div)
Figure 2-23 Line current and line voltage with integrated buck-boost PFC
(vs: 100V/div; is: 0.2A; time: 10ms/div)
Figure 2-24 Measured line current from proposed single circuit with integrated SEPIC PFC
80
(is: 50mA/div; frequency: 180Hz/div)
Figure 2-25 Line current harmonics spectrum from a commercial 13W non-dimmable CFL
(is: 50mA/div; frequency: 180Hz/div)
Figure 2-26 Line current harmonics spectrum from proposed circuit with integrated buck-
boost PFC
(is: 50mA/div; frequency: 180Hz/div)
Figure 2-27 Line current harmonics spectrum from proposed single circuit with integrated
SEPIC PFC
i s,1 i s,3 i s,5 i s,7 i s,9 is,11
81
Figure 2-28 shows steady-state operating waveforms of vds, iLb and iin of the proposed single-
switch electronic ballast with integrated buck-boost PFC. Figure 2-29 shows the same operating
waveforms within the low line frequency. The peak MOSFET voltage is measured to be 280V.
(vds: 100V/div; iLb: 0.5A/div; iin: 0.3A/div; time: 5µs/div)
Figure 2-28 MOSFET voltage (vds), inductor Lb current (iLb) and inverter input current iin
(vds: 100V/div; ids: 0.5A/div; time: 2ms/div)
Figure 2-29 MOSFET voltage (vds) and inductor Lb current (iLb) within line frequency
82
Figure 2-30 shows the steady-state MOSFET current and voltage waveforms of the proposed
single-switch circuit with integrated SEPIC PFC. Figure 2-31 shows the same operating
waveforms but within the two line frequency cycles. It is observed that the peak voltage across
the MOSFET and the peak current flowing through the MOSFET is approximately 320V and
0.85A respectively. The measured peak voltage and current values are also close to the
calculated values obtained in the previous section.
(vds: 100V/div; ids: 0.5A/div; time: 5µs/div)
Figure 2-30 MOSFET current and voltage waveforms in the proposed SEPIC type single-
stage electronic ballast
(vds: 100V/div; ids: 0.5A/div; time: 2ms/div)
Figure 2-31 MOSFET current and voltage waveforms within line frequency
dsv
dsi
dsv
dsi
83
Figure 2-32 and Figure 2-33 show the measured DC-link voltage of the proposed circuit with
integrated buck-boost PFC and SEPIC PFC respectively.
(vdc: 50V/div; time: 5ms/div)
Figure 2-32 DC-link voltage from single-switch ballast circuit with integrated buck-boost
PFC
(vdc: 50V/div; ids: 0.2A/div; time: 5ms/div)
Figure 2-33 DC-link voltage and lamp current from single-switch ballast circuit with
integrated SEPIC PFC
Figure 2-34 and Figure 2-35 illustrate the PF and efficiency performance respectively for the two
proposed circuits under different line voltages. It is observed that a PF of at least 0.98 is
84
maintained under all operating conditions for both circuits. The overall efficiency of the
proposed circuit with integrated buck-boost PFC and SEPIC PFC are measured to be 83% and
81.7% respectively. The majority of the power loss in the two circuits is due to the turn-off
switching loss of the MOSFET and the copper losses in the inductors. It is believed that higher
efficiency can be achieved by using low DCR inductors.
Figure 2-34 PF performance of the proposed circuits
Figure 2-35 Efficiencies of the proposed circuits
0.97
0.975
0.98
0.985
0.99
0.995
1
90 100 110 120 130 140
Power Factor
Line Voltage (Vrms)
Power Factor Peformance
PF with SEPIC PFC
PF with buck‐boost PFC
77787980818283
90 100 110 120 130
Efficiency (%
)
Line voltage (Vrms)
Efficiency
with SEPIC PFC
with buck‐boost PFC
85
2.4 Chapter Summary
This chapter describes the proposed solution on the electronic ballast power circuit for CFL
applications. In the first section of this chapter, a new single-switch current fed resonant inverter
was proposed to overcome the high voltage and current stress problems in the Class-E resonant
inverter. The mathematical equations that describe the characteristics of the inverter and
harmonics analysis of the resonant circuit were then provided. A series of new single-stage high
PF electronic ballast was then derived based on the single-switch current fed resonant inverter
described in the first section. The first circuit was a buck-boost derived single-stage single-
switch inverter and the second the circuit was a SEPIC-based single-stage single-switch inverter.
The detailed explanations of these circuits’ operating principles were then provided. The key
waveforms that illustrate the circuit operating principles were also discussed in detail.
In the last section of this chapter, simulation and experimental results have been provided
on a 13W CFL to verify the feasibility of the proposed circuits. The results have shown that a
high PF of at least 0.99 and an overall efficiency of 82% were achieved in the two proposed
single-stage single-switch electronic ballast circuits.
86
Chapter 3
Proposed Dimming Control with Phase-Cut Dimmers and Stability
Analysis
With the continuous replacement of incandescent lamps by CFLs in the near future, it is
important for CFLs to be compatible with the existing dimmers designed for incandescent lamps
so that existing wiring connections can remain the same. The previous chapter proposed two
different electronic ballast topologies that were able to achieve very high input PF. By drawing a
sinusoidal line current, the ballast circuit allows the load (i.e. the CFL) to behave more like a
resistor from the AC input point of view. However, as introduced in Chapter 1, the main issue
with incandescent phase-cut dimmer is that the input PF decreases when the conduction time of
the line voltage is decreased to reduce the lamp power. Hence, even though high PF was
achieved with the proposed circuit at full power condition, the same consequence can also happen
to the proposed ballast circuit when phase-cut dimmer is used. In order to extend the high PF
performance throughout dimming with incandescent phase-cut dimmer, a novel dimming control
concept is proposed in this chapter to achieve the aforementioned objective. But before going
into the detailed explanations of the proposed dimming controller, the theoretically analysis on
the basic operating principles of an incandescent phase-cut dimmers will first be discussed.
3.1 Operating Principles of Phase-cut Dimmers
Conceptually, when a standard phase-cut dimmer is to be connected to standard high PF
electronic ballast for fluorescent lamp, the lamp power can be controlled by changing the firing
angle of the dimmer between 0 and π. If we let vs and is be the line voltage and line current, they
can then be described by equations (Eq. 3-1) and (Eq. 3-2) respectively (where ωL = 2πfL is the
87
line angular frequency). If we let α represents the firing angle of the dimmer, then the average
voltage after the rectifier can be obtained as a function of α and is therefore expressed as (Eq.
3-3). The input instantaneous power and the average input power (pi,avg(ωt)) can be expressed by
(Eq. 3-4) and (Eq. 3-5) respectively. From (Eq. 3-5), it is obvious that the maximum power (pmax)
occurs at α = 0 and is therefore given by (Eq. 3-6). The normalized average input power can then
be obtained to be (Eq. 3-7) by dividing (Eq. 3-5) by (Eq. 3-6). Comparing (Eq. 3-5) and (Eq.
3-6), it can be observed that the lamp input power can be controlled by varying the firing angle of
the dimmer from 0 to π rad.
( ) ( )tVtv Lps ωω sin= (Eq. 3-1)
( ) ( )tIti Lps ωω sin= (Eq. 3-2)
( ) ( ) ( ) ( ) ( )απ
ωωπ
ααπ
α
cos1sin1+=== ∫
pLLprectin
VtdtVVV
(Eq. 3-3)
( ) ( ) ( ) ( )tIVtitvtp LppLsLsLs ωωωω 2sin== (Eq. 3-4)
( ) ( ) ( ) ( ) ( ) ( )⎟⎠⎞
⎜⎝⎛ +−== ∫ 2
2sin2
1,
ααππ
ωωωπ
απ
α
ppLLsLsavgi
IVtdtitvp
(Eq. 3-5)
( )2
0,max,pp
avgii
IVpp ==
(Eq. 3-6)
( ) ( ) ( ) ( )⎟⎠⎞
⎜⎝⎛ +−==
22sin1
max,
,_,
ααππ
αα
i
avginoravgi p
pp
(Eq. 3-7)
At the full power condition (i.e. α = 0), it can be seen that unity PF is achieved at the line input.
However, as the conduction times of the voltage after the dimmer and the line current decrease,
the resultant PF drops as the firing angle increases. This relationship can be illustrated from the
88
PF equation as shown in (Eq. 3-8), where α becomes the independent variable. The relationship
between PF and α is displayed in Figure 3-1. It shows that as the firing angle of the dimmer
increases, the PF drops significantly; which consequentially affect the total harmonic distortion
(THD) of the line current. THD, which is related to PF according to (Eq. 3-9), is shown in Figure
3-2 to demonstrate the relationship between α and THD. It shows that the THD of the line
current increases exponentially as the firing angle increases.
( ) ( )
( )
( ) ( )
( ) ( )( ) ( )
⎟⎠⎞
⎜⎝⎛ +−=
⎟⎟⎠
⎞⎜⎜⎝
⎛+−⎟⎟
⎠
⎞⎜⎜⎝
⎛
⎟⎠⎞
⎜⎝⎛ +−
==22sin1
22sin
22
22sin
2,,
ααππααπ
π
ααππ
αα
αpp
pp
rmssrmss
avg
IV
IV
ivp
PF (Eq. 3-8)
( )1
)(1)( 2 −=α
αPF
THD
(Eq. 3-9)
Figure 3-1 PF versus α with typical phase-cut dimmer
0 20 40 60 80 100 120 140 160 1800
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
firing angle (degrees)
pow
er fa
ctor
89
Figure 3-2 THD versus α in conventional phase-cut dimmer
Hence, even for a resistive load such as incandescent lamp, there will be a significant drop in the
input PF when phase-cut dimmer is used to control the output power of the load. In order to
reduce the amount of line current harmonics drawn from the CFL during dimming, it is therefore,
necessary to develop a new control circuit that is able to extend the high PF performance when
phase-cut dimmer is in use.
3.2 Proposed Dimming Control Concept
To correct the poor compatibility issue of phase-cut dimmer with CFL and to improve the input
PF of CFL during dimming, the proposed dimmable electronic ballast controls the lamp output
power by controlling both the firing angle of the phase-cut dimmer and the duty ratio of the
switch in the power circuit. A system diagram of the proposed controller with the single-switch
electronic ballast power circuit is shown in Figure 3-3. Since the SEPIC PFC has been shown to
inherit more advantages than the buck-boost PFC, the single-switch ballast circuit with integrated
SEPIC PFC will be considered in this analysis.
0 20 40 60 80 100 120 1400
0.5
1
1.5
2
2.5
3
3.5
4
firing angle (degrees)
Tota
l Har
mon
ic D
isto
rtion
(TH
D)
90
Figure 3-3 Proposed dimmable electronic ballast
In the proposed controller, the rectified voltage (Vrect) and the DC-link capacitor voltage (Vdc) are
connected to the input of the duty ratio controller. The output lamp power is controlled by
adjusting the pulse-width of the gate signal applied to switch (M1). In Figure 3-3, the rectified
AC line voltage is scaled down first (Vrect1) and fed to compare with a DC signal inside the
controller. At the output of the comparator (U1), a pulse will be generated when the DC signal is
higher than Vrect1. Figure 3-4 illustrates the key waveforms at the controller. Suppose that a firing
angle of α0 is applied at t0, part of the rectified voltage is chopped and the discontinuous-time of
Vrect increases. The corresponding pulse-width of Vu1 generated at the output of U1is increased.
A RC network is then used to obtain the average voltage of Vu1 and is labeled as VRC in Figure
3-3. VRC is then amplified and subtracted from the reference signal. Hence, the pulse-width of
Vu1 is able to provide the information on how much firing angle has been applied to the phase-cut
dimmer during dimming. The purpose of utilizing duty ratio control to provide dimming with the
phase-cut dimmer at the same time is to control the lamp output power without using the full
91
dimming range on the dimmer. By doing this, the lower control range of the phase-cut dimmer
that results in very poor PF in the line current can be avoided.
t0
rect1V
u1V
xV
RCV
refV
Figure 3-4 Key waveforms at the control circuit
3.2.1 Duty ratio analysis with proposed control
According to the proposed control concept, there should exist a particular duty ratio that
corresponds to a particular firing angle, namely, d(α). d(α) can be derived by assuming that the
power losses in the SEPIC converter is negligible, then pavg(α)≈ Vdc(α)Idc(α) = pi,avg (α). The
reference signal (Vref) inside the control circuit, which also equals to the scaled-down output
voltage of the SEPIC converter Vdc1(α) can be expressed as a function of α as shown in (Eq.
3-10), where K is the multiplier gain and G is the scale down factor. The average output current
Idc(α) is equal to the average current flowing diode Db as shown in Figure 3-5. Hence, Idc(α) can
be obtained by averaging iDb over one line period as shown in (Eq. 3-11), where Δ1 represents the
conduction time of the diode Db. The average input power of the SEPIC converter can also be
expressed in the form of (Eq. 3-13) where Ri(α) represents the input mean resistance of the SEPIC
converter and is given by (Eq. 3-14). By setting (Eq. 3-12) equals to (Eq. 3-13), d(α) can be
92
obtained as shown in
(Eq. 3-15). The maximum duty cycle occurs at α = 0 and it can be
expressed in terms of the maximum input power Pimax as shown in (Eq. 3-16). Vdc,max can then be
determined by setting
(Eq. 3-15) equals to (Eq. 3-16), and the final equation is shown in (Eq.
3-17).
Figure 3-5 Diode Db current
( ) ⎟⎠⎞
⎜⎝⎛ −==
παα KGV
GVV dcrefdc max,
1
(Eq. 3-10)
( ) ( ) ( ) ( )( )απ
ωωπ
απ
α
cos12
sin2
1 11 +Δ
=Δ
= ∫eq
spLL
eq
spdc L
TVdtdt
LTVd
I
(Eq. 3-11)
( ) ( ) ( ) ( ) ( )( )⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜
⎝
⎛ −+
Δ==
G
KGV
LTVd
IVpdc
eq
spdcdcavgo
πα
απ
αααα
max,1
, cos12
(Eq. 3-12)
( ) ( )( )
( ) ( )⎟⎠⎞
⎜⎝⎛ +−==
22sin
4
222
,ααπ
πα
αα
αeq
sp
i
iavgi L
TVdR
Vp
(Eq. 3-13)
( ) ( )eq
si L
TdR
2α
α =
(Eq. 3-14)
93
( )
( )( )
( )⎟⎠⎞
⎜⎝⎛ +−
Δ⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜
⎝
⎛ −+
=
22sin
cos12 1
max,
ααπ
πα
α
α
p
dc
V
G
KGV
d
(Eq. 3-15)
( )s
ei
p TLP
Vdd max,
max20 ==
(Eq. 3-16)
s
eidc T
LPV max,
1max, 2
1Δ
=
(Eq. 3-17)
The maximum output power occurs when α = 0. Hence, pomax,avg(α) is given by (Eq. 3-18). The
normalized output power is then obtained as shown in (Eq. 3-19) by dividing (Eq. 3-12) with (Eq.
3-18). To illustrate graphically the relationship between the firing angle of the dimmer and the
required duty ratio of the power circuit, (Eq. 3-15) is plotted in Figure 3-6 for different values of
K with the following design parameters on a 13W lamp: vs = 120Vrms; Ts = 70kHz; G = 0.01; Pimax
= 13W. It shows that the duty ratio is decreasing at the same time while the dimmer firing angle
increases. The normalized power equation given by (Eq. 3-19), is shown in Figure 3-7, to
illustrate the effectiveness of the proposed control concept. It is observed that with a large value
of K, the lamp power can be varied with a much narrow control range of the firing angle.
According to Figure 3-1, high PF can then be achieved even during dimming by limiting the
control range of the phase-cut dimmer. However, it is not very practical from the user point of
view with a large value of K as the lamp power becomes too sensitive to the firing angle of the
dimmer. Hence, the value of K should not be too large in the actual design.
( ) ( ) ( ) ( )πeq
sdcpdcdcavgo L
TVVdIVp max,1
max,
0000
Δ==
(Eq. 3-18)
94
( ) ( )( ) ( )( )
⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜
⎝
⎛ −+=
G
KGV
dVdp
dc
dcnoravgo
πα
αααmax,
max,,, cos1
02
(Eq. 3-19)
Figure 3-6 Duty ratio versus α for different values of K in proposed control
Figure 3-7 Normalized power versus α for different values of K in proposed control
0 20 40 60 80 1000.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
Firing angle (degrees)
duty
K = 1.1
K = 1.5
K = 2
0 20 40 60 80 100 1200
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Firing angle (degrees)
Nor
mai
lzed
Pow
er (W
)
Output Power VS Firing angle
power characteristics with K = 1.5power characteristics with K = 2Original power curve
95
3.2.2 DC-link capacitor voltage ripple analysis
The voltage ripple in the DC-link capacitor can be analyzed according to Figure 3-8. At full
power condition (i.e. α = 0), the voltage ripple |vripple1| imposed on the average output voltage
(Vdc) is a sinusoidal waveform with frequency equals to twice the line frequency as given in (Eq.
3-20). The magnitude of the DC voltage ripple is then given by the peak-to-peak voltage of
vripple1(t) as shown in (Eq. 3-21).
Figure 3-8 vripple during dimming
As α increases during dimming, it can be observed from Figure 3-8 that vripple2 becomes less
sinusoidal and can be described as consisting of two portions: a partly sinusoidal waveform and
the discharge of the DC-link capacitor during the discontinuous period of the line voltage. The
DC-link voltage during the discontinuous period of the line voltage can be obtained by noting that
the DC-link capacitor must discharge its stored energy to the inverter side during this period. vdc
during this period of time is then given by (Eq. 3-22), where Rinv(α) represents the mean input
resistance of the inverter stage. Since t << Rinv(α)C2, (Eq. 3-22) can be represented in terms of
Taylor series as shown in (Eq. 3-23). By combining (Eq. 3-21) and (Eq. 3-23), |vripple (α)|, which
represents the magnitude of DC voltage ripple as a function of α is given by (Eq. 3-24), with
96
Rinv(α) defined by (Eq. 3-25). It is observed from (Eq. 3-24) that when α = 0, |vripple (α)| is equal
to |vripple1| that is given earlier in (Eq. 3-21). The DC-link capacitor can then be designed
according to voltage ripple requirement provided by (Eq. 3-24).
( ) ( )tfCf
Itv L
L
dcripple π
π2sin
4 21 =
(Eq. 3-20)
21 2 Cf
Iv
L
dcripple π
=
(Eq. 3-21)
( ) ( ) ( )⎟⎟
⎠
⎞
⎜⎜
⎝
⎛−=
−
21,CR
t
avgodcinveVtv αα
(Eq. 3-22)
( ) ( ) ( ) ( ) ⎟⎟
⎠
⎞
⎜⎜
⎝
⎛
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛+−−=
2
22, 2
111CR
tCR
tVtvinvinv
avgodc ααα
(Eq. 3-23)
( ) ( ) ( ) ( ) ( ) ⎟⎟
⎠
⎞
⎜⎜
⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛−+=
2
22,
2 21
2 CRCRV
CfI
vinvinv
avgoL
dcripple α
αααα
πα
α
(Eq. 3-24)
( ) ( )( )αα
αdc
dcinv I
VR =
(Eq. 3-25)
3.2.3 Lamp ignition at low dimming level
In order to provide sufficient high voltage to ignite the lamp at low dimming level, it is necessary
to investigate the relationship between the dimmer firing angle and the output voltage of the
proposed resonant inverter. According to (Eq. 2-4), the output voltage can be determined once
iin,1 is known. iin,1 during the lamp ignition stage can be analyzed based on Figure 3-9, which
shows the equivalent circuit of the inverter stage when the MOSFET is on. The output of the
SEPIC converter in Figure 3-9 is modeled as a constant voltage source that is dependent of α.
97
Since the SEPIC PFC stage is required to operate in DCM, the boundary condition CCM-DCM
will provide the least DC-link voltage. Therefore, (Eq. 3-26) is used to determine Vdc(α), where
d(α) is given by (Eq. 3-15).
r
rC
L
pL v+
_out
filr
filr
v+_cr
ini resiinL
+_Vdc(α)
Figure 3-9 Equivalent circuit when the MOSFET is on during lamp ignition
( ) ( )( ) ( )( )ααα
πα
ddV
V pdc −
+=1
cos1min, (Eq. 3-26)
As Rlamp in this stage is assumed to be infinitely large, the lamp is considered to be an open-circuit
at the output of the resonant circuit. Since the input impedance of the inverter stage is purely
reactive (i.e. no resistor), it can be deduced from (Eq. 2-37) that vcr must be 90˚ lagging behind iin.
As a result of that, ires becomes inverse of iin. The key waveforms of the inverter during this stage
are illustrated in Figure 3-10. A set of differential equations that describe the behavior of Lin and
Cr in the resonant inverter is then given in (Eq. 3-27). By solving (Eq. 3-27), iin is obtained as
shown in (Eq. 3-28), which is similar to
(Eq. 3-15) derived earlier in Chapter 2, except that θVcr
must be equal to 90˚ in this case. Since the magnitude of vout during the lamp ignition phase is
given by (Eq. 3-29), iin,rms can then be approximately given by (Eq. 3-29) according to [61], where
iin,pk represents the peak value of iin and it occurs when ωst equals to (Eq. 3-30).
98
Figure 3-10 Key waveforms at the resonant inverter during lamp ignition
( ) ( ) ( ))( tdtdi
LtvVs
sininscrdc ω
ωωα =−
( ) 00 =ini ,
( ) ( )( ) ( )( )( )td
tdvCtiti
s
scrrsressin ω
ωωω =−
( ) pkcrcr Vv ,0 =
(Eq. 3-27)
( ) ( )( ) ( )( )( )( ) ( ) ( )
( )( )sVcr
s
in
rdc
sVcr
sVcrssVcrressin
tLCV
titi
ωθω
αωθ
ωθωωθω
cossin
coscos
1 +⎟⎟⎠
⎞⎜⎜⎝
⎛ −−= (Eq. 3-28)
( ) ( )⎟⎠⎞
⎜⎝⎛ −=
dddi
i pkinrmsin π
ππ cossin12
2,
, (Eq. 3-29)
( ) ( )
( )⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛−
= −
dLC
Vidt in
rdcres
s π
απω
cos
sintan 1 (Eq. 3-30)
99
To support the presented theoretical calculations, the resonant inverter stage during the lamp
ignition phase is simulated in PSIM with a variable input DC source to emulate Vdc(α). The
circuit parameters at the resonant inverter are the same as those given in Table 2-2. Figure 3-11
shows the magnitude of the ignition voltage as a function of α for both cases. It can be observed
that the peak of the output voltage is maintained at above the minimum ignition voltage for a
wide range of dimmer control angle.
Figure 3-11 Relationship between Vign and α
3.3 Negative Impedance of Fluorescent Lamp
When fluorescent lamp operates at high frequency, its steady-state lamp current and
voltage are directly proportional to each other. The steady-state lamp resistance is then said to be
resistive. However, in the presence of any low frequency signal that is imposed on the high
frequency lamp current and voltage waveforms, then the fluorescent lamp would exhibit negative
incremental impedance characteristics, that is, the low frequency envelope imposed on the lamp
0 20 40 60 80 100 120240
260
280
300
320
340
360
380
400
420
440
Dimmer firing angle (degrees)
Mag
nitu
de o
f ign
ition
vol
tage
(Vpk
)
Theoretical valuesSimulation results
100
current and lamp voltage changes in the opposite direction. Since fluorescent lamp is powered
from the AC mains for most of the cases, the frequency of the low frequency signal is equal to
twice the line frequency. When the low frequency signal of the lamp current and voltage change
in the opposite direction, it physically means that the two low frequency signals are simply 180˚
out of phase. These characteristics are illustrated by the waveforms shown in Figure 3-12, where
|^v | is the magnitude of the low frequency signal on the lamp voltage and |
^i | is the magnitude of
the low frequency signal on the lamp current; φ is the phase difference between the two signals
and ωLo is the angular frequency of the envelope signal. Several mathematical models have been
reported in [70]-[72] to describe the characteristics of the lamp negative impedance. In [70], an
approach to model the lamp impedance in the frequency domain is reported. It has been
concluded that the negative incremental impedance of the lamp can be modeled effectively by a
low frequency LHP pole (pL) and a low frequency RHP zero (zL) in the transfer function as shown
in (Eq. 3-31). Due to the presence of a RHP zero in (Eq. 3-31), it means that the lamp cannot be
connected directly to a voltage source as the lamp current transfer function would contain a RHP
pole and it becomes unstable. The complex plot of (Eq. 3-31) is shown in Figure 3-13(a). It
shows that when ωLo is low (i.e. s ≈ 0), the phase of the lamp impedance is 180˚ and its
magnitude is determined by the magnitude of the imaginary axis. According to Figure 3-13(b),
the negative rate of change in the lamp impedance can be explained by changing the operating
from A to B, where the slope of the lamp V-I curve is negative. Hence, the lamp impedance is
negative. As ωLo increases, zlamp follows the trajectory shown in Figure 3-13(a) and eventually
when ωLo approaches to a higher value (i.e. switching frequency), the lamp impedance is no
longer negative (i.e. resistive case in high frequency range). This can be explained graphically by
the line O-A or O-B in Figure 3-13(b), where A and B represent the steady-state operating points
101
of the lamp at two different power levels. From the circuit analysis point of view, in order to
provide stable operation for the lamp as the lamp power changes, the output impedance of the
electronic ballast must be high enough to offset the negative rate of change of the lamp
impedance. In the electronic ballast circuit design, the output impedance provided by the
resonant inverter becomes critical in determining the stability of a dimmable ballast system.
( ) ⎟⎟⎠
⎞⎜⎜⎝
⎛+−
=L
Lllamp ps
zsKsz
(Eq. 3-31)
Figure 3-12 Lamp current and voltage waveforms with low frequency envelope
The main objective of this analysis is to investigate the stability of the proposed system with the
negative incremental impedance of the lamp taken into consideration. An emphasis is especially
placed on how the small signal change in the low frequency envelope of the lamp current or
voltage waveforms affect the stability of the ballast during dimming.
102
(b)
Figure 3-13 (a) Lamp incremental impedance on complex plane; (b) Lamp V-I curve
3.4 Small-signal Modeling of the Proposed Ballast System
The stability of the proposed ballast system is analyzed based on the small signal block diagram
shown in Figure 3-14. The loop transfer function that is of interest in this design is then given by
(Eq. 3-32), where Hsepic(s) is the control-to-vdc transfer function; Hsense,vdc(s) is the transfer function
of the DC-link voltage sensing circuit; Hpwm(s) is the transfer function for the PWM circuit;
Hcomp(s) is the compensator transfer function. To design a stable ballast circuit, the control-to-
DC-link voltage transfer function (^
dcv /^d ) should be studied first.
( ) ( ) ( ) ( ) ( )sHsHsHsHsH SEPICpwmvdcsensecomploop ,= (Eq. 3-32)
103
Resonant circuit
Hcomp(s) Hpwm(s)
Lamp
vcer+_
Hsense,vdc(s)
iout^
_
Hgain(s)
vdc^
vcon
vrect^
vrect1^
vdc1^
d
Hsense,rect(s)
Single-switch electronic
ballast Hpower(s)
Diode rectifier
Tloop (s)
Figure 3-14 Block diagram for the small-signal model of the proposed ballast system
In order to obtain ^
dcv /^d , the small signal model of the power circuit can be analyzed by dividing
the circuit into two different stages: the SEPIC PFC stage and the resonant inverter stage. The
SEPIC PFC that operates in DCM is modeled using the technique given in [63]. The small signal
equivalent circuit of the DCM SEPIC PFC is then shown in Figure 3-15. The control-to-output
transfer function, is then derived as given in (Eq. 3-33), where rL,ac(s) represents the AC load
impedance of the SEPIC converter as given by (Eq. 3-34) and Gd(α) is given by (Eq. 3-36), with
Vrect(α) given by (Eq. 3-3) and Vdc(α) given by (Eq. 3-10). It can be observed from (Eq. 3-33) that
the SEPIC DCM converter exhibits a single pole characteristic that is dominated by the DC-link
capacitor C2. To avoid any unnecessary amplified oscillations from the low frequency ripple on
C2, it should be noted that the crossover frequency (fc) of the final overll loop transfer function
should be well below the pole (pse) that is governed by C2.
( )( )
( ) ( )( ) 1,2
,^
^
+=
srsCsrG
sd
sv
acL
acLddc α
(Eq. 3-33)
104
( ) ( )( ) LL
LLacL Rsr
Rsrsr+
=, (Eq. 3-34)
Lse rC
p2
1=
(Eq. 3-35)
( ) ( ) ( )( ) eqdc
srectd LV
TdVGααα
α2
2
=
(Eq. 3-36)
Figure 3-15 Output stage of the small signal equivalent circuit of a DCM SEPIC
converter
In the proposed ballast system, the AC load impedance (rL,ac) of the SEPIC PFC is given by the
output impedance (zo) of the resonant inverter and the small-signal lamp impedance (zlamp). To
ensure a stable system, the magnitude of the small signal output impedance of the resonant
inverter must be greater than the small signal impedance of the lamp at the low frequency range;
so that the overall AC load impedance is positive at the output of the SEPIC converter. Figure
3-16 shows the general equivalent ballast circuit at the inverter stage, where i^in(s) is the inverter
small signal input current. From Figure 3-16, the small signal output lamp current is given by
(Eq. 3-37). It can be observed that to have a stable output current, the denominator (1+
zlamp(s)/zo(s)) in (Eq. 3-37) must not have any RHP zero as the current response otherwise would
have contain a RHP pole. According to the Nyquist stability criterion, a necessary condition to
105
have a stable lamp current in Figure 3-16 is not to have the impedance ratio zlamp(s)/zo(s) encircle
(-1,0) on the Nyquist plot. This condition applies only when the targeting system (i.e. lamp
current in this case) does not want to have any RHP poles. A physical insight of this stability
requirement implies that the ratio of the magnitude of zlamp(s) over the magnitude of zo(s) must be
less than one, as shown in (Eq. 3-38). The characteristics of the resonant circuit output
impedance and its relationship with the lamp impedance will be discussed in the next section.
( ) ( ) ( ))(/)(1)()(
)(^^
^
szszsi
szszszsisi
olamp
in
lampo
oinout +
=+
=
(Eq. 3-37)
( )( ) 1<szsz
o
lamp (Eq. 3-38)
Figure 3-16 Small-signal equivalent circuit at the inverter stage
3.4.1 Modeling of the resonant inverter
The small signal model of the resonant inverter stage is obtained by applying the time-varying
phasor transformation technique discussed in [67]-[69]. Based on [68], any sinusoidal signals
with amplitude modulation and constant switching frequency in the form of (Eq. 3-39) can also
be represented by (Eq. 3-40) as a funcitn of its time-varying phaor given by ( )tx , where ωs is the
angular switching frequency and θo is the initial phase angle. Phasor transformation can then be
106
applied to any linear circuit elements so that the corresponding phasor model can be derived to
perform the small-signal analysis. The phasor models for the capacitor and inductor are then
derived using the phasor transformation technique and their models [69] are shown in Figure
3-17, where ( )tv is the phasor voltage across the capacitor and ( )ti is the phasor current flowing
through the inductor.
( ) ( )oso txXtx θω +⎟⎠⎞
⎜⎝⎛ += cos
^
(Eq. 3-39)
( ) ( )[ ]tj setxtx ωRe= (Eq. 3-40)
(a) (b)
Figure 3-17 Phasor models for (a) capacitor; (b) inductor [69]
By substituting the phasor model of the inductor and capacitor into the proposed resonant circuit,
the small signal equivalent circuit of the inverter stage is obtained as shown in Figure 3-18. In
this model, all the high frequency components are removed; only the slow variation of the
envelope signal on the lamp current or voltage is considered. This model can then be used to
obtain the small signal output impedance of the resonant circuit.
107
Figure 3-18 Small signal equivalent circuit for the resonant inverter
3.4.2 Small signal output impedance of proposed resonant inverter
As mentioned in the previous section, the interaction between the output impedance of the
resonant inverter and the negative lamp impedance is critical in determining the stability of the
ballast system. The small signal output impedance of the resonant inverter stage is obtained from
Figure 3-18 by open-circuiting the small signal input current source. The final expression of zo(s)
is then given in (Eq. 3-41). For simplicity, the steady-state lamp resistance (Rlamp) is first used in
the calculations. A Bode plot of (Eq. 3-41) and the small signal lamp impedance equation of the
Osram 13W CFL is then displayed in Figure 3-19. It is observed that during the low frequency
range, where the phase of zlamp(s) is 180˚, |zo(s)| is much higher than |zlamp(s)|. This implies that
the output impedance of the designed resonant circuit is high enough to compensate the low
frequency negative lamp impedance. Hence, similar to the conventional voltage-fed LCC
resonant inverter, the proposed resonant inverter is able to provide stable operation for the lamp-
ballast system. When the frequency variation of the small signal envelope imposed on ( )^
siout
and ( )^
svout is small, zo(s) can be approximately given by (Eq. 3-42). The circuit diagram that
describes (Eq. 3-42) is displayed in Figure 3-20.
108
( ) ( ) ( ) ( ) ( )
⎟⎟⎠
⎞⎜⎜⎝
⎛−−++⎟
⎟⎠
⎞⎜⎜⎝
⎛−++⎟
⎟⎠
⎞⎜⎜⎝
⎛++⎟
⎟⎠
⎞⎜⎜⎝
⎛
−+−++=
32223
3223
1323
33
slamp
rprsrt
lamp
pss
lamp
rpr
lamp
rts
lamp
ps
lamp
rprrt
lamp
rpr
rprsprprsprprsrpro
RCLL
jCLR
LjR
CLLR
CLjRL
sjR
CLLCLs
RCLL
s
CLLjjLCLLLsCLLjsCLLssz
ωωω
ωωω
ωωωω
(Eq. 3-41)
( ) ( )( )rprssrtlamppslamp
prslamppsfreqlowo CLLjCLRLjR
LLjRLjsz 32
3^
_, ωωωωω
−−+
−≈
(Eq. 3-42)
Figure 3-19 Bode plot of zo(s) and zlamp(s)
Figure 3-20 Simplified circuit with only low frequency component
20
25
30
35
40
45
50
Mag
nitu
de (d
B)
101
102
103
104
105
0
45
90
135
180
225
270
315
Phas
e (d
eg)
Bode Diagram
Frequency (rad/sec)
Lamp impedance
Inverter output impedance
Lamp impedance
Inverter output impedance
109
When a phase-cut dimmer is used for dimming, the increase in the firing angle of the dimmer will
change Vrect(α), Vdc(α) and d(α). Hence, the stability margin will be changed under different
dimming conditions. If we let αmax represents the maximum firing angle of the dimmer, then
d(αmax) and Vdc(αmax) will become (Eq. 3-43)and (Eq. 3-44) respectively. At the lowest dimming
level, Rlamp increases significantly, which changes Kl in zlamp(s) discussed in (Eq. 3-31). As Kl
changes, the stability requirement of the ballast system (i.e. zlamp(s)/zo(s) not to encircle (-1, 0) on
the Nyquist plot) will also be changed accordingly. Figure 3-21(a) illustrates the Nyquist plot for
zlamp(s)/zo(s) under two different lamp power conditions with the following circuit parameters at
the inverter stage: Lin = 0.39mH; Lr = 1mH; Cr = 2.7nF; Lp = 1.5mH. It can be observed that the
solid-line contour, which represents the ballast circuit at low dimming condition, is very close to
the point (-1,0). The dotted-line contour represents the lamp at full power condition. This
observation implies that unstable lamp current usually occurs when the effect of the negative
lamp impedance becomes more significant at low dimming level.
( )
( )( )
( )⎟⎠⎞
⎜⎝⎛ +−
Δ⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜
⎝
⎛ −+
=
22sin
cos12
maxmax
1
maxmax,
max
max ααπ
πα
α
α
p
dc
V
G
KGV
d
(Eq. 3-43)
( ) ⎟⎠⎞
⎜⎝⎛ −=
πα
αK
GVG
V dcdcmax
max,max1
(Eq. 3-44)
To improve the stability margin at low dimming level, it can be deduced from (Eq. 3-42) that by
increasing Lp, the effective output impedance of the resonant inverter can be increased. Then the
contour curve should be able to move further away from the point (-1,0). Figure 3-21(b) shows
the case when Lp = 2.2mH
110
(a)
(b)
Figure 3-21 Nyquist plot of zlamp(s)/zo(s) (a): Lp = 1.5mH; (b) Lp = 2.2mH
-1.5 -1 -0.5-3
-2
-1
0
1
2
3
0 dB
-10 dB-6 dB-4 dB
-2 dB
20 dB10 dB
6 dB
4 dB
2 dB
Nyquist Diagram
Real Axis
Imag
inar
y A
xis
full pow erat dimming
Nyquist Diagram
Real Axis
Imag
inar
y A
xis
-1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0-3
-2
-1
0
1
2
3
0 dB
-2020 dB
10 dB
6 dB
4 dB
2 dB
full powerat dimming
111
In terms of the compensator design, the control-to-vdc Bode plot needs to be studied first, which is
shown in Figure 3-22.
Figure 3-22 Bode plot of ^^
/ dvdc for different power levels
From Figure 3-22, it is observed that a simple integrator as shown in (Eq. 3-45) is sufficient
enough to increase the DC gain of Figure 3-22 and increase the roll-off rate of the magnitude plot.
In (Eq. 3-45), ki represents the gain of the integrator. By substituting (Eq. 3-45) into (Eq. 3-32),
the overall loop transfer function Tloop(s) can be obtained as given in (Eq. 3-46), where Vpp is the
peak voltage of the saw-tooth signal at the PWM comparator and rL,ac(s) is given by (Eq. 3-47).
From (Eq. 3-46), it can be deduced that the magnitude of Tloop(s) deceases as Gd(α) decreases
during dimming. The optimum phase margin (i.e. close to 45˚), therefore, will occur at full
power condition. Figure 3-23 presents the overall loop Bode plot of the designed system.
112
( )sk
sG icomp =
(Eq. 3-45)
( ) ( ) ( )( )( )1,2
,
+=
srsCsVsrGGk
sTacLpp
acLdiloop
α (Eq. 3-46)
( ) ( ) ( )( ) ( )szsz
szszsr
lampfreqlowo
lampfreqlowoacL +
=_,
_,, (Eq. 3-47)
Figure 3-23 Overall open-loop loop Bode plot at full power condition
It is observed that a phase margin of 47˚ is achieved at full power condition. The crossover
frequency fc is then measured to be around 10Hz. Since fc must be less than one-third of the line
frequency to avoid excessive 2nd harmonic injection from the output voltage into the system [73],
the transient response of the system is quite slow in this design. This is acceptable as fast
transient response is not a mandatory requirement in dimmable electronic ballast designs.
113
3.5 Design Example of Proposed Control Circuit
To confirm the feasibility of the proposed control circuit in dimmable ballast applications, a
proof-of-concept prototype has been built using analog circuitry. The power circuit used in the
experimental prototype circuit is the single-switch resonant inverter with integrated SEPIC PFC
that was proposed in the previous chapter. Table 3-1 lists the design specifications of the tested
prototype.
Table 3-1 Design Specifications
Line voltage: 90 ~ 120Vrms, 60Hz
Dimmer Type: 300W SKYLARK Dimmer from Lutron, SELVB-300P
Lamp: 13W 4-pins Dulux D/E 3500K from Osram Sylvania
Commercial product: 14W Dimmable CFL from Osram Sylvania, CF14EL/TWIST/DIM
3.5.1 Simulation Results
The performance of the proposed control circuit is first validated through PSIM simulation. The
dimmable fluorescent lamp model used in the simulation is a power-dependent model proposed in
[64]. The V-I characteristics of the tested lamp is first obtained, then the power-dependent lamp
resistance equation is derived and is used in PSIM simulation as given in (Eq. 3-48). Figure 3-24
shows the simulated line current and lamp current at different dimming conditions. The PF
obtained at the lowest dimming level in Figure 3-24(c) is 0.67. This dimming level corresponds
to 15% of the full power condition when α = 0. The steady-state lamp current and the
corresponding gate signal waveforms are then shown in Figure 3-25. From the gate signal
displayed in Figure 3-25(b) and (c), it is observed that the duty ratio decreases when dimming
114
occurs with an increase in the dimmer firing angle. The lamp CF in Figure 3-25(c) is measured to
be 1.98, which still meets the ANSI requirement discussed earlier in Chapter 2.
( ) ( ) ( )( ) lamplamplamplamplamp PPPPR /8.64exp158exp7568 −−−+= (Eq. 3-48)
(a) α = 10˚ (b) α = 56˚
(c) α = 92˚
Figure 3-24 Simulated line current and lamp current
115
(a) α = 0˚ (b) α = 56˚
(c) α = 92˚
Figure 3-25 Simulated lamp current and its duty ratio
3.5.2 Experimental Results
This section will present all the experimental results to demonstrate the effectiveness of the
proposed control circuit in dimmable applications. The performance of the proposed circuit is
first compared to the commercial dimmable CFL. Then the PF performance of the proposed
ballast circuit with feed-forward duty ratio control is compared with the same ballast power
circuit but without control.
116
Figure 3-26 shows the line current and lamp current performance of the commercial
dimmable CFL. At full power condition, where α = 0˚, the achieved PF is 0.79, which is much
higher than the non-dimmable CFL tested in the experimental section in Chapter 2. Figure
3-26(b) and (c) show the line current drawn from the same CFL with α = 101˚ and 137˚
respectively. The PF obtained is 0.45 and 0.26 respectively. This shows that the PF decreases
significantly as the dimmer firing angle increases. Figure 3-27 shows the line current
performance of the proposed SEPIC single-stage electronic ballast with fixed duty ratio under
different dimming conditions. Figure 3-27(b) and (c) show the line current and lamp current
when α is 84° and 113° respectively. It is observed that the peak of the line current also increases
as the firing angle of the dimmer increases. This is due to the fact the presence of the DC-link
capacitor causes a relatively slow rise on the DC-link voltage, which indirectly causes a high peak
current at the line when the DC-link capacitor is charged up again.
Figure 3-28 then shows the line current performance obtained from the same ballast
power circuit with the proposed control. It is observed that to achieve the same power level as
displayed in Figure 3-27(b) and (c), the required firing angle with proposed control is 56° and 96°
respectively. The corresponding PF achieved is 0.85 and 0.62 respectively. As a result, the input
PF is increased at each dimming level with the proposed control.
Figure 3-29 shows the steady-state DC-link voltage and the lamp current under different
dimming levels. Figure 3-30 shows the steady-state lamp current and the MOSFET driver signal
at different dimming levels. It is observed that the duty ratio changes from 0.35 (full power) to
0.26 at the lowest dimming level. These results are in good agreement with the simulation
results.
117
α = 0˚ (vs: 100V/div; is: 0.2A/div; time: 5ms/div)
(a)
vs
is
iout
α = 101˚ (vs: 100V/div; is: 0.2A/div; time: 5ms/div)
(b)
α = 137˚ (vs: 100V/div; is: 0.4A/div; is: 0.2A/div; time: 5ms/div)
(c)
Figure 3-26 Line current and line voltage from a commercial dimmable 14W CFL
118
α = 0˚ (vs: 100V/div; is: 0.2A/div; iout: 0.2A/div; time: 5ms/div)
(a)
α = 84˚ (vs: 100V/div; is: 0.2A/div; iout: 0.2A/div; time: 5ms/div)
(b)
α = 113˚ (vs: 100V/div; is: 0.2A/div; iout: 0.2A/div; time: 5ms/div)
(c)
Figure 3-27 Line current performance from proposed single-switch ballast without control
119
α = 56˚ (vs: 100V/div; is: 0.2A/div; iout: 0.2A/div; time: 5ms/div)
(a)
α = 96˚ (vs: 100V/div; is: 0.2A/div; iout: 0.2A/div; time: 5ms/div)
(b)
Figure 3-28 Line current performance with proposed control
120
α = 0˚ (vdc: 50V/div; is: 0.2A/div; iout: 0.2A/div; time: 2ms/div)
(a)
α = 56˚ (vdc: 50V/div; is: 0.2A/div; iout: 0.2A/div; time: 2ms/div)
(b)
α = 96˚ (vdc: 50V/div; iout: 0.2A/div; time: 2ms/div)
(c)
Figure 3-29 DC-link voltage and lamp current waveforms under dimming
121
α = 0˚ (VG: 5V/div; iout: 50mA/div; time: 10µs/div)
(a)
α = 56˚ (VG: 5V/div; iout: 100mA/div; time: 10µs/div)
(b)
α = 96˚ (VG: 5V/div; iout: 100mA/div; time: 10µs/div)
(c)
Figure 3-30 Duty cycle and lamp current during dimming
122
Figure 3-31 shows the lamp ignition waveforms at the low dimming level. In Figure 3-31(a), the
lamp is first dimmed to about 60% of its full power level and is turned off for three seconds.
After that, the lamp is turned on again. Figure 3-31(b) shows the case where the lamp is dimmed
to the lowest dimming condition. It can be observed from both figures that the lamp current and
lamp voltage are able to restore to their original status after the dimmer is switched off and on.
These waveforms demonstrated that with the proposed circuit, the lamp is able to be ignited at
any dimming level when it is used with phase-cut dimmer.
α = 56˚ (vout: 200V/div; iout: 150mA/div; time: 2s/div)
(a)
α = 96˚ (vout: 200V/div; iout: 150mA/div; time: 2s/div)
(b)
Figure 3-31 Lamp current and voltage at low dimming transition
123
Figure 3-32 shows the normalized lamp power curve with respect to the firing angle for all the
tested circuits. It shows that for the same firing angle of the dimmer, the lamp power is able to be
decreased at a much lower level with the proposed control. The lamp power of the commercial
CFL only changes significantly at the lower control range of the dimmer; at the upper control
range of the dimmer, the dimming range is very narrow. As a result, with the proposed control,
the ballast circuit is allowed to control the lamp power in a more linear fashion even when the
dimmer is adjusted to only the upper control range of the dimmer.
Figure 3-32 Normalized input power versus dimmer firing angle
Figure 3-33 shows the relationship between the measured luminous level of the lamp and the
dimmer firing angle. It is observed that the luminous level of the lamp with the proposed control
decreases at a much faster rate than the commercial lamp. Figure 3-34 summarizes the PF
performance of all the tested circuits. It is observed that a PF of 0.8 is still achieved at about 50%
of the full power condition. In order to achieve the same dimming level, the PF of the
0 50 100 1500.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Firing angle (degrees)
Nor
mal
ized
inpu
t pow
er (%
)
With proposed controlWithout controlCommercial dimmable 14W CFL
124
commercial CFL drops to 0.32. By decreasing the duty ratio during dimming with phase-cut
dimmer, the sharp rise at the peak of the line current no longer exists; which allows higher input
PF to be achieved for the same dimming condition.
Figure 3-33 Luminous level versus dimmer firing angle
Figure 3-34 PF performance
0 20 40 60 80 100 120 1400
10
20
30
40
50
60
70
80
90
100
Firing angle (degrees)
Lum
inou
s le
vel (
%)
With proposed controlWithout controlCommercial dimmable 14W CFL
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Normalized input power
pow
er fa
ctor
With proposed controlWithout controlCommercial dimmable 14W CFL
125
3.6 Chapter Summary
In this chapter, a new dimming controller has been proposed to enhance the input PF performance
during dimming by using duty ratio control at the same time when adjusting the firing angle of
the phase-cut dimmer. In the first section of this chapter, the detailed explanations of the
operating principles of a standard phase-cut dimmer using in incandescent lamps were provided.
The features and drawbacks in dimming incandescent lamps with phase-cut dimmer have also
been discussed. Then the proposed control concept was introduced. The goal of this controller
was to extend the high PF performance to dimming CFL with standard phase-cut dimmers. The
controller operating principles, key waveforms, and mathematical analysis have been given to
support the theoretical explanations of the proposed controller.
In the last section of this chapter, both simulation and experimental results were provided
on a 13W CFL design example to highlight the merits of the proposed dimming control concept.
The PF performance obtained from the prototype with the proposed control was also compared to
other commercial dimmable CFL. The final results confirmed that the proposed controller was
capable to maintain a much higher input PF for most of the dimming range with incandescent
phase-cut dimmer than other commercial dimmable CFLs on the market.
126
Chapter 4
Digital Implementation of Proposed Control Concept
It is a known fact that analog control circuits normally occupy large amounts of system space
since they are comprised of various discrete circuit components that perform specific
mathematical or control functions. Analog control circuits are susceptible to problems such as
variations in circuit component tolerances and ambient conditions (e.g. temperature). To address
these problems, digital control techniques such as FPGA (Field Programmable Gate Array) or
ASIC (Application-Specific Integrated Circuit) are used to implement the desired control scheme.
These techniques allow the multiple functions (that make up the control logic) to be embedded on
a small digital control chip; thereby reducing the size of the control circuit while providing the
same functionality of its analog counterpart [74]. Digital control has been used in several
electronic ballast applications. A digital implementation of phase control has been discussed in
[75]. Digitized versions of variable frequency control have also been documented in [76] and
[77]. Both control methods were applied to the half-bridge resonant inverter where the totem-
pole connected MOSFETS were controlled.
Since half-bridge resonant inverters were used as the ballast power circuit in the above
literatures, only variable frequency control or phase-shift control could be used to provide all the
ballast basic functions while at the same time, ensure ZVS operations. One of the design
challenges with digital control in half-bridge inverters is that proper dead-time control must be
considered for the MOSFETs gate signals to avoid over-lapping the turn-on time of the
MOSFETs. Also, these literatures focused only on non-dimmable electronic ballast applications.
If dimming operation needs to be included, the overall digital control architecture will become
127
much more complicated. As the proposed electronic ballast topology is a single-switch single-
stage inverter, conventional duty ratio control that is used commonly in PWM converters could
be applied to greatly simplify the control methods for the switch. When duty ratio control is
implemented in the digital environment, it can be implemented in a much less-complicated
fashion than the conventional control methods used in half-bridge or full bridge resonant
inverters. As discussed in the previous chapter, duty ratio control is used in the proposed work to
achieve high PF when phase-cut dimmer is in use. This means that when duty ratio control is
implemented inside the digital controller, it does not only eliminate all the design challenges in
the conventional digital control methods in half-bridge resonant inverters, but also allows high
input PF to be achieved during dimming in the proposed circuit. If PFC function needs to be
included in the digital controller for the half-bridge resonant inverters, additional control
implementations have to be considered for the front-end PFC converter, which also results in a
much more complicated digital design architecture than the proposed solution.
4.1 Motivations for Digital Control Implementation in Proposed Electronic Ballast
This chapter presents a discussion on the digital implementation of the proposed
controller (see Chapter 3). Because digital controllers are implemented by means of computer
coding (e.g. VHDL: (VHSIC (Very High Speed Integrated Circuit) Hardware Description
Language), they have greater design flexibility than analog circuits. With digital controllers, an
increase in the control scheme complexity does not translate to an increased in its amount of
required system space. This is true since the control functions of digital controllers are
implemented through coding rather than the combination of physical circuit components (e.g.
capacitors, resistors, etc.). To verify the control logic and functionality of the proposed
controller, it was first implemented by analog circuitry as shown in the previous chapter.
128
As analog control circuits require higher components count than digital control
implementation, the analog version of the proposed control circuit was solely focused on the
function for achieving high PF for dimming operations. In the proof-of-concept prototype
provided in the previous chapter, several ICs were used to implement the PF control concept in
the analog control circuit. If more sophisticated control functions such as lamp over-voltage
protection need to be included in the analog control circuit, the components count and the overall
size of the ballast circuit could be further increased. Digital implementation by means of using
VHDL codes allow more advanced control functions to be included in the controller to further
enhance the overall performance of the proposed ballast system without increasing the size of the
ballast circuit. The following section will discuss some other desirable control functions that
could be implemented in the digital controller.
4.2 Control Requirements with Digital Implementation
To enhance the lamp lifetime and its overall performance with standard phase-cut dimmer,
several other desirable functions that could be included in the proposed digital controller are
outlined as follows:
1. Provide soft-start for lamp ignition. The duty ratio in the controller would be increased
slowly from a small value until the point where sufficient high ignition voltage is
provided across the lamp. In soft-start ignition, a small voltage is initially provided
across the lamp electrodes to ensure that the lamp life-time is not affected during the
lamp ignition process.
2. Detection of lamp low power level; when phase-cut dimmer is in use, it is very likely that
unstable lamp operation can occur when the dimmer is switched to a very low position.
Unstable lamp behavior occurs when the lamp current is forced to drop below the
129
negative impedance range of the lamp. In the proposed design, the controller will switch
the entire system into a very low power state where the lamp is essentially off when it is
attempted to dim towards the lower control end of the dimmer. The goal of this function
is to avoid the lamp from being entered into unstable operating range where visible light
flickering occurs. When the dimmer is switched back to a higher control position, the
light should be able to come back automatically.
3. DC-link capacitor over-voltage protection, this function is to protect the circuit from
being strike by any sudden surge in the line voltage. In this protection mode, once the
DC-link voltage exceeds a certain level, the MOSFET should be turned off immediately
to protect the lamp.
Figure 4-1 General diagram of proposed electronic ballast with digital control block
130
In addition, the proposed controller must also be able to provide the same function that the analog
version of the proposed control circuit provided during dimming. In general, the digital version
of the proposed control circuit would be comprised of the following parts: (1) digital pulse-width
modulation (DWPM); (2) digital feed-forward loop; (3) digital compensator. In this section, the
implementation process of each part will be described in detail.
4.2.1 Implementation of digital pulse-width modulation (DWPM)
In analog circuit, duty ratio control is implemented by comparing the control signal at the output
of the compensator with a saw-tooth signal that oscillates at the switching frequency of the power
circuit. This widely used control method is shown in Figure 4-2(a). When duty ratio control is
implemented with digital control logic, it is known as digital pulse-width modulation (DPWM).
Several ways of implementing DPWM have been reported in [78]-[81]. One of the simplest
approaches to implement DPWM is to employ a “counter” concept so that the clock signal is
synchronized as a counting signal to provide the switching frequency of the power circuit. Since
fast transient response and very high switching frequency are not critical requirements in lighting
applications, the DPWM “counter” concept was used in the proposed controller for duty ratio
control. A hardware implementation of the proposed duty ratio control is suggested in Figure
4-2(b), where a reset up-counter with two comparators is used to form the basic functional block
for DPWM. In Figure 4-2(b), Clk represents the clock signal of the digital control circuit; Vcon[n]
is the digitalized control data; Vfre[n] is a pre-defined discrete-time signal that determines the
switching frequency. The counter resets to zero whenever the output of the counter reaches the
value that is given by Vfre[n]. This allows the output signal of the counter to form a discrete-time
based saw-tooth waveform that is compared with d[n]. Figure 4-3 illustrates the key operating
131
waveforms in the DPWM, where VG represents the gate driver signal and d[n] is the digitalized
duty cycle data. The switching frequency provided from the DPWM is then given by (Eq. 4-1).
Figure 4-2 (a): Basic principle of PWM in analog circuit; (b) Implementation of DPWM
[ ]nVClkffre
s = (Eq. 4-1)
Figure 4-3Key waveforms in DPWM
132
4.2.2 Implementation of the digital feed-forward control loop
Recall from Chapter 3 that the key function in the proposed controller is to allow the lamp power
to dim at a faster rate so that the input PF can be increased by limiting the control range on the
phase-cut dimmer. In analog control, a RC network is used to provide the average DC signal of
the pulse generated at the output of a comparator according to Figure 3-3. This DC signal is a
critical parameter that provides the information about the magnitude of the firing angle being
applied to the dimmer. With digital control, the same function can be implemented by using a
logic counter to provide even more accurate pulse-width information. Figure 4-4 shows the logic
flow chart of the feed-forward loop in the controller.
The sampled rectified voltage signal (vrect[n]) is compared with a pre-defined reference
signal (vrect,ref [n]). A digital counter is then used to determine the pulse-width of the pulse at the
output of the digital comparator. If vrect[n] is higher than vrect,ref[n], then the counter will
increment by one and the register will keep the updated value from the counter. Once the output
of the comparator reaches zero, the counter will be reset to zero again. At this time, the register
keeps the final value of the counter (vcount[n]) and passes this value to the bit-shifting block, where
the gain multiplication is performed. The output signal of the bit-shifting block will then be
subtracted from a pre-defined constant signal, where the final output signal will be processed to
the digital compensator.
133
v rect
v [n]rect, ref
yes
nov [n]rect v [n]rect, ref>
Register
Reset counter and go to next clock cycleSample data
Bits-shifting
v [n]rect
Output = 1
Output = 0
Counter = 0
Counter increments by 1
v [n]count
Figure 4-4 Logic flow diagram of the proposed feed-forward loop
4.2.3 Implementation of the low power shut-off detection mode
In the low power detection mode, the objective is to shut down the circuit power when the lamp is
attempted to dim below its stable operating region (i.e. beyond the negative impedance range).
This is because as the lamp is forced to dim over its lamp negative impedance range, the lamp
current drops to below a few mill-amps, the lamp then cannot sustain the same lamp arc across
the lamp electrodes and eventually, only a small amount of light appears at the end of the tube.
Although this situation only happens during the transition between the lamp lowest dimming
point and its off-state, this situation can significantly shorten the lamp lifetime. As a result, by
cutting off the lamp power when the dimmer is forced to dim the lamp beyond the lamp negative
impedance region, the lamp lifetime can be extended even during dimming.
134
The logic flow chart of this control mode is shown in Figure 4-5. In this operating mode, both
vrect and vdc are required to provide proper automatic power shut-off function.
yes
vdc > vdc_shut-off
nov [n]count,max>
Exit shut-off mode
Apply dshut-off
Normal operation mode
yes
no
v [n]dc
Store current vdc[n] vdc_shut-off
v [n]count
?
Figure 4-5 Logic flow diagram in low power detection mode
The first step in this mode is to compute the width of the discontinuous portion of vrect(α), in
which this information can be provided by the feed-forward loop shown in Figure 4-4. If this
value is greater than vcount,max, than the shut-off power mode is entered and an extremely small
duty ratio is applied to the MOSFET. The lamp is essentially off in this stage. Meanwhile, the
corresponding digitalized DC-link voltage signal is also stored. This information is needed when
the dimmer is switched to a higher control position, at this time, the lamp should work in the
normal operation mode. This transition is achieved by monitoring vdc[n] with the previously
stored vdc[n] that corresponds to the lamp power shut-off condition. If the current vdc[n] is greater
135
than the stored value, the system should exit this mode and enter the normal operation mode
immediately.
In order to maximize the lamp dimming range, αshut-off, which is the maximum allowable firing
angle of the dimmer, should be chosen properly in the design. αshut-off can be calculated according
to (Eq. 4-2), where η is the efficiency between the average power at the DC-link capacitor and
lamp output power
( ) ( )( ) ( ) ( )ηαα
απ
α offshutdcoffshut
offshutp
offshutoffshutlamp Id
dVP −
−−−− −
+=1
cos1_ (Eq. 4-2)
4.2.4 Soft-start lamp ignition
In contrast to the instant-start method used in the analog circuit, soft-start ignition is implemented
in the digital controller by slowly increasing the duty ratio of the MOSFET. In this technique, a
small voltage is initially applied across the lamp once the power is turned on. Then the voltage
across the lamp will increase gradually as the duty ratio increases. Once the lamp is ignited, the
system will enter normal operation mode, where the duty ratio will be adjusted according to
different dimming levels.
136
Figure 4-6 Logic flow chart for soft-start function
4.2.5 Implementation of the overall digital control circuit
The overall diagram of the digital control unit is shown in Figure 4-7 by combining all the
aforementioned required functions in the proposed controller. In general, the controller always
works as follows: when the power is on, the lamp ignition mode will be executed immediately.
After the lamp is successfully ignited, the duty ratio decreases to its steady-state value and both
vdc and vrect are then monitored continuously. Any changes occur in vrect means that the dimmer
firing angle is being adjusted and a proper duty ratio will be provided to the MOSFET to control
the lamp power and maintain high PF. Low power shut-off mode will be activated once the
dimmer firing angle exceeds vcount,max[n]. DC-link over-voltage protection is also achieved by
continuously monitoring the DC-link voltage with a pre-defined threshold value inside the
controller so that when the DC-link voltage exceeds the threshold value, a proper signal is sent to
the multiplexer (MUX3) and the controller shifts the ballast system to the over-voltage protection
137
mode, where the duty ratio will be limited to a low value. In this way, the DC-link voltage is
limited to a low value to protect the lamp under abnormal operating conditions.
Figure 4-7 Overall diagram of proposed single-switch electronic ballast with digital
controller
4.3 z-Domain Analysis of Proposed Control
To design a proper digital compensator in the discrete-time controller, a model of the complete
ballast system is first developed as shown in Figure 4-9, where the continuous-time model (s-
domain) of the power circuit is combined with the discrete-time model (z-domain) of the
controller. Stability analysis of the overall system, however, becomes not as straightforward as in
the continuous-time model displayed in Figure 3-14 since the system now consists of both
continuous-time and discrete-time transfer functions. Several approaches such as the Matched
Poles-Zero (MPZ) method, Emulation control method and Tustin’s method have been reported in
[84]-[86] to design a proper compensator in the discrete-time model analysis. Of all the
138
approaches, the direct digital design is the most accurate approach that allows the entire system to
be analyzed in the z-domain. Conventional linear control theory used in the s-domain analysis
can then be applied to the z-domain system, where proper compensator can be designed based on
the overall open-loop behavior. In direct digital design, the continuous-time model of the plant is
first converted into its discrete-time model and then the closed-loop analysis is performed in the
z-domain environment. (Eq. 4-3) shows the relationship between the continuous-time model of
the plant and its discrete-time model, where ΖH(s)/s represents the z-transform of H(s)/s and
H(s) is the continuous-time model of the plant. The conversion in (Eq. 4-3) is then illustrated by
Figure 4-8, where C(s) is the controller; H(s) is the controlled plant; Y(s) is the output signal in
continuous-time and R(s) is the reference signal in continuous-time.
As shown in Figure 4-8(b), the sampler (i.e. ADC) and the zero-order hold (ZOH) block are
simplified and are represented by (1-z-1) and 1/s in (Eq. 4-3). The presence of the step response
term 1/s means that the control signal comes from the ZOH block during each sampling period is
a step signal.
Figure 4-8 (a): Mixed control system; (b): Pure discrete equivalent system
139
( ) ( ) ( )⎟⎠⎞
⎜⎝⎛Ζ−= −
ssHzzH 11 (Eq. 4-3)
From Figure 4-9, the loop transfer function that consists of both s-domain and z-domain models
can be represented by (Eq. 4-4), where Hcomp(z) is the discrete-time model of the compensator and
HZOH(s) is the s-domain ZOH transfer function that accounts for the DAC function or the PWM
model. The transfer function of HZOH(s) is given in (Eq. 4-5), where Tsp is the sampling period.
( ) ( ) ( ) ( )sHzHKsHsHT ZOHcompADCvdcsensepowerloop ,= (Eq. 4-4)
( )sp
ZOH sTzsH
11 −−= (Eq. 4-5)
As can be observed from (Eq. 4-4), except Hcomp(z), the rest of the models are represented by their
s-domain transfer functions. Hence, before going into the design considerations for the
compensator, the overall open-loop transfer function that is represented in z-domain is studied
first, which is given by (Eq. 4-6) using (Eq. 4-3), where Hpower(s) is given by (Eq. 3-33);
Hsense,vdc(s) is a simple resistive scale-down network represented by G and Gd(α) is given by (Eq.
3-36).
( ) ( ) ( ) ( )
( ) ( ) ( )( )( )⎟⎟⎠
⎞⎜⎜⎝
⎛
+Ζ−=
⎟⎟⎠
⎞⎜⎜⎝
⎛Ζ−=
−
−−
11
1
,2
,1
,1
srsCssrGG
z
ssHsH
zzH
acL
acLd
vdcsensepowerloopopen
α (Eq. 4-6)
Since fc is very small in this design, all the high frequency poles and zeros introduced by rL,ac(s)
do not have any significant effects on the system response and the phase margin of the system.
This allows further simplification to be done in (Eq. 4-6). One way to simply (Eq. 4-6) is to
140
consider rL,ac(s) as a mean resistance at each dimming level. (Eq. 3-25) describes this relationship
and is expressed as a function of α. Based on the circuit parameters used in Chapter 3, the
corresponding z-domain overall open-loop transfer function is then given in (Eq. 4-7).
Figure 4-9 Overall system model with continuous-time and discrete-time domains
( ) ( ) ⎟⎟⎠
⎞⎜⎜⎝
⎛+−
−+−−= −−
−−−
− 21
211
9996.0218153.18153.11
zzzezezzH loopopen
(Eq. 4-7)
A Bode plot of (Eq. 4-7) is shown in Figure 4-10. It can be observed that due to the presence of
Gd(α), the low frequency gain in Figure 4-10 during dimming is much lower than at full power
condition. Hence, similar to the continuous-time model analysis, in order to achieve infinite high
DC gain to eliminate any steady-state error, a single-pole compensator that introduces very high
DC gain can be used in the z-domain design. According to the s-to-z domain transform given in
(Eq. 4-8), the discrete-time model of the integrator is then given by (Eq. 4-9), where vc(z) is the z-
141
domain of the input control signal to DPWM and er(z) is the z-domain of the error signal. (Eq.
4-9) is also known as that is the Euler integrator representation. In order to implement the Euler
integrator in the actual digital controller, (Eq. 4-9) must first be converted into a time domain
equation so that it can be realized using VHDL codes inside the digital controller. The discrete-
time domain of (Eq. 4-9) is then given by (Eq. 4-10) using inverse z-transform, where n
represents the nth sampling time. A block diagram of (Eq. 4-10) is then given in Figure 4-11.
spsp fTjsT eez π21 −−− == (Eq. 4-8)
( ) ( )( ) 11 −−
==zzer
zvzG c
compβ
(Eq. 4-9)
[ ] [ ] [ ]nernvnv cc β+−= 1 (Eq. 4-10)
Figure 4-10 Bode Plot of overall open-loop transfer function
-60
-40
-20
0
20
Mag
nitu
de (d
B)
10-1 100 101 102 103-135
-90
-45
0
Phas
e (d
eg)
Bode Diagram
Frequency (Hz)
full powerdimming
142
Figure 4-11 Implementation of discrete-time integrator
The overall loop z-domain transfer function is given in (Eq. 4-11). fc can be obtained by first
converting (Eq. 4-11) into its s-domain function and equating |Hloop(s)| = 1. The equation to
calculate fc is then given in (Eq. 4-12). In this design, fc is determined to be 3.4Hz and the phase
margin achieved is 48.2˚ at full power and 69˚ during dimming condition.
Figure 4-12 Bode Plot of the loop transfer function in z-domain
-150
-100
-50
0
50
Mag
nitu
de (d
B)
10-1 100 101 102 103-225
-180
-135
-90
-45
Phas
e (d
eg)
Bode Diagram
Frequency (Hz)
full powerdimming
143
( ) 21
21
9996.0217229.17229.1
−−
−−
+−−+−
=zz
zezezH loop (Eq. 4-11)
( ) ( )( )
2/1
2
2422
2141
21
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛ −+=
ααα
π inv
dinvc RC
GRCf (Eq. 4-12)
4.4 Design Example
To verify the functionality of the proposed digital controller, a design example is given here. The
design specifications of the digital control portion are listed in Table 4-1. Both the line voltage
range and the tested lamp model are same as the one used in Chapter 2 and 3.
Table 4-1 Design Specifications of the Design Example with Digital Control
A/D conversion data (bits): 10bits
Clock frequency: 10MHz
Switching frequency: 70 kHz
4.4.1 Simulation Results
In order to obtain simulation results from the completed simulated system, the software
implementation that is realized in ModelSIM 6.3 is combined with the analog power circuit (in
PSIM) and the entire system is then simulated in Simulink. Figure 4-13 shows the interactions
between the simulation software. In order to achieve a switching frequency of 70 kHz, the digital
counter in the DPWM would reset to zero once 144 clock cycles are counted. The two input
signals (vdc and vrect) to the digital control block are both 10-bits data. In PSIM, the analog-to
digital (A/D) conversion of vdc and vrect is performed by using discrete control blocks that
implements the same function the A/D conversion chip ADS 7884 does, where the A/D
conversion is performed by sampling the complete 10-bits data every 16 clock cycles [82].
144
Figure 4-13 Block diagram for power circuit simulation with digital control in Simulink
As for the digital compensator, the z-domain of (Eq. 3-45) is obtained through the continuous-to-
discrete-time transform in MATLAB as shown in (Eq. 4-13), where the sampling frequency is
equal to the clock frequency, which is 10MHz. The corresponding gain is then determined to be
0.000083.
To verify the functionality of the designed digital compensator, Figure 4-14 shows the
simulated lamp current when there is a step change in the dimmer firing angle. A stable lamp
current can be observed. Due to the relative slow response of the system, the lamp current takes a
few line cycles to return to the next steady-state operation.
( ) 11006-4.167e
−−=
zzGcomp
(Eq. 4-13)
145
Figure 4-14 Simulated waveforms during dimming transition
4.4.2 Experimental Results
Experimental results are provided in this section to further support the functionality of the
proposed controller. The Digital-Signal Processing (DSP) board used in the experimental
prototype is the Altera Stratix Edition II EP2S60F1020C4 model [85]. The design specifications
of the ballast power circuit were given in Table 3-1.
Figure 4-15 shows the steady-state line current and lamp current waveforms at full power
and during dimming operation. The PF measured in Figure 4-15(b) is 0.76. The lamp current
during the dimming transition is then displayed in Figure 4-16. It is observed that as the firing
angle of the line voltage increases during dimming, the lamp current maintains in a very stable
operation.
146
α = 0˚ (vs: 100V/div; is: 0.3A/div; iout: 0.2A/div; time: 5ms/div)
(a)
α = 86˚(vs: 100V/div; is: 0.3A/div; iout: 0.2A/div; time: 5ms/div)
(b)
Figure 4-15 Line current performance with digital control
Figure 4-17 and Figure 4-18 show the lamp voltage and current during the lamp ignition process.
The top figure shows the case when the dimmer is at its full conduction angle and the bottom
figure shows the case when the lamp is ignited at low dimming level. In the bottom figure, the
147
lamp is first turned off for 1.5 seconds and then turned back on again. In both figures, the lamp
voltage increases gradually until the point where the lamp current starts to increase to its steady-
state level. As a result, lamp soft-start ignition is achieved throughout the whole dimming range.
(vs: 100V/div; is: 0.3A/div; iout: 0.2A/div; time: 50ms/div)
Figure 4-16 Lamp current during dimming with digital control
The low power shut-off mode feature in the digital controller is then verified by Figure 4-19,
which shows the voltage after the dimmer (vdim); the line current and the lamp current. It is
observed in Figure 4-19(a) that as the dimmer firing angle increases, the lamp current decreases
gradually until the point where the discontinuous portion of the line voltage exceeds the pre-
defined value in the digital controller, then both the line current and lamp current go to zero. The
reverse operation mode (i.e. from low power shut-off mode to low dimming) is then illustrated in
Figure 4-19(b). Hence, the results shown in Figure 4-19 justified the logic design of the proposed
digital controller, where the lamp power is automatically cut off by reducing the duty ratio to an
extremely small value when dimmer switch is set at a very low control range.
148
(vout: 200V/div; iout: 0.2A/div; time: 500ms/div)
Figure 4-17 Ignition at full power with soft-start feature
(vout: 300V/div; iout: 0.2A/div; time: 500ms/div)
Figure 4-18 Ignition during dimming with soft-start feature
149
(vout: 100V/div; is: 0.3A/div; iout: 0.2A/div; time: 50ms/div)
(a)
si
outi
dimv
Shut -off power mode
(vout: 100V/div; is: 0.3A/div; iout: 0.2A/div; time: 50ms/div)
(b)
Figure 4-19 Illustration of low power shut-off mode
Figure 4-20 shows the starting transients of vdim and is when the dimmer is turned on at low
dimming level. Different from Figure 4-19, vdim in Figure 4-20 increases from zero at the moment
150
when the dimmer is switched on. In conclusion, Figure 4-19 and Figure 4-20 demonstrate that
regardless of the status of the dimmer on/off switch, the proposed digital controller allows the
lamp to enter the shut-off power mode before the lamp enters its positive impedance operating
region, where unstable lamp operation occurs.
si
outi
dimv
si
outi
dimv
(vout: 100V/div; is: 0.3A/div; iout: 0.2A/div; time: 50ms/div)
Figure 4-20 Illustration of input current and voltage waveforms at low dimming start-up
151
Figure 4-21 shows vdc and is in the over-voltage protection mode. In this example, the maximum
value of vdc is internally set to 100V. Hence, when vdc goes over 100V, the ballast system will
shift to over-voltage protection mode and as observed from Figure 4-21, the lien current drops to
zero immediately when DC-link over-voltage is detected.
Figure 4-21Line current and DC-link voltage in over-voltage protection mode
The performance comparisons between the proposed control with analog circuit and digital
control logic are summarized in Table 4-2.
Table 4-2 Performance comparisons between proposed control with analog and digital logic
Control with analog
circuit
Control with digital
control logic
PF at full power 0.991 0.992
Dimming range with PF > 0.8 70% 70%
Ignition capability at low dimming Yes Yes
Soft-start capability No Yes
Low lamp power shut-off function No Yes
152
Both control schemes are able to provide a PF of at least 0.8 for 70% of the dimming range.
However, with digital control, additional control functions were implemented without increasing
the actual size of the control circuit when the final control chip is implemented.
4.5 Chapter Summary
In this chapter, a digital implementation of the proposed dimming controller was given using
FPGA technique. The functions of the proposed controller with digital implementation included:
the proposed control high PF concept given in chapter 3; low lamp power detection mode, lamp
soft-start function and DC-link capacitor over-voltage protection. Then, the s-domain of the
proposed controller that was implemented using analog-control was transformed into the z-
domain. Then the digital implementation of the control circuit was performed with the VHDL
program written in ModelSIM. Analytical explanations and logic flow charts were all presented
and explained in detail.
Simulation of the entire ballast system was then performed in Simulink by combining the
analog portion of the proposed single-switch electronic ballast power circuit with the digital
control algorithm created in ModelSIM. Experimental results were then presented at the end of
this chapter to further support all the theoretical concepts and highlight the performance of the
proposed controller.
153
Chapter 5
Summary and Conclusions
With increased concern regarding the world’s depleting energy resources, power electronics is
now playing a significant role in providing improved energy-saving technology. In the lighting
industry, it has been proposed in many countries to gradually replace conventional incandescent
lamps with Compact Fluorescent Lamps (CFL) to save energy. However, it should be noted that
the PF drawn by an incandescent lamp is much higher than the typical commercial CFL. If a
lamp has poor PF, it means that reactive power is consumed in the power conversion process
between the utility and the actual lamp. In another words, the use of these conventional CFLs
with poor PF will not offer significant energy savings when compared to the incandescent lamps.
Also, because of stringent size and cost constraints on CFL electronic ballast circuits, the ballasts
used in the CFLs currently on the market cannot work well with standard phase-cut incandescent
dimmers. The state-of-the-art ballasts that work with phase-cut dimmers are bulky and too
expensive to be practically used. The motivation for this thesis stem from the drawbacks of the
CFLs that are currently on the market. The CFL electronic ballast presented in this thesis is a
more cost-effective alternative to the dimmable ballasts mentioned in literature. The proposed
ballast allows CFLs to achieve the same lighting performance as incandescent lamps while
consuming less energy.
5.1 Contributions
A new dimmable electronic ballast system has been proposed in this thesis to improve both the
poor PF in CFLs and its dimming capability with incandescent phase-cut dimmer. The
contributions of this thesis are summarized as follows:
154
1. A novel single-switch current fed resonant inverter has been proposed to overcome the
high current and voltage stress problem in the Class E resonant inverter that is used in
electronic ballast applications. Experiment results have shown that the proposed circuit
has significantly lower MOSFET voltage and current stress than the Class E resonant
inverter. Detailed descriptions regarding the circuit operating principles and the
mathematical analysis of the resonant circuit has been provided.
2. Two novel single-stage single-switch high PF electronic ballasts have been derived based
on the proposed single-switch resonant inverter. The first electronic ballast circuit
consists of a buck-boost PFC stage and the second electronic ballast circuit consists of a
SEPIC PFC stage. Both circuits have the following advantages: (1) they are able to
achieve very high input PF with very low THD in the line current; (2) it eliminates the
need for a large high voltage DC-link capacitor as in the DCM boost PFC case; (3) only
one switch is required in the ballast power circuit and it has much lower voltage stress
across the switch than any other reference topologies; (4) ZCS is provided at the turn-on
of the MOSFET to minimize the switching loss.
3. The proposed single-switch electronic ballast with integrated SEPIC PFC has the
additional advantage that the input rectified current always in CCM, which allows much a
simpler EMI filter design compared to the single-switch electronic ballast with integrated
buck-boost PFC case.
4. The proposed single-switch electronic ballast with integrated buck-boost PFC requires
fewer components (one less inductor and capacitor) than the SEPIC PFC ballast.
5. A new control concept has been proposed to extend the high PF performance to a wide
dimming range when the proposed electronic ballast power circuit was used with
155
incandescent phase-cut dimmer. The proposed control scheme controls the lamp power
by using both the duty ratio control of the switch and the firing angle of the dimmer to
provide a wide dimming range for CFLs. All the mathematical equations, simulation and
experimental results have been provided to support the feasibility and functionality of the
proposed controller.
6. The small signal model of the proposed ballast system has been derived. The stability of
the overall system has been studied; the negative lamp incremental impedance was taken
into account in the stability analysis.
7. A digital version of the proposed control scheme was implemented using the FPGA
technique. Additional control functions that could result in increased size of the analog
circuit have been implemented using a digital controller. These functions included: soft-
start lamp ignition throughout the whole dimming range; detection of lamp low power
mode and DC-link capacitor over-voltage protection. The operating principles,
simulation and experimental results have been provided to justify all the theoretical
analysis.
5.2 Future Works
With regards to the research conducted in this thesis, some possible future works are summarized
in the list below:
1. Design of the proposed electronic ballast power circuit for high line voltage: the
proposed circuits have been designed for North American line voltage range. To ensure
that the proposed circuit can be practically used in countries where high line voltage
range is required, the circuit parameters should be re-designed and a prototype circuit
could be built and tested accordingly.
156
2. Apply the proposed dimming control concept to conventional half-bridge electronic
ballast: the proposed dimming controller was designed for the single-switch electronic
ballast proposed in this dissertation, where duty ratio control can be used. However, the
proposed control concept can be applied to the two-stage high PF electronic ballast with
half-bridge resonant inverters. With half-bridge resonant inverters, duty ratio control
cannot be used. Therefore, to extend its applications to half-bridge resonant converters,
the proposed controller should use other control methods such as variable frequency
control or phase-shift control to control the output power of the ballast. The different
implementations of the proposed controller would thus allow other types of ballasts to
also achieve high PF performance when phase-cut dimmers are used.
5.3 Conclusions
A new dimmable electronic ballast system that is compatible with incandescent lamp phase-cut
dimmers has been presented in this thesis. The proposed electronic ballast power circuit uses
only one switch to achieve the PFC function and provide all the essential ballast functions of a
conventional resonant inverter stage. It has been demonstrated that the dimming performance of
a CFL was comparable to that of the incandescent lamp when the proposed dimmable electronic
ballast was used. Also, it has been verified that the proposed dimming control concept allowed
the ballast to achieve high PF over the majority of the dimming range of a standard phase-cut
dimmer. A novel digital implementation of the proposed control method has also been provided.
In this thesis, detailed explanations of the circuit operating principles, theoretical analyses of the
circuit characteristics, and the stability analysis of the whole ballast system have been provided.
Finally, experimental and simulation results have been provided on a 13W CFL to support the
feasibility and highlight the merits of the proposed work.
157
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169
Appendix A
Derivation of Resonant Inverter Current Expression
The general form of any Fourier series that is periodic in the range [-π, π] is shown in (Eq. A-1),
where a0, an and bn represented by (Eq. A-2), (Eq. A-3) and (Eq. A-4) respectively. Hence, the
Fourier series that represents iin can also be written in the form of (Eq. A-1) as given in (Eq. A-5),
where the corresponding a0 represents the average component of iin, a1 and b1 represent the
fundamental coefficient, an and bn represent the high order coefficients with n ≥ 2, as given in
(Eq. A-6) and (Eq. A-7) respectively.
( ) ( )∑∑∞
=
∞
=
++=,...2,1,...2,1
0 sincos2
)(n
nn
n nxbnxaaxf
(Eq. A-1)
( )∫−
=π
ππdxxfa 1
0
(Eq. A-2)
( ) ( )∫−
=π
ππdxnxxfan cos1
(Eq. A-3)
( ) ( )∫−
=π
ππdxnxxfbn sin1
(Eq. A-4)
( ) ( ) ( ) ( )∑∞
=
++++=,...3,2
110 sincossincos
2)(
nsnsnsssin tnbtnatbta
ati ωωωωω
(Eq. A-5)
( )( ) ( )( )
( )( ) ( ) ( )∫
−⎟⎟⎠
⎞⎜⎜⎝
⎛+⎟⎟
⎠
⎞⎜⎜⎝
⎛ −−=
π
π
ωωαω
ααω
ωθπ
tdtntLCVtia ss
s
in
rdc
ssVcrresn cos
cossin
coscos11
(Eq. A-6)
170
( )( ) ( )( )
( )( ) ( ) ( )∫
−⎟⎟⎠
⎞⎜⎜⎝
⎛+⎟⎟
⎠
⎞⎜⎜⎝
⎛ −−=
π
π
ωωαω
ααωωθ
πtdtnt
LCVtib ss
s
in
rdc
ssVcrresn sin
cossin
coscos11 (Eq. A-7)
The conduction time of iin is given by 2πd as shown in Figure 2-14. d can be determined
accordingly by substituting ωst = 2πd into (Eq. 2-35) and equating (Eq. 2-35) to zero as shown in
(Eq. A-8), with K given by (Eq. 2-20). Let K1 given by (Eq. A-9), then squaring both sides of
(Eq. A-8) and then adding one on each side results in (Eq. A-10). Then K1 can be expressed in
terms of d as shown in (Eq. A-11). Finally, d is also obtained as expressed in (Eq. A-12) by
solving (Eq. A-10) in terms of K1.
( )( ) ( )( )
( )( )
( )( ) ( )( )
( )( )d
d
iK
tLCV
ti
sVcrres
s
in
rdc
ssVcrres
ππ
ωθα
α
αω
ααω
ωθ
2cos12sin
sin
cos
0cos
sincos
cos1
−=
−∴
=+⎟⎟⎠
⎞⎜⎜⎝
⎛ −−
(Eq. A-8)
( )( ) ( )( )sVcrresi
KK
ωθα
α
−=
sin
cos1
(Eq. A-9)
( )( ) ( )
( )dK
dddK
π
πππ
2cos121
2cos2cos212cos221
21
22
1
−=+∴
+−−
=+
(Eq. A-10)
( ) ( ) 12cos1
21 −
−=∴
ddK
π (Eq. A-11)
( ) ⎟⎟⎠
⎞⎜⎜⎝
⎛+−
=∴ −
11cos
21
21
211
1 KKKd
π (Eq. A-12)
171
Appendix B
Derivation of RMS Current Expression for Diodes Din and Db
The RMS expressions for iDin in the single-switch SEPIC type electronic ballast within a line
period can be obtained by first obtaining the average of the square of the signal within a
switching period, as given in (Eq. B-1). The RMS expression of iDin over half of the line cycle is
then given in (Eq. B-2):
( )2
3222
0
2
2
2
3sin1
eq
sLpdT
eq
s
sTsDin L
dTtVdtt
Lv
Ti
s ω=⎟
⎟⎠
⎞⎜⎜⎝
⎛= ∫
(Eq. B-1)
( ) ( ) ( )
( )6
sin3
3sin11
2/3
0
22
322
02
322
0
2,
eq
sp
eq
sp
L
T
eq
sLp
LL
T
TsDinL
rmsDin
LdTV
dL
dTV
tdL
dTtVT
tdiT
iLL
==
==
∫
∫∫
θθπ
ωω
ω
ρ
(Eq. B-2)
Similarly, TsDbi2 can be derived as given in (Eq. B-3) according to the boundary condition to
operate the SEPIC PFC in DCM. iDb,rms is then derived as shown in (Eq. B-4) using the same
technique obtained for iDin,rms.
( ) ( )22
22222
2
2
2
31sin1
LddTtV
dttLV
Ti sLp
T
dT
dc
sTsDb
s
s
−=⎟⎟
⎠
⎞⎜⎜⎝
⎛−= ∫
ω
(Eq. B-3)
( ) ( ) ( ) ( )
( )6
1
31sin11
2
022
2222
0
2,
L
ddTV
tdL
ddTtVtdi
Ti
sp
LsLp
L
T
TsDbL
rmsDb
L
−=
−== ∫∫ ω
ωπ
ωπ
(Eq. B-4)
172
Appendix C
Input Filter Design for Proposed Single-switch Electronic Ballast
Figure C-1shows the simplified circuit at the input side with the L-C input filter. The simplified
equivalent circuit with the output current source represents the average current drawn at the input
of the rectifier is shown in Figure C-2. Li and Ci are then designed by first analyzing the circuit
using superposition theorem.
Figure C-1 Input circuit stage at the rectifier
Figure C-2 Simplified equivalent circuit at the input filter side with superposition
The total input current (is) is then given by (Eq. C-1) in its phasor form and the corresponding
phase angle of is is given in (Eq. C-2).
173
iiL
piLpfcs CL
VCjii 21 ω
ω−
+=
(Eq. C-1)
( ) ⎟⎟⎠
⎞⎜⎜⎝
⎛= −
pfc
piLiis i
VCC
ωφ 1tan
(Eq. C-2)
From (Eq. C-2), it is observed that the presence of Ci can introduce a phase shift between
the line voltage and the line current. Hence, Ci should not be too big in the actual design. On the
other hand, the cut-off frequency (fc), which is given by (Eq. C-3), should be around 1/5 of fs [83].
In the design example, Vp = 170; ωL = 2π*60; ipfc = 0.16; fs = 70 kHz. Hence, fc is chosen to be 7
KHz. The relationship between Li and Ci is then displayed in Figure C-3. The final values of Li
and Ci are then chosen to be 1.5mH and 10nF.
iic CL
fπ2
1= (Eq. C-3)
Figure C-3 LC filter design curve
0 0.2 0.4 0.6 0.8 1x 10-7
0
0.005
0.01
0.015
0.02
0.025
Capacitance (F)
Indu
ctan
ce (H
)
Design curve for input filter
174
Appendix D
Schematic in PSIM Simulation
Figure D-1 Power-dependent lamp model in PSIM
Figure D-2 Single-switch electronic ballast with integrated buck-boost PFC in PSIM
175
Figure D-3 Single-switch electronic ballast with integrated SEPIC PFC in PSIM
Figure D-4 Single-switch SEPIC type electronic ballast with proposed control in PSIM
176
Figure D-5 PSIM schematic of the power circuit and A/D circuit interface
177
Figure D-6 Simulation of the proposed ballast system with digital control implemented in
Simulink
duty
error
Vrec_Q
ADCLK
PS_CHSel3
PS_CHSel2
PS_CHSel1
PS_CHSel0
AD_CS
PS_CHSel7
PS_CHSel6
PS_CHSel5
PS_CHSel4
Vg
Data_VI
Vrectdata
sepicballastserialAtoD
Continuous
powergui
Step
Vrectdata
reset
Data_VI
PS_CHSe7
PS_CHSe4
PS_CHSe5
PS_CHSe6
CLK_VI
PS_CHSe3
PS_CHSe1
PS_CHSe2
Ersignal
PS_CHSe0Q
dutycycle
Vrect_Q
CS_VI
HDL Cosimulation
double
Data Type Conversion9
double
Data Type Conversion8
double
Data Type Conversion7
double
Data Type Conversion6
booleanData Type Conversio n
double
Data Type Conversion4
double
Data Type Conversion3
double
Data Type Conversion2
double
Data Type Conversion16
double
Data Type Conversion15
double
Data Type Conversion14
double
Data Type Conversion13
booleanData Type Conversion12
boolean
Data Type Conversion11
double
Data Type Conversion10
double
Data Type Conversion1
double
Data Type Conversion
178
Appendix E
Bill of Materials of Control Circuit Components and CFL Data
Figure E-1 Electrical diagram of proposed control with analog circuit
179
Table E-1 BOM of Control Circuit
Component Designator Description
R1, R3 1MegΩ, SM 1206
R2 15kΩ, SM 0805, 1/4W
R4 12kΩ, SM 0805, 1/4W
R6, R16 10kΩ, SM 0805, 1/4W
R7 33kΩ, Axial 1/4W
R8, R9, R11, R13, R18 100kΩ, SM 0805, 1/4W
R12, R14 100kΩ, SM 1206
R10 150kΩ, SM 0805, 1/4W
R15 180kΩ, SM 0805, 1/4W
R17 47kΩ, SM 0805, 1/4W
R5 1kΩ, SM 1206
R19 470Ω, SM 0805, 1/4W
R20 220Ω, SM 0805, 1/4W
R21 11kΩ, SM 0805, 1/4W
R22 220Ω, SM 0805, 1/4W
C1 0.01µF, SM 0805
C2 4.7µF, SM 0805
C3 0.22µF, SM 0805, 1/4W
C4 0.27nF, SM 0805
C6 1 µF, SM 0805
C7 0.01 µF, SM 1206
C5 2.2nF, 125V film cap
Q1 Q2N2907, TO-18
M7 LM555, 8-SOIC
M2, M3, M4 LM258, 8-SOIC
M1, M5 ADCMP370, 5-lead SC70
M6 IR4427, 8-SOIC
180
Table E-2 13W CFL D/E Dulux type (Osram Sylvania) data
lamp RMS current (mA) lamp RMS voltage (V) Approx. Lamp Resistance (Ω)
132.9 92.9 699.02 122.1 94.1 770.68 110.5 95.5 864.25 104.5 96.7 925.36 94.2 101.7 1079.62 76.5 104.7 1368.63 65.2 109.8 1684.05 53.7 111.4 2074.49 39.2 112.1 2859.69 29.9 113.2 3785.95 24.5 115.2 4702.04 15.2 117.5 7730.26 12.7 123.9 9755.91 6.9 130 18840.58 4.5 131.5 29222.22 4 128.5 32125.00
Figure E-2 Measured 13W CFL V-I characteristics
0 0.02 0.04 0.06 0.08 0.1 0.12 0.1480
90
100
110
120
130
140
Lamp current (mA)
Lam
p vo
ltage
(V)
Experimental datacurve-fitting
181
Appendix F
Printed Circuit Board (PCB)Layouts
Figure F-1 PCB layout of single-switch SEPIC type ballast circuit with fixed duty ratio
Figure F-2 PCB layout of the control circuit with duty ratio control
182
z
Figure F-3 PCB layout for A/D conversion circuit
183
Appendix G
VHDL Codes Created in ModelSIM 6.3 for Digital Control
The VHDL codes written for the proposed digital control logic is given as follows:
-----------------------------------------------------------------------------------------------
--- Chip-selection Signal Generator (ADC Timing) for ADS 7884 ------
-----------------------------------------------------------------------------------------------
library ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.all;
ENTITY ADCTiming IS PORT (
resetn:IN std_logic;
CLK: IN std_logic;
CS: OUT std_logic
);
END ADCTiming;
ARCHITECTURE behavioral OF ADCTiming IS
BEGIN
PROCESS(clk,resetn)
variable count: integer range 0 to 15;
BEGIN
if resetn='0'then
count:=0;
CS<='1';
else
if rising_edge(clk) then
if count<15 then
count:=count+1;
CS<='0';
else
count:=0;
CS<='1';
184
end if;
end if;
end if;
END PROCESS;
END behavioral;
-----------------------------------------------------------------------
--- Main program ------
----------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.Numeric_std.all;
ENTITY compensator IS PORT (
clk : IN std_logic;
resetn: IN std_logic;
Data_VI: IN std_logic;
Vrectdata: IN std_logic;
CS_VI: IN std_logic;
CHSEL: OUT std_logic;
ADErrorData: OUT signed(9 downto 0);
Vdc_data_signal: OUT unsigned(7 downto 0);
Vdc_data_out9:OUT std_logic;
Vdc_data_out8:OUT std_logic;
Vdc_data_out7:OUT std_logic;
Vdc_data_out6:OUT std_logic;
Vdc_data_out5:OUT std_logic;
Vdc_data_out4:OUT std_logic;
Vdc_data_out3:OUT std_logic;
Vdc_data_out2:OUT std_logic;
Vdc_data_out1:OUT std_logic;
Vdc_data_out0:OUT std_logic;
ign_flag:OUT std_logic;
ReadyVolData:OUT std_logic;
185
Q: OUT std_logic);
END compensator;
ARCHITECTURE behavioral OF compensator IS
type StateType is (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15);
signal CurState: StateType;
SIGNAL Vrect_Q: std_logic;
SIGNAL Vrect_count: signed(31 DOWNTO 0);
SIGNAL Vrect_pulse_width: signed(25 DOWNTO 0);
SIGNAL Vrect_pulse_width1: signed(31 DOWNTO 0);
SIGNAL comp: signed(24 DOWNTO 0);
BEGIN
PROCESS(clk, resetn)
variable NextState: StateType;
variable VolRef : unsigned(9 downto 0):="0110001000";
variable VarData_ACQD: unsigned(15 downto 0);
variable VrectData_ACQD: unsigned(15 downto 0);
variable VAR_CS_TIMING,VarReady_VolData,VarReady_CurData,VarCHSel: std_logic;
variable VarADErrorData: signed(10 downto 0);
variable Vdc_data: unsigned(9 downto 0);
variable Vdc_data_threshold: unsigned(9 downto 0):="0000000001";
variable Rectified_volt: unsigned(9 downto 0);
variable abnormal_Vdc: unsigned(9 downto 0):="0111110001";
variable Threshold: signed(8 DOWNTO 0):= "010010000";
variable Count: signed(8 DOWNTO 0):= "000000000";
variable V_count: signed(31 DOWNTO 0):= "00000000000000000000000000000000";
variable V_count_max: signed(31 DOWNTO 0):= "00000000000000000000000000000000";
variable counter: unsigned(3 DOWNTO 0):= "0000";
variable VrectPW: signed(31 DOWNTO 0):= "00000000000000000000000000000000";
variable VrectPW1: signed(25 DOWNTO 0):="00000000000000000000000000";
variable VrectPW2: signed(31 DOWNTO 0):= "00000000000000000000000000000000";
variable VrectPW_max: signed(31 DOWNTO 0):= "00000000000000000000101111000000";
variable VrectPW3: signed(10 DOWNTO 0);
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variable VrectPW4: signed(8 DOWNTO 0);
variable Vrect_result: signed(31 DOWNTO 0):= "00000000000000000000000000000000";
variable Vrect_comp: unsigned(9 DOWNTO 0):= "0000001101";
variable Vrect_output: std_logic;
variable Result: signed(8 DOWNTO 0);
variable Q1: std_logic;
variable ign_indicator: std_logic;
variable flag_Vrect: integer range 0 to 15;
variable flag_Vdc: integer range 0 to 15 := 15;
variable flag_ign: integer range 0 to 5 := 1;
--DC-LINK OVER VOLTAGE OPERATION VARIABLES ------
variable voltage_protection: integer range 0 to 5 := 0;
variable duration: integer range 0 to 150000000 :=0;
variable protection_count: integer range 0 to 150000000 :=0;
------------------------------------------------------------------------------------
variable abnormal_flag: integer range 0 to 15 :=1;
variable abnormal_count: integer range 0 to 15000000 :=0;
variable trans_counter: integer range 0 to 15000000 :=0;
variable ign_counter: integer range 0 to 15000000;
variable coeff: signed(24 DOWNTO 0);
variable coeff1: signed(24 DOWNTO 0);
variable coeff2: signed(24 DOWNTO 0):="0000000000000000000000000";
variable Y: signed(24 DOWNTO 0);
variable d: signed(8 DOWNTO 0):="000111000";
variable duty: signed(8 DOWNTO 0);
variable duty_max: signed(8 DOWNTO 0):="000111000";
variable duty_fixed: signed(8 DOWNTO 0):="000110100";
variable duty_min: signed(8 DOWNTO 0):="000000010";
variable Vdc_max: unsigned(9 DOWNTO 0):="0101101001";
variable over_DC_voltage: unsigned(9 DOWNTO 0):="0111100001";
variable Vdc_min: unsigned(9 DOWNTO 0):="0000001101";
variable Er: signed(7 DOWNTO 0);
variable Y_delay1: signed(24 DOWNTO 0):= "0000000000000000000000000";
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BEGIN
if resetn = '0' then
CurState<=S15;
NextState:=S15;
VarData_ACQD:=(others=>'0');
VrectData_ACQD:=(others=>'0');
CHSEL<='0';
VarCHSel:='0';
VarReady_VolData:='0';
ReadyVolData<='0';
VarADErrorData:=(others=>'0');
ADErrorData<=(others=>'0');
elsif rising_edge(clk) then
--elsIF (clk'EVENT AND clk = '1' AND reset = '1') THEN
Case CurState Is
when S0 => VarData_ACQD(15):= Data_VI; ---first '0'
VrectData_ACQD(15):= Vrectdata;
NextState:=S1;
when S1 => VarData_ACQD(14):= Data_VI; ---sencond '0'
VrectData_ACQD(14):= Vrectdata;
NextState:=S2;
when S2 => VarData_ACQD(13):= Data_VI; ---data(9) MSB
VrectData_ACQD(13):= Vrectdata;
NextState:=S3;
when S3 => VarData_ACQD(12):= Data_VI; ---data(8)
VrectData_ACQD(12):= Vrectdata;
NextState:=S4;
when S4 => VarData_ACQD(11):= Data_VI; ---data(7)
VrectData_ACQD(11):= Vrectdata;
NextState:=S5;
when S5 => VarData_ACQD(10):= Data_VI; ---data(6)
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VrectData_ACQD(10):= Vrectdata;
NextState:=S6;
when S6 => VarData_ACQD(9):= Data_VI; ---data(5)
VrectData_ACQD(9):= Vrectdata;
NextState:=S7;
when S7 => VarData_ACQD(8):= Data_VI; ---data(4)
VrectData_ACQD(8):= Vrectdata;
NextState:=S8;
when S8 => VarData_ACQD(7):= Data_VI; ---data(3)
VrectData_ACQD(7):= Vrectdata;
NextState:=S9;
when S9 => VarData_ACQD(6):= Data_VI; ---data(2)
VrectData_ACQD(6):= Vrectdata;
NextState:=S10;
when S10 => VarData_ACQD(5):= Data_VI; ---data(1)
VrectData_ACQD(5):= Vrectdata;
NextState:=S11;
when S11 => VarData_ACQD(4):= Data_VI; ---data(0) LSB
VrectData_ACQD(4):= Vrectdata;
Vdc_data := VarData_ACQD(13 downto 4);
Vdc_data_signal <= VarData_ACQD(13 downto 6);
Vdc_data_out9 <= VarData_ACQD(13);
Vdc_data_out8 <= VarData_ACQD(12);
Vdc_data_out7 <= VarData_ACQD(11);
Vdc_data_out6 <= VarData_ACQD(10);
Vdc_data_out5 <= VarData_ACQD(9);
Vdc_data_out4 <= VarData_ACQD(8);
Vdc_data_out3 <= VarData_ACQD(7);
Vdc_data_out2 <= VarData_ACQD(6);
Vdc_data_out1 <= VarData_ACQD(5);
Vdc_data_out0 <= VarData_ACQD(4);
Rectified_volt:= VrectData_ACQD (13 downto 4);
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if (Rectified_volt < Vrect_comp) then
Vrect_output := '1';
V_count := V_count +1;
Vrect_result := V_count;
flag_Vrect:=10;
elsif (Rectified_volt> Vrect_comp) then
if(flag_Vrect > 5)then
V_count_max := Vrect_result;
flag_Vrect := 1;
end if;
Vrect_output := '0';
V_count := "00000000000000000000000000000000";
end if;
Vrect_Q <= Vrect_output;
Vrect_count <= Vrect_result;
VrectPW1(23 downto 9) := V_count_max (14 downto 0);
VrectPW2 := VrectPW + VrectPW1;
VrectPW3 := VrectPW2 ( 22 downto 12);
VrectPW4 := VrectPW2 ( 25 downto 17);
VarADErrorData:= signed('0' & VolRef)-signed('0' & VarData_ACQD(13 downto 4))-
VrectPW3;
ADErrorData<= VarADErrorData(9 downto 0);
NextState:=S12;
when S12 => VarData_ACQD(3):= Data_VI; ---lagging "0'
VrectData_ACQD (3):= Vrectdata;
NextState:=S13;
when S13 => VarData_ACQD(2):= Data_VI; ---lagging "0'
VrectData_ACQD (2):= Vrectdata;
NextState:=S14;
when S14 => VarData_ACQD(1):= Data_VI; ---lagging "0'
VrectData_ACQD (1):= Vrectdata;
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NextState:=S15;
when S15 => VarData_ACQD(0):= Data_VI; ---lagging "0'
VrectData_ACQD (0):= Vrectdata;
if CS_VI='1' then
NextState:=S0;
else
NextState:=S15;
end if;
when others => null;
End case;
CurState<=NextState;
ReadyVolData<=VarReady_VolData;
Vrect_pulse_width1 <= VrectPW2 ;
coeff := VarADErrorData + coeff2;
coeff1 := coeff2 + coeff (17 DOWNTO 6);
Y := Y_delay1 + coeff1; -- Y_delay1 is y[n-1], coeff1 is k*x[n]
Y_delay1 := Y;
if(flag_Vdc = 10) then
duty := "000000110";
if(Vdc_data < "0000100110") then
duration := duration + 1;
if(duration = 20000) then
flag_Vdc := 15;
duration := 0;
end if;
end if;
end if;
if (flag_Vdc = 15) then
duty:="000001000";
flag_Vdc := 1;
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elsif(Vdc_data < Vdc_data_threshold) then
trans_counter := trans_counter +1;
if(trans_counter = 300000)then
duty:="000001000";
flag_Vdc := 1;
end if;
else
trans_counter := 0;
end if;
if(flag_Vdc = 1) then
if(Vdc_data > Vdc_data_threshold) then
duty:= "000001001";
flag_Vdc:= 2;
ign_counter:=0;
end if;
end if;
if(flag_Vdc = 2) then
ign_counter := ign_counter +1;
if (ign_counter = 350000) then
duty:= duty + 1;
ign_counter := 0;
end if;
if(duty = "000110110") then
flag_Vdc:= 3;
end if;
end if;
if (flag_Vdc = 3) then
if (V_count_max > VrectPW_max) then
duty := "000000010";
if(abnormal_flag = 1) then
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abnormal_count := abnormal_count+1;
if(abnormal_count = 30000) then
abnormal_Vdc := Vdc_data;
abnormal_flag := 2;
abnormal_count := 0;
end if;
end if;
if(Vdc_data > abnormal_Vdc) then
duty := "000011111";
--abnormal_flag := 1;
end if;
elsif (V_count_max < VrectPW_max) then
abnormal_flag := 1;
duty := Y(23 DOWNTO 15);
if (Vdc_data > Vdc_max) THEN -- DC-link over-voltage protection
protection_count := protection_count + 1;
if(protection_count = 100) then
flag_Vdc := 10;
duty := "000000110";
protection_count :=0;
end if;
end if;
end if; --end normal op and abnormal op
end if; --end flag 3
if( duty > duty_max) then
duty := duty_max;
end if;
if( Count < Threshold) then
Count := Count + 1;
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if( Count = Threshold) then
Count := "000000000";
end if;
end if;
Result := Count;
end if;
if (Result < duty) THEN
Q1 := '1';
elsif (Result > duty) THEN
Q1 := '0';
end if;
Q <= Q1;
ign_flag <= ign_indicator;
END PROCESS;
END behavioral;
