A Compact Priority based Architecture Designed and Simulated for Data Sharing based on Reconfigurable Computing

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A Compact Priority based ArchitectureDesigned and Simulated for Data Sharing

based on Reconfigurable ComputingBhavya Alankar and B K Kanaujia

AbstractReconfigurable Computing devices are coming very strongly in the digital hardware systems due to the availability ofready to use resources, parallel logic operations and reconfigurable designs. The usage of Reconfigurable systems in real time do-main is also a very fruitful proposition as the FPGA devices are coming with processing cores for Real Time data processing. This

paper mainly focuses on the application of Reconfigurable Computing systems in the data sharing domain and in order to depict thisapplication we have designed and simulated a priority based data sharing architecture through which we can interface two Proces-sors, which in turn can intercommunicate with each other. The main advantage of this architecture is that it is highly compact, easyto use and designed using a modular approach so that it could be easily implemented on Reconfigurable hardware. All the different

modules along with the complete architecture is simulated using modelsim 6.0 and synthesized using Xilinx 7.1(iSE).

Index TermsReconfigurable Computing, FPGA, Master-Slave processor.

1 INTRODUCTION

econfigurable computing based architectures offers aunique opportunity to address the memory accessand interfacing issues via customization. Improve-

ments can be achieved by creating specialized architec-tures and this architecture is mainly designed to explorethose opportunities of Reconfigurable computing [1], [2],[3]. In our design FPGA Spartan-3 kit [7] is acting as aninteractive device through which two processors can in-tercommunicate with each other such that one processorhas been given priority over the other processor and their

priority is been decided by the conflict resolving block.Initially this design is simulated for 8-bit processor but itcan be extended up to any number of bits.

The organization of this paper is as follows: Section 2shows the design overview and the details of differentfunctional modules. Section 3 depicts the simulationwaveform of the architecture. Section 4 discuss the con-clusion and future work

2 DESIGNOVERVIEW

Thedesigned architecture is fully user friendly, flexible

andsynchronous.

One

Processor

acts

as

MASTER

and

the

otherProcessoractslikeaSLAVEandcanintercommunicatewitheachother[4].Memoryprovidedviatwoseparateandfullysynchronousports.Masterwillalwayshave

the priority over slave and we have usedmultiplexedaddress databus for themasterwhich canbe used forslaveaswell.Moreover in ourdesignwe haveused the signals of

peripheralcomponentinterconnectbus[5]forthemasterprocessor to communicate and the slave processor cancommunicateviabusy,address,dataandreadwritesignalsasshowninFig1.,butdependingupontheapplicationyoucanmodifythem.Thedetaileddescriptionofeachoftheblocksdepicted

inthe

main

block

diagram

along

with

their

functional

descriptionanddeviceutilizationsummary isgivenandit canbe seen that thearchitecture ishighly compactasthedeviceutilizationisquietlow.

2.1 Conflict Resolving Block

This block grants the control for accessing Dualportmemory to the requestingsystem.wearemainlyhavingtwo signals viz slave request (pr) and master request(pcirq)andthemainfunctioningofthisblockistoresolvethe conflictbetween thembymaking either slavebusy(probussy)ormasterbusy(pcibussy)aslow(seeTable1)

TABLE1TRUTHTABLEOFCONFLICTRESOLVINGBLOCK

pcirqmaster

prslave

pcibussymaster

Probussyslave

Low Low Low HighLow High Low HighHigh Low High LowHigh High High High

Bhavya Alankar is a Assistant Professor, Hamdard University, New Delhi,India.

B.K. Kanaujia is a Associate Profoessor, Ambedkar Institute of AdvancedCommunication Technologies & Research (AIACTR) Govt. of N.C.T..NewDelhi, India.

R

JOURNAL OF COMPUTING, VOLUME 5, ISSUE 4, APRIL 2013, ISSN (Online) 2151-9617

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Fig.1.CompactArchitectureofDatasharingbetweenMasterSlave.

Based on the information obtained from the abovetruth table, Two Boolean equations have been derivedand based on that equations, following digital design ofConflict resolving block has been obtained in Fig 2.

Fig. 2.Digital design of conflict resolving block

The device utilization summary of thisblock implementedontheSpartan3XC3S200FPGA(200Kgates) isshown inTable2.And It shows that thisblockwasdesignedinsuchawaysoastoutilizetheminimumnumber

of

resources

on

FPGA.

TABLE2DEVICE UTILIZATION SUMMARY OF CONFLICT RE-

SOLVING BLOCK

Number ofslices

1 out of 1920 0%

Number of 4input LUTs

1 out of 3840 0%

Number ofbonded IOBs

3 out of 173 1%

2.2 Interactive Controller Blocks

Whenboth(MasterandSlave)requestfortheaccessofmemory,TheConflictresolvingblockdrivesthebusyline of theMaster(pcibussy)while keeping the Slaveprocessor inawait stateuntil theMaster finishes itsoperation.When theMaster generates the address on

address

lines,

data

on

data

lines

and

write/read

signal

thenthecontrolblockcheckfor thebusy lineofMaster.When the controlblock receives thebusy line ofMaster driven to low, it allows the address on validaddresslines,dataonvaliddatalinesandwr_rdsignalasvalidwr_rdsignaltoaccessthememory.WhentheSlaveProcessorgeneratestheaddressonaddresslines,dataondata linesandwrite/readsignalthenthecontrolblockcheck for thebussy lineofSlaveProcessor.Whenthecontrolblockreceivesthebusylineof SlaveProcessor(probussy)driventolow itallowstheaddresson valid address lines, data on val id data lines andwr_rdsignalasvalidwr_rdsignaltoaccessthememoryasshowninFig3.

Fig.3.InteractiveControllerBlock

Now its clear that themain function of the Interactivecontrollerblock is to just select or decidewhether theMasterorSlaveshouldaccessthememoryonthebasisoftheoutputofConflictresolvingblock,Sothisblockisjusta combination of the Conflict resolving block and the

memory

read

and

write

block.

ThedeviceutilizationsummaryoftheInteractiveController block implemented on the Spartan3 XC3S200FPGA (200Kgates) isshown inTable3.As thisblock isthecombinationofmainlythemuxes.Itshowsthenumberofslicesandotherresourcesavailableutilized in implementingthedesignonFPGA.





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TABLE3DEVICEUTILIZATIONSUMMARYOFINTERACTIVE

CONTROLLERBLOCK

2.3 Memory block

Itisoneofthemainblockandasitisclearfromthenamethatthemainpurposeofthisblockistofulfillthestoragerequirementofboth theMasterand theSlaveProcessor.

Thisstorage

core

is

adual

port

memory

of

64

ksize,

fully

synchronous such that the data is tobewritten on therisingedgeof theclock. It is thecentralblockwhichdependsontheoutputofalltheblockssuchthatfirstofalltheConflict resolvingblockwilldecidewhetherMasterorSlaveProcessorwillaccessthememoryanddependingon theoutputof that the controllerblockwillallow thevalidsignalstoaccessthememoryasshowninFig.4.Thedeviceutilization summary of thememoryblock

implemented on the Spartan3 XC3S200 FPGA (200 Kgates) isshown inTable4. Itshowsthenumberofslicesand other resources available utilized in implementingthedesignonFPGA.

Fig. 4. Memory Block and Its Connectivity

TABLE4DEVICEUTILIZATIONSUMMARYOFMEMORY

BLOCK

Numberofslices 9outof1920 0%

Numberofsliceflip

flops

16outof3840 0%

Numberof4inputLUTs 3outof3840 0%

NumberofbondedIOBs 49outof173 28%

NumberofBRAMs 1outof12 8%

NumberofGCLKs 2outof8 25%

3. SIMULATION RESULTS

3.1MasterContinuouswriteandSlavecontinuousreadcycle:In this the Master take the control from the Conflictresolving block by driving its bus request (pcirq) to accessthe memory. Then it broadcasts the address and data onaddress_data line such that first the address is send andby driving frame# as low and irdy# and trdy# drivinghigh the address is latched and then the data is send andby driving frame# high and driving irdy# and trdy# lowthe data is latched and in the mean time thepciwr(Master write) signal is also made low such that thedata is written in the memory.After the data is written into the memory the data can be continuously read by theSlave processor by just giving the address in the read ad-dress line and by applying read clock and in the meantime the pw(Slave write) signal should also be high andthe data ouput will be coming on the Slave processordata (pd) output line, Fig 5.

Fig. 5. Master Write and Slave read cycle

Numberof

slices

1out

of

1920

0%

Numberof4inputLUTs 1outof3840 0%

NumberofbondedIOBs 4outof173 1%

NumberofGCLKs 1outof8 15%





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3.2SlaveContinuouswrite andSlave continuous readcycle:In this the Slave processor take the control from theConflict resolving block by driving its bus request (pr) toaccess the memory. Then it broadcasts the address onaddresslines (pa [0:7]) and data on datalines (pd [0:7])then it drives its write/read signal (pw) to low after thatit drives its chip enable signal (pe) to low, which causesthe data to be written to memory of the specified ad-dress.For reading the data from memory the Slave pro-cessor broadcasts the address on addresslines (pa [0:7])then it drives its write/read signal (pw) to high after thatit drives its enable signal (pe) to low, which causes thedata to be read from the memory corresponding to thespecified address,asshowninFig 6.

Fig. 6. Slave Write and Slave read cycle

3.3 Master Continuous write and Master continuousread cycle: In this the Master take the control from theConflict resolving block by driving its bus request (pcirq)to access the memory. Then it broadcasts the address anddata on address_data line such that first the address is

send and by driving frame# as low and irdy# and trdy#driving high ,the address is latched and then the data issend and by driving frame# high and driving irdy# andtrdy# low ,the data is latched and in the mean time thepciwr(Master write) signal is also made low such that thedata is written in the memory. After the data is written into the memory the data can be continuously read by justgiving the address in the same way on the address_dataline and afterwards just driving the pciwr signal as highsuch that the data will appear on the output line(pcida),Fig 7.

Fig. 7. Master Write and Master read cycle

4 CONCLUSION

TheperformanceofanyReconfigurableComputing systemmainlydependscriticallyuponitsflexibilityandeaseof interfacingwithotherhardware architectures. In thispaperwe have described an architecturewhich couldeasilybeusedfor intercommunicationbetweentheprocessors

in

prioritized

manner

.We

have

also

described

clearlythearchitectureandworkingofdifferentmodulesalongwiththeirdeviceutilizationsummary.Thearchitectureisfullysynthesizedandsimulatedforinterprocessorcommunication. The ongoingwork is the implementation of this architecture using FPGA kit alongwith themicrocontrollers which could easily depicts the interprocessorcommunicationinrealtime,asthisarchitectureisbasicallydesigned to support the advances inReconfigurableComputing.

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f

[7] FPGASpartan3 website:

http://www.xilinx.com/support/documentation/boards_and_kit

s/ug230.pdf

Bhavya Alankaris a Assitant Professor in Hamdard University, NewDelhi. He has acquired his Master degree in VLSI design. His mainresearch interests areReconfigurable computing, VLSI design andSoftware Engineering.He is having years of research experience inVLSI design and published numerous research papers and conduct-ed workshops related to his research area.

B K Kanaujia is a Associte Professor in Ambedkar Institute ofAdvancedCommunicationsTechnologies& Research (AIACTR), Govt.of N.C.T.New Delhi, India. He did his M.Tech. & Ph.D. from Electron-ics Engineering Department of Banaras Hindu University Varanasi,His keen research interest are in design and Modeling ofMicrostrip Antenna, Dielectric Resonator Antenna, Left handedMetamaterial Microstrip Antenna, Shorted Microstrip Antenna Wire-less Communication, Wireless Communication, Microwave Engi-neering,Reconfigurable computing and VLSI design etc.Till date hehas been credited to publish more than 45 research papers in peer-reviewed journals and International/national conferences.




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A Compact Priority based Architecture Designed and Simulated for Data Sharing based on Reconfigurable Computing