A CMOS Rail-To-rail Linear VI-Converter

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A CMOS rail-to-rail linear VI-converterP. P. Vervoort and R. F. Wassenaar

MESA Research InstituteTwente UniversityP.O. Box 217

7500 A E E nschede, the N etherlandsPhone: x-31 53 892732Fax: x-31 53 341903Abstract: A l inear CMOS VI-converte r

opera t ing in s t rong inversion wi th a common-mode inpu t r a nge f rom the ne ga t ive t o t hepositive supplly rail is presented. The circuitconsists of three linear VI-converters based onthe d i f fe rence of squares pr inc ip le [l-31. Tw oof these perform the ac tua l V to I conversion ,whi le the th i rd changes the b ias cur rent s of thefirst two in response to changes in t h e i n p u tcom mon -mo de level.The resul t ing c i rcui t has a la rge signa lt r a nsc onduc ta nc e w h ich is constant to wi th in3% over the ent i re common-mode input range .I t c a n ope ra t e f rom a single supply vol tage of

2.2Volt.s.I. In t roduct ion

transconductance can be made independent of thecommon-mode input level by biasing the N-typeand P-type VI-converters with the individualoutput currents of a third VI-converter aftercurrent limiting. This third VI-converter is single-ended and driven by the common-mode inputvoltage. Figure 1 shows the structure of theproposed V I-converter circuit.

11.Princ ip leThe individual output currents of a linear VI-

converter based on the difference of squaresprinciple can be described as:

Wwith K =pCox-Lhe common-m ode input range of a single (N-type) transconductor reaches from a certain and herefore:voltage level above the n egative supply rail up toorder to cover the entire rail-to-rail common-a certain level above the positive supply rail. In Id l- d 2 =g, vi,, with g, =2K vdc (2)mode input range* an N-type an d a

have to be driven incircuit is needed to combineIf the Dc-voltage Source V,, is formed by the V g sof a MOSFET with a constant drain current Id cthe large signal transconductance value of the VI-arallel. Athe output currents of th e individual VI-converters. The combined large signal converter is proportional to &. If the

currentmirror out IFig. 1 tructure of the VI-converter circuit.

0-7803-2570-2/95 $4.00 0 1 9 9 5 IEEE 825


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total g, of the circuit of figure 1 has to beconstant, then the condition:(31+g, =constant

has to be satisfied. Since g, is proportional toJKrdc and assuming KN=K p equation 3 can berewritten as:

JrdcN+JIncp=constant ( 4 )It now happens that the currents of equation Isatisfy this condition:

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if V,, is constant. This means that these currentscan be provided by a similar VI-converter.If one of both currents becomes zero, theother one has to be limited to a constant value inorder to keep the total transconductance constant,this explains the need for the current limiters infigure 1.111. Circuit description

A possible realisation of a transconductorbased on the difference of squares principle is thecircuit shown in figure 2. Here the DC-voltagesources are formed by MOSFETs M3 and M4.Their drain currents are kept constant by thecurrent sources M5 and M6 and the feedbackloops formed by M7, M9 and M8, M10. Thetransistors M7 and M8 disconnect the drains ofM3 and M 4 from the gates of M9 and M10 and soenlarge the common-mode input range. Thistransconductor has been selected for its lowminimal supply voltage and its efficient use ofcurrent.

Vdd

k, ,4

I ,

Fig. 2 Schematic of a square-law transconductorAfter som e modification the transconductor offigure2 can also be used as the biasing circuit. In

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figure 3, one half of the circuit of thetransconductor of figure 2 is shown together witha circuit that limits its output current to a value of4Zdc.The current limiting is based on the principlethat in a series connection of a current sink and acurrent source the lowest current alwaysdominates [4]. The transistor that wants to carrythe larger current is forced into the triode regionin order to carry the lower current. In figure 3 th eoutput of the current mirror formed by M 11- Ml 4ac t as the current source and is connected inseries with the drain of transistor M1 which actsas the current sink. A mirrored copy of the draincurrents of M 1,M 13 and M 14 is available at thedrain of transistor M1 5.

v d d

16-LFig. 3 Part of the transconductor with currentlimiter.

A combination of the circuit of figure 3 and itscomplementary version can be used to bias thetwo linear transconductors as is shown in figure 4. The complementary version of the circuit offigure 3 is used in order to eliminate the need forone of the current mirrors in figure 1. The inputvoltages for the biasing circuit will be a referencevoltage (normally V d d / 2 ) nd the common-modeinput voltage.The transconductor of figure 2 and itscomplementary version are used for thetransconductors of figure 1. The transconductorwith the N-type input transistors (like the one infigure 2) is biased as a function of the common-mode input level by using the circuit of figure 3. The complementary version of the transconductor(with P-type input transistors) is biased by acomplementary version of the circuit of figure 3.This results in the complete linear transconductorwith a rail-to-rail common-mode input range,shown in figure 4.


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i"Fig. 4 Complete circuit of the linear VI-converter.

177. Simulations:Several PSPICE simulations have beenperformed with the circuit of figure 4, using the

parameters of a 2.5pm CMOS process and asupply-voltage of 3 Volts. The value of Id c was8pA. The length of the transistors used for theactual VI-converters equals 10pm. The width ofthe PMOS transistors was taken 3.2 times thewidth of the NMBS transistors in an attempt tomake K p equal KN. Under these conditions a

small-signal bandwidth of 4.8 MHz can beachieved. The adap tive biasing circuit reduces thevariation of the transconductance from 33% toless than 3%. Using an I d , of 2pA the minimalsupply voltage is 2.2 Volts.Table 1 gives an overview of severalperformance characteristics of the presentedcircuit. T he figures are given for a nominal valuefor V, which is equal to V, 12 and the valueover the entire common-mode input range(V,,,,,, varies between 0 to V d d ) .

I nominal I over entire commo n- Ivalue mode rangeDC-transconductance 116 110- 116 P A PSmall signal bandwidth (-3dB point) 4.8 4.8 - 9.0 MHzEquivalent input noise 47 45 - 48

I value I moderange IDC-transconductance 116 110- 116 P A PSmall signal bandwidth (-3dB point) 4.8 4.8 - 9.0 MHzEquivalent input noise 47 45 - 48THD differential input(Vin=400mV,,)THD single-ended input voltage(Vin=400mV,,)CMRRvcommon= vcommon dc+vac( OomVtt, OoHz)PSRRSupply currentConditions: Vdd=3V , Id,= 8p A, V in= OOmV,,, 1kHz; unless stated otherwiseTable 1 Simulated Performance characteristics of the transconductor.

Vdd=3Vdc+Vac( 0hlVtt , 100Hz)

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V. Conclusions ReferencesA low-voltage linear CMOS transconductorwith a rail-to-rail common-mode input range anda large signal transconductance which isindependent of the common-mode input voltage

has been presented. The circuit can be used fordifferential signals with varying common-modelevels or single-ended signals. In both cases thetransconductance value will remain constantwithin 3%. It can operate on a supply voltage of2.2 Volts or higher.

AcknowledgementsThe authors would like to thank K. Bult andC.J. Abel fo r their assistance during this project.

[ l ] Nedungadi, A. P., Viswanathan, T. R.:"Design of linear CMOS transconductanceelements", I EEE Transistor Circuits andSystems, 1984, CAS-31, pp. 891-894

[2] Seevinck, E. , Wassenaar, R. F.: "Aversatile CMOS lineartransconductorlsquare-law functioncircuit", IEEE J. solid-state circuits, 1987,

[3] Viswanathan, T. R.: "CMOStransconductance element", Proceedingsof the IE E E , 1986, Vol. 74, pp . 222-224

141 Botma, J. H. , Wassenaar, R. F.,Wiegerink, R. J.: "Simple rail-to-rail low-voltage constant-transconductance CMOSinput stage in weak inversion", Electron.Lett., 1993, Vol. 29, no. 12, pp.1145-1146

Vol. SC-22, pp.366-377

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A CMOS Rail-To-rail Linear VI-Converter