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i
A 4GS/s 6-Bit Time Based ADC
by Time Interleaving Technique
By
Ahmed Gebril AbdAllah Gebril
Ghada labeb Radwan
Hossam Mohamed Gamal Eldin
Mohamed Tarek Abdelmoniem Ali
Mohamed Ramadan Abdalrhman Abdalkader
Under the Supervision of
Dr. Hassan Mostafa
Dr. Mohamed Refky Amin
A Graduation Project Report Submitted to
the Faculty of Engineering at Cairo University
In Partial Fulfillment of the Requirements for the
Degree of
Bachelor of Science
in
Electronics and Communications Engineering
Faculty of Engineering, Cairo University
Giza, Egypt
July 2015
ii
Table of Contents
List of Symbols and Abbreviations.............................................................................. vii
Abstract ......................................................................................................................... ix
Chapter 1: Introduction .............................................................................................. 1
1.1 Motivation ....................................................................................................... 2
1.2 Background ..................................................................................................... 5
1.2.1 Sampling .................................................................................................. 5
1.2.2 Quantization ............................................................................................. 7
1.3 ADC Specification .......................................................................................... 9
1.3.1 The Ideal Transfer Function................................................................... 10
1.3.2 Static specification ................................................................................. 11
1.3.3 Dynamic specification ........................................................................... 14
1.4 ADC Types .................................................................................................... 17
1.4.1 Nyquist rate-Conventional ADC............................................................ 18
1.4.2 Indirect ADCs (Time-Based ADC) ....................................................... 22
Chapter 2: Time-Based ADC................................................................................... 23
2.1 Introduction ................................................................................................... 23
2.2 Time-based ADC Architecture: .................................................................... 23
2.3 Voltage to Time Converter:........................................................................... 23
2.3.1 VTC Block: ............................................................................................ 24
2.3.2 Theory of Operation:.............................................................................. 25
2.3.3 Step by step theoretical analysis: ........................................................... 25
2.4 Linearity and Voltage Sensitivity .................................................................. 26
2.5 Linearization method..................................................................................... 26
2.6 Voltage Sensitivity and Linearity .................................................................. 27
2.7 Simulated Results .......................................................................................... 27
2.8 TDC Definition ............................................................................................. 29
iii
2.9 Vernier Delay Line: ....................................................................................... 29
2.9.1 6-bit Vernier delay line: ......................................................................... 29
2.9.2 Delay Blocks: ......................................................................................... 31
2.10 Simulated results: ...................................................................................... 31
2.11 Output decoding using thermometer encoder: ........................................... 33
Chapter 3: Time Interleaving T-ADC...................................................................... 35
3.1 Introduction ................................................................................................... 35
3.2 Time interleaving Definition ......................................................................... 35
3.3 4Gs/s 6bit resolution Time interleaved T-ADC: ........................................... 36
3.3.1 Theory of operation: .............................................................................. 37
3.4 Simulated results: .......................................................................................... 38
Chapter 4: Calibration.............................................................................................. 39
4.1 Offset Calibration .......................................................................................... 41
4.2 Gain Calibration ............................................................................................ 42
4.3 Timing calibration ......................................................................................... 44
4.4 Different Calibration systems........................................................................ 44
4.4.1 Digital Background Calibration ............................................................. 44
Chapter 5: Conclusion ............................................................................................. 49
5.1 Summery ....................................................................................................... 49
5.1.1 Simulation Result ................................................................................... 49
5.2 Future Work .................................................................................................. 49
References .................................................................................................................... 50
Appendix ...................................................................................................................... 52
iv
List of Tables
Table 1Thermometer Truth Table ................................................................................ 35
Table 2 Results of Implemented Design ...................................................................... 49
v
List of Figures
Figure 1 ADC Symbol ................................................................................................... 1
Figure 2 Moore's Law [2] .............................................................................................. 3
Figure 3 Scaling Down Effects [2] ................................................................................ 3
Figure 4 Generic digital signal processing..................................................................... 4
Figure 5 Futuristic Digital signal Processing ................................................................. 5
Figure 6 Sampling Process............................................................................................. 5
Figure 7 Sampled Sine Wave at high sampling frequency ............................................ 6
Figure 8 Base Band Signal ............................................................................................. 7
Figure 9 NYQUIST Rate sampled Signal ...................................................................... 7
Figure 10 Frequency Domain Aliasing .......................................................................... 7
Figure 11 Quantization Error ......................................................................................... 8
Figure 12 Encoding ........................................................................................................ 9
Figure 13 Quantized Sine Wave .................................................................................... 9
Figure 14 Digital System ............................................................................................... 9
Figure 15 Ideal Transfer Function [3] .......................................................................... 10
Figure 16 Shifted Transfer Function [3] ...................................................................... 11
Figure 17 Offset Error [3] ............................................................................................ 12
Figure 18 Gain Error [3] .............................................................................................. 12
Figure 19 Missing Codes [3]........................................................................................ 13
Figure 20 DNL Error [3] ............................................................................................. 13
Figure 21 INL Error [3] ............................................................................................... 14
Figure 22 Fundamental Frequency and Noise Floor [3] .............................................. 15
Figure 23 Total Harmonic Distortion [3] ..................................................................... 16
Figure 24 ADC Types .................................................................................................. 17
Figure 25 Ramp ADC [6] ........................................................................................... 18
Figure 26 Successive Approximation ADC [7] ........................................................... 19
Figure 27 4-Bit Resolution SAR [7] ............................................................................ 20
Figure 28 Flash ADC [8] ............................................................................................. 21
Figure 29 Sigma Delta Modulator ............................................................................... 22
Figure 30 Time based ADC architecture [4] ................................................................ 23
Figure 31 Current starved inverter [4] ......................................................................... 24
Figure 32 Modified current starved inverter [4] .......................................................... 24
vi
Figure 33 Dc sweep on the input ................................. Error! Bookmark not defined.
Figure 34 Sinusoidal input ........................................................................................... 28
Figure 35 Delay against Vin ........................................................................................ 28
Figure 36 Typical Vernier Delay Line [9] ................................................................... 29
Figure 37 6 bit VDL [4] ............................................................................................... 30
Figure 38 Parallel VDL [4] .......................................................................................... 30
Figure 39 Delay Cell [4] .............................................................................................. 31
Figure 40 sweep on Vgn .............................................................................................. 32
Figure 41 sweep on Vgn to get δ ................................................................................. 33
Figure 42 Time interleaved ADC [11] ......................................................................... 36
Figure 43 4Gs/s Time interleaved TADC .................................................................... 36
Figure 44 Time interleaving operation ........................................................................ 37
Figure 45: 6 bit output.................................................................................................. 38
Figure 46 digital sine wave .......................................................................................... 38
Figure 47 Mismatches .................................................................................................. 39
Figure 48 Offset Calibration Flow chart [12] .............................................................. 42
Figure 49 Gain Calibration Flow Chart [12] ................................................................ 43
Figure 50 General Time Interleaved T-ADC System with Calibration [10] ............... 44
Figure 51 Two Channel ADC with Gain Calibration System [13] .............................. 46
Figure 52 Offset calibration [13] ................................................................................. 47
Figure 53 four channel T-ADC calibration .................................................................. 47
Figure 54 Mixed Signals Adaptive Calibration System .............................................. 48
vii
List of Symbols and Abbreviations
ADC Analog-to-Digital Converter
DAC Digital-to-Analog Converter
TADC Time Based Analog-to-Digital Converter
CMOS Complementary Metal Oxide Semiconductor
DSP Digital Signal Processing
UWB Ultra Wide band
4G Fourth Generation
IC Integrated Circuit
A/D Analog-to-Digital Converter
𝐹𝑠 Sampling Frequency
𝐹𝑚 Max Input Signal Frequency
ENOB Effective Number Of Bits
LSB Least Significant Bit
MSB Most Significant Bit
FS Full Scale
DR Dynamic Range
DNL Differential Non Linearity
INL Integral Non Linearity
SNR Signal-to-Noise Ratio
RMS Root Mean Square
SNDR Signal-to-Noise-Distortion Ratio
THD Total Harmonic Distortion
OSR Over Sampling Ratio
SAR Successive Approximation Register
S/H Sample and Hold
DA Delay Adjustment
VTC Voltage-to-Time-Converter
TDC Time-to-Digital Converter
TI-TADC Time Interleaved Time Based ADC
viii
Acknowledgments
We would like to express our appreciation and special thanks to our supervisors Dr.
Hassan Mostafa and Dr. Mohamed Amin and express our gratitude for their great
support, encouragement, and guidance throughout this project.
Nevertheless, we express our gratitude toward our families and colleagues for their
kind co-operation and encouragement which help us in completion of this project.
This project consumed huge amount of work, research and dedication. Still,
implementation would not have been possible if we did not have a support of many
individuals. Therefore we would like to extend our sincere gratitude to all of them.
Last but not least, the biggest debt and gratitude is for our dear Allah who applied us
with the capabilities, patience and power to complete our project and reach our goals.
ix
Abstract
Analog-to-Digital Converter (ADC) is a very important module in mixed analog to
digital systems because most embedded system applications need an analog-digital
interface.
SDR (Software defined Radio) is the future of communication systems. Therefore,
highly specification modules are needed to be integrated in SDR system like Time
based ADC which is considered an essential block in designing software radio receivers
than using conventional ADC. The analog-to-digital interface circuit in highly
integrated CMOS wireless transceivers exhibits keen sensitivity to technology scaling
down very fast. The trend toward more digital signal-processing for multi-standard
agility in receiver designs has recently created a great demand for low-power, low-
voltage analog-to-digital converters (ADCs). Intended for embedded applications, the
specifications of such converters emphasize high dynamic range and low spurious
spectral performance. Conventional ADCs are facing challenging obstacles in
accuracy, resolution and power. In particular, due to power supply reduction these
obstacles make the conventional ADCs incapable of providing the high speed
requirement of the software receivers front-end.
On the other hand, positive side of CMOS technology scaling down in terms of gate
delay and area is that high specification communication systems could be reached by
taking the trend of increasing the digital part in the system removing a lot of analog
processing blocks so that the ADC moves more and more towards the input of the
system. Moving the ADC towards the system input makes its design more challenging
as the signal will be converted directly to digital which makes the role of ADC more
critical and helps to reduce the power consumption. The decrease of rising and falling
times, the switching characteristics of MOS transistors (which considered to be one of
the positive side) offer excellent timing accuracy at high frequencies. Consequently, the
time based ADCs (TADC) appears as the best candidate to achieve the front-end ADCs
high speed requirements.
The TADCs converts the analog signal to a time delay representation through a block
called Voltage-to-Time Converter (VTC). Then, the time-represented signal is
converted to digital through a circuit called Time-to-Digital Converter (TDC).
Our proposed design is to implement Time-based ADCs by using time interleaving
technique which enables the sample rate to be pushed further than that achievable of
single ADC so our target is to reach a 4GS/s 6 Bit time interleaving Time based ADC
with calibration system to remove mismatch errors of each ADC and finally layout
could be achieved while this system will be fabricated under the 65nm Technology.
1
Chapter 1: Introduction
Analog-to-digital conversion is an electronic process in which a continuously
variable (analog) signal is changed, without altering its essential content, into a multi-
level (digital) signal as shown an Example on Fig(1)
Figure 1 ADC Symbol
𝐷 = 𝑓(𝐴)
The input can assume an infinite number of values, whereas the output can be selected
from a finite set of codes [1]. Analog-to-digital (A/D) conversion lies at the heart of
most modern signal processing systems where digital circuitry performs the bulk of
the complex signal manipulation. In communication transceiver ADC plays the role of
an interface between the analog front-end and the back-end digital signal processing
(DSP) functions. As digital signal processing (DSP) integrated circuits become
increasingly developed and attain higher operating speeds more processing functions
are performed in the digital domain.
The input to an analog-to-digital converter (ADC) consists of a voltage that varies
among a theoretically infinite number of values. Examples are sine waves. The output
of the ADC, in contrast, has defined levels or states. The number of states is almost
always a power of two (exponentially increasing) 2, 4, 8, 16, etc. The simplest digital
signals have only two states, and are called binary. All whole numbers can be
represented in binary form as strings of ones and zeros. Digital signals propagate more
efficiently than analog signals, largely because digital impulses, which are well-defined
and orderly, are easier for electronic circuits to distinguish from noise, which is chaotic
[2].
2
A/D converters are widely used in numerous applications. Recently, the applications
for A/D converters have expanded widely as many electronic systems that used to be
entirely analog have been implemented using digital electronics. Examples of such
applications include digital telephone transmission, cordless phones, transportation,
and medical imaging. Consumer products, such as high-fidelity audio and image
processing, require very high resolution, while advanced radar systems and satellite
communications with ultra-wide-bandwidth require very high sampling rates (above 1
GHz). Advanced radar, surveillance, and intelligence systems, which demand even
higher frequency and wider bandwidth, would benefit significantly from high
resolution A/D converters having broad bandwidths [2].
Organization
In this thesis we introduce 4 chapters. The first one is an introduction about
ADC and the role of ADC in Electronics world, scaling down and its pros and cons,
ADC specification and ADC types. In the next chapter we introduce a specific type of
indirect ADC which is the Time based ADC that considered to be the center of focus
in our project, the analysis of the main blocks of the time-based ADC which is VTC, TDC
and thermometer Encoder presented. The Third one will introduce the Time interleaving
technique which will be used to obtain higher speeds and push the overall system
speed further than the power of the single ADC to increase the speed of the system
and obtain higher specification. Finally Calibration chapter, we will describe the
different mismatches of the ADC due to the manufacturing Process that has effect on
the whole system performance.
1.1 Motivation
Over the past three decades, CMOS technology scaling has been a primary driver
of the electronics industry and has provided a path toward both denser and faster
integration. The number of devices per chip and the system performance has been
improving exponentially over the last two decades. As the channel length is reduced,
the performance improves, the power per switching event decreases, and the density
improves.
3
The realization of scaling theory was defined in “Moore’s Law” which is a
phenomenological observation that the number of transistors on integrated circuits
doubles every two years, as shown in Fig(2).
Figure 2 Moore's Law [2]
There does not seem to be any fundamental physical limitation that would prevent
Moore’s Law from characterizing the trends of integrated circuits. However, sustaining
this rate of progress is not a straightforward achievement. Fig (3) shows the trends of
power supply voltage, threshold voltage, and gate oxide thickness versus channel length
for high performance CMOS logic technologies
Figure 3 Scaling Down Effects [2]
4
The reason is that the supply voltage reduction that accompanies technology scaling
results in lowering voltage swing. Small voltage swing will have effect on two things
[3].
The first one is the low signal to noise ratio (SNR) because the noise level does not
decrease with the same ratio as the supply voltage decrease with. The second problem
arises from the fact that the threshold voltage of the transistor too does not decrease
with the same ratio as the supply voltage, this results in making transistor cascoding
difficult. Thus, the design of the operational amplifier (op-amp), which is a main
building block in the ADC, becomes difficult, and a new solution must be found.
Using the advantage of CMOS technology scaling down in terms of area and gate delay,
we need to increase digital part implemented on chip relative to analog part by
removing pre-processing analog blocks like Low-Noise- Amplifier, Baseband filters,
Variable-Gain-Amplifiers,..etc.
Figure 4 Generic digital signal processing
Fig(4) shows the generic digital signal processing system but due to technology
scaling and removing analog part of system on the other hand increase the digital one
future digital signal processing system could be like that
5
Figure 5 Futuristic Digital signal Processing
1.2 Background
Often the domain and the range of an original signal 𝑥(𝑡) are modeled as
continuous. That is, the time (or spatial) coordinate t is allowed to take on arbitrary
real values (perhaps over some interval) and the value 𝑥(𝑡) of the signal itself is
allowed to take on arbitrary real values (again perhaps within some interval). Such
signals are called analog signals. A continuous model is convenient for some
situations, but in other situations it is more convenient to work with digital signals —
i.e., signals which have a discrete (often finite) domain and range. The process of
digitizing the domain is called sampling and the process of digitizing the range is
called quantization.
1.2.1 Sampling
Figure 6 Sampling Process
Fig (6) shows an analog signal together with some samples of the signal. The samples
shown are equally spaced and simply pick off the value of the underlying analog
signal at the appropriate times. If we let 𝑇𝑠 denote the time interval between samples,
then the times at which we obtain samples are given by nTs where n = . . . , −2, −1, 0,
1, 2 . . . . Thus, the discrete-time (sampled) signal x[n] is related to the continuous-
time signal by “𝑥[𝑛] = 𝑥(𝑛𝑇𝑠 )”. It is often convenient to talk about the sampling
frequency “𝑓𝑠”. If one sample is taken every 𝑇𝑠 seconds, then the sampling frequency
6
is “fs = 1/Ts Hz”. The sampling frequency could also be stated in terms of radians,
denoted by “𝜔𝑠”. Clearly “𝜔𝑠 = 2𝜋𝑓𝑠 = 2𝜋/𝑇𝑠” [3].
1.2.1.1 Sampling Theorem
Sampling Theorem, also called the Shannon Sampling Theorem. This result
gives conditions under which a signal can be exactly reconstructed from its samples.
The basic idea is that a signal that changes rapidly will need to be sampled much
faster than a signal that changes slowly, but the sampling theorem formalizes this in a
clean and elegant way.
Figure 7 Sampled Sine Wave at high sampling frequency
To begin, consider Fig (7) a sinusoid 𝑥(𝑡) = 𝑠𝑖𝑛(𝜔𝑡) where the frequency ω is not
too large. If we sample at rate fast compared to ω, that is if 𝜔𝑠 >> 𝜔. In this case,
knowing that we have a sinusoid with ω not too large, it seems clear that we can
exactly reconstruct “𝑥(𝑡)”. On the other hand, if the number of samples is small with
respect to the frequency of the sinusoid then in this case, not only does it seem
difficult to reconstruct x(t), but the samples actually appear to fall on a sinusoid with
a lower frequency than the original. Thus, from the samples we would probably
reconstruct the lower frequency sinusoid. This phenomenon is called aliasing, since
one frequency appears to be a different frequency if the sampling rate is too low. It
turns out that if the original signal has frequency f, then we will be able to exactly
reconstruct the sinusoid if the sampling frequency satisfies “𝑓𝑠 > 2𝑓”, that is, if we
7
sample at a rate faster than twice the frequency of the sinusoid. If we sample slower
than this rate then we will get aliasing.
Sampling Theorem A band limited signal with maximum frequency 𝜔𝑏 can be
perfectly reconstructed from samples if the sampling frequency satisfies 𝜔𝑠 > 2𝜔𝑏
(or equivalently, if “𝑓𝑠 > 2𝑓𝑏”).
In the Frequency domain representation we could assume a Fourier Transform of a
band limited signal in fig (8).
Figure 8 Base Band Signal
The frequency 2ωB, or 2fB in Hertz, is called the Nyquist rate. Thus, the sampling
theorem can be rephrased as: a band limited signal can be perfectly reconstructed if
sampled above its Nyquist rate fig (9).
Figure 9 NYQUIST Rate sampled Signal
If a signal is sampled too slowly, then aliasing will occur fig (10).
Figure 10 Frequency Domain Aliasing
1.2.2 Quantization
Quantization makes the range of a signal discrete, so that the quantized signal
takes on only a discrete, usually finite, set of values. Unlike sampling (where we saw
that under suitable conditions exact reconstruction is possible), quantization is
generally irreversible and results in loss of information. It therefore introduces
8
distortion into the quantized signal that cannot be eliminated. Quantization is the
process of assigning certain ranges of values from a continuous signal range to
discrete values where step size is equal to the Least Significant Bit (LSB)=Fs
2^N where
N is the number of bits in the digital word and FS is the Full Scale of the analog input.
Due to this assignment, quantization errors occur. A quantization error is the
difference between the quantized value and the original signal.
If we take an example for an analog input is swept from 0 to FS, the quantization error
of a 3 bits ADC will look like a saw-tooth waveform as shown in fig (11).
Figure 11 Quantization Error
For an ADC, quantization error is always in the range of -0.5xLSB ≤ Quantization
error ≤ 0.5xLSB Quantization errors are directly related to the resolution of the ADC.
An ADC that needs an accuracy within a very small margin of error is going to need
more quantization levels. More levels require a larger number of digital bits to encode
all the information. Higher resolution often comes at the cost of converter speed, so
converters need to be optimized for required speeds and resolutions. This optimization
depends greatly on the type of architecture chosen for the ADC design.
After quantization serial binary bits could be found which each specific number of
bits represents specific sample of the input continuous signal has encoded to digital
output fig (12). [4]
9
Figure 12 Encoding
Or we can see the quantized sine wave fig (13). [1]
Figure 13 Quantized Sine Wave
A typical digital system with analog input and output quantities is shown in fig (14).
[5]
Figure 14 Digital System
1.3 ADC Specification
ADC measurements deviate from the ideal due to variations in the
manufacturing process common to all integrated circuits (ICs) and through various
sources of inaccuracy in the analog-to-digital conversion process. The ADC
performance specifications will quantify the errors that are caused by the ADC itself.
ADC performance specifications are generally categorized in two ways: DC accuracy
and dynamic performance. Most applications use ADCs to measure a relatively static,
DC-like signal (for example, a temperature sensor or strain-gauge voltage) or a
dynamic signal (such as processing of a voice signal or tone detection). The
10
application determines which specifications the designer will consider the most
important.
1.3.1 The Ideal Transfer Function
The transfer function of an ADC is a plot of the voltage input to the ADC versus
the code's output by the ADC. Such a plot is not continuous but is a plot of 2^N codes,
where N is the ADC's resolution in bits. If you were to connect the codes by lines
(usually at code-transition boundaries), the ideal transfer function would plot a straight
line. A line drawn through the points at each code boundary would begin at the origin
of the plot, and the slope of the plot for each supplied ADC would be the same as shown
in Fig (15).
Figure 15 Ideal Transfer Function [3]
Fig (15) depicts an ideal transfer function for a 3-bit ADC with reference points at code
transition boundaries. The output code will be its lowest (000) at less than 1/8 of the
full-scale (the size of this ADC's code width). Also, note that the ADC reaches its full-
scale output code (111) at 7/8 of full scale, not at the full-scale value. Thus, the
transition to the maximum digital output does not occur at full-scale input voltage. The
transition occurs at one code width—or least significant bit (LSB)—less than full-scale
input voltage (in other words, voltage reference voltage).
11
Figure 16 Shifted Transfer Function [3]
The transfer function can be implemented with an offset of - 1/2 LSB, as shown in Fig
(16). This shift of the transfer function to the left shifts the quantization error from a
range of (- 1 to 0 LSB) to (- 1/2 to +1/2 LSB). Although this offset is intentional.
Limitations in the materials used in fabrication mean that real-world ADCs won't
have this perfect transfer function.
1.3.2 Static specification
Other than the quantization error, new types of error are introduced due to
non-idealities in circuit implementation of the ADC. In this section, some of errors
that are independent on time (static) is reviewed like (Offset and Gain errors,
Differential non Linearity (DNL), Integral non linearity (INL) and Missing Codes)
1.3.2.1 Offset and gain Errors
The ideal transfer function line will intersect the origin of the plot. The first code
boundary will occur at 1 LSB as shown in Fig (17). You can observe offset error as a
shifting of the entire transfer function left or right along the input voltage axis.
12
Figure 17 Offset Error [3]
While the gain error is the deviation fig (18) of the slope of the ADC characteristics
line from that of the ideal ADC after removing the offset error.
Figure 18 Gain Error [3]
Full-scale error accounts for both gain and offset deviation from the ideal transfer
function. Both full-scale and gain errors are commonly used by ADC manufacturers.
1.3.2.2 Missing Codes
Missing codes is said to be found in ADC when one of the ADC’s digital output
codes is skipped. No missing codes is said to be guaranteed if DNL error doesn’t exceed
1LSB
or if INL error doesn’t exceed 0.5 LSB. Fig (19) shows an example of a missing code
in ADC
13
Figure 19 Missing Codes [3]
1.3.2.3 Differential non-linearity (DNL)
Ideally, each code width (LSB) on an ADC's transfer function should be
uniform in size. For example, all codes in Figure 2 should represent exactly 1/8th of the
ADC's full-scale voltage reference. The difference in code widths from one code to the
next is differential nonlinearity (DNL). The code width (or LSB) of an ADC is shown
in Equation 1. (𝐿𝑆𝐵) =𝐹𝑠
2^𝑁
Figure 20 DNL Error [3]
𝐷𝑁𝐿 =(𝑉𝑛 + 1) − (𝑉𝑛)
𝑉𝐿𝑆𝐵
1.3.2.4 Integral non-linearity
The integral nonlinearity (INL) is the deviation of an ADC's transfer function
from a straight line. INL is determined by measuring the voltage at which all code
transitions occur and comparing them to the ideal. The difference between the ideal
voltage levels at which code transitions occur and the actual voltage is the INL error,
14
expressed in LSBs. INL error at any given point in an ADC's transfer function is the
accumulation of all DNL errors of all previous (or lower) ADC codes, hence it's
called integral nonlinearity. This is observed as the deviation from a straight-line
transfer function, as shown in Fig (21).
𝐼𝑁𝐿 = ∑ 𝐷𝑁𝐿
𝑘
𝑖=0
Figure 21 INL Error [3]
Because nonlinearity in measurement will cause distortion, INL will also affect the
dynamic performance of an ADC.
1.3.3 Dynamic specification
An ADC's dynamic performance is specified using parameters obtained via
frequency-domain in Fig (22), the fundamental frequency is the input signal
frequency. This is the signal measured with the ADC. Everything else is noise—the
unwanted signals—to be characterized with respect to the desired signal. This
includes harmonic distortion, thermal noise, 1/ƒ noise, and quantization noise.
15
Figure 22 Fundamental Frequency and Noise Floor [3]
1.3.3.1 ADC Sampling rate and conversion time
ADC sampling rate is the Frequency used or the speed which ADC can convert
a sample of input to a digital output code and the conversion time is the inverse of the
sampling rate which considered to be 𝑇 = 1/𝑓 is the delay time taken by the ADC to
take input and get output.
1.3.3.2 Signal to noise ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio of the root mean square (RMS)
power of the input signal to the RMS noise power (excluding harmonic distortion),
expressed in decibels (dB), as shown in Equation
𝑆𝑁𝑅(𝑑𝑏) = 20log (𝑉𝑠𝑖𝑔𝑛𝑎𝑙(𝑟𝑚𝑠)
𝑉𝑛𝑜𝑖𝑠𝑒(𝑟𝑚𝑠) )
SNR is a comparison of the noise to be expected with respect to the measured signal.
The noise measured in an SNR calculation doesn't include harmonic distortion but does
include quantization noise (an artifact of quantization error) and all other sources of
noise (for example, thermal noise). For a given ADC resolution, the quantization noise
is what limits an ADC to its theoretical best SNR because quantization error is the only
error in an ideal ADC. The theoretical best SNR is calculated in Equation
𝑆𝑁𝑅(𝑑𝐵) = 6.02𝑁 + 1.76
Where N is the ADC resolution
16
Quantization noise can only be reduced by making a higher resolution measurement
(in other words, a higher-resolution ADC or oversampling). Other sources of noise
include thermal noise, 1/ƒ noise, and sample clock jitter.
1.3.3.3 Harmonic distortion
Nonlinearity in the data converter results in harmonic distortion when analyzed
in the frequency domain. This distortion is referred to as total harmonic distortion
(THD) fig (23), and its power is calculated in Equation
𝑇𝐻𝐷 = 20log (√(𝑉2)2 + (𝑉3)2 + (𝑉4)2
(𝑉1)1)
Figure 23 Total Harmonic Distortion [3]
The magnitude of harmonic distortion diminishes at high frequencies to the point that
its magnitude is less than the noise floor or is beyond the bandwidth of interest.
1.3.3.4 Signal to noise and Distortion ratio (SNDR)
Signal-to-noise and distortion (SNDR) offers a more complete picture by
including the noise and harmonic distortion in one specification. SNDR gives a
description of how the measured signal will compare to the noise and distortion. SNDR
could be calculated by using the following Equation
𝑆𝑁𝐷𝑅 = 20log (𝑉1
√(𝑉2)2 + (𝑉3)2 + (𝑉4)2 + ⋯ + (𝑉𝑛)2)
17
1.3.3.5 Effective number of bits (ENOB)
SNDR (which includes noise and distortion powers) is less than ideal ADC
SNR (which includes only the quantization noise), the actual number of bits will be
less than that
gotten from
SNR = 6.02D+1.76 dB
Effective number of bits (ENOB) is the number of bits that if it is substituted in the
previous equation the value of SNDR will equal to the SNR value. Thus we can
express
ENOB as
ENOB =𝑆𝑁𝐷𝑅|𝑑𝐵 −1.76
6.02
1.4 ADC Types
ADC could be classified according to following fig (24).
Figure 24 ADC Types
ADCs are classified according to two ways. The first way is in which sampling is
performed and have two types. The first type is the Nyquist rate ADCs like flash
ADC, successive approximation ADC, and pipelined ADC. The second type is the
oversampling ADCs like sigma-delta modulator. The oversampling conversion
technique avoids many of difficulties found with Nyquist ADCs like using of anti-
aliasing analog filters. The second way is in which conversion is performed and
divided into two types. The first type is the direct conversion of analog input into
digital output without passing any intermediate stage. The ADCs of the first type are
called Conventional ADCs. The second type is the indirect conversion and this is
done by first converting the analog input signal into an intermediate representation
ADC
Sampling rate
NYQUIST rate
Oversampling rate
Way of conversion
Direct way
Indirect way
18
such as time and then quantize the time representation to digital output which
considered to be the fundamental concept of TADC which will be the center of our
talking in the next chapter.
1.4.1 Nyquist rate-Conventional ADC
1.4.1.1 Digital Ramp ADC
Also known as the stair step-ramp, or simply counter A/D converter. The
basic idea is to connect the output of a free-running binary counter to the input of a
DAC, then compare the analog output of the DAC with the analog input signal to
be digitized and use the comparator’s output to tell the counter when to stop
counting and reset. The following fig (25) shows the basic idea:
Figure 25 Ramp ADC [6]
As the counter counts up with each clock pulse, the DAC outputs a slightly higher
(more positive) voltage. This voltage is compared against the input voltage by the
comparator. If the input voltage is greater than the DAC output, the comparator’s
output will be high and the counter will continue counting normally. Eventually,
though, the DAC output will exceed the input voltage, causing the comparator’s
output to go low. This will cause two things to happen: first, the high-to-low
transition of the comparator’s output will cause the shift register to “load” whatever
binary count is being output by the counter, thus updating the ADC circuit’s output;
secondly, the counter will receive a low signal on the active-low LOAD input,
causing it to reset to 00000000 on the next clock pulse.
19
1.4.1.2 Successive approximation ADC
Successive-approximation-register (SAR) analog-to-digital converters (ADCs)
represent the majority of the ADC market for medium- to high-resolution ADCs. SAR
ADCs provide up to 5Msps sampling rates with resolutions from 8 to 18 bits. The
SAR architecture allows for high-performance, low-power ADCs to be packaged in
small form factors for today's demanding applications.
The analog input voltage (VIN) is held on a track/hold fig (26). To implement the
binary search algorithm, the N-bit register is first set to midscale (that is, 100... .00,
where the MSB is set to 1). This forces the DAC output (VDAC) to be VREF/2, where
VREF is the reference voltage provided to the ADC. A comparison is then performed
to determine if VIN is less than, or greater than, VDAC. If VIN is greater than VDAC, the
comparator output is a logic high, or 1, and the MSB of the N-bit register remains at
1. Conversely, if VIN is less than VDAC, the comparator output is a logic low and the
MSB of the register is cleared to logic 0. The SAR control logic then moves to the
next bit down, forces that bit high, and does another comparison. The sequence
continues all the way down to the LSB. Once this is done, the conversion is complete
and the N-bit digital word is available in the register.
Figure 26 Successive Approximation ADC [7]
Fig (27) will show an example of a 4-bit conversion. The DAC output voltage on Y-
axis. In the example, the first comparison shows that VIN < VDAC. Thus, bit 3 is set to
0. The DAC is then set to 01002 and the second comparison is performed. As VIN >
VDAC, bit 2 remains at 1. The DAC is then set to 01102, and the third comparison is
20
performed. Bit 1 is set to 0, and the DAC is then set to 01012 for the final comparison.
Finally, bit 0 remains at 1 because VIN > VDAC.
Figure 27 4-Bit Resolution SAR [7]
1.4.1.3 Flash ADC
Flash analog-to-digital converters, also known as parallel ADCs, are the
fastest way to convert an analog signal to a digital signal. Flash ADCs are ideal for
applications requiring very large bandwidth, but they consume more power than other
ADC architectures and are generally limited to 8-bit resolution.
Flash ADCs are made by cascading high-speed comparators. The following
figure shows a typical flash ADC block diagram. For an N-bit converter, the circuit
employs 2N-1 comparators. A resistive-divider with 2N resistors provides the reference
voltage. The reference voltage for each comparator is one least significant bit (LSB)
greater than the reference voltage for the comparator immediately below it. Each
comparator produces a 1 when its analog input voltage is higher than the reference
voltage applied to it. Otherwise, the comparator output is 0. Thus, if the analog input is
between VX4 and VX5, comparators X1 through X4 produce 1s and the remaining
comparators produce 0s. The point where the code changes from ones to zeros is at
which the input signal becomes smaller than the respective comparator reference
voltage levels.
21
Figure 28 Flash ADC [8]
This architecture (fig (28)) is known as thermometer code encoding. The thermometer
code is then decoded to the appropriate digital output code. The comparators are
typically a cascade of wideband low-gain stages. They are low gain because at high
frequencies it is difficult to obtain both wide bandwidth and high gain. The
comparators are designed for low-voltage offset, so that the input offset of each
comparator is smaller than an LSB of the ADC. Otherwise, the comparator's offset
could falsely trip the comparator, resulting in a digital output code that is not
representative of a thermometer code. A regenerative latch at each comparator output
stores the result. The latch has positive feedback, so that the end state is forced to
either a 1 or a 0.
1.4.1.4 Over sampling ADC-conventional ADC
1.4.1.4.1 Sigma delta modulator
The basic concept of the sigma-delta modulator is the use of high sampling
rate and feedback for improving the effective resolution of the quantizer. In a
22
conventional ADC, an analog signal is integrated, or sampled, with a sampling
frequency and subsequently quantized in a multi-level quantizer into a digital signal.
This process introduces quantization error noise. The first step in a delta-sigma
modulation is delta modulation. In delta modulation the change in the signal (its delta)
is encoded, rather than the absolute value. The result is a stream of pulses, as opposed
to a stream of numbers as is the case with PCM. In delta-sigma modulation, the
accuracy of the modulation is improved by passing the digital output through a 1-bit
DAC and adding 5 (sigma) the resulting analog signal to the input signal, thereby
reducing the error introduced by the delta-modulation. Fig (29) shows sigma-delta
Modulator diagram. One of the most important sigma-delta modulator characteristics
is the oversampling ratio (OSR) which defined as the ratio of the sampling frequency
to the Nyquist frequency.
Figure 29 Sigma Delta Modulator
1.4.2 Indirect ADCs (Time-Based ADC)
The main advantage of time based ADC is to make use of CMOS technology
scaling down positively. While CMOS technology continues to scale down very fast,
conventional voltages to digital ADCs are facing challenging obstacles concerning
accuracy, resolution and power. In particular, due to supply voltage reduction, the
voltage domain is becoming noisier. In addition, the relatively high threshold voltage
makes the available headroom very small for any sophisticated analog architectures.
On the positive side of scaling, with decreased rising and falling times, the switching
characteristics of MOS transistors offer excellent timing accuracy at high frequencies
.it will be discussed in the following chapters.
23
Figure 30 Time based ADC architecture [4]
Chapter 2: Time-Based ADC
2.1 Introduction
In this chapter we will discuss a Vernier delay-line-based analog to-digital
converter. The basic idea of the ADC is to convert the sampled input voltage to a time
representation which controls the propagation speed of a digital pulse through the
delay line. The generation of the output digital code is based on the
propagation length of the pulse in the delay line in a fixed time window.
The analog to digital conversion can be done using the concept of time-to-digital
quantization where the sampled input voltage is represented in time domain through the
voltage to time converter cell , and then quantized using a delay line structure.
2.2 Time-based ADC Architecture:
The Time-based ADC architecture consists of 2 parts:
Voltage to Time Converter(VTC)
Time to Digital Converter(TDC)
As shown in the Fig (30), When the analog signal is applied to the TADC, The VTC
transforms the input into a series of delayed versions of the clock each representing the
analog input at a given sample, when these pulses are applied to the TDC, the are
converted into a digital output corresponding to the pulse delay at a given instance,
which completes the conversion process from analog to digital.
2.3 Voltage to Time Converter:
The VTC block, can be implemented using single-input-single-output
inverter Fig (31) The conversion is done by controlling the current flowing through
the upper two transistors (M1, and M2) using the analog input signal so we can
24
Figure 31 Current starved inverter [4]
Figure 32 Modified current starved inverter [4]
control the charging or discharging rate of the capacitor connected to the output of the
inverter This will allow us to control the time it takes 𝑉𝑜𝑢𝑡 to reaches a certain
voltage.
2.3.1 VTC Block:
The main disadvantage of using a current starved inverter is the voltage to time
nonlinear relation; the input voltage controls the current through MOS current equation:
𝐼 = 𝐾(𝑉𝑖𝑛 − 𝑉𝑡)(𝑉𝑑𝑠) − (𝑉𝑑𝑠2/2)
This current flows through the transistors to discharge the capacitor through the
equation:
𝐼 = 𝐶(𝑑𝑉/𝑑𝑇)
This leads to a nonlinear inverse relation between the input voltage and
the delay, to reduce the nonlinearity we will use a modified current starved
inverter as shown in Fig (32).
25
2.3.2 Theory of Operation:
The VTC process can be explained by assuming ideal transistor models with the
addition of parasitic capacitor 𝐶𝑜𝑢𝑡, which is mainly formed from the drain
capacitances of M1 and M2 and the gate capacitances of M5 and M6. It is assumed that
all other node capacitances are considerably less than 𝐶𝑜𝑢𝑡.In the figure, M5-M6
forms a standard CMOS inverter, while M1-M4 makes up a current-starved
inverter. The gate input to M3 is the input signal to the VTC (𝑉in). The gate input to
M4, 𝑉𝑐𝑜𝑛𝑠𝑡 is a DC bias voltage used to tune the gain and linearity of the VTC. Since
the M1-M2 inverter has starving devices between M2 and ground but not between
M1 and VDD, rising edges of 𝐶𝐿𝐾 will be slowed down by the starved inverter,
depending on the value of 𝑉in. However, falling edges of 𝐶𝐿𝐾 will be passed through
to 𝑉𝑜𝑢𝑡.
The VTC operation summary is as follows: When a rising edge occurs on 𝐶𝐿𝐾
(𝑡), 𝑉𝑜𝑢𝑡 (𝑡) begins to ramp downwards from VDD at a rate dependent on 𝑉in. When
this ramping signal reaches the threshold of the M5-M6 inverter, a rising edge is
triggered on the inverter output.
2.3.3 Step by step theoretical analysis:
1. Initial conditions:
In steady state, 𝐶𝐿𝐾(𝑡) and 𝑉𝑥(𝑡) equal to zero and
𝑉𝑜𝑢𝑡(𝑡)equals to𝑉𝐷𝐷. In the starved inverter, devices M1, M3
and M4 are in deep triode while M2 is in cut-off. In the second
inverter, M5 is in cut-off while M6 is in deep triode.
2. Rising edge on clock input:
𝐶𝐿𝐾 (𝑡) changes to high, M2 becomes cut-off. M1 switches on,
entering the saturation region. M3 and M4 are still in deep triode
so conduct very little current. Charge stored on 𝐶𝑜𝑢𝑡 flows
through M1.The result is a rapid voltage increase of 𝑉(𝑡) .
3. M3 and M4 enter saturation region:
When 𝑉(𝑡) is increasing rapidly, it can be assumed that M3 and
M4 enter saturation mode simultaneously. Therefore, they limit
the current flowing through M2 to a constant amount, 𝐼𝑚𝑎𝑥.
This causes 𝑉𝑜𝑢𝑡 to linearly ramp down at a constant rate.
26
4. M1 enters triode:
When 𝑉𝐷𝑆1≤ 𝑉𝐺𝑆1−𝑉𝑇, which will match to 𝑉𝑜𝑢𝑡 (𝑡) dropping
by VT. After this point, 𝑉𝐺𝑆2 will no longer be constant, causing
𝑉𝑥to decrease. However, the current through M2 will still be
𝐼𝑚𝑎𝑥, so the linear ramp on 𝑉𝑜𝑢𝑡 is retained. It is expected that
𝑉𝑜𝑢𝑡 (𝑡) will reach the threshold of the M5-M6 inverter during
this step, triggering a rising edge on the inverter output. 𝑉𝑜𝑢𝑡 (𝑡)
will no longer affect the VTC output after this switching point.
5. M3 and M4 enter triode:
When 𝑉(𝑡) reaches the greater of 𝑉𝐼𝑁 − 𝑉th and 𝑉𝑐𝑜𝑛𝑠𝑡– 𝑉𝑇,
either M3 or M4 enters triode, the current through M2 will
begin to decrease, and the ramp on 𝑉𝑜𝑢𝑡 will no longer be
linear. It can be concluded that 𝑉𝑖𝑛 and 𝑉𝑐𝑜𝑛𝑠𝑡 should each be
no higher than 𝑉𝐷𝐷/2− 𝑉𝑇 to ensure that M3 and M4
remain saturated until after the M5-M6 inverter is triggered.
6. System returns to steady state:
𝑉(𝑡) And 𝑉𝑜𝑢𝑡 (𝑡) continue to ramp down until they reach 0.
2.4 Linearity and Voltage Sensitivity
Linearity is an important property of any converter. There are various
metrics for quantifying linearity, including integral non-linearity (INL), differential
non-linearity (DNL), total harmonic distortion (THD), signal to noise and distortion
ratio (SNDR), and effective number of bits (ENOB). Of these, ENOB is the most
commonly used for data converters. The main problem with this delay cell is the
nonlinearity between the controlled voltage (𝑉𝐼𝑁) and the delay value. This
nonlinearity results in introducing distortion.
2.5 Linearization method
The main current starving device M3 is linearized by using source
degeneration implemented with M6. Several current starving devices with different
gate bias voltages were used in parallel with M3. This eases the compression of the
pulse delay time versus input voltage characteristic at high input voltages. The
additional parallel current starving devices also increase the voltage sensitivity of the
27
Figure 33 Dc sweep on the input
VTC. Simulated results show the proposed linearization scheme improves the linearity
and sensitivity of the VTC.
2.6 Voltage Sensitivity and Linearity
The voltage sensitivity and linearity of the VTC were simulated by
sweeping the DC input of the VTC and measuring the clock pulse delay time using a
transient analysis. The linear range is significantly lower for the VTC with no
linearization. Although the linearity of the VTC linearized with degeneration only is
comparable to that of the VTC with the enhanced linearization scheme, the voltage
sensitivity of the VTC with the enhanced linearization scheme is much higher. Using
only source degeneration for linearization and increasing the width of the main current
starving devices, M3, does not result in a VTC as sensitive to the input voltage as the
VTC with the enhanced linearization scheme.
2.7 Simulated Results
The transient output of the VTC were simulated by sweeping the
DC input of the VTC and measuring the clock pulse delay time using transient analysis
fig (33), Then checking the behavior under a sinusoidal input fig (34).
28
Figure 35 Delay against Vin
Figure 34 Sinusoidal input
The dynamic range was chosen by picking the most linear region in the delay against
Vin curve fig (35), delay curve refers to the delay between rising edge on the VTC
output and a rising edge on the output clock signal.
29
Figure 36 Typical Vernier Delay Line [9]
2.8 TDC Definition
A time to digital converter is a device which converts time representation into
digital output, the approach we are using is the Vernier delay line [4].
2.9 Vernier Delay Line:
The resolution achievable, in the digital delay lines is limited to a gate delay.
Which is accordingly limited by the speed of the technology in use. This problem is
overcome by using a Vernier delay line (VDL). VDL uses the differential approach to
transform the time representation into digital output code.
The basic structure is shown in Fig (36). The goal is to measure the time interval
between start and stop. There are two parallel delay chains. The delay of the buffer in
the upper chain is t1 and is slightly greater than the delay of the buffer in the lower
chain t2. The start and stop travel through the delay chains until they become aligned.
The position ‘n’ in the delay line at which stop catches up with the start signal, shows
the time distance between start and stop.
2.9.1 6-bit Vernier delay line:
the design of the 6-bit VDL-based TDC Fig (37). The inputs lnP (positive line)
and InN (negative line) are pulse trains in time that represent sampled information
as the difference between the rising edges of the two signals (Δtin). The TDC is
designed to operate with time delay step=tδ.
30
Figure 37 6 bit VDL [4]
Figure 38 Parallel VDL [4]
The TDC consists of 63 stages, each stage consists of a tunable delay cell and a flipflop.
The delays are tuned using control signals VPi and VNi. The first delay is
designed to delay the negative input relative to the positive by 31tδ. All subsequent
delay cells delay the inputs in the opposite direction, delaying the positive input
relative to the negative input by tδ. After each delay, a flip-flop decides according to
which input’s rising edge occurs first, and stores the output.This output represents a
thermometer code not the actual digital representation , Thus a thermometer encoder
will be needed to transform the output into the digital representation.
In this design, the speed of the ADC was required to be at 1GS/s.In the above
configuration the two signals return to the initial state after 32 stages due to 31δ delay
of one signals and each delay cell delays the other signal by 1δ [4], so due to the
limitation on speed we split the series line into two parellel lines so the speed is
increased as shown in Fig (38).
31
Figure 39 Delay Cell [4]
2.9.2 Delay Blocks:
We produced the variable delays needed for the VDL by the delay block shown
in Fig (39).The core of the delay block is made by M4 and M5 in a standard CMOS
inverter structure, but using voltage-controlled current-starving devices M3 and M6,
we are limiting the maximum current through the inverter.By tuning the voltages VgP
and VgN we adjust the delay of the rising and falling edges, respectively, of the
inverter.
Devices M7 and M8 make a standard CMOS inverter which refines the edge
transitions and negates the inversion of the first part of the delay block. By this way,
the output rising edges continue to correspond to the input rising edges, and
likewise for the falling edges.
2.10 Simulated results:
We sweep VgN and VgP from 0 to VDD Fig (40). This is the absolute delay
of the block; that is, the ti me between the input rising edge crossing the 50% threshold
and the output rising edge crossing the same threshold.
32
Figure 40 sweep on Vgn
The delay of each cell can be determined as follows:
𝐷𝑒𝑙𝑎𝑦 𝑓𝑟𝑜𝑚 𝑡ℎ𝑒 𝑉𝑇𝐶 𝑙𝑖𝑛𝑒𝑎𝑟 𝑟𝑒𝑔𝑖𝑜𝑛 = 200𝑝𝑠
𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑠𝑡𝑎𝑔𝑒𝑠 𝑜𝑓 𝑡ℎ𝑒 𝑉𝐷𝐿 = 64
1 𝛿 = 200/64 = 3.125𝑝𝑠
So by choosing the value of Vgn that produces the required δ value we can produce the
required delay , this is shown in Fig (41).
33
Figure 41 sweep on Vgn to get δ
2.11 Output decoding using thermometer encoder:
As stated above,the output of the vernier delay line doesn’t represent the digital
value of the input signal directly, but it produces a thermometer code which needs to
be converted through a thermometer encoder to produce the digital signal,the truth table
of this encoder would be as follows:
bit5 bit4 bit3 bit2 bit1 bit0 Thermometer Code
0 0 0 0 0 0 000000000000000000000000000000000000000000000000000000000000000
0 0 0 0 0 1 000000000000000000000000000000000000000000000000000000000000001
0 0 0 0 1 0 000000000000000000000000000000000000000000000000000000000000011
0 0 0 0 1 1 000000000000000000000000000000000000000000000000000000000000111
0 0 0 1 0 0 000000000000000000000000000000000000000000000000000000000001111
34
0 0 0 1 0 1 000000000000000000000000000000000000000000000000000000000011111
0 0 0 1 1 0 000000000000000000000000000000000000000000000000000000000111111
0 0 0 1 1 1 000000000000000000000000000000000000000000000000000000001111111
0 0 1 0 0 0 000000000000000000000000000000000000000000000000000000011111111
0 0 1 0 0 1 000000000000000000000000000000000000000000000000000000111111111
0 0 1 0 1 0 000000000000000000000000000000000000000000000000000001111111111
0 0 1 0 1 1 000000000000000000000000000000000000000000000000000011111111111
0 0 1 1 0 0 000000000000000000000000000000000000000000000000000111111111111
0 0 1 1 0 1 000000000000000000000000000000000000000000000000001111111111111
0 0 1 1 1 0 000000000000000000000000000000000000000000000000011111111111111
0 0 1 1 1 1 000000000000000000000000000000000000000000000000111111111111111
0 1 0 0 0 0 000000000000000000000000000000000000000000000001111111111111111
0 1 0 0 0 1 000000000000000000000000000000000000000000000011111111111111111
0 1 0 0 1 0 000000000000000000000000000000000000000000000111111111111111111
0 1 0 0 1 1 000000000000000000000000000000000000000000001111111111111111111
0 1 0 1 0 0 000000000000000000000000000000000000000000011111111111111111111
0 1 0 1 0 1 000000000000000000000000000000000000000000111111111111111111111
0 1 0 1 1 0 000000000000000000000000000000000000000001111111111111111111111
0 1 0 1 1 1 000000000000000000000000000000000000000011111111111111111111111
0 1 1 0 0 0 000000000000000000000000000000000000000111111111111111111111111
0 1 1 0 0 1 000000000000000000000000000000000000001111111111111111111111111
0 1 1 0 1 0 000000000000000000000000000000000000011111111111111111111111111
0 1 1 0 1 1 000000000000000000000000000000000000111111111111111111111111111
0 1 1 1 0 0 000000000000000000000000000000000001111111111111111111111111111
0 1 1 1 0 1 000000000000000000000000000000000011111111111111111111111111111
0 1 1 1 1 0 000000000000000000000000000000000111111111111111111111111111111
0 1 1 1 1 1 000000000000000000000000000000001111111111111111111111111111111
1 0 0 0 0 0 000000000000000000000000000000011111111111111111111111111111111
1 0 0 0 0 1 000000000000000000000000000000111111111111111111111111111111111
1 0 0 0 1 0 000000000000000000000000000001111111111111111111111111111111111
1 0 0 0 1 1 000000000000000000000000000011111111111111111111111111111111111
1 0 0 1 0 0 000000000000000000000000000111111111111111111111111111111111111
1 0 0 1 0 1 000000000000000000000000001111111111111111111111111111111111111
1 0 0 1 1 0 000000000000000000000000011111111111111111111111111111111111111
1 0 0 1 1 1 000000000000000000000000111111111111111111111111111111111111111
1 0 1 0 0 0 000000000000000000000001111111111111111111111111111111111111111
1 0 1 0 0 1 000000000000000000000011111111111111111111111111111111111111111
1 0 1 0 1 0 000000000000000000000111111111111111111111111111111111111111111
1 0 1 0 1 1 000000000000000000001111111111111111111111111111111111111111111
1 0 1 1 0 0 000000000000000000011111111111111111111111111111111111111111111
1 0 1 1 0 1 000000000000000000111111111111111111111111111111111111111111111
1 0 1 1 1 0 000000000000000001111111111111111111111111111111111111111111111
1 0 1 1 1 1 000000000000000011111111111111111111111111111111111111111111111
1 1 0 0 0 0 000000000000000111111111111111111111111111111111111111111111111
35
1 1 0 0 0 1 000000000000001111111111111111111111111111111111111111111111111
1 1 0 0 1 0 000000000000011111111111111111111111111111111111111111111111111
1 1 0 0 1 1 000000000000111111111111111111111111111111111111111111111111111
1 1 0 1 0 0 000000000001111111111111111111111111111111111111111111111111111
1 1 0 1 0 1 000000000011111111111111111111111111111111111111111111111111111
1 1 0 1 1 0 000000000111111111111111111111111111111111111111111111111111111
1 1 0 1 1 1 000000001111111111111111111111111111111111111111111111111111111
1 1 1 0 0 0 000000011111111111111111111111111111111111111111111111111111111
1 1 1 0 0 1 000000111111111111111111111111111111111111111111111111111111111
1 1 1 0 1 0 000001111111111111111111111111111111111111111111111111111111111
1 1 1 0 1 1 000011111111111111111111111111111111111111111111111111111111111
1 1 1 1 0 0 000111111111111111111111111111111111111111111111111111111111111
1 1 1 1 0 1 001111111111111111111111111111111111111111111111111111111111111
1 1 1 1 1 0 011111111111111111111111111111111111111111111111111111111111111
1 1 1 1 1 1 111111111111111111111111111111111111111111111111111111111111111
Table 1Thermometer Truth Table
Chapter 3: Time Interleaving T-ADC
3.1 Introduction
The demand for a high speed, high resolution analog to digital converters leads
to the Dilemma , Increasing the Speed requires using less stages in the delay line which
leads to a lower resolution, The other way around is usually reducing the gate delay,
which is dependent on the technology so it cannot be reduced indefinitely. This leads
us to the concept of Time interleaving.
3.2 Time interleaving Definition
It is a method of increasing the overall system sampling speed by using multiple
ADC in parallel, thus multiplying the sampling speed by the number of ADC used Fig
(42) [9]. As easy as this sounds, the main problem arises during the manufacturing
process, due to the tolerance in manufactured devices, a gain, offset and phase
mismatch will appear between the multiple ADCs used. These mismatches are fixed by
using a calibration circuit for each of these errors, this will be discussed later in the
following chapter.
36
Figure 42 Time interleaved ADC [11]
3.3 4Gs/s 6bit resolution Time interleaved T-ADC:
In this report we will present a 4Gs/s T-ADC by using 4 parallel T-ADC
presented earlier, Fig (43) shows the system structure.
Figure 43 4Gs/s Time interleaved TADC
TADC
TADC
TADC
1 to 4
DE
multiplexer
4 to 1
multiplexer
Digital
Output
Analog
Input
TADC
37
Figure 44 Time interleaving operation
3.3.1 Theory of operation:
When the analog input is applied to the system, It is sampled through the 1:4 de
multiplexer, first sample is sent to the first ADC which starts the conversion to digital,
second sample is sent to the second ADC which starts the conversion process as well,
this continues in the third and fourth ADC, by the time the de multiplexer cycles back
to the first TADC, it would have already finished processing the previous sample and
would be ready to process the next sample.
The output of the ADC is sent to a 4:1 multiplexer which recombines the output of the
4 ADC into 1 signal Fig (44).
38
Figure 45: 6 bit output
Figure 46 digital sine wave
3.4 Simulated results:
Applying a sine-wave analog input with 100 MHz frequency to the system and
then reconstructing the 6 bit output Fig (45) into a digital sine wave to check the
functionality of the system Fig (46), this will also be used to calculate the ENOB of the
system.
39
Chapter 4: Calibration
Calibration general definition is the setting or correcting of a measuring device
or base level [10], usually by adjusting it to match or conform to a dependably known
and unvarying measure or we can consider one more generally which is a comparison
between measurements – one of known magnitude or correctness made or set with one
device and another measurement made in as similar way as possible with a second
device. The device with the known or assigned correctness is called the standard. The
second device is the unit under test, test instrument, or any of several other names for
the device being calibrated.
Our Main proposed work based on TI-ADC which is several A/D converters can be
used in parallel to be interleaved in time so that the effective sampling frequency could
be higher than only one ADC.
Due to manufacturing process, the different ICs of the same component mightn’t do
the same functionality accurately. The non-uniform manufacturing process of the TI-
ADC ICs causes mismatches (errors) in the form of time, frequency, offset and gain
introduced in the output signals during conversion process fig (47). The sampling
rates of analog-to-digital converters (ADC’s) often limit the operating speeds of
signal processing systems. Mismatches in offsets, gains, and sampling times among
the component ADC’s limit the performance of the ADC system.
Figure 47 Mismatches
Fig (48) shows a TI-ADCs channels with different gain and offset errors in each channel
which represent mismatches perfectly due to manufacturing process result and limit the
performance.
40
Figure 48 Different Channel Errors [11]
Calibration can be used to compensate for these errors. In this section, different kinds
of calibrations are discussed together. Calibration of a circuit can be split-up into
several parts, see Fig (49). From left to right, the following blocks can be found: a
test-signal generation block, the circuit which is calibrated, an error detection block
and a correction block.
Figure 49 Generic ADC Calibration System [10]
The blocks are now discussed, starting with the test-signal generation block.
Depending on the calibration, this may have a relatively easy function of shorting the
inputs, swapping the input signals or generating a noncritical DC test-signal, or it may
have a more sophisticated function, like generating accurate high-speed test signals.
In order to perform calibration of a circuit, the error should be measured first and
41
usually some signal processing and memory is needed for the calibration, therefore,
the result of the measurement should preferably be in a digital format.
As S&H is normally followed by an ADC, this ADC can also serve as measurement
device for the S&H. Moreover, the combination of S&H and ADC can be calibrated
as one system. Therefore, the circuit to be calibrated is assumed to be a combination
of S&H and ADC.
The detection block detects the errors and controls the signal generation block and
correction blocks. Several techniques exist for performing a calibration. In foreground
calibration, the ADC is not usable during calibration and specific input signals are
applied. This kind of calibration can be performed at start-up, after warm up or
periodically if the application allows for this. Also, several background calibration
techniques (a technique used to improve the linearity of the system) exist and the
ADC is usable during this kind of (usually continuously running) calibration (Blind
calibration techniques do not interrupt the normal conversion of the TI-ADC).
Depending on the application, the normal input signal can be used to determine the
errors or pseudo random data is added to the input (or the differential input signals
can be interchanged) to distinguish between ADC errors and the input signal.
The correction of errors can be done both in the analog and in the digital domain. An
advantage of digital correction is that the correction is fully transparent: e.g. an
addition of 1 LSB is always exactly an addition of 1 LSB. A disadvantage is that the
digital correction can consume a significant amount of power, especially in the case of
more complex operations such as needed for bandwidth or timing correction. Analog
correction has the advantage that it can be implemented with little or
no additional power consumption, that it is possible to do sub-LSB corrections (e.g.
subtract 0.3 LSB from the input signal, or decrease the gain with 1%) without
increasing the number of output bits and that the input range is not decreased.
4.1 Offset Calibration
Mismatch of the sample-switches causes channel-to-channel variation of clock feed
through and channel-charge injection, which leads to offset between channels. If a
buffer is used in a channel it can also cause offset. Reducing buffer offsets by circuit
scaling to a small enough level (for example 1/ 2 LSB) can, even for moderate
42
resolutions, be unfeasible as the input capacitance becomes very large and limits the
input bandwidth unacceptably.
Offset mismatches among the ADC channels contribute to a periodic additive pattern
in the output of the ADC array. In the frequency domain, this pattern appears as tones
at integer multiples of the channel sampling rate.
Both the detection and the correction of offset errors is relatively easy. In the case of
foreground calibration, the differential inputs can simply be shorted to detect the
channel offsets and for background calibration the average signal level over a long
period can be determined, assuming the input signal is DC free. Correction of the
error in both the analog and digital domain is feasible.
To measure the offset error, increase the input voltage from GND until the first
transition in the output value occurs. Calculate the difference between the input
voltage for which the perfect ADC would have shown the same transition and the
input voltage corresponding to the actual transition. This difference, converted to
LSB, equals the offset error. Here’s a Flowchart fig (50) for measuring single ended
offset errors
Figure 48 Offset Calibration Flow chart [12]
4.2 Gain Calibration
Gain differences between channels can have the same origin as offset errors.
Foreground detection of gain errors is not complicated: after offset correction, a
43
noncritical DC input signal can be applied to determine the channel gain. Analog
correction of e.g. the gain of a buffer is feasible and does not have to cost power.
Gain mismatches between the parallel channels cause amplitude modulation of the
input samples by the sequence of channel gains. In the frequency domain, this
mismatch causes copies of the input signal spectrum to appear centered around integer
multiples of the channel sampling rate.
The gain error is defined as the deviation of the last output step’s midpoint from the
ideal straight line, after compensating for offset error. After compensating for offset
errors, applying an input voltage of 0 always give an output value of 0. However, gain
errors cause the actual transfer function slope to deviate from the ideal slope. This
gain error can be measured and compensated for by scaling the output values. Run-
time compensation often uses integer arithmetic, since floating point calculation
takes too long to perform. Therefore, to get the best possible precision, the slope
deviation should be measured as far from 0 as possible. The larger the values, the
better precision you get. This is described in detail later in this document.
Here’s another flow chart fig (51) for measuring gain errors
Figure 49 Gain Calibration Flow Chart [12]
For some applications it can be beneficial to perform calibration based on the
measured temperature or supply voltage. This is possible if e.g. the gain is dependent
on the temperature and this dependency can be determined accurately. Also in this
case, the adjustment can be performed in the analog domain.
44
4.3 Timing calibration
Calibration of timing is complicated. In the case of foreground calibration, high
frequency test signals are required and the detection of timing differences requires
sophisticated algorithms. The correction of timing errors is also non-trivial and
flexibility in timing tends to increase the power consumption and/or jitter of the clock
signal. Background calibration often relies on spectral characteristics of the input
signal and usually involves additional hardware. So, although timing calibration is
possible, it is better to make the timing alignment accurate by itself, such that
calibration can be avoided. [10]
Finally, the desired block diagram system fig (52) needed for TI-ADCs with
calibration is as follow
Figure 50 General Time Interleaved T-ADC System with Calibration [10]
4.4 Different Calibration systems
4.4.1 Digital Background Calibration
One way to do background calibration in a time-interleaved ADC is to add an extra
parallel channel so that one channel can be calibrated while the others operate in a
time-interleaved fashion. The channel undergoing calibration at any given time can be
rotated so that all channels are periodically calibrated. This approach requires 𝑀 + 1
channels to increase the conversion rate by a factor of 𝑀. To eliminate the need for an
extra parallel channel to do the calibration in the background, background calibration
45
is done here by adding a calibration signal to the ADC input and processing both
simultaneously.
First, consider a technique that allows background calibration of the gain of each
channel in a time-interleaved ADC. The concept is as follows: if the channel gain of
one ADC can be forced to equal a desired value by some method, then this method
can be applied to every ADC in the parallel array to force all the ADC channels in the
array to have the same desired gain value (and therefore to match each other). The
following Figure shows the adaptive system used to calibrate the gain of one ADC.
The key blocks are: a pseudorandom number generator (RNG), a 1-bit DAC, the ADC
under calibration, a digital multiplier with variable gain G determined by the adaptive
loop, and a digital accumulator. The sequence N generated by the pseudo-RNG is
binary and approximately white. It has zero mean and is uncorrelated with the input
signal S. During calibration, the random number is converted to an analog noise
through the 1-bit DAC and is added to the input of the ADC. The same random
number is then subtracted at the output, and the difference € is taken as the ADC final
output. Then € is multiplied by N, scaled by a small negative number (-µgain), and
accumulated to determine the gain G through feedback. In practice, (-µgain≥0)
therefore, the feedback is negative.
To simplify the analysis, a linear model is used in which the ADC and DAC are
represented as amplifiers with gains GA and GD, respectively. Consider the two paths
from the RNG to the inputs of the subtractor that computes €. If the random-number
gain in one path (which is GD*GA times the variable gain G) does not equal the
random-number gain in the other path (which is one), the subtraction of the
calibration signal is not complete at the output, leaving a random-number residue in .
In general, includes the sum of two parts: one is related to the input signal S, the other
is related to the random-number residue. When € is multiplied by the random number
N, the term that contains the product of S and N is averaged out by the accumulator
since the random number is uncorrelated with the input signal. However, the term that
contains (N2 =1) has a nonzero mean value and will produce a nonzero output from
the digital accumulator. The key of the scheme is that the adaptive algorithm updates
the variable gain through negative feedback. If the digital accumulator is ideal, its dc
46
gain is infinite and the negative feedback will force its input to be zero mean. This
occurs when the average random-number residue in is driven to zero, or equivalently
when the average gain applied to the random number in the path through the ADC
(GD*GA times the average G) equals one.
The equations that are used to compute the variable gain are:
𝐺[𝑛 + 1] = 𝐺[𝑛] + (−µ𝑔𝑎𝑖𝑛 ∗ € [𝑛] ∗ 𝑁[𝑛]) (1)
€[𝑛] = 𝐺𝐴𝐺[𝑛]𝑆[𝑛] + 𝐺𝐷𝐺𝐴𝐺[𝑛]𝑁[𝑛] – 𝑁[𝑛] (2)
Where n is a discrete-time index and µ𝑔𝑎𝑖𝑛 is the update step size. Substituting (2)
into (1) and using because N[n] = (+/-)*1 gives:
𝐺[𝑛 + 1] = 𝐺[𝑛] + (µ𝑔𝑎𝑖𝑛 𝐺𝐴𝐺[𝑛]𝑆[𝑛]𝑁[𝑛] − µ𝑔𝑎𝑖𝑛 𝐺𝐷𝐺𝐴𝐺[𝑛] + µ𝑔𝑎𝑖𝑛)
Here’s a two channel TI-ADC fig (53) with gain calibration system added
Figure 51 Two Channel ADC with Gain Calibration System [13]
Offset calibration system fig (54) used in the same two channel TP-ADC is a part of
the previous system
47
Figure 52 Offset calibration [13]
The sequences €1 and €2 are the outputs of the gain calibration system shown in Fig.
Each sequence contains the input signal and the offset of the associated ADC, but the
gain mismatch terms are eliminated by the calibration shown in Fig. 4. Let Vos1 and
Vos2 represent the output-referred offset codes of the two ADC’s, respectively. A
variable offset 𝑂 is added to the gain-corrected output of ADC2, and the result is
subtracted from the ADC1 output. The difference is scaled by and accumulated to
determine. If the step size µoffset is small, the average offset correction O” converges to
a value that makes the average accumulator update equal to zero; that is
O”=Vos1-Vos2
After convergence, the average offsets of the interleaved channels are equalized.
Again, the random component of the offset arising from noise in the adaptive system
can be made arbitrarily small by reducing the step size µoffset. Here’s a prototype of
the Block diagram for a four channel TI-ADC fig(55).
Analog
Input
TADC
TADC 1 to 4
DE
multiplexer
4 to 1
multiplexer
Digital
Output TADC
TADC
Calibration
system
Figure 53 four channel T-ADC calibration
48
4.4.1.1 Mixed signals adaptive calibration loop
Figure 54 Mixed Signals Adaptive Calibration System
Fig (56) shows the calibration loops for one of the three ADC channels. This system
is a mixed-signal version of a model reference adaptive control loop. Here the ADC
under calibration is ADCi; 𝑜i is the i𝑡ℎ channel offset adjustment; 𝑔i’s is the i𝑡ℎ
channel gain adjustment; ei is the difference between the output codes of ADCi and
the reference ADC, and 𝑛 is the sample time index. The output from the calibration-
signal generator 𝑉(𝑛) is the input for the reference ADC and the ADCi under
calibration. The LMS loops adjust oi and gi of ADC until the power of the error ei is
minimized, which occurs when the overall offsets and gains of the reference ADC and
ADCi are the same. The gain and offset terms are updated using the following
equations:
𝑂𝑖(𝑛 + 1) = 𝑂𝑖(𝑛) + µ ∗ 𝑠𝑔𝑛[𝑒𝑖(𝑛)] (1)
𝑔𝑖 (𝑛 + 1) = 𝑔𝑖 (𝑛) + µ ∗ 𝑠𝑖𝑔𝑛(𝑌𝑖(𝑛)) ∗ 𝑠𝑔𝑛[𝑒𝑖(𝑛)] (2)
In (1), the (sgn) function produces a three-level quantization of the error signal. The
sgn(ei)=0 if the reference ADC and ADCi have identical output codes. If the code
from the reference ADC is greater than the code from ADCi, then sgn(ei)=1.
Otherwise, (𝑒𝑖) = −1 . With this three-level quantization, and are constant when the
error is zero. (𝑠𝑖𝑔𝑛[]) function represents a two-level quantization. The
𝑠𝑖𝑔𝑛[𝑌𝑖(𝑛)] is equal to the sign-bit output by ADC. In (1) and (2), the gain or offset
adjustment is either ±µ or zero in each calibration clock period.
49
Chapter 5: Conclusion
5.1 Summery
5.1.1 Simulation Result
Design Achieved Result in Table 2
Technology TSMC 65nm CMOS
Resolution 6 Bits
ENOB 5.4 Bits
Sampling Rate 4 GS/s
Input Dynamic Range 172.2 mV Single Ended
Table 2 Results of Implemented Design
5.2 Future Work
We should take many points in our consideration in order to optimize and enhance the
performance of TI-TADC such as:
- Resolution needs Enhancement.
- Time interleaving Technique could be used again to gain speed more than 4
GS/s.
- Resolve problems for Increasing ENOB.
- Calibration Circuit is needed not only a known design but a circuit that could
be implemented with the main design to remove mismatches.
- Optimize Layout and overall area
50
References
[1] "analog-to-digital conversion (ADC):Whatis.com," [Online]. Available:
http://whatis.techtarget.com/definition/analog-to-digital-conversion-ADC.
[Accessed 2 7 2015].
[2] S. Meroli, "Stefano Meroli blog," [Online]. Available:
http://meroli.web.cern.ch/meroli/lecture_scaled_CMOS_Technology.html.
[Accessed 2 7 2015].
[3] L. Staller, "embedded.com," [Online]. Available:
http://www.embedded.com/design/configurable-
systems/4025078/Understanding-analog-to-digital-converter-specifications.
[Accessed 2 7 2015].
[4] A. A. E. S. A. A. E. H. A. H. M. A. A. A. G. M. M. M. H. and N. M. N. G. , "A
1 GS/s 6 bits Time-Based Analog-to-Digital Converter," 2014.
[5] A. Zjajo and J. P. d. Gyvez, Low-Power High-Resolution Analog to Digital
Converters, London: Springer Science+Business Media, 2011.
[6] "allaboutcircuits.com," [Online]. Available:
http://www.allaboutcircuits.com/textbook/digital/chpt-13/digital-ramp-adc/.
[Accessed 2 7 2015].
[7] "Understanding SAR ADCs: Their Architecture and Comparison with Other
ADCs:maximintegrated.com," [Online]. Available:
http://www.maximintegrated.com/en/app-notes/index.mvp/id/1080. [Accessed 2
7 2015].
[8] "Understanding Flash ADCs:maximintegrated.com," [Online]. Available:
http://www.maximintegrated.com/en/app-notes/index.mvp/id/810. [Accessed 2 7
2015].
51
[9] "Multiply Your Sampling Rate with Time-Interleaved Data
Converters:maximintegrated.com," [Online]. Available:
http://www.maximintegrated.com/en/app-notes/index.mvp/id/989. [Accessed 4 7
2015].
[10] S. Louwsma, E. v. Tuijl and B. Nauta, Time-interleaved Analog-to-Digital
Converters, London: Springer Science+Business Media, 2011.
[11] R. Rovatti, A. Cabrini, F. Maloberti and G. Setti, "On-line Calibration of Offset
and Gain Mismatch in Time-Interleaved ADC using a Sampled-data Chaotic Bit-
stream," 2006.
[12] AVR120: Characterization and Calibration of the ADC on an AVR, 2006.
[13] Stephen H. Lewis, Paul J. Hurst, Kenneth C. Dyer and Daihong Fu, "A Digital
Background Calibration Technique for Time-Interleaved Analog-to-Digital
Converters," 1998.
[14] S. Naraghi, "TIME-BASED ANALOG TO DIGITAL CONVERTERS,"
Michigan , 2009 .
[15] Z. Liu, K. Honda, Masanori Furuta and Shoji Kawahito, Timing Error Calibration
in Time-Interleaved ADC by Sampling Clock Phase Adjustment, warsaw, 2007.
52
Appendix
Appendix A: Steps towards tape-out of an IC
1. In order to create new library in cadence 6.1x:
2. In order to create new cell view to draw your own schematic:
53
3. Begin by drawing schematic:
Inserting components press “i”
Change component parameter press “Q”
For wiring between different components press “w”
For make I/O pins press “p”
Here is an inverter shown as example:
4. Create symbol from this schematic:
54
5. Change symbol block as you like as shown:
6. Now, we want to make a test bench file, so we will create new cell-view as
shown: and we can pick ideal voltage sources from analog-lib as Vpulse, Vdc,
Vsin.
55
7. for simulation of this cell view: First, Launch ADE L as shown:
Then, choose type of analyses required:
56
After that, choose outputs need to be plotted as shown:
Finally, you can simulate your test bench file
57
8. After, Creating symbol to use inverter as building block like any other
component, we need to make layout for this schematic as shown:
9. After, Layout extractor appear as shown we need to generate
components like next step:
58
10. Now, We will generate our transistors and I/O pins
11. Label of I/O pins still need to be modified as shown:
12. Transistor internal structure is hidden, In order to make it appear press
“shift + f”
And you will find some difficulty while moving components, so need to edit
display options as shown:
13. To make interconnections between transistors with each other and
with I/O pins, we use following steps:
59
I. To make a path from node to another make check that you select
required metal layer and beside it written that is used for drawing “dra” , Then
press “p” and make your path
II. To zoom on components press “cntrl + z”
III. To stretch edge of path just press “s” followed by one left click,
then start to move
IV. For ruler to check spacing press “k”,
after finishing press “shift + k “
V. To be notified in case of DRC violation takes place, activate this option as shown:
VI. To make via follow shown figure as we need to make via in different cases:
Between to different metal layers
Between Metal 1 and Substrate: to create bulk terminal of NMOS
transistor
Between Metal 1 and N-Well: to create bulk terminal of PMOs
transistor
Between Metal layer and poly
60
14. Now, after finish drawing layout we need to run different checks that we
mentioned before:
First, DRC is done as shown figure:
We will talk about common errors that would appear with DRC:
1- Errors that can be neglected like the following
Anything contain “Density or CSR”
61
2- Errors that is related to dimensions like following can’t be neglected
just close layout view and press on error
Second, LVS is done as shown figure:
62
If your connections were right, you get this smiley face as shown:
Third, PEX is done as shown figure:
63
After, you run PEX You get this window
After PEX finish its work You get this shown figure
64
15. Now, We need to simulate parasitic components extracted from
drawn layout to know its effect on the circuit functionality:
Now we will test a file called calibre view for old test bench file as shown:
Then, edit options as shown:
65
Finally, we run simulation and get shown figure:
66
Appendix B: VTC Linearity test
1- Plot Output Delay Signal Vs Input Voltage
2- Differentiate output Delay Signal by cadence calculator
3- Calculate Average and Non-Linearity Error of differentiated curve:
Average = 𝑀𝑎𝑥−𝑀𝑖𝑛
2 & Non-Linearity Error =
𝑀𝑎𝑥−𝑎𝑣𝑔,
𝑎𝑣𝑔. x 100 %
4- We can use also Matlab to check Non-Linearity Error: First: By importing
Output Delay Signal Vs Input Voltage to Matlab Then, Run this script:
% Imported Delay Vs Input Voltage .csv file from
cadence
%n: order for fitting
n=1; % to be linear
x=x*10^3; % Input Voltage is converted to mV
y=y*10^12; % Time Delay is converted to psec
p=polyfit(x,y,1);
y2=p(:,1)*x+p(:,2);
slope = (max(y)-min(y))/350;
error=abs(y2-y);
nonlin=( max(error)/slope ) / (350/2^n-bits) ;
% of nonlin
plot(x,y)
hold on
grid
plot(x,y2,'r')
67
Appendix C: ENOB calculations
1. We will simulate our TADC at least for 512 cycle using sinusoidal input
source with Fm=𝐹𝑠
2 , then save output data stream from cadence after
calculation of this equation which model DAC (Decimal Weighting for
each bit):
Digital Output=A0 *𝐷𝑅
2𝑁−𝑏𝑖𝑡𝑠−1 + 2* A1 *
𝐷𝑅
2𝑁−𝑏𝑖𝑡𝑠−1 + 4* A2 *
𝐷𝑅
2𝑁−𝑏𝑖𝑡𝑠−1 +……..
Importing data from cadence as shown:
Then, save output table as .csv file to import it to Matlab.
68
2. We will import data to Matlab, and use Delta-sigma toolbox built-in functions
to calculate ENOB using the following code:
data_stream = Cadence_Output*63/1.08;
dc_offset = sum(data_stream)./length(data_stream);
data_stream = data_stream-dc_offset;
N = length(data_stream);
%Length of your timedomain data
w=hann(N)/(N/4); %Hann window
bw=150e6; %Base-band
Fs=500e6; %Sampling frequency
f=110e6/Fs; %Normalized signal frequency
%choose f&N so that f*N be an integer number
fB=N*(bw/Fs); % Base-band frequency bins
%the BW you are looking at
[snr,ptot,psig,pnoise]=calcSNR(data_stream,f,3,fB,w,N);
Rbit=(snr-1.76)/6.02; % Equivalent resolution in bits
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