A 1.4mW 8b 350MS/s Loop-Unrolled SAR ADCwith Background Offset Calibration in 40nm CMOS

Kareem Ragab and Nan SunUniversity of Texas at Austin, Austin, TX

Email: kragab@utexas.edu, nansun@mail.utexas.edu

Abstract—A divide-and-conquer approach to address com-parator offset mismatch in loop-unrolled SAR ADC is presented.Redundancy and coarse foreground calibration mitigate MSBcomparators offset mismatches. A novel background calibrationloop matches LSB comparators offsets to a reference comparator.The proposed scheme avoids a dedicated calibration cycle thatwould slow down conversion. Additionally, it ensures inputcommon mode voltage tracking for each comparator during bothcalibration and normal operation, without requiring externalinputs or special DAC configuration. This enabled the use ofa simple bidirectional single-side switching scheme to eliminateswitching logic which further boosts speed and reduces switchingpower. An 8b prototype ADC achieves 45dB SNDR and a NyquistFOM of 31.3fJ/conv-step at 350MS/s in 40nm CMOS.

I. INTRODUCTION

Recent years have witnessed a significant increase inthe speed of single-channel SAR ADCs reaching 750MS/sin 28nm CMOS [1] and 1.2GS/s in 32nm SOI [2] for 8bresolution. This is enabled by both technology scaling andcircuit innovations including asynchronous clocking [1-3],multi-bit per step [1,4-5], comparator alternation [2], and loopunrolling [6,7]. The loop-unrolled architecture uses a dedicatedcomparator for each bit decision. This boosts speed by not onlyremoving comparator reset time from the critical path, but alsoeliminating logic and memory delay between the comparatorand the capacitive DAC (CDAC) [6]. However, its linearitysignificantly suffers from offset mismatches between the N -comparators used in an N -bit realization.

Offset mismatch was addressed using foreground calibra-tion [6,7] and residue amplification [7]. However, as compara-tor offset and residue amplification gain drift with voltage andtemperature variations, these schemes require system operationto be interrupted for offline ADC recalibration. To circumventthis limitation, we propose a background offset calibrationtechnique that relies on a reference comparator with alternatingtrigger time. The offset of each LSB comparator is matchedto that of the reference by firing them simultaneously duringSAR conversion and checking their output difference. Thismethod avoids the need for a dedicated background calibrationcycle that slows down conversion speed. MSB comparatorsoffsets are foreground calibrated at power-on. The proposedforeground calibration does not require external inputs [6] ordirect CDAC control [7] which introduces additional delays.

This paper is organized as follows. Section II presentsthe proposed ADC architecture. Section III describes circuitimplementation details. Measurement results of the prototypeADC are reported in Section IV, followed by the conclusionin Section V.

II. ADC ARCHITECTURE

A. Basic Operation

Fig. 1 shows ADC architecture and timing diagram. Beforedescribing the basic operation, the three key architecturalimprovements that tackle the offset mismatch problem arehighlighted. First, a redundant bit is added after the 4th

decision to provide an error budget for MSB comparators offsetmismatches and CDAC settling errors. This relaxes offsetmatching requirement for the first four MSB comparators, sim-ply referred to as the MSB comparators. Second, a calibrationunit performs power-on foreground coarse offset calibrationfor the MSB comparators. Third and more importantly, anauxiliary reference comparator enables background fine offsetcalibration for LSB comparators.

For basic operation, we may ignore the reference com-parator. The differential input is tracked using boot-strappedtrack-and-hold switches [9] and is top-plate sampled on thedifferential CDAC on clks falling edge. clks is generated bygating the ADC 50% duty-cycle external clock clkext as shownin Fig. 1. A dedicated comparator is used to resolve each bitdecision and stores comparison result. No additional memoryelements are needed as the comparators are only reset afterconversion is completed. The 1st MSB comparator is triggeredon clks falling edge. Buffered comparator outputs dp[8] anddn[8] directly drive MSB capacitor bottom plate without theneed for any logic. A 3-bit programmable delay line (PDL)ensures sufficient time for DAC settling. A dynamic OR detectsthe completion of the first SAR step and generates clk[7] totrigger the 2nd MSB comparator. This operation repeats in adomino-like fashion until all bits are resolved. Finally, digitaloutputs dp[8:0] are latched using clkl and then the entire ADCis reset on Reset high.

B. LSB Comparators Background Calibration

Each conversion cycle, the reference comparator is trig-gered simultaneously with one of the LSB comparators. Thisis achieved by periodically aligning the reference comparatorclock with each of the LSB comparators clocks clk[4:0], onceevery five cycles, using a multiplexer as shown in Fig. 1. Thedifference of the reference comparator output dref and outputof the ith LSB comparator being calibrated dp[i], i ∈ [0 : 4]represents offset mismatch error. This error signal is lowpass filtered, to suppress fluctuation due to comparators noise,and fedback to cancel the LSB comparator offset mismatch.Performing the calibration during normal SAR operation of-fers two advantages. First, it avoids budgeting a dedicatedcalibration time slot that would slow down conversion speed.

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Fig. 1. Proposed loop-unrolled SAR ADC architecture and timing diagram.

Second, the calibration is intrinsically performed at the rightinput common mode voltage. After convergence, all LSBcomparators would have the same offset as the referencecomparator, which sets the entire ADC offset.

C. MSB Comparators Foreground Calibration

The background offset calibration described in the previ-ous section can be extended to calibrate MSB comparators.However, this would slow down convergence due to the lowprobability of MSB comparator input falling close to compara-tor threshold. Therefore, an alternative approach is taken tohandle MSB comparators offset mismatch. First, a redundantbit is placed after the 4th decision that provides an error budgetof 8LSB, divided into 4LSB for CDAC settling error and4LSB for MSB comparators offset mismatches. This relaxesthe offset matching requirement for the MSB comparators andallows for offset drift after foreground calibration.

During power-on foreground calibration, ADC inputs Vin,p

and Vin,n are shorted to apply a zero input and the ADCoperates exactly like in normal operation except for twodifferences. First, switch S0 shorts the two CDACs as shownin Fig. 1. This ensures that: (a) a zero-input is applied toeach comparator regardless of the decision of its precedingcomparator, and (b) the input common mode voltage for eachcomparator is the same as in normal operation. Second, inorder to reduce S0 size, all PDLs are set to their maximumdelay and ADC clock is reduced to allow sufficient time forsettling during foreground calibration. With zero-input applied,the calibration unit digitally trims the offset for each of theMSB comparators and the reference comparator, based on theiroutputs, to ±2LSB.

III. CIRCUIT IMPLEMENTATION

A. Capacitive DAC

CDAC schematic is shown in Fig. 2. A MOM capacitorof 1.9fF is used for the unit capacitor Cu. CDAC switchesare scaled in proportion to the switched capacitor. Redundantcapacitor 8Cu is used to provide an error budget for MSBdecisions. Conversion time saving from MSB steps CDAC in-complete settling compensates for the additional time requiredfor the redundant SAR step. As incomplete settling error islargest for the second comparison and is negligible for thefirst comparison, the second MSB capacitor is sized to 28Cu

instead of 32Cu. This translates 4LSB of redundancy fromthe first comparison to the second comparison increasing itsincomplete settling error budget to 8LSB.

A bidirectional single-side switching scheme is used [8].This scheme allows the comparators to directly drive theCDAC without additional logic. After each comparison, onlyone side of the CDAC is switched. Additionally, this switchingscheme enables control of CDAC common mode voltageduring SAR operation. The common mode voltage profile isoptimized to increase speed and improve LSB comparators off-set matching. A mean common mode voltage close to 0.6Vdd

increases Strong-Arm latch comparator regeneration speedwithout significantly increasing its input referred noise [2].Moreover, by proper selection of the up and down transitions,the common mode variation is minimized for the LSB SARsteps. This reduces the residual systematic offset mismatchdue to dependence of the reference comparator offset on thecommon mode voltage in the LSB steps.

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Fig. 2. Schematic of the differential CDAC (a) and its common mode voltageprofile (b).

Fig. 3. Schematic of MSB comparator with coarse offset correction (a) andLSB comparator with fine offset correction (b).

B. Comparators

Schematic of the MSB comparator with coarse offsetcorrection is shown in Fig. 3a. A Strong-Arm latch is chosenfor its good balance between speed, noise, and power [2]. Thecomparator is sized for noise and speed. It has an input referredRMS noise and offset of 0.6mV and 7mV respectively. BothMSB and LSB comparators share the same latch design andsize. MSB comparator offset is corrected using auxiliary binaryweighted input devices that are digitally controlled by thecalibration unit. The gate terminals of the auxiliary transistorsare connected to a switched capacitor (SC) reference. For eachMSB comparator, capacitor ratio C1/C2 is chosen such thatthe gate voltage of the auxiliary transistors is nearly equal tothe comparator’s input common mode voltage. Cref is sizedto 22fF for negligible impact of comparator kickback on thereference value.

Fig. 3b shows the schematic of the LSB comparator. Anauxiliary input pair is used for offset correction. Positiveinput Vcal,p is connected to a fixed SC reference, which isre-used in all LSB slices given their similar common mode

Fig. 4. Die Photograph.

voltage. Negative input Vcal,n is used to correct comparatoroffset and is stored on capacitor Ccal = Cref for nominalmatching. This structure is similar to [2] with difference inthe driving logic. Calibration unit uses the difference betweenthe reference comparator output dref and LSB comparatorlatched output d[i] to dynamically update Vcal,n by adding orsubtracting charge from Ccal using the UP/DN control signals.If dref = 0 and d[i] = 1, UP is set to 1 which increases Vcal,n.If dref = 1 and d[i] = 0, DN is set to 1 which decreasesVcal,n. If dref = d[i], Vcal,n remains unchanged. All Vcal,n

updates and SC reference refreshes are performed during ADCreset in order to avoid disturbing comparator offset during SARoperation.

In order to reduce Vcal,n ripple at steady state, a large deep-trench Ccal was used in [2]. As deep-trench capacitors werenot available in the target standard CMOS process, we adoptan alternative approach to reduce the requirement on Ccal sizeand save area. First, Cpar1 and Cpar2 are realized using onlyparasitic capacitance. Second, a narrow pulse is used to drivethe charge transfer switches to further reduce the transferredcharge as shown in Fig. 3b. Using these two methods, a smallCcal of only 22fF equal to that used in the SC reference issufficient to suppress the ripple power to a negligible levelbelow ADC noise floor.

IV. MEASUREMENT RESULTS

The prototype ADC was implemented in 40nm CMOS.Die photograph is shown in Fig. 4. The ADC operates at350MS/s under 1.1V supply. It consumes in total 1.37mWwhich includes the on-chip background calibration. Fig. 5shows measured SNDR and SFDR vs. input frequency. SNDRis better than 43.7dB in the first Nyquist zone. Measured ADCspectrum for a 158MHz 0dBFS input signal with an SNDR of43.7dB and SFDR of 59.5dB is shown in Fig. 6. MeasuredDNL and INL are improved from +1.7/-1 LSB and +2.3/-0.7 LSB respectively to +0.8/-0.9 LSB and +0.6/-0.9 LSBrespectively with background calibration enabled as shown inFig. 7.

Table I summarizes the performance of the proposed ADC.The ADC achieves a FOM that is in line with state-of-the-art SAR ADCs with single-channel speeds ≥250MS/s andresolutions ≥8b and is the smallest for implementations thatresolve single-bit per cycle in bulk CMOS. Simple logic, fullydynamic comparators, and eliminated CDAC latches enable

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Fig. 5. Measured SNDR and SFDR as a function of input frequency.

Fig. 6. Measured spectrum (16-times averaged 8192 points FFT) of a158MHz input frequency.

Fig. 7. Measured DNL/INL without background calibration (gray) and withbackground calibration (black).

TABLE I.PERFORMANCE COMPARISON WITH STATE-OF-THE-ART

[1] [2] [3] [4]* [5] This work

Technology [nm] 28 32 SOI 65 45 65 40

Resolution [bits] 8 8 8 10 8 8

Bits per step 2 1 1 2 2 1

Supply Voltage [V] 1.0 1.0 1.2 1.2 1.2 1.0 1.1

Channel Clock [MHz] 750 1200 450 425 400 250 350

SNDR near Nyquist [dB] 43.3 39.3 47.3 51.2 40.1 44 43.7

Power [mW] 4.5 3.1 5.4 15.4 4 1.8 1.37

FOM @ Nyquist [fJ/Conv] 41 34 76 30.4 117 60 31.3* TI-SAR

the proposed architecture to achieve a good balance betweenpower and speed. FOM can be further improved by sizingdown MSB comparators as in [7].

V. CONCLUSION

This paper presented an 8b loop-unrolled SAR ADC withbackground offset calibration. Incorporating redundancy sim-plifies the offset mismatch problem for the MSB comparators.Both MSB and LSB comparators are calibrated at their cor-responding common mode voltage in normal operation. Theproposed calibration maintains the high-speed merit of theloop-unrolled architecture and enables robust operation underprocess, voltage, and temperature variations.

ACKNOWLEDGMENT

The authors are grateful to the TSMC University ShuttleProgram for chip fabrication. This work was supported in partby NSF grants 1254459, 1509767, and 1527320.

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